EVAL-AD7866CB [ADI]
Dual 1 MSPS, 12-Bit, 2-Channel SAR ADC with Serial Interface; 双通道1 MSPS ， 12位，双通道SAR ADC ，具有串行接口
| 型号： | EVAL-AD7866CB |
| 厂家： | 
ADI |
| 描述： | Dual 1 MSPS, 12-Bit, 2-Channel SAR ADC with Serial Interface |
| 文件： | 总20页 (文件大小：300K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 1 MSPS, 12-Bit, 2-Channel
SAR ADC with Serial Interface
a
AD7866
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Dual 12-Bit, 2-Channel ADC
Fast Throughput Rate
V
D
A
AV
DV
DD
REF
CAP
REF SELECT
DD
1 MSPS
Specified for VDD of 2.7 V to 5.25 V
Low Power
11.4 mW Max at 1 MSPS with 3 V Supplies
24 mW Max at 1 MSPS with 5 V Supplies
Wide Input Bandwidth
2.5V
REF
BUF
AD7866
12-BIT
SUCCESSIVE-
APPROXIMATION
ADC
V
A1
OUTPUT
DRIVERS
D
A
T/H
OUT
MUX
V
A2
70 dB SNR at 300 kHz Input Frequency
Onboard Reference 2.5 V
Flexible Power/Throughput Rate Management
Simultaneous Conversion/Read
No Pipeline Delays
A0
RANGE
SCLK
CS
CONTROL
LOGIC
V
DRIVE
12-BIT
SUCCESSIVE-
APPROXIMATION
ADC
High-Speed Serial Interface SPITM/QSPITM
MICROWIRETM/DSP Compatible
Shut-Down Mode
/
V
B1
OUTPUT
DRIVERS
D
B
T/H
OUT
MUX
V
B2
1 A Max
BUF
20-Lead TSSOP Package
D
B
AGND AGND
DGND
CAP
GENERAL DESCRIPTION
reference is preferred. Each on-board ADC can also be supplied
with a separate individual external reference.
The AD7866 is a dual 12-bit high-speed, low power, successive-
approximation ADC. The part operates from a single 2.7 V to 5.25 V
power supply and features throughput rates up to 1 MSPS. The
device contains two ADCs, each preceded by a low-noise, wide
bandwidth track/hold amplifier which can handle input frequencies
in excess of 10 MHz.
The AD7866 is available in a 20-lead thin shrink small outline
(TSSOP) package.
PRODUCT HIGHLIGHTS
1. The AD7866 features two complete ADC functions allowing
simultaneous sampling and conversion of two channels. Each
ADC has a 2-channel input multiplexer. The conversion
result of both channels is available simultaneously on separate
data lines, or both may be taken on one data line if only one
serial port is available.
The conversion process and data acquisition are controlled
using standard control inputs allowing easy interfacing to
microprocessors or DSPs. The input signal is sampled on the
falling edge of CS and conversion is also initiated at this point.
The conversion time is determined by the SCLK frequency.
There are no pipelined delays associated with the part.
2. High Throughput with Low Power Consumption—The
AD7866 offers a 1 MSPS throughput rate with 11.4 mW
maximum power consumption when operating at 3 V.
The AD7866 uses advanced design techniques to achieve very low
power dissipation at high throughput rates. With 3 V supplies
and 1 MSPS throughput rate, the part consumes a maximum of
3.8 mA. With 5 V supplies and 1 MSPS, the current consumption
is a maximum of 4.8 mA. The part also offers flexible power/
throughput rate management when operating in sleep mode.
3. Flexible Power/Throughput Rate Management—The
conversion rate is determined by the serial clock allowing
the power consumption to be reduced as the conversion time
is reduced through a SCLK frequency increase. Power
efficiency can be maximized at lower throughput rates if the
part enters sleep during conversions.
The analog input range for the part can be selected to be a 0 V
to VREF range or a 2 × VREF range with either straight binary or
two’s complement output coding. The AD7866 has an
on-chip 2.5 V reference which can be overdriven if an external
4. No Pipeline Delay—The part features two standard successive-
approximation ADCs with accurate control of the sampling
instant via a CS input and once off conversion control.
SPI and QSPI are trademarks of Motorola Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
(TA = TMIN to TMAX, VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, Reference = 2.5 V
External on DCAPA and DCAPB, fSCLK = 20 MHz, unless otherwise noted.)
AD7866–SPECIFICATIONS1
Parameter
A Version1 B Version1
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal to Noise + Distortion (SINAD)2
Total Harmonic Distortion (THD)2
68
–75
68
–75
–76
dB min
dB max
dB max
fIN = 300 kHz Sine Wave, fS = 1 MSPS
fIN = 300 kHz Sine Wave, fS = 1 MSPS
fIN = 300 kHz Sine Wave, fS = 1 MSPS
Peak Harmonic or Spurious Noise (SFDR)2 –76
Intermodulation Distortion (IMD)2
Second Order Terms
Third Order Terms
Channel to Channel Isolation
–88
–88
–88
–88
–88
–88
dB typ
dB typ
dB typ
SAMPLE AND HOLD
Aperture Delay3
10
50
200
12
2
10
50
200
12
2
ns max
ps typ
ps max
MHz typ
MHz typ
Aperture Jitter3
Aperture Delay Matching3
Full Power Bandwidth
@ 3 dB
@ 0.1 dB
DC ACCURACY
Resolution
Integral Nonlinearity
12
1.5
12
1
1.5
Bits
LSB max
LSB max
B Grade, 0 V to VREF range only; 0.5 LSB typ
0 V to 2 × VREF range; 0.5 LSB typ
Guaranteed No Missed Codes to 12 Bits
Straight Binary Output Coding
Differential Nonlinearity
0 V to VREF Input Range
Offset Error
Offset Error Match
Gain Error
Gain Error Match
2 × VREF Input Range
Positive Gain Error
Zero Code Error
Zero Code Error Match
Negative Gain Error
–0.95/+1.25 –0.95/+1.25 LSB max
8
8
LSB max
LSB typ
LSB max
LSB typ
1.2
2.5
0.2
1.2
2.5
0.2
–VREF to +VREF Biased about VREF with
Two’s Complement Output Coding
2.5
8
0.2
2.5
2.5
8
0.2
2.5
LSB max
LSB max
LSB typ
LSB max
ANALOG INPUT
Input Voltage Ranges
0 to VREF
0 to VREF
V
V
RANGE Pin Low upon CS Falling Edge
RANGE Pin High upon CS Falling Edge
0 to 2 × VREF 0 to 2 × VREF
500 500
30 30
DC Leakage Current
Input Capacitance
nA max
pF typ
pF typ
When in Track
When in Hold
10
10
REFERENCE INPUT/OUTPUT
Reference Input Voltage
2.5
2/3
30
160
20
2.5
2/3
30
160
20
V
1% for Specified Performance
Reference Input Voltage Range4
DC Leakage Current
V min/V max REF SELECT Pin Tied High
µA max
µA max
pF typ
VREF Pin;
DCAPA, DCAPB Pins;
Input Capacitance
Reference Output Voltage5
VREF Output Impedance6
2.45/2.55
2.45/2.55
V min/V max
Ω typ
25
45
50
15
25
45
50
15
VDD = 5 V
VDD = 3 V
Ω typ
Reference Temperature Coefficient
REF OUT Error (TMIN to TMAX
ppm/°C typ
mV typ
)
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
0.7 VDRIVE
0.3 VDRIVE
1
10
0.7 VDRIVE
0.3 VDRIVE
1
10
V min
V max
µA max
pF max
Typically 15 nA, VIN = 0 V or VDRIVE
3
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
VDRIVE – 0.2 VDRIVE – 0.2
V min
ISOURCE = 200 µA
ISINK = 200 µA
0.4
1
10
0.4
1
10
V max
µA max
pF max
VDD = 2.7 V to 5.25 V
Floating-State Output Capacitance3
Output Coding
Straight (Natural) Binary
Two’s Complement
Selectable with Either Input Range
–2–
REV. 0
AD7866
Parameter
A Version1 B Version1
Unit
Test Conditions/Comments
CONVERSION RATE
Conversion Time
16
300
1
16
300
1
SCLK cycles 800 ns with SCLK = 20 MHz
ns max
Track/Hold Acquisition Time3
Throughput Rate
MSPS max
See Serial Interface Section
POWER REQUIREMENTS
VDD
2.7/5.25
2.7/5.25
2.7/5.25
2.7/5.25
V min/max
V min/max
VDRIVE
7
IDD
Digital I/Ps = 0 V or VDRIVE
Normal Mode (Static)
3.1
2.8
4.8
3.8
1.6
560
1
3.1
2.8
4.8
3.8
1.6
560
1
mA max
mA max
mA max
mA max
mA max
µA max
VDD = 4.75 V to 5.25 V. Add 0.5 mA
Typical if Using Internal Reference
VDD = 2.7 V to 3.6 V. Add 0.35 mA
Typical if Using Internal Reference
VDD = 4.75 V to 5.25 V. Add 0.5 mA
Typical if Using Internal Reference
VDD = 2.7 V to 3.6 V. Add 0.5 mA
Typical if Using Internal Reference
fS = 100 kSPS, fSCLK = 20 MHz
Add 0.2 mA Typ if Using Internal Reference
(Static) Add 100 µA Typical if Using Internal
Reference
Operational, fS = 1 MSPS
Partial Power-Down Mode
Partial Power-Down Mode
Full Power-Down Mode
Power Dissipation7
µA max
SCLK On or Off.
Normal Mode (Operational)
24
24
mW max
mW max
mW max
mW max
µW max
µW max
VDD = 5 V
11.4
2.8
1.68
5
11.4
2.8
1.68
5
VDD = 3 V
Partial Power-Down (Static)
Full Power-Down (Static)
VDD = 5 V. SCLK On or Off.
VDD = 3 V. SCLK On or Off.
DD = 5 V. SCLK On or Off.
VDD = 3 V. SCLK On or Off.
V
3
3
NOTES
1Temperature ranges as follows: A, B Versions: –40°C to +85°C.
2See Terminology section.
3Sample tested @ 25°C to ensure compliance.
4External reference range that may be applied at VREF, DCAPA, or DCAPB.
5Relates to pins VREF, DCAPA, or DCAPB.
6See Reference section for DCAPA, DCAPB output impedances.
7See Power Versus Throughput Rate section.
Specifications subject to change without notice.
–3–
REV. 0
AD7866
TIMING SPECIFICATIONS1
(VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.)
Limit at
TMIN, TMAX
Parameter
Unit
Description
2
fSCLK
10
20
kHz min
MHz max
ns max
ns max
ns max
ns min
tCONVERT
16 × tSCLK
800
50
10
25
tSCLK = 1/fSCLK
fSCLK = 20 MHz
tQUIET
Minimum Time Between End of Serial Read and Next Falling Edge of CS
CS to SCLK Setup Time
Delay from CS Until DOUTA and DOUTB Three-State Disabled
Data Access Time After SCLK Falling Edge. VDRIVE Ն 3 V, CL = 50 pF;
VDRIVE < 3 V, CL = 25 pF
t23
t33
ns max
ns max
t4
40
t5
t6
t74
t84
t9
0.4 tSCLK
0.4 tSCLK
10
25
10
50
ns min
ns min
ns min
ns max
ns min
ns max
SCLK Low Pulsewidth
SCLK High Pulsewidth
SCLK to Data Valid Hold Time
CS Rising Edge to DOUTA, DOUTB, High Impedance
SCLK Falling Edge to DOUTA, DOUTB, High Impedance
SCLK Falling Edge to DOUTA, DOUTB, High Impedance
NOTES
1Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
2Mark/Space ratio for the CLK input is 40/60 to 60/40.
3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4t8, t9 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times t8 and t9 quoted in the timing characteristics are the true bus
relinquish times of the part and are independent of the bus loading.
Specifications subject to change without notice.
200A
I
OL
TO
OUTPUT
PIN
1.6V
C
L
50pF
200A
I
OH
Figure 1. Load Circuit for Digital Output
Timing Specifications
ABSOLUTE MAXIMUM RATINGS1
Storage Temperature Range . . . . . . . . . . . . –65oC to +150oC
(TA = 25oC unless otherwise noted)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VDRIVE to DGND . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V
VDRIVE to AGND . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Analog Input Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND . . . . . . . . . . . –0.3 V to +7 V
VREF to AGND . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
Digital Output Voltage to DGND . . –0.3 V to VDRIVE + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . . 10 mA
Operating Temperature Range
JA Thermal Impedance . . . . . . . . . . . . 143°C/W (TSSOP)
JC Thermal Impedance . . . . . . . . . . . . . 45°C/W (TSSOP)
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 kV
NOTES
1 Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Commercial (A, B Versions) . . . . . . . . . . . . . –40oC to +85oC
2 Transient currents of up to 100 mA will not cause SCR latch up.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7866 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. 0
AD7866
ORDERING GUIDE
Resolution
(Bits)
Package
Option
Model
Temperature Range
Package Description
AD7866ARU
–40°C to +85°C
–40°C to +85°C
Evaluation Board
12
12
Thin Shrink SO (TSSOP)
Thin Shrink SO (TSSOP)
(TSSOP)
RU-20
RU-20
AD7866BRU
EVAL-AD7866CB1
EVAL-CONTROL BRD22 Controller Board
NOTES
1This can be used as a stand-alone evaluation board or in conjunction with the evaluation board controller for evaluation/demonstration purposes.
2This evaluation board controller is a complete unit, allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
PIN CONFIGURATION
1
2
20
19
18
17
16
15
14
13
12
11
A0
REF SELECT
D
B
CS
CAP
3
SCLK
AGND
4
V
V
DRIVE
B2
V
5
B1
D
B
A
AD7866
TOP VIEW
(Not to Scale)
OUT
V
6
D
A2
OUT
V
7
DGND
A1
8
AGND
DV
AV
DD
DD
9
D
A
CAP
V
10
RANGE
REF
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1
REF SELECT
Internal/External Reference Selection Pin. Logic Input. If this pin is tied to GND, the on-chip
2.5 V reference is used as the reference source for both ADC A and ADC B. In addition, pins VREF
,
D
CAPA, and DCAPB must be tied to decoupling capacitors. If the REF SELECT pin is tied to a
logic high, an external reference can be supplied to the AD7866 through the VREF pin, in which
case decoupling capacitors are required on DCAPA and DCAPB. However, if the VREF pin is tied to
AGND while REF SELECT is tied to a logic low, an individual external reference can be applied
to both ADC A and ADC B through pins DCAPA and DCAPB, respectively. See Reference section.
2, 9
3, 8
D
CAPB, DCAP
A
Decoupling capacitors are connected to these pins to decouple the reference buffer for each respective
ADC. The on-chip reference can be taken from these pins and applied externally to the rest of a
system. Depending on the polarity of the REF SELECT pin and the configuration of the VREF pin,
these pins can also be used to input a separate external reference to each ADC. The range of the
external reference is dependent on the analog input range selected. See Reference section.
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7866. All analog input
signals and any external reference signal should be referred to this AGND voltage. Both of these
pins should connect to the AGND plane of a system. The AGND and DGND voltages should
ideally be at the same potential and must not be more than 0.3 V apart even on a transient basis.
4, 5
6, 7
10
V
V
B2, VB1
A2, VA1
Analog Inputs of ADC B. Single-ended analog input channels. The input range on each channel is 0 V
to VREF or a 2 × VREF range depending on the polarity of the RANGE pin upon the falling edge of CS.
Analog Inputs of ADC A. Single-ended analog input channels. The input range on each channel is 0 V
to VREF or a 2 × VREF range depending on the polarity of the RANGE pin upon the falling edge of CS.
VREF
Reference Decoupling Pin and External Reference Selection Pin. This pin is connected to the inter-
nal reference and requires a decoupling capacitor. The nominal reference voltage is 2.5 V and this
appears at the pin; however, if the internal reference is to be used externally in a system, it must be
taken from either the DCAPA or DCAPB pins. This pin is also used in conjunction with the REF SELECT
pin when applying an external reference to the AD7866. See REF SELECT pin description.
REV. 0
–5–
AD7866
PIN FUNCTION DESCRIPTIONS (continued)
Function
Pin No.
Mnemonic
11
RANGE
Analog Input Range and Output Coding Selection Pin. Logic Input. The polarity on this pin will
determine what input range the analog input channels on the AD7866 will have, and it will also
select what type of output coding the ADC will use for the conversion result. On the falling edge of
CS, the polarity of this pin is checked to determine the analog input range of the next conversion. If
this pin is tied to a logic low, the analog input range is 0 V to VREF and the output coding from the
part will be straight binary (for the next conversion). If this pin is tied to a logic high when CS goes
low, the analog input range is 2 × VREF and the output coding for the part will be two’s complement.
However, if after the falling edge of CS the logic level of the RANGE pin has changed upon the eighth
SCLK falling edge, the output coding will change to the other option without any change in the
analog input range. (See Analog Input and ADC Transfer Function sections.)
12
AVDD
Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on
the AD7866. The AVDD and DVDD voltages should ideally be at the same potential and must not
be more than 0.3 V apart even on a transient basis. This supply should be decoupled to AGND.
13
DVDD
DGND
Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the
AD7866. The DVDD and AVDD voltages should ideally be at the same potential and must not be
more than 0.3 V apart even on a transient basis. This supply should be decoupled to DGND.
14
Digital Ground. This is the ground reference point for all digital circuitry on the AD7866. The
DGND and AGND voltages should ideally be at the same potential and must not be more than
0.3 V apart even on a transient basis.
15, 16
D
OUTA, DOUT
B
Serial Data Outputs. The data output is supplied to this pin as a serial data stream. The bits are
clocked out on the falling edge of the SCLK input. The data appears on both pins simultaneously
from the simultaneous conversions of both ADCs. The data stream consists of one leading zero
followed by three STATUS bits, followed by the 12 bits of conversion data. The data is provided
MSB first. If CS is held low for a further 16 SCLK cycles after the conversion data has been output
on either DOUTA or DOUTB, the data from the other ADC follows on the DOUT pin. This allows
data from a simultaneous conversion on both ADCs to be gathered in serial format on either DOUTA
or DOUTB alone using only one serial port. See Serial Interface section.
17
18
19
20
VDRIVE
SCLK
CS
Logic Power Supply Input. The voltage supplied at this pin determines what voltage the interface
will operate at. This pin should be decoupled to DGND.
Serial Clock. Logic Input. A serial clock input provides the SCLK for accessing the data from the
AD7866. This clock is also used as the clock source for the conversion process.
Chip Select. Active low logic input. This input provides the dual function of initiating conversions
on the AD7866 and also frames the serial data transfer.
A0
Multiplexer Select. Logic Input. This input is used to select the pair of channels to be converted
simultaneously, i.e. Channel 1 of both ADC A and ADC B, or Channel 2 of both ADC A and
ADC B. The logic state of this pin is checked upon the falling edge of CS and the multiplexer is set
up for the next conversion. If it is low, the following conversion will be performed on Channel 1 of
each ADC; if it is high, the following conversion will be performed on Channel 2 of each ADC.
–6–
REV. 0
AD7866
TERMINOLOGY
Integral Nonlinearity
up to half the sampling frequency (fS/2), excluding dc. The ratio
is dependent on the number of quantization levels in the digiti-
zation process; the more levels, the smaller the quantization
noise. The theoretical signal to (noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by:
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB
above the last code transition.
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7866, it is defined as:
Offset Error
This applies when using Straight Binary output coding. It is the
deviation of the first code transition (00 . . . 000) to (00 . . . 001)
from the ideal, i.e., AGND + 1 LSB.
2
V22 +V32 +V4 +V52 +V62
THD (dB) = 20 log
V
1
Offset Error Match
This is the difference in Offset Error between the two channels.
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Gain Error
This applies when using Straight Binary output coding. It is the
deviation of the last code transition (111 . . . 110) to (111 . . . 111)
from the ideal (i.e., VREF – 1 LSB) after the offset error has been
adjusted out.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for ADCs
where the harmonics are buried in the noise floor, it will be a
noise peak.
Gain Error Match
This is the difference in Gain Error between the two channels.
Zero Code Error
This applies when using the two’s complement output coding option,
in particular with the 2 × VREF input range as –VREF to +VREF biased
about the VREF point. It is the deviation of the midscale transition
(all 1s to all 0s) from the ideal VIN voltage, i.e., VREF – 1 LSB.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and fb,
any active device with nonlinearities will create distortion products
at sum and difference frequencies of mfa nfb where m, n = 0,
1, 2, 3, etc. Intermodulation distortion terms are those for which
neither m nor n are equal to zero. For example, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb).
Zero Code Error Match
This is the difference in Zero Code Error between the two
channels.
Positive Gain Error
This applies when using the two’s complement output coding
option, in particular with the 2 × VREF input range as –VREF to
+VREF biased about the VREF point. It is the deviation of the
last code transition (011 . . . 110) to (011 . . . 111) from the
ideal (i.e., +VREF – 1 LSB) after the Zero Code Error has
been adjusted out.
The AD7866 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used. In
this case, the second order terms are usually distanced in frequency
from the original sine waves while the third order terms are usually at
a frequency close to the input frequencies. As a result, the second
and third order terms are specified separately. The calculation of
the intermodulation distortion is as per the THD specification
where it is the ratio of the rms sum of the individual distortion
products to the rms amplitude of the sum of the fundamentals
expressed in dB.
Negative Gain Error
This applies when using the two’s complement output coding
option, in particular with the 2 × VREF input range as –VREF to
+VREF biased about the VREF point. It is the deviation of the first
code transition (100 . . . 000) to (100 . . . 001) from the ideal
(i.e., –VREF + 1 LSB) after the Zero Code Error error has been
adjusted out.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of crosstalk
between channels. It is measured by applying a full-scale (2 × VREF),
455 kHz sine wave signal to all non selected input channels and
determining how much that signal is attenuated in the selected
channel with a 10 kHz signal (0 V to VREF). The figure given is
the worst-case across all four channels for the AD7866.
Track/Hold Acquisition Time
The track/hold amplifier returns into track mode after the end
of conversion. Track/Hold acquisition time is the time required
for the output of the track/hold amplifier to reach its final value,
within 1/2 LSB, after the end of conversion.
PSR (Power Supply Rejection)
Signal to (Noise + Distortion) Ratio
See Performance Curves section.
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental signals
REV. 0
–7–
AD7866
PERFORMANCE CURVES
Pf = Power at frequency f in ADC output, PfS = power at fre-
quency fS coupled onto the ADC AVDD supply. Here a 100 mV
peak-to-peak sine wave is coupled onto the AVDD supply while
the digital supply is left unaltered. TPCs 3a and 3b show the
PSRR of the AD7866 when there is no decoupling on the supply,
while TPCs 4a and 4b show the PSRR with decoupling capacitors
of 10 µF and 0.1 µF on the supply.
TPC 1 shows a typical FFT plot for the AD7866 at 1 MHz sample
rate and 300 kHz input frequency. TPC 2 shows the signal-to-
(noise + distortion) ratio performance versus input frequency for
various supply voltages while sampling at 1 MSPS with an SCLK
of 20 MHz.
TPC 3a through TPC 4b show the power supply rejection ratio
versus AVDD supply ripple frequency for the AD7866 under differ-
ent conditions. The power supply rejection ratio is defined as the
ratio of the power in the ADC output at full-scale frequency f,
to the power of a 100 mV sine wave applied to the ADC AVDD
supply of frequency fS:
TPC 5 and TPC 6 show typical DNL and INL plots for the AD7866.
TPC 7 shows a graph of the total harmonic distortion versus analog
input frequency for various source impedances.
TPC 8 shows a graph of total harmonic distortion versus analog
input frequency for various supply voltages. See Analog Input
section.
PSRR (dB) = 10 log (Pf/PfS)
Typical Performance Characteristics
0
0
4098 POINT FFT
100mV p-p SINEWAVE ON AV
DD
fSAMPLE = 1MSPS
fIN = 300kHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
2.5V EXT REFERENCE ON V
REF
–15
T
= 25؇C
A
SNR = 70.31dB
THD = –85.47dB
SFDR = –86.64dB
–35
–55
V
= 2.7V
DD
V
= 5.25V
DD
–75
–95
V
= 4.75V
DD
V
= 3.6V
DD
–115
0
50
100 150 200 250 300 350 400 450 500
FREQUENCY – kHz
1k
10k
100k
1M
AV RIPPLE FREQUENCY – Hz
DD
TPC 3a. PSRR vs. Supply Ripple Frequency,
without Supply Decoupling
TPC 1. Dynamic Performance
0
–61
–63
–65
–67
–69
–71
–73
–75
T
= 25 C
100mV p-p SINEWAVE ON AV
DD
A
–10 2.5V EXT REFERENCE ON D
A, D
B
CAP
CAP
T
= 25؇C
A
–20
–30
–40
V
= V
= 2.7V
DRIVE
DD
V
= V
= 3.6V
DD
DRIVE
–50
–60
V
= 5.25V
DD
V
= 2.7V
DD
–70
–80
V
= V
= 5.25V
DRIVE
DD
V
= V
= 4.75V
DD
DRIVE
–90
V
= 4.75V
V
= 3.6V
DD
DD
–100
10k
100k
INPUT FREQUENCY – Hz
1000k
1k
10k
100k
1M
AV RIPPLE FREQUENCY – Hz
DD
TPC 2. SINAD vs. Input Frequency
TPC 3b. PSRR vs. Supply Ripple Frequency,
without Supply Decoupling
–8–
REV. 0
AD7866
0
1.0
0.8
100mV p-p SINEWAVE ON AV
DD
–10
2.5V EXT REFERENCE ON V
REF
T
= 25؇C
A
–20
–30
–40
–50
–60
–70
–80
–90
0.6
0.4
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
V
= 2.7V
DD
V
= 3.6V
DD
–100
0
500
1000 1500 2000 2500 3000 3500 4000
1k
10k
100k
1M
ADC – Code
AV RIPPLE FREQUENCY – Hz
DD
TPC 4a. PSRR vs. Supply Ripple Frequency,
with Supply Decoupling
TPC 6. DC INL Plot
0
–60
–65
–70
–75
–80
–85
–90
100mV p-p SINEWAVE ON AV
DD
R
= 100⍀
T
V
= 25؇C
IN
A
–10
–20
–30
–40
–50
–60
–70
–80
–90
2.5V EXT REFERENCE ON D
A, D
B
= 4.75V
CAP
CAP
DD
T
= 25؇C
A
R
= 50⍀
IN
R
= 10⍀
IN
V
= 2.7V
DD
V
= 3.6V
10k
DD
V
= 4.75V
DD
–100
1k
100k
1M
10k
100k
1000k
AV RIPPLE FREQUENCY – Hz
INPUT FREQUENCY – Hz
DD
TPC 4b. PSRR vs. Supply Ripple Frequency,
with Supply Decoupling
TPC 7. THD vs. Analog Input Frequency
for Various Source Impedances
1.0
0.8
0.6
–70
V
= V
= 2.7V
DRIVE
DD
T
= 25؇C
A
–72
–74
–76
–78
–80
–82
–84
–86
–88
–90
V
= V
= 3.6V
DRIVE
DD
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
V
= V
= 5.25V
DRIVE
DD
V
= V
= 4.75V
DRIVE
DD
0
500
1000 1500 2000 2500 3000 3500 4000
10k
100k
1000k
ADC – Code
INPUT FREQUENCY – Hz
TPC 5. DC DNL Plot
TPC 8. THD vs. Analog Input Frequency
for Various Supply Voltages
REV. 0
–9–
AD7866
CIRCUIT INFORMATION
CAPACITIVE
DAC
The AD7866 is a fast, micropower, dual 12-bit, single supply,
A/D converter that operates from a 2.7 V to 5.25 V supply.
When operated from either a 5 V supply or a 3 V supply, the
AD7866 is capable of throughput rates of 1 MSPS when provided
with a 20 MHz clock.
A
V
IN
CONTROL
LOGIC
SW1
B
SW2
COMPARATOR
The AD7866 contains two on-chip track/hold amplifiers, two
successive-approximation A/D converters, and a serial interface
with two separate data output pins, housed in a 20-lead TSSOP
package, which offers the user considerable space-saving advantages
over alternative solutions. The serial clock input accesses data
from the part but also provides the clock source for each
successive-approximation A/D converter. The analog input range for
the part can be selected to be a 0 V to VREF input or a 2 × VREF input
with either straight binary or two’s complement output coding.
The AD7866 has an on-chip 2.5 V reference which can be over-
driven if an external reference is preferred. In addition, each ADC
can be supplied with an individual separate external reference.
AGND
Figure 3. ADC Conversion Phase
ANALOG INPUT
Figure 4 shows an equivalent circuit of the analog input structure
of the AD7866. The two diodes D1 and D2 provide ESD pro-
tection for the analog inputs. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 300 mV. This will cause these diodes to become forward-
biased and start conducting current into the substrate. 10 mA
is the maximum current these diodes can conduct without causing
irreversible damage to the part. The capacitor C1 in Figure 4
is typically about 10 pF and can primarily be attributed to pin
capacitance. The resistor R1 is a lumped component made up
of the on resistance of a switch. This resistor is typically about
100 Ω. The capacitor C2 is the ADC sampling capacitor and
has a capacitance of 20 pF typically. For ac applications, remov-
ing high-frequency components from the analog input signal is
recommended by use of an RC low-pass filter on the relevant
analog input pin. In applications where harmonic distortion and
signal-to-noise ratio are critical, the analog input should be driven
from a low impedance source. Large source impedances will
significantly affect the ac performance of the ADC. This may
necessitate the use of an input buffer amplifier. The choice of
the op amp will be a function of the particular application.
The AD7866 also features power-down options to allow power
saving between conversions. The power-down feature is imple-
mented across the standard serial interface as described in the
Modes of Operation section.
CONVERTER OPERATION
The AD7866 has two successive-approximation analog-to-digital
converters, each based around a capacitive DAC. Figures 2 and 3
show simplified schematics of one of these ADCs. The ADC is
comprised of control logic, a SAR, and a capacitive DAC, all of
which are used to add and subtract fixed amounts of charge from
the sampling capacitor to bring the comparator back into a bal-
anced condition. Figure 2 shows the ADC during its acquisition
phase. SW2 is closed and SW1 is in position A, the comparator is
held in a balanced condition and the sampling capacitor acquires
the signal on VA1 for example.
V
DD
D1
C2
CAPACITIVE
DAC
R1
V
IN
C1
D2
A
V
IN
CONTROL
LOGIC
SW1
B
SW2
CONVERT PHASE – SWITCH OPEN
TRACK PHASE – SWITCH CLOSED
COMPARATOR
AGND
Figure 4. Equivalent Analog Input Circuit
When no amplifier is used to drive the analog input the source
impedance should be limited to low values. The maximum
source impedance will depend on the amount of total harmonic
distortion (THD) that can be tolerated. The THD will increase
as the source impedance increases and performance will degrade
(see TPC 7).
Figure 2. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 3), SW2 will
open and SW1 will move to position B causing the comparator
to become unbalanced. The Control Logic and the capacitive
DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator back
into a balanced condition. When the comparator is rebalanced
the conversion is complete. The Control Logic generates the ADC
output code. Figures 10 and 11 show the ADC transfer functions.
Analog Input Ranges
The analog input range for the AD7866 can be selected to be 0 V
to VREF or 2 × VREF with either straight binary or two’s comple-
ment output coding. The RANGE pin is used to select both the
analog input range and the output coding, as shown in Figures 5
through 8. On the falling edge of CS, point A, the logic level of
the RANGE pin is checked to determine the analog input range
of the next conversion. If this pin is tied to a logic low then the
–10–
REV. 0
AD7866
analog input range will be 0 V to VREF and the output coding
from the part will be straight binary (for the next conversion). If this
pin is at a logic high when CS goes low, then the analog input
range will be 2 × VREF and the output coding for the part will
be two’s complement. However, if after the falling edge of CS,
the logic level of the RANGE pin has changed upon the eighth
falling SCLK edge, point B, the output coding will change to the
other option without any change in the analog input range. So for
the next conversion, two’s complement output coding could be selected
with a 0 V to VREF input range, for example, if the RANGE pin
is low upon the falling edge of CS and high upon the eighth falling
SCLK edge, as shown in Figure 7. Figures 5 through 8 show
examples of timing diagrams when selecting a particular analog input
range with a particular output coding format. Table I also summarizes
the required logic level of the RANGE pin for each selection.
The Logic Input A0 is used to select the pair of channels to be
converted simultaneously. The Logic state of this pin is also
checked upon the falling edge of CS and the multiplexers are set
up for the next conversion. If it is low, the following conversion
will be performed on Channel 1 of each ADC; if it is high,
the following conversion will be performed on Channel 2 of
each ADC.
Handling Bipolar Input Signals
Figure 9 shows how useful the combination of the 2 × VREF input
range and the two’s complement output coding scheme is for
handling bipolar input signals. If the bipolar input signal is biased
about VREF and two’s complement output coding is selected,
then VREF becomes the zero code point, –VREF is negative full-
scale and +VREF becomes positive full-scale, with a dynamic
range of 2 × VREF
.
Transfer Functions
The designed code transitions occur at successive integer LSB
values (i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = VREF/4096.
The ideal transfer characteristic for the AD7866 when straight
binary coding is selected is shown in Figure 10 and the ideal
transfer characteristic for the AD7866 when two’s complement
coding is selected is shown in Figure 11.
Table I. Analog Input and Output Coding Selection
Range Level
@ Point A1
Range Level
@ Point B2
Input Range3
Output Coding3
Low
High
Low
High
Low
High
High
Low
0 V to VREF
VREF VREF
Straight Binary
Two’s Complement
Two’s Complement
Straight Binary
VREF /2 VREF /2
0 V to 2 × VREF
NOTES
1Point A = Falling edge of CS.
2Point B = Eighth falling edge of SCLK.
3Selected for NEXT conversion.
A
B
CS
0V TO V
REF
INPUT RANGE
1
8
16
1
16
SCLK
RANGE
D
A
OUT
STRAIGHT BINARY
D
B
OUT
Figure 5. Selecting 0 V to VREF Input Range with Straight Binary Output Coding
A
B
CS
V
؎ V
REF
REF
INPUT RANGE
1
8
16
1
16
SCLK
RANGE
D
A
OUT
TWO’S COMPLEMENT
D
B
OUT
Figure 6. Selecting VREF VREF Input Range with Two’s Complement Output Coding
–11–
REV. 0
AD7866
A
B
CS
V
/2 ؎ V
/2
REF
REF
INPUT RANGE
1
8
16
1
16
SCLK
RANGE
D
A
OUT
TWO’S COMPLEMENT
D
B
OUT
Figure 7. Selecting VREF/2 VREF/2 Input Range with Two’s Complement Output Coding
A
B
CS
0V TO 2
؋
V REF
INPUT RANGE
1
8
16
1
16
SCLK
RANGE
D
A
OUT
STRAIGHT BINARY
D
B
OUT
Figure 8. Selecting 0 V to 2 × VREF Input Range with Straight Binary Output Coding
V
V
REF
DD
100nF
V
REF SELECT
DD
V
REF
D
A
CAP
V
R4
470nF
470nF
DRIVE
DSP/P
V
D
B
CAP
TWO'S
COMPLEMENT
AD7866
R3
R2
D
OUT
V
IN
0V
V
+V
REF
(= 2
؋
V )
011
000
111
000
REF
R1
V
REF
R1 = R2 = R3 = R4
(= 0V)
–V
REF
100
000
Figure 9. Handling Bipolar Signals with the AD7866
1LSB = 2
؋
V /4096 REF
011...111
011...110
111...111
111...110
000...001
000...000
111...111
111...000
011...111
1LSB = V /4096
REF
100...010
100...001
100...000
000...010
000...001
000...000
–V
+ 1LSB
+V
REF
– 1LSB
REF
V
REF
– 1LSB
1LSB
V
REF
– 1LSB
0V
ANALOG INPUT
ANALOG INPUT
Figure 10. Straight Binary Transfer Characteristic with 0 V
to VREF Input Range
Figure 11. Two’s Complement Transfer Characteristic
with VREF VREF Input Range
–12–
REV. 0
AD7866
Digital Inputs
D
A
CAP
The digital inputs applied to the AD7866 are not limited by the
maximum ratings which limit the analog inputs. Instead, the
digital inputs applied can go to 7 V and are not restricted by the
VDD + 0.3 V limit as on the analog inputs. See maximum ratings.
470nF
470nF
100nF
AD7866
D
B
CAP
V
REF
Another advantage of SCLK, RANGE, REF SELECT, A0,
and CS not being restricted by the VDD + 0.3 V limit is the fact
that power supply sequencing issues are avoided. If one of
these digital inputs is applied before VDD, there is no risk of
latch-up as there would be on the analog inputs if a signal greater
Figure 12. Relevant Connections When Using
Internal Reference
Figure 13 shows the connections required when an external
reference is applied to DCAPA and DCAPB. In this example the same
reference voltage is applied at each pin; however, a different volt-
age may be applied at each of these pins for each on-chip ADC.
An external reference applied at these pins may have a range from
2 V to 3 V but for specified performance it must be within 1%
of 2.5 V. Figure 14 shows the third option which is to overdrive the
internal reference through the VREF pin. This is possible due to the
series resistance from the VREF pin to the internal reference. This
external reference can have a range from 2 V to 3 V, but again to get
as close as possible to the specified performance a 2.5 V reference is
desirable. DCAPA and DCAPB decouple each on-chip reference buffer
as shown in Figure 15. If the on-chip 2.5 V reference is being used,
and is to be applied externally to the rest of the system, it may
than 0.3 V were applied prior to VDD
.
VDRIVE
The AD7866 also has the VDRIVE feature. VDRIVE controls the
voltage at which the serial interface operates. VDRIVE allows the
ADC to easily interface to both 3 V and 5 V processors. For
example, if the AD7866 was operated with a VDD of 5 V, the
V
DRIVE pin could be powered from a 3 V supply, allowing a large
dynamic range with low voltage digital processors. For example,
the AD7866 could be used with the 2 × VREF input range, with a
VDD of 5 V while still being able to interface to 3 V digital parts.
REFERENCE SECTION
The AD7866 has various reference configuration options. The
REF SELECT pin allows the choice of using an internal 2.5 V
reference or applying an external reference, or even an individual
external reference for each on-chip ADC if desired. If the REF
SELECT pin is tied to AGND then the on-chip 2.5 V reference
is used as the reference source for both ADC A and ADC B. In
addition, pins VREF, DCAPA, and DCAPB must be tied to decoupling
capacitors (100 nF, 470 nF, and 470 nF recommended, respec-
tively). If the REF SELECT pin is tied to a logic high, then an
external reference can be supplied to the AD7866 through the
VREF pin to overdrive the on-chip reference, in which case decoupling
capacitors are required on DCAPA and DCAPB again. However, if
the VREF pin is tied to AGND while REF SELECT is tied to a
logic low, then an individual external reference can be applied to
both ADC A and ADC B through pins DCAPA and DCAPB,
respectively. Table II summarizes these reference options.
D
A
CAP
V
REF
AD7866
D
B
CAP
REF SELECT
V
REF
Figure 13. Relevant Connections When Applying an
External Reference at DCAP A and/or DCAP
B
D
A
CAP
470nF
470nF
AD7866
V
D
B
DRIVE
CAP
For specified performance the last configuration was used, with
the same reference voltage applied to both DCAPA and DCAPB.
The connections for the relevant reference pins are shown in the
typical connection diagrams. If the internal reference is being
used, the VREF pin should have a 100 nF capacitor connected to
AGND very close to the VREF pin. These connections are shown
in Figure 12.
REF SELECT
V
V
REF
REF
Figure 14. Relevant Connections When Applying an
External Reference at VREF
Table II. Reference Selection
1
Reference Option
REF SELECT
VREF
DCAP A and DCAPB2
Internal
Externally through VREF
Externally through
Low
High
Decoupling Capacitor
External Reference
Decoupling Capacitor
Decoupling Capacitor
D
CAP A and/or DCAP
B
Low
AGND
External Reference A and/or
Reference B
NOTES
1Recommended value of decoupling capacitor = 100 nF.
2Recommended value of decoupling capacitor = 470 nF.
REV. 0
–13–
AD7866
to provide flexible power management options. These options
can be chosen to optimize the power dissipation/throughput
rate ratio for differing application requirements.
EXT REF
100nF
EXT REF
470nF
V
D
A
REF
CAP
Normal Mode
ADC A
ADC B
This mode is intended for fastest throughput rate performance as
the user does not have to worry about any power-up times with
the AD7866 remaining fully powered all the time. Figure 16 shows
the general diagram of the operation of the AD7866 in this mode.
2.5V
REF
BUF A
BUF B
The conversion is initiated on the falling edge of CS as described in
the Serial Interface section. To ensure the part remains fully pow-
ered up at all times CS must remain low until at least 10 SCLK
falling edges have elapsed after the falling edge of CS. If CS is
brought high any time after the 10th SCLK falling edge, but before
the 16th SCLK falling edge, the part will remain powered up but
the conversion will be terminated and DOUTA and DOUTB will go
back into three-state. Sixteen serial clock cycles are required to
complete the conversion and access the conversion result. The
DOUT line will not return to three-state after 16 SCLK cycles have
elapsed, but instead when CS is brought high again. If CS is left
low for a further 16 SCLK cycles then the result from the other
ADC on board will also be accessed on the same DOUT line as
shown in Figure 22 (see Serial Interface section). The STATUS
bits provided prior to each conversion result will identify which
ADC the following result will be from. Once 32 SCLK cycles
have elapsed, the DOUT line will return to three-state on the 32nd
SCLK falling edge. If CS is brought high prior to this, the DOUT line
will return to three-state at that point. Hence, CS may idle low after
32 SCLK cycles, until it is brought high again sometime prior to the
next conversion (effectively idling CS low), if so desired, as the bus
will still return to three-state upon completion of the dual result read.
D
B
CAP
470nF
EXT REF
Figure 15. Reference Circuit
be taken from either the VREF pin or one of the DCAPA or DCAP
B
pins. If it is taken from the VREF pin, it must be buffered before
being applied elsewhere as it will not be capable of sourcing more
than a few microamps. If the reference voltage is taken from
either the DCAPA pin or DCAPB pin, a buffer is not strictly neces-
sary. Either pin is capable of sourcing current in the region of
100 µA; however, the larger the source current requirement, the
greater the voltage drop seen at the pin. The output impedance of
each of these pins is typically 50 Ω. In addition, this point repre-
sents the actual voltage applied to the ADC internally so any
voltage drop due to the current load or disturbance due to a
dynamic load will directly affect the ADC conversion. For
this reason, if a large current source is necessary, or a dynamic
load is present, it is recommended to use a buffer on the output
to drive a device.
Examples of suitable external reference devices that may be
applied at pins VREF, DCAPA, or DCAPB are the AD780, REF192,
REF43, or AD1582.
Once a data transfer is complete and DOUTA and DOUTB have
returned to three-state, another conversion can be initiated after
the quiet time, tQUIET, has elapsed by bringing CS low again.
Partial Power-Down Mode
MODES OF OPERATION
This mode is intended for use in applications where slower
throughput rates are required. Either the ADC is powered down
between each conversion, or a series of conversions may be per-
formed at a high throughput rate and the ADC is then powered
down for a relatively long duration between these bursts of several
conversions. When the AD7866 is in Partial Power-Down, all
analog circuitry is powered down except for the on-chip reference
and reference buffer.
The mode of operation of the AD7866 is selected by controlling
the (logic) state of the CS signal during a conversion. There
are three possible modes of operation, Normal Mode, Partial
Power-Down Mode, and Full Power-Down Mode. The point at
which CS is pulled high after the conversion has been initiated
will determine which power-down mode, if any, the device will
enter. Similarly, if already in a power-down mode, CS can
control whether the device will return to normal operation or
remain in power-down. These modes of operation are designed
CS
1
10
16
SCLK
D
A
OUT
STATUS BITS AND CONVERSION RESULT
D
B
OUT
Figure 16. Normal Mode Operation
–14–
REV. 0
AD7866
To enter Partial Power-Down, the conversion process must be
interrupted by bringing CS high anywhere after the second falling
edge of SCLK and before the 10th falling edge of SCLK as shown
in Figure 17. Once CS has been brought high in this window of
SCLKs, the part will enter Partial Power-Down and the conver-
sion that was initiated by the falling edge of CS will be terminated
and DOUTA and DOUTB will go back into three-state. If CS is
brought high before the second SCLK falling edge, the part
will remain in normal mode and will not power down. This will
avoid accidental power-down due to glitches on the CS line.
in Full Power-Down, all analog circuitry is powered down. Full
Power-Down is entered in a similar way as Partial Power-Down,
except the timing sequence shown in Figure 17 must be executed
twice. The conversion process must be interrupted in a similar
fashion by bringing CS high anywhere after the second falling
edge of SCLK and before the 10th falling edge of SCLK. The device
will enter Partial Power Down at this point. To reach Full Power-
Down, the next conversion cycle must be interrupted in the
same way, as shown in Figure 19. Once CS has been brought high
in this window of SCLKs, the part will power down completely.
In order to exit this mode of operation and power the AD7866 up
again, a dummy conversion is performed. On the falling edge of CS
the device will begin to power up, and will continue to power up as
long as CS is held low until after the falling edge of the 10th SCLK.
In the case of an external reference, the device will be fully pow-
ered up once 16 SCLKs have elapsed and valid data will result
from the next conversion as shown in Figure 18. If CS is brought
high before the second falling edge of SCLK, the AD7866 will again
go into partial power-down. This avoids accidental power-up due
to glitches on the CS line; although the device may begin to power
up on the falling edge of CS, it will power down again on the rising
edge of CS. If the AD7866 is already in Partial Power-Down mode
and CS is brought high between the second and tenth falling edges
of SCLK, the device will enter Full Power-Down mode. For more
information on the power-up times associated with partial power-
down in various configurations, see the Power-Up Times section.
NOTE: It is not necessary to complete the 16 SCLKs once CS
has been brought high to enter a power-down mode.
To exit Full Power-Down, and power the AD7866 up again, a
dummy conversion is performed, as when powering up from
Partial Power-Down. On the falling edge of CS the device
will begin to power up, and will continue to power up as long as
CS is held low until after the falling edge of the 10th SCLK.
The power-up time required must elapse before a conversion
can be initiated as shown in Figure 20. See the Power-up Times
section for the power-up times associated with the AD7866.
POWER-UP TIMES
The AD7866 has two power-down modes, Partial Power-
Down and Full Power-Down, which are described in detail in
the Modes of Operation section. This section deals with the
power-up time required when coming out either of these
modes. It should be noted that the power-up times quoted
apply with the recommended capacitors on the VREF, DCAPA,
and DCAPB pins in place.
Full Power-Down Mode
This mode is intended for use in applications where slower
throughput rates are required than those in the Partial Power-
Down mode, as power-up from a Full Power-Down takes sub-
stantially longer than that from partial power-down. This mode is
more suited to applications where a series of conversions performed
at a relatively high throughput rate would be followed by a long
period of inactivity and hence power-down. When the AD7866 is
To power up from Full Power-Down approximately 4 ms should
be allowed from the falling edge of CS, shown in Figure 20 as
t
POWER UP. Powering up from Partial Power-Down requires
much less time. If the internal reference is being used, the power-up
CS
1
2
10
16
SCLK
THREE-STATE
D
A
OUT
D
B
OUT
Figure 17. Entering Partial Power-Down Mode
THE PART MAY BE FULLY
POWERED UP; SEE POWER-UP
TIMES SECTION
THE PART BEGINS
TO POWER UP
CS
10
16
1
16
1
SCLK
A
D
A
OUT
INVALID DATA
VALID DATA
D
B
OUT
Figure 18. Exiting Partial Power-Down Mode
–15–
REV. 0
AD7866
THE PART ENTERS
PARTIAL POWER-DOWN
THE PART BEGINS
TO POWER-UP
THE PART ENTERS
FULL POWER-DOWN
CS
10
10
1
2
16
1
16
2
SCLK
THREE-STATE
THREE-STATE
D
A
OUT
INVALID DATA
INVALID DATA
D
B
OUT
Figure 19. Entering Full Power-Down Mode
THE PART BEGINS
TO POWER UP
THE PART IS
FULLY POWERED UP
tPOWER UP
CS
10
16
1
16
1
SCLK
D
A
OUT
INVALID DATA
VALID DATA
D
B
OUT
Figure 20. Exiting Full Power-Down Mode
time is typically 4 µs; but if an external reference is being used, the
power-up time is typically 1 µs. This means that with any fre-
quency of SCLK up to 20 MHz, one dummy cycle will always be
sufficient to allow the device to power up from Partial Power-Down
(see Figure 18) when using an external reference. Once the dummy
cycle is complete, the ADC will be fully powered up and the input
signal will be acquired properly. A dummy cycle may well be suffi-
cient to power up the part when using an internal reference also,
provided the SCLK is slow enough to allow the required power-
up time to elapse before a valid conversion is requested. In addition
to this, it should be ensured that the quiet time, tQUIET, has still
been allowed from the point where the bus goes back into three-
state after the dummy conversion to the next falling edge of CS.
Alternatively, instead of slowing the SCLK to make the dummy
cycle long enough, the CS high time could just be extended to
include the required power-up time as in Figure 20 when power-
ing up from Full Power-Down.
mode. Because of this, it is best to allow a dummy cycle to elapse to
ensure the part is fully powered up before attempting a valid con-
version. Likewise, if it is intended to keep the part in the partial
power-down mode immediately after the supplies are applied,
two dummy cycles must be initiated. The first dummy cycle must
hold CS low until after the 10th SCLK falling edge (see Figure 16);
in the second cycle CS must be brought high before the 10th
SCLK edge but after the second SCLK falling edge (see Figure 17).
Alternatively, if it is intended to place the part in Full Power-
Down mode when the supplies have been applied, three dummy
cycles must be initiated. The first dummy cycle must hold CS low
until after the 10th SCLK falling edge (see Figure 16); the
second and third dummy cycles place the part in Full Power-
Down (see Figure 19). See the Modes of Operation section.
Once supplies are applied to the AD7866, enough time must be
allowed for any external reference to power up and charge any
reference capacitor to its final value, or enough time must be
allowed for the internal reference buffer to charge the various
reference buffer decoupling capacitors to their final values. Then,
to place the AD7866 in normal mode, a dummy cycle (1 µs to
4 µs approximately) should be initiated. If the first valid con-
version is then performed directly after the dummy conversion,
care must be taken to ensure that adequate acquisition time has
been allowed. As mentioned earlier, when powering up from the
power-down mode, the part will return to track upon the first
SCLK edge applied after the falling edge of CS. However, when
the ADC powers up initially after supplies are applied, the track-
and-hold will already be in track. This means that (assuming one
has the facility to monitor the ADC supply current) if the ADC
powers up in the desired mode of operation and thus a dummy
cycle is not required to change mode, then neither is a dummy
cycle required to place the track-and-hold into track. If no current
monitoring facility is available, the relevant dummy cycle(s)
should be performed to ensure the part is in the required mode.
The difference in the power-up time needed, when coming out
of Partial Power-Down, between the two cases where an internal
or external reference is being used, is primarily due to the on-chip
reference buffers. These power down in Partial Power-Down
mode and must be powered up again if the internal reference is
being used, but do not need to be powered up again if an exter-
nal reference is being used. The time needed to power these
buffers up is not just their own power-up time but also the time
required to charge up the decoupling capacitors present on the
pins VREF, DCAPA, and DCAPB.
It should also be noted that when powering up from Partial
Power-Down, the track-and-hold, which was in hold mode
while the part was powered down, returns to track mode after
the first SCLK edge the part receives after the falling edge of
CS. This is shown as point A in Figure 18.
When power supplies are first applied to the AD7866, the ADC
may power up in either of the power-down modes or the normal
–16–
REV. 0
AD7866
POWER VERSUS THROUGHPUT RATE
24 mW for 2 µs during each conversion cycle. For the remainder of
the conversion cycle, 8 µs, the part remains in Partial Power-Down
mode. The AD7866 can be said to dissipate 2.8 mW for the
remaining 8 µs of the conversion cycle. If the throughput rate is
100 kSPS, the cycle time is 10 µs and the average power dissipated
during each cycle is (2/10) ϫ (24 mW) + (8/10) ϫ (2.8 mW) =
7.04 mW. If VDD = 3 V, SCLK = 20 MHz and the device is again
in Partial Power-Down mode between conversions, the power
dissipated during normal operation is 8.4 mW. The AD7866 can
be said to dissipate 8.4 mW for 2 ms during each conversion
cycle and 1.68 mW for the remaining 8 ms where the part is
in Partial Power-Down. With a throughput rate of 100 kSPS,
the average power dissipated during each conversion cycle is
(2/10) ϫ (8.4 mW) + (8/10) ϫ (1.68 mW) = 3.02 mW. Figure 21
shows the power versus throughput rate when using the Partial
Power-Down mode between conversions with both 5 V and 3 V
supplies for the AD7866.
By using the Partial Power-Down mode on the AD7866 when not
converting, the average power consumption of the ADC decreases
at lower throughput rates. Figure 21 shows how as the throughput
rate is reduced, the part remains in its partial power-down state longer
and the average power consumption over time drops accordingly.
100
V
= 5V
DD
SCLK = 20MHz
10
1
V
= 3V
DD
SCLK = 20MHz
0.1
0.01
SERIAL INTERFACE
Figure 22 shows the detailed timing diagram for serial interfacing
to the AD7866. The serial clock provides the conversion clock
and also controls the transfer of information from the AD7866
during conversion.
0
50
100
150
200
250
300
350
THROUGHPUT – kSPS
Figure 21. Power vs. Throughput for Partial Power-Down
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode,
takes the bus out of three-state and the analog input is sampled at
this point. The conversion is also initiated at this point and will
require 16 SCLK cycles to complete. Once 13 SCLK falling edges
have elapsed, then the track and hold will go back into track on
the next SCLK rising edge as shown in Figure 22 at point B. On
For example, if the AD7866 is operated in a continuous sampling
mode with a throughput rate of 100 kSPS and an SCLK of 20 MHz
(VDD = 5 V), and the device is placed in Partial Power-Down mode
between conversions, then the power consumption is calculated
as follows. The maximum power dissipation during normal
operation is 24 mW (VDD = 5 V). If the power-up time allowed
from Partial Power-Down is one dummy cycle, i.e., 1 µs, (assumes
use of an external reference) and the remaining conversion time is
another cycle, i.e., 1 µs, then the AD7866 can be said to dissipate
the rising edge of CS, the conversion will be terminated and DOUT
and DOUTB will go back into three-state. If CS is not brought
high, but instead held low for a further 16 SCLK cycles on
A
CS
t6
t2
B
1
2
3
4
5
13
14
t5
15
16
SCLK
t7
t8
t4
t3
tQUIET
D
A
OUT
0
RANGE
A0
A/B
DB11
DB10
DB2
DB1
DB0
THREE-
STATE
THREE-
STATE
D
B
OUT
1 LEADING ZERO,
3 STATUS BITS
Figure 22. Serial Interface Timing Diagram
CS
t6
t2
32
1
2
3
4
17
5
14
15
16
SCLK
t5
t9
t7
t3
t4
D
A
OUT
0
RANGE
A0/A0
ZERO
DB11A
DB1A
DB0A
ZERO
RANGE
A0/A0
ONE
DB11B
DB1B
DB0B
THREE-
STATE
THREE-
STATE
1 LEADING ZERO,
3 STATUS BITS
1 LEADING ZERO,
3 STATUS BITS
Figure 23. Reading Data from Both ADCs on One DOUT Line
–17–
REV. 0
AD7866
Table III. STATUS Bit Description
Bit
Bit Name
Comment
15
14
ZERO
RANGE
Leading Zero. This bit will always be a zero output.
The polarity of this bit reflects the analog input range that has been selected with the RANGE
pin. If it is a 0, it means that in the previous transfer upon the falling edge of the CS, the range pin was
at a logic low providing an analog input range from 0 V to VREF for this conversion. If it is a 1,
it means that in the previous transfer upon the falling edge of CS, the RANGE pin was at a logic high
resulting in an analog input range of 2 × VREF selected for this conversion. See Analog Input section.
13
12
A0
This bit indicates on which channel the conversion is being performed, Channel 1 or Channel 2 of the
ADC in question. If this bit is a 0, the conversion result will be from Channel 1 of the ADC, and
if it is a 1, the result will be from Channel 2 of the ADC in question.
This bit indicates which ADC the conversion result is from. If this bit is a 0, the result is from ADC A;
and if it is a 1, the result is from ADC B. This is especially useful if only one serial port is available
for use and one DOUT line is used, as shown in Figure 23.
A/B
DOUTA, the data from conversion B will be output on DOUTA.
Likewise, if CS is held low for a further 16 SCLK cycles on DOUTB,
the data from conversion A will be output on DOUTB. This is illus-
trated in Figure 23 where the case for DOUTA is shown. Note that
in this case the DOUT line in use will go back into three-state on
the 32nd SCLK rising edge or the rising edge of CS, whichever
occurs first.
The SPORT0 control register should be set up as follows:
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
SLEN = 1111, 16-Bit Data Words
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0
Sixteen serial clock cycles are required to perform the conversion
process and to access data from one conversion on either data
line of the AD7866. CS going low provides the leading zero to
be read in by the microcontroller or DSP. The remaining data is
then clocked out by subsequent SCLK falling edges, beginning
with the first of three data STATUS bits, thus the first falling clock
edge on the serial clock has the leading zero provided and also
clocks out the first of three STATUS bits. The final bit in the
data transfer is valid on the 16th falling edge, having being clocked
out on the previous (15th) falling edge. In applications with a
slower SCLK, it is possible to read in data on each SCLK rising
edge, i.e., the first rising edge of SCLK after the CS falling edge
would have the leading zero provided and the 15th rising SCLK
edge would have DB0 provided.The three STATUS bits that
follow the leading zero provide information with respect to
the conversion result that follows them on the DOUT line in use.
Table III shows how these identification bits can be interpreted.
ITFS = 1
The SPORT1 control register should be set up as follows:
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
SLEN = 1111, 16-Bit Data Words
ISCLK = 0, External Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0
ITFS = 1
To implement the power-down modes on the AD7866 SLEN
should be set to 1001 to issue an 8-bit SCLK burst. The con-
nection diagram is shown in Figure 24. The ADSP-218x has the
TFS0 and RFS0 of the SPORT0 and the RFS1 of SPORT1 tied
together, with TFS0 set as an output and both RFS0 and RFS1
set as inputs. The DSP operates in Alternate Framing Mode
and the SPORT control register is set up as described. The Frame
synchronization signal generated on the TFS is tied to CS and
as with all signal processing applications equidistant sampling is
necessary. However, in this example, the timer interrupt is used
to control the sampling rate of the ADC and under certain con-
ditions, equidistant sampling may not be achieved.
MICROPROCESSOR INTERFACING
The serial interface on the AD7866 allows the parts to be directly
connected to a range of many different microprocessors. This
section explains how to interface the AD7866 with some of the
more common microcontroller and DSP serial interface protocols.
AD7866 to ADSP-218x
The ADSP-218x family of DSPs are directly interfaced to the
AD7866 without any glue logic required. The VDRIVE pin of the
AD7866 takes the same supply voltage as that of the ADSP-218x.
This allows the ADC to operate at a higher supply voltage than
the serial interface, i.e., ADSP-218x, if necessary. This example
shows both DOUT A and DOUT B of the AD7866 connected to
both serial ports of the ADSP-218x.
The Timer and other registers are loaded with a value that
will provide an interrupt at the required sample interval. When
an interrupt is received, a value is transmitted with TFS/DT
(ADC control word). The TFS is used to control the RFS and
hence the reading of data. The frequency of the serial clock is set
in the SCLKDIV register. When the instruction to transmit with
TFS is given, (i.e., AX0 = TX0), the state of the SCLK is checked.
The DSP will wait until the SCLK has gone High, Low, and
High before transmission will start. If the timer and SCLK values
are chosen such that the instruction to transmit occurs on or near
the rising edge of SCLK, the data may be transmitted or it may
wait until the next clock edge.
–18–
REV. 0
AD7866
For example, if the ADSP-2189 had a 20 MHz crystal, such that
it had a master clock frequency of 40 MHz then the master cycle
time would be 25 ns. If the SCLKDIV register is loaded with
the value 3, a SCLK of 5 MHz is obtained, and eight master
clock periods will elapse for every 1 SCLK period. Depending
on the throughput rate selected, if the timer register was loaded
with the value, say 803, (803 + 1 = 804) 100.5 SCLKs will occur
between interrupts and subsequently between transmit instructions.
This situation will result in non-equidistant sampling as the
transmit instruction is occurring on a SCLK edge. If the number
of SCLKs between interrupts is a whole integer figure of N,
equidistant sampling will be implemented by the DSP.
The connection diagram is shown in Figure 25. It should be
noted that for signal processing applications, it is imperative
that the frame synchronization signal from the TMS320C541
will provide equidistant sampling. The VDRIVE pin of the AD7866
takes the same supply voltage as that of the TMS320C541. This
allows the ADC to operate at a higher voltage than the serial
interface, i.e., TMS320C541, if necessary.
AD7866 to DSP-563xx
The connection diagram in Figure 26 shows how the AD7866
can be connected to the ESSI (Synchronous Serial Interface) of the
DSP-563xx family of DSPs from Motorola. Each ESSI (two on-board)
is operated in Synchronous Mode (Bit SYN = 1 in CRB register)
with internally generated word length frame sync for both Tx and
Rx (bits FSL1 = 0 and FSL0 = 0 in CRB). Normal operation
of the ESSI is selected by making MOD = 0 in the CRB. Set the
word length to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA.
To implement the power-down modes on the AD7866 the
word length can be changed to eight bits by setting bits WL1 = 0
and WL0 = 0 in CRA. The FSP Bit in the CRB should be set to 1
so the frame sync is negative. It should be noted that for signal pro-
cessing applications, it is imperative that the frame synchronization
signal from the DSP-563xx will provide equidistant sampling.
ADSP-21xx*
AD7866*
SCLK
SCLK0
SCLK1
TFS0
CS
RFS0
RSF1
DR0
D
A
OUT
D
B
DR1
OUT
V
DRIVE
In the example shown in Figure 26, the serial clock is taken from
the ESSI0 so the SCK0 pin must be set as an output, SCKD = 1,
while the SCK1 pin is set up as an input, SCKD = 0. The frame
sync signal is taken from SC02 on ESSI0, so SCD2 = 1, while
on ESSI1, SCD2 = 0 so SC12 is configured as an input. The
VDRIVE pin of the AD7866 takes the same supply voltage as that
of the DSP-563xx. This allows the ADC to operate at a higher
voltage than the serial interface, i.e., DSP-563xx, if necessary.
*ADDITIONAL PINS OMITTED
FOR CLARITY
V
DD
Figure 24. Interfacing the AD7866 to the ADSP-218x
AD7866*
TMS320C541*
CLKX0
CLKR0
CLKX1
CLKR1
DR0
SCLK
AD7866*
DSP-563xx*
SCK0
SCLK
SCK1
SRD0
SRD1
D
A
B
D
A
B
OUT
OUT
D
DR1
OUT
D
OUT
FSX0
FSR0
FSR1
CS
CS
SC02
SC12
V
DRIVE
V
DRIVE
*ADDITIONAL PINS OMITTED
FOR CLARITY
V
DD
*ADDITIONAL PINS OMITTED
FOR CLARITY
V
Figure 25. Interfacing the AD7866 to the TMS320C541
DD
AD7866 to TMS320C541
Figure 26. Interfacing to the DSP-563xx
APPLICATION HINTS
The serial interface on the TMS320C541 uses a continuous serial
clock and frame synchronization signals to synchronize the data
transfer operations with peripheral devices like the AD7866. The
CS input allows easy interfacing between the TMS320C541 and
the AD7866 without any glue logic required. The serial ports of
the TMS320C541 are set up to operate in burst mode with internal
CLKX (Tx serial clock on serial port 0) and FSX0 (Tx frame
sync from serial port 0). The serial port control registers (SPC)
must have the following setup:
Grounding and Layout
The analog and digital supplies to the AD7866 are independent
and separately pinned out to minimize coupling between the analog
and digital sections of the device. The AD7866 has very good
immunity to noise on the power supplies as can be seen by the
PSRR vs. Supply Ripple Frequency plots, TPC 3a – TPC 4b.
However, care should still be taken with regard to grounding
and layout.
SPC0: FO = 0, FSM = 1, MCM = 1 and TxM = 1
SPC1: FO = 0, FSM = 1, MCM = 0 and TxM = 0
The printed circuit board that houses the AD7866 should be de-
signed such that the analog and digital sections are separated and
confined to certain areas of the board. This facilitates the use of
ground planes that can be easily separated. A minimum etch
technique is generally best for ground planes as it gives the best
The format bit, FO, may be set to 1 to set the word length to 8 bits,
in order to implement the power-down modes on the AD7866.
REV. 0
–19–
AD7866
shielding. Both AGND pins of the AD7866 should be sunk in the
AGND plane. Digital and analog ground planes should be joined
at only one place. If the AD7866 is in a system where multiple
devices require an AGND-to-DGND connection, the connection
should still be made at one point only, a star ground point that
should be established as close as possible to the AD7866.
Inductance (ESI), such as common ceramic or surface mount types,
which provide a low impedance path to ground at high frequen-
cies to handle transient currents due to internal logic switching.
Figure 27 shows the recommended supply decoupling scheme.
For information on the decoupling requirements of each reference
configuration, see the Reference section.
Avoid running digital lines under the device as these will couple
noise onto the die. The analog ground plane should be allowed
to run under the AD7866 to avoid noise coupling. The power
supply lines to the AD7866 should use as large a trace as pos-
sible to provide low impedance paths and reduce the effects of
glitches on the power supply line. Fast switching signals like
clocks should be shielded with digital ground to avoid radiating
noise to other sections of the board, and clock signals should
never be run near the analog inputs. Avoid crossover of digital
and analog signals. Traces on opposite sides of the board should
run at right angles to each other. This will reduce the effects of
feedthrough through the board. A microstrip technique is by far
the best but is not always possible with a double-sided board. In
this technique, the component side of the board is dedicated to
ground planes while signals are placed on the solder side.
AV
DV
DD
DD
10F
0.1F
0.1F
0.1F
10F
DGND
AGND
AGND
V
DRIVE
AD7866
Figure 27. Recommended Supply Decoupling Scheme
Evaluating the AD7866 Performance
The recommended layout for the AD7866 is outlined in the evalu-
ation board for the AD7866. The evaluation board package includes
a fully assembled and tested evaluation board, documentation, and
software for controlling the board from the PC via the EVAL-
BOARD CONTROLLER. The EVAL-BOARD CONTROLLER
can be used in conjunction with the AD7866 Evaluation board, as
well as many other Analog Devices evaluation boards ending in the
CB designator, to demonstrate/evaluate the ac and dc performance
of the AD7866.
Good decoupling is also important. All analog supplies should be
decoupled with 10 µF tantalum in parallel with 0.1 µF capacitors
to AGND. All digital supplies should have at least a 0.1 µF disc
ceramic capacitor to DGND. VDRIVE should have a 0.1 µF ceramic
capacitor to DGND. To achieve the best from these decoupling
components, they must be placed as close as possible to the device,
ideally right up against the device. The 0.1 µF capacitors should
have low Effective Series Resistance (ESR) and Effective Series
The software allows the user to perform ac (fast Fourier transform)
and dc (histogram of codes) tests on the AD7866.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead Thin Shrink Small Outline Package
(RU-20)
0.260 (6.60)
0.252 (6.40)
20
11
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
10
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0433 (1.10)
MAX
8؇
0؇
0.0256 (0.65) 0.0118 (0.30)
0.028 (0.70)
0.020 (0.50)
0.0079 (0.20)
0.0035 (0.090)
SEATING
PLANE
BSC
0.0075 (0.19)
–20–
REV. 0
相关型号：
©2020 ICPDF网 联系我们和版权申明