EVAL-AD7843CB [ADI]
Touch Screen Digitizer; 摸屏
| 型号： | EVAL-AD7843CB |
| 厂家： | 
ADI |
| 描述： | Touch Screen Digitizer |
| 文件： | 总16页 (文件大小：191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
Touch Screen Digitizer
AD7843
FEATURES
FUNCTIONAL BLOCK DIAGRAM
4-Wire Touch Screen Interface
Specified Throughput Rate of 125 kSPS
Low Power Consumption:
+V
CC
PENIRQ
1.37 mW Max at 125 kSPS with VCC = 3.6 V
Single Supply, VCC of 2.2 V to 5.25 V
Ratiometric Conversion
PEN
INTERRUPT
AD7843
X+
X–
High-Speed Serial Interface
Programmable 8- or 12-Bit Resolution
Two Auxiliary Analog Inputs
Y+
Y–
T/H
4-TO-1
Shutdown Mode: 1
A max
I/P
16-Lead QSOP and TSSOP Packages
MUX
IN3
IN4
COMP
APPLICATIONS
Personal Digital Assistants
Smart Hand-Held Devices
Touch Screen Monitors
Point-of-Sales Terminals
Pagers
V
GND
REF
CHARGE
REDISTRIBUTION
DAC
+V
CC
SAR + ADC
CONTROL LOGIC
SPORT
DOUT
GENERAL DESCRIPTION
The AD7843 is a 12-bit successive-approximation ADC with a
synchronous serial interface and low on resistance switches for
driving touch screens. The part operates from a single 2.2 V to
5.25 V power supply and features throughput rates greater than
125 kSPS.
DIN
CS
DCLK
BUSY
PRODUCT HIGHLIGHTS
1. Ratiometric conversion mode available eliminating errors
due to on-board switch resistances.
The external reference applied to the AD7843 can be varied
from 1 V to +VCC, while the analog input range is from 0 V to
2. Maximum current consumption of 380 µA while operating at
V
REF. The device includes a shutdown mode that reduces the
125 kSPS.
current consumption to less than 1 µA.
3. Power-down options available.
The AD7843 features on-board switches. This coupled with low
power and high-speed operation make this device ideal for
battery-powered systems such as personal digital assistants with
resistive touch screens and other portable equipment. The part
is available in a 16-lead 0.15" Quarter Size Outline (QSOP) pack-
age and a 16-lead Thin Shrink Small Outline (TSSOP) package.
4. Analog input range from 0 V to VREF
.
5. Versatile serial I/O port.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
REF = 2.5 V, fSCLK = 2 MHz unless otherwise noted; TA =
–40؇C to +85؇C, unless otherwise noted.)
AD7843–SPECIFICATIONS (V = 2.7 V to 3.6 V, V
CC
Parameter
AD7843A1
Unit
Test Conditions/Comments
DC ACCURACY
Resolution
12
11
2
Bits
No Missing Codes
Integral Nonlinearity2
Offset Error2
Bits min
LSB max
LSB max
LSB max
LSB typ
LSB max
LSB max
LSB typ
dB typ
6
VCC = 2.7 V
Offset Error Match3
1
0.1
4
1
0.1
70
Gain Error2
Gain Error Match3
Power Supply Rejection
SWITCH DRIVERS
On-Resistance2
Y+, X+
5
6
Ω typ
Ω typ
Y–, X–
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
0 to VREF
0.1
37
Volts
µA typ
pF typ
REFERENCE INPUT
V
REF Input Voltage Range
1.0/+VCC
1
5
20
1
1
V min/max
µA max
GΩ typ
µA max
µA typ
DC Leakage Current
V
REF Input Impedance
CS = GND or +VCC
8 µA typ
VREF Input Current3
f
SAMPLE = 12.5 kHz
µA max
CS = +VCC; 0.001 µA typ
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.4
1
V min
V max
µA max
pF max
Typically 10 nA, VIN = 0 V or +VCC
4
Input Capacitance, CIN
10
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
PENIRQ Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance4
Output Coding
VCC – 0.2
0.4
0.4
10
10
V min
ISOURCE = 250 µA; VCC = 2.2 V to 5.25 V
ISINK = 250 µA
ISINK = 250 µA; 100 kΩ Pull-Up
V max
V max
µA max
pF max
Straight (Natural) Binary
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
Throughput Rate
12
3
125
DCLK Cycles max
DCLK Cycles min
kSPS max
POWER REQUIREMENTS
VCC5 (Specified Performance)
ICC
2.7/3.6
V min/max
Functional from 2.2 V to 5.25 V
Digital I/Ps = 0 V or VCC
VCC = 3.6 V, 240 µA typ
VCC = 2.7 V, fDCLK = 2 00 kHz
Normal Mode (fSAMPLE = 125 kSPS)
Normal Mode (fSAMPLE = 12.5 kSPS)
Normal Mode (Static)
380
170
150
1
µA max
µA typ
µA typ
µA max
VCC = 3.6 V
Shutdown Mode (Static)
Power Dissipation5
Normal Mode (fSAMPLE = 125 kSPS)
Shutdown
1.368
3.6
mW max
µW max
VCC = 3.6 V
VCC = 3.6 V
NOTES
1Temperature range as follows: A Version: –40°C to +85°C.
2See Terminology.
3Guaranteed by design.
4Sample tested @ 25°C to ensure compliance.
5See Power vs. Throughput Rate section.
Specifications subject to change without notice.
–2–
REV. 0
AD7843
TIMING SPECIFICATIONS1
(TA = TMIN to TMAX, unless otherwise noted; VCC = 2.7 V to 3.6 V, VREF = 2.5 V)
Parameter
Limit at TMIN, TMAX
Unit
Description
2
fDCLK
10
2
1.5
10
60
kHz min
MHz max
µs min
ns min
ns max
ns max
ns min
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns max
tACQ
t1
Acquisition Time
CS Falling Edge to First DCLK Rising Edge
CS Falling Edge to BUSY Three-State Disabled
CS Falling Edge to DOUT Three-State Disabled
DCLK High Pulsewidth
t23
t3
60
t4
t5
t6
t7
200
200
60
10
10
200
0
200
DCLK Low Pulsewidth
DCLK Falling Edge to BUSY Rising Edge
Data Setup Time Prior to DCLK Rising Edge
Data Valid to DCLK Hold Time
Data Access Time after DCLK Falling Edge
CS Rising Edge to DCLK Ignored
t83
t9
t10
t11
t12
CS Rising Edge to BUSY High Impedance
CS Rising Edge to DOUT High Impedance
4
200
NOTES
1Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V.
2Mark/Space ratio for the SCLK input is 40/60 to 60/40.
3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 2.0 V.
4t12 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t12, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
I
200A
OL
TO
OUTPUT
PIN
1.6V
C
L
50pF
I
200A
OH
Figure 1. Load Circuit for Digital Output Timing Specifications
REV. 0
–3–
AD7843
ABSOLUTE MAXIMUM RATINGS1
(TA = 25°C unless otherwise noted)
QSOP, TSSOP Package, Power Dissipation . . . . . . . 450 mW
JA Thermal Impedance . . . . . . . . . . . 149.97°C/W (QSOP)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150.4°C/W (TSSOP)
θ
+VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to GND . . . . . . . –0.3 V to VCC + 0.3 V
Digital Input Voltage to GND . . . . . . . –0.3 V to VCC + 0.3 V
Digital Output Voltage to GND . . . . . –0.3 V to VCC + 0.3 V
θJC Thermal Impedance . . . . . . . . . . . . . 38.8°C/W (QSOP)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.6°C/W (TSSOP)
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
V
REF to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . 10 mA
Operating Temperature Range
NOTES
1Stresses above those listed under Absolute Maximum Rating may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Commercial . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
2Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
Temperature
Range
Linearity
Package
Package
Description
Branding
Information
Model
Error (LSB)1 Option
AD7843ARQ
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Evaluation Board
Controller Board
2
2
2
2
2
2
RQ-162
RQ-162
RQ-162
RU-16
RU-16
RU-16
QSOP
QSOP
QSOP
TSSOP
TSSOP
TSSOP
AD7843ARQ
AD7843ARQ
AD7843ARQ
AD7843ARU
AD7843ARU
AD7843ARU
AD7843ARQ-REEL
AD7843ARQ-REEL7
AD7843ARU
AD7843ARU-REEL
AD7843ARU-REEL7
EVAL-AD7843CB3
EVAL-CONTROL BRD24
NOTES
1Linearity error here refers to integral linearity error.
2RQ = 0.15" Quarter Size Outline Package.
3This can be used as a stand-alone evaluation board or in conjunction with the EVALUATION BOARD CONTROLLER for evaluation/demonstration purposes.
4This EVALUATION BOARD CONTROLLER is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the
CB designators.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7843 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION QSOP/TSSOP
1
2
3
4
5
6
7
8
16 DCLK
+V
CC
15
X+
CS
14
13
12
11
10
9
Y+
X–
Y–
DIN
AD7843
TOP VIEW
(Not to Scale)
BUSY
DOUT
PENIRQ
GND
IN3
+V
CC
IN4
V
REF
–4–
REV. 0
AD7843
PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
1, 10
+VCC
Power Supply Input. The +VCC range for the AD7843 is from 2.2 V to 5.25 V. Both +VCC pins should
be connected directly together.
2
3
4
5
6
X+
Y+
X–
Y–
GND
X+ Position Input. ADC Input Channel 1.
Y+ Position Input. ADC Input Channel 2.
X– Position Input.
Y– Position Input.
Analog Ground. Ground reference point for all circuitry on the AD7843. All analog input signals and
any external reference signal should be referred to this GND voltage.
7
8
9
IN3
IN4
VREF
Auxiliary Input 1. ADC Input Channel 3.
Auxiliary Input 2. ADC Input Channel 4.
Reference Input for the AD7843. An external reference must be applied to this input. The voltage
range for the external reference is 1.0 V to +VCC. For specified performance it is 2.5 V.
11
12
PENIRQ
Pen Interrupt. CMOS Logic open drain output (requires 10 kΩ to 100 kΩ pull-up resistor externally).
DOUT
Data Out. Logic Output. The conversion result from the AD7843 is provided on this output as a
serial data stream. The bits are clocked out on the falling edge of the DCLK input. This output is
high impedance when CS is high.
13
14
BUSY
DIN
BUSY Output. Logic Output. This output is high impedance when CS is high.
Data In. Logic Input. Data to be written to the AD7843’s Control Register is provided on this input
and is clocked into the register on the rising edge of DCLK (see Control Register section).
15
16
CS
Chip Select Input. Active Low Logic Input. This input provides the dual function of initiating con-
versions on the AD7843 and also enables the serial input/output register.
External Clock Input. Logic Input. DCLK provides the serial clock for accessing data from the part.
This clock input is also used as the clock source for the AD7843’s conversion process.
DCLK
Gain Error
TERMINOLOGY
This is the deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal (i.e., VREF – 1 LSB) after the offset
error has been adjusted out.
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB
above the last code transition.
Track/Hold Acquisition Time
The track/hold amplifier enters the acquisition phase on the fifth
falling edge of DCLK after the START bit has been detected.
Three DCLK cycles are allowed for the Track/Hold acquisition
time and the input signal will be fully acquired to the 12-bit
level within this time even with the maximum specified DCLK
frequency. See Analog Input section for more details.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
On-Resistance
This is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, i.e., AGND + 1 LSB.
This is a measure of the ohmic resistance between the drain and
source of the switch drivers.
REV. 0
–5–
AD7843–Typical Performance Characteristics
207
206
205
204
203
202
201
200
199
198
141
140
139
138
137
136
135
134
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
TEMPERATURE – ؇C
TEMPERATURE – ؇C
TPC 1. Supply Current vs. Temperature
TPC 4. Power-Down Supply Current vs. Temperature
230
220
210
200
190
180
170
160
150
1000
f
V
= 12.5kHz
SAMPLE
= +V
REF
CC
V
= +V
CC
REF
100
2.2
2.2
2.6
3.0
3.4
+V – V
3.8
4.2
4.6
5.0
2.7
3.2
3.7
4.2
4.7
5.2
CC
+V – V
CC
TPC 2. Supply Current vs. +VCC
TPC 5. Maximum Sample Rate vs. +VCC
0.20
0.15
0.6
0.4
0.10
0.2
0.05
0.00
0.0
–0.05
–0.10
–0.15
–0.20
–0.2
–0.4
–0.6
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
TEMPERATURE – ؇C
TEMPERATURE – ؇C
TPC 3. Change in Gain vs. Temperature
TPC 6. Change in Offset vs. Temperature
–6–
REV. 0
AD7843
14
13
12
11
10
9
7.5
6.5
5.5
4.5
3.5
2.5
1.5
0.5
8
7
6
5
4
3
2
–40
–20
0
20
40
60
80
10
25
40
55
70
85
100
115
130
TEMPERATURE – ؇C
SAMPLE RATE – kHz
TPC 7. Reference Current vs. Sample Rate
TPC 10. Reference Current vs. Temperature
10
9
9
8
7
6
5
4
8
Y+
Y+
X+
X+
7
X–
6
Y–
X–
5
Y–
4
3
–40
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
–20
0
20
40
60
80
100
+V –V
TEMPERATURE – ؇C
CC
TPC 11. Switch-On-Resistance vs. Temperature (X+, Y+:
+VCC to Pin; X–, Y–: Pin to GND)
TPC 8. Switch-On-Resistance vs. +VCC (X+, Y+: +VCC to
Pin; X–, Y–: Pin to GND)
0
2.0
1.8
f
f
= 125kHz
= 15kHz
SAMPLE
IN
20
40
SNR = 68.34dB
1.6
INL: R = 2k⍀
1.4
1.2
INL: R = 500⍀
60
1.0
0.8
DNL: R = 2k⍀
80
0.6
0.4
100
120
DNL: R = 500⍀
0.2
0
0
7.50
15.0
22.5
30.0
37.5
45.0
52.5
60.0
15
35
55
75
95
115
135
155
175
195
FREQUENCY – kHz
SAMPLING RATE – kSPS
TPC 12. Auxiliary Channel Dynamic Performance
TPC 9. Maximum Sampling Rate vs. RIN
REV. 0
–7–
AD7843
TPC 12 shows a typical FFT plot for the auxiliary channels of
the AD7843 at 125 kHz sample rate and 15 kHz input frequency.
converter. The analog input range is 0 V to VREF (where the
externally-applied VREF can be between 1 V and VCC).
TPC 13 shows the power supply rejection ratio versus VCC
supply frequency for the AD7843. The power supply rejection
ratio is defined as the ratio of the power in the ADC output at
full-scale frequency f, to the power of a 100 mV sine wave applied
to the ADC VCC supply of frequency fS:
The analog input to the ADC is provided via an on-chip multi-
plexer. This analog input may be any one of the X and Y panel
coordinates. The multiplexer is configured with low resistance
switches that allow an unselected ADC input channel to provide
power and an accompanying pin to provide ground for an exter-
nal device. For some measurements the on-resistance of the
switches may present a source of error. However, with a dif-
ferential input to the converter and a differential reference
architecture this error can be negated.
PSRR (dB) = 10 log (Pf/Pfs)
Pf = Power at frequency f in ADC output, Pfs = power at fre-
quency fS coupled onto the ADC VCC supply. Here a 100 mV
peak-to-peak sine wave is coupled onto the VCC supply. Decou-
pling capacitors of 10 µF and 0.1 µF were used on the supply.
ADC TRANSFER FUNCTION
The output coding of the AD7843 is straight binary. The
designed code transitions occur at successive integer LSB values
(i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = VREF/4096. The ideal
transfer characteristic for the AD7843 is shown in Figure 2 below.
0
V
= 3V, V
= 2.5V
CC
REF
100mV p-p SINEWAVE ON +V
CC
f
= 125kHz, f = 20kHz
–20
–40
SAMPLE
IN
111...111
111...110
–60
111...000
1LSB = V
/4096
–80
REF
011...111
–100
–120
000...010
000...001
000...000
1LSB
0V
+V
–1LSB
REF
0
10
20
30
CC
40
50
60
70
80
90
100
ANALOG INPUT
V
RIPPLE FREQUENCY – kHz
Figure 2. AD7843 Transfer Characteristic
TPC 13. AC PSRR vs. Supply Ripple Frequency
TYPICAL CONNECTION DIAGRAM
CIRCUIT INFORMATION
Figure 3 shows a typical connection diagram for the AD7843 in
a touch screen control application. The AD7843 requires an exter-
nal reference and an external clock. The external reference can
be any voltage between 1 V and VCC. The value of the reference
voltage will set the input range of the converter. The conversion
result is output MSB first followed by the remaining eleven bits
and three trailing zeroes depending on the number of clocks used
per conversion, see the Serial Interface section. For applications
where power consumption is of concern, the power management
option should be used to improve power performance. See
Table III for the available power management options.
The AD7843 is a fast, low-power, 12-bit, single supply, A/D
converter. The AD7843 can be operated from a 2.2 V to 5.25 V
supply. When operated from either a 5 V supply or a 3 V supply,
the AD7843 is capable of throughput rates of 125 kSPS when
provided with a 2 MHz clock.
The AD7843 provides the user with an on-chip track/hold,
multiplexer, A/D converter, and serial interface housed in a tiny
16-lead QSOP or TSSOP package, which offers the user consid-
erable space-saving advantages over alternative solutions. The
serial clock input (DCLK) accesses data from the part but also
provides the clock source for the successive-approximation A/D
2.2V TO 5V
1F TO 10F
(OPTIONAL)
0.1F
+V
DCLK
1
2
3
4
5
6
7
8
16
SERIAL/CONVERSION CLOCK
CHIP SELECT
CC
X+
Y+
X–
Y–
CS 15
AD7843
DIN
SERIAL DATA IN
14
13
BUSY
CONVERTER STATUS
SERIAL DATA OUT
TOUCH
SCREEN
DOUT 12
11
GND
IN3
PENIRQ
PEN INTERRUPT
+V
10
9
CC
AUXILIARY INPUTS
100k⍀
(OPTIONAL)
V
IN4
REF
0.1F
Figure 3. Typical Application Circuit
–8–
REV. 0
AD7843
ANALOG INPUT
Acquisition Time
Figure 4 shows an equivalent circuit of the analog input struc-
ture of the AD7843 which contains a block diagram of the input
multiplexer, the differential input of the A/D converter and the
differential reference.
The track and hold amplifier enters its tracking mode on the
falling edge of the fifth DCLK after the START bit has been
detected (see Figure 13). The time required for the track and
hold amplifier to acquire an input signal will depend how
quickly the 37 pF input capacitance is charged. With zero
source impedance on the analog input three DCLK cycles will
always be sufficient to acquire the signal to the 12-bit level.
With a source impedance RIN on the analog input, the actual
acquisition time required is calculated using the formula:
Table I shows the multiplexer address corresponding to each
analog input, both for the SER/DFR bit in the control register
set high and low. The control bits are provided serially to the
device via the DIN pin. For more information on the control
register see the Control Register section.
t
ACQ = 8.4 × (RIN +100 Ω) × 37 pF
When the converter enters the hold mode, the voltage difference
between the +IN and –IN inputs (see Figure 4) is captured on
the internal capacitor array. The input current on the analog
inputs depends on the conversion rate of the device. During the
sample period, the source must charge the internal sampling
capacitor (typically 37 pF). Once the capacitor has been fully
charged, there is no further input current. The rate of charge
transfer from the analog source to the converter is a function of
conversion rate.
where RIN is the source impedance of the input signal, and
100 Ω, 37 pF is the input RC value. Depending on the frequency
of DCLK used, three DCLK cycles may or may not be suffi-
cient to acquire the analog input signal with various source
impedance values.
V
CC
X+
X–
Y+
Y–
REF
EXT
X+ Y+
3-TO-1
MUX
ON-CHIP SWITCHES
X+
REF+
ADC CORE
IN+
Y+
4-TO-1
MUX
IN+
DATA OUT
IN3
IN– REF–
IN4
3-TO-1
MUX
X– Y– GND
Figure 4. Equivalent Analog Input Circuit
REV. 0
–9–
AD7843
Table I. Analog Input, Reference, and Touch Screen Control
A21
A11
A01
SER/DFR
Analog In
X Switches
Y Switches
+REF2
–REF2
0
0
1
1
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
1
0
1
1
1
1
0
0
0
X+
IN3
Y+
IN4
X+
Y+
OFF
OFF
ON
OFF
OFF
ON
ON
VREF
VREF
VREF
VREF
Y+
GND
GND
GND
GND
Y–
OFF
OFF
OFF
ON
OFF
X+
X–
Outputs Identity Code, 1000 0000 0000
NOTES
1All remaining configurations are invalid addresses.
2Internal node – not directly accessible by the user.
Touch Screen Settling
When making touch screen measurements, conversions can be
made in the differential (ratiometric) mode or the single-ended
mode. If the SER/DFR bit is set to 1 in the control register, a
single-ended conversion will be performed. Figure 6 shows the
configuration for a single-ended Y coordinate measurement.
The X+ input is connected to the analog to digital converter,
the Y+ and Y– drivers are turned on and the voltage on X+ is
digitized. The conversion is performed with the ADC refer-
enced from GND to VREF. The advantage of this mode is that
the switches that supply the external touch screen can be turned
off once the acquisition is complete, resulting in a power saving.
However, the on-resistance of the Y drivers will affect the input
voltage that can be acquired. The full touch screen resistance
may be in the order of 200 Ω to 900 Ω, depending on the manu-
facturer. Thus if the on-resistance of the switches is approximately
6 Ω, true full-scale and zero-scale voltages cannot be acquired
regardless of where the pen/stylus is on the touch screen.
In some applications, external capacitors may be required across
the touch screen to filter noise associated with it, e.g., noise
generated by the LCD panel or backlight circuitry. The value of
these capacitors will cause a settling time requirement when the
panel is touched. The settling time will typically show up as a
gain error. There are several methods for minimizing or elimi-
nating this issue. The problem may be that the input signal, or
reference, or both, have not settled to their final value before the
sampling instant of the ADC. Additionally, the reference voltage
may still be changing during the conversion cycle. One option is
to stop, or slow down the DCLK for the required touch screen
settling time. This will allow the input and reference to stabilize
for the acquisition time. This will resolve the issue for both
single-ended and differential modes.
The other option is to operate the AD7843 in differential mode
only for the touch screen, and program the AD7843 to keep the
touch screen drivers ON and not go into power-down (PD0 =
PD1 = 1). Several conversions may be required depending on
the settling time required and the AD7843 data rate. Once the
required number of conversions have been made, the AD7843
can then be placed in a power-down state on the last measure-
ment. The last method is to use the 15 DCLK cycle mode, which
maintains the touch screen drivers ON until it is commanded to
stop by the processor.
Note: The minimum touch screen resistance recommended for
use with the AD7843 is approximately 70 Ω.
+V
CC
Y+
V
REF
REF+
IN+ ADC CORE
REF–
X+
IN+
Reference Input
IN–
The voltage difference between +REF and –REF (see Figure 4)
sets the analog input range. The AD7843 will operate with a
reference input in the range of 1 V to VCC. The voltage into
the VREF input is not buffered and directly drives the capaci-
tor DAC portion of the AD7843. Figure 5 shows the reference
Y–
GND
Figure 6. Single-Ended Reference Mode (SER/DFR = 1)
input circuitry. Typically, the input current is 8 µA with VREF
2.5 V and fSAMPLE = 125 kHz. This value will vary by a few
microamps, depending on the result of the conversion. The
=
In this mode of operation, therefore, some voltage is likely to be
lost across the internal switches and, in addition to this, it is
unlikely that the internal switch resistance will track the resis-
tance of the touch screen over temperature and supply, providing
an additional source of error.
reference current diminishes directly with both conversion rate
and reference voltage. As the current from the reference is
drawn on each bit decision, clocking the converter more quickly
during a given conversion period will not reduce the overall
current drain from the reference.
The alternative to this situation is to set the SER/DFR bit low.
If one again considers making a Y coordinate measurement,
but now the +REF and –REF nodes of the ADC are connected
directly to the Y+ and Y– pins, this means the analog to digital
conversion will be ratiometric. The result of the conversion will
always be a percentage of the external resistance, independent of
how it may change with respect to the on-resistance of the internal
switches. Figure 7 shows the configuration for a ratiometric Y
coordinate measurement. It should be noted that the differential
X+
Y+
3-TO-1
MUX
ADC
V
REF
Figure 5. Reference Input Circuitry
–10–
REV. 0
AD7843
reference mode can only be used with +VCC as the source of the
+REF voltage and cannot be used with VREF
MODE
.
The MODE bit sets the resolution of the analog to digital con-
verter. With a 0 in this bit the following conversion will have
12 bits of resolution. With a 1 in this bit the following conver-
sion will have 8 bits of resolution.
The disadvantage of this mode of operation is that during both
the acquisition phase and conversion process, the external touch
screen must remain powered. This will result in additional sup-
ply current for the duration of the conversion.
SER/DFR
The SER/DFR bit controls the reference mode which can be
either single ended or differential if a 1 or a 0 is written to this
bit respectively. The differential mode is also referred to as
the ratiometric conversion mode. This mode is optimum for
X-Position and Y-Position measurements. The reference is
derived from the voltage at the switch drivers, which is almost
the same as the voltage to the touch screen. In this case a sepa-
rate reference voltage is not needed as the reference voltage to
the analog to digital converter is the voltage across the touch
screen. In the single-ended mode, the reference voltage to the
converter is always the difference between the VREF and GND pins.
See Table I and Figures 4 through 7 for further information.
+V
CC
Y+
REF+
ADC CORE
X+
IN+
IN+
REF–
IN–
Y–
GND
Figure 7. Differential Reference Mode (SER/DFR = 0)
As the supply current required by the device is so low, a preci-
sion reference can be used as the supply source to the AD7843.
It may also be necessary to power the touch screen from the
reference, which may require 5 mA to 10 mA. A REF19x volt-
age reference can source up to 30 mA and, as such, could supply
both the ADC and the touch screen. Care must be taken, how-
ever, to ensure that the input voltage applied to the ADC does
not exceed the reference voltage and hence the supply voltage.
See Maximum Ratings section.
CONTROL REGISTER
The control word provided to the ADC via the DIN pin is
shown in Table II. This provides the conversion start, channel
addressing, ADC conversion resolution, configuration and
power-down of the AD7843. Table II provides detailed infor-
mation on the order and description of these control bits within
the control word.
Initiate START
NOTE: The differential mode can only be used for X-Position
and Y-Position measurements All other measurements require
the single-ended mode.
The first bit, the “S” bit, must always be set to 1 to initiate the
start of the control word. The AD7843 will ignore any inputs on
the DIN line until the start bit is detected.
PD0 and PD1
Channel Addressing
The power management options are selected by programming
the power management bits, PD0 and PD1, in the control regis-
ter. Table III summarizes the available options.
The next three bits in the control register, A2, A1 and A0, select
the active input channel(s) of the input multiplexer (see Table I
and Figure 4), touch screen drivers, and the reference inputs.
Table II. Control Register Bit Function Description
MSB
LSB
PD0
S
A2
A1
A0
MODE
SER/DFR
PD1
Bit
Mnemonic
Comment
7
S
Start Bit. The Control word starts with the first high bit on DIN. A new control word can start every fifteenth
DCLK cycle when in the 12-bit conversion mode or every eleventh DCLK cycle when in 8-bit conversion mode.
6–4 A2–A0
Channel Select Bits. These three address bits along with the SER/DFR bit control the setting of the multi-
plexer input, switches, and reference inputs, as detailed in Table I.
3
2
MODE
12-Bit/8-Bit Conversion Select Bit. This bit controls the resolution of the following conversion. With a 0 in
this bit the conversion will have 12-bit resolution or with a 1 in this bit, 8-bit resolution.
Single-Ended/Differential Reference Select Bit. Along with bits A2–A0, this bit controls the setting of the
multiplexer input, switches, and reference inputs as described in Table I.
SER/DFR
1, 0 PD1, PD0
Power Management Bits. These two bits decode the power-down mode of the AD7843 as shown in Table III.
REV. 0
–11–
AD7843
Table III. Power Management Options
Description
PD1
PD0
PENIRQ
0
0
Enabled
This configuration will result in power-down of the device between conversions. The AD7843
will only power down between conversions. Once PD1 and PD0 have been set to 0, 0, the
conversion will be performed first and the AD7843 will power down upon completion of that
conversion. At the start of the next conversion, the ADC instantly powers up to full power. This
means there is no need for additional delays to ensure full operation and the very first conversion
is valid. The Y– switch is ON while in power-down.
0
1
1
1
0
1
Disabled
Enabled
Disabled
This configuration will result in the same behavior as when PD1 and PD0 have been programmed
with 0, 0, except that PENIRQ is disabled. The Y– switch is OFF while in power-down.
This configuration will result in keeping the AD7843 permanently powered up with the PENIRQ
enabled.
This configuration will result in keeping the AD7843 always powered up with the PENIRQ
disabled.
POWER VS. THROUGHPUT RATE
SERIAL INTERFACE
By using the power-down options on the AD7843 when not con-
verting, the average power consumption of the device decreases at
lower throughput rates. Figure 8 shows how, as the through-
put rate is reduced while maintaining the DCLK frequency at
2 MHz, the device remains in its power-down state longer and
the average current consumption over time drops accordingly.
Figure 9 shows the typical operation of the serial interface of the
AD7843. The serial clock provides the conversion clock and
also controls the transfer of information to and from the AD7843.
One complete conversion can be achieved with twenty-four
DCLK cycles.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS takes the BUSY output and the serial
bus out of three-state. The first eight DCLK cycles are used to
write to the Control Register via the DIN pin. The Control
Register is updated in stages as each bit is clocked in and once
the converter has enough information about the following con-
version to set the input multiplexer and switches appropriately,
the converter enters the acquisition mode and if required, the
internal switches are turned on. During the acquisition mode
the reference input data is updated. After the three DCLK
cycles of acquisition, the control word is complete (the power
management bits are now updated) and the converter enters the
conversion mode. At this point the track and hold goes into hold
mode and the input signal is sampled and the BUSY output
goes high (BUSY will return low on the next falling edge of
DCLK). The internal switches may also turn off at this point if
in single-ended mode.
For example, if the AD7843 is operated in a 24 DCLK continu-
ous sampling mode, with a throughput rate of 10 kSPS and a
SCLK of 2 MHz, and the device is placed in the power-down
mode between conversions, (PD0, PD1 = 0, 0), the current
consumption is calculated as follows. The power dissipation
during normal operation is typically 210 µA (VCC = 2.7 V). The
power-up time of the ADC is instantaneous, so when the part
is converting it will consume 210 µA. In this mode of operation
the part powers up on the 4th falling edge of DCLK after the
start bit has been recognized. It goes back into power-down at
the end of conversion on the 20th falling edge of DCLK. This
means the part will consume 210 µA for 16 DCLK cycles only,
8 µs, during each conversion cycle. With a throughput rate of
10 kSPS, the cycle time is 100 µs and the average power dissi-
pated during each cycle is (8/100) × (210 µA) = 16.8 µA.
1000
The next 12 DCLK cycles are used to perform the conversion
and to clock out the conversion result. If the conversion is
ratiometric (SER/DFR set low) the internal switches are on
during the conversion. A thirteenth DCLK cycle is needed to
allow the DSP/micro to clock in the LSB. Three more DCLK
cycles will clock out the three trailing zeroes and complete the
twenty four DCLK transfer. The twenty-four DCLK cycles may
be provided from a DSP or via three bursts of eight clock cycles
from a microcontroller.
f
DCLK
= 16
؋
f SAMPLE
100
10
1
f
DCLK
= 2MHz
V
T
= 2.7V
CC
= –40؇C to +85؇C
A
0
20
40
60
80
100
120
THROUGHPUT – kSPS
Figure 8. Supply Current vs. Throughput (µA)
–12–
REV. 0
AD7843
CS
tACQ
1
8
1
8
1
8
DCLK
DIN
SER/
DFR
A2 A1 A0 MODE
IDLE
PD1 PD0
AQUIRE
S
(START)
CONVERSION
IDLE
THREE-STATE
THREE-STATE
BUSY
THREE-STATE
ZERO FILLED
THREE-STATE
3
1
0
11
10
9
8
7
6
5
4
2
DOUT
(LSB)
(MSB)
(1)
OFF
OFF
OFF
ON
X/Y SWITCHES
(SER/DFR HIGH)
(1,2)
OFF
ON
X/Y SWITCHES
(SER/DFR LOW)
NOTES
1
Y DRIVERS ARE ON WHEN X؉ IS SELECTED INPUT CHANNEL (A2–A0 = 001), X DRIVERS ARE ON WHEN Y؉ IS SELECTED INPUT CHANNEL (A2–A0 = 101).
WHEN PD1, PD0 = 10 OR 00, Y– WILL TURN ON AT END OF CONVERSION.
2
DRIVERS WILL REMAIN ON IF POWER-DOWN MODE IS 11 (NO POWER-DOWN) UNTIL SELECTED INPUT CHANNEL, REFERENCE MODE,
OR POWER-DOWN MODE IS CHANGED.
Figure 9. Conversion Timing, 24 DCLKS per Conversion Cycle, 8-Bit Bus Interface. No DCLK delay required with dedi-
cated serial port
Detailed Serial Interface Timing
conversion cycle, then the part will wait for the next START bit
to initiate the next conversion. This means each conversion
need not necessarily be framed by CS, as once CS goes low the
part will detect each START bit and clock in the control word
after it on DIN. When the AD7843 is in the 12-bit conversion
mode, a second START bit will not be detected until seven DCLK
pulses have elapsed after a control word has been clocked in on
DIN, i.e., another START bit can be clocked in on the eighth
DCLK rising edge after a control word has been written to the
device (see Fifteen Clock Cycle section). If the device is in the
8-bit conversion mode, a second START bit will not be recog-
nized until three DCLK pulses have elapsed after the control
word has been clocked in, i.e., another START bit can be
clocked in on the fourth DCLK rising edge after a control word
has been written to the device.
Figure 10 shows the detailed timing diagram for serial interfacing
to the AD7843. Writing of information to the Control Register
takes place on the first eight rising edges of DCLK in a data
transfer. The Control Register is only written to if a START bit
is detected (see Control Register section) on DIN and the initia-
tion of the following conversion is also dependent on the presence
of the START bit. Throughout the eight DCLK cycles when
data is being written to the part, the DOUT line will be driven
low. The MSB of the conversion result is clocked out on the
falling edge of the ninth DCLK cycle and is valid on the rising
edge of the tenth DCLK cycle, therefore nine leading zeros may
be clocked out prior to the MSB. This means the data seen on
the DOUT line in the twenty four DCLK conversion cycle, will
be presented in the form of nine leading zeros, twelve bits of
data and three trailing zeros.
Because a START bit can be recognized during a conversion, it
means the control word for the next conversion can be clocked
in during the current conversion, enabling the AD7843 to com-
plete a conversion cycle in less than twenty-four DCLKs.
The rising edge of CS will put the bus and the BUSY output
back into three-state, the DIN line will be ignored and if a con-
version is in progress at the time then this will also be aborted.
However, if CS is not brought high after the completion of the
CS
t4
t8
t6
t6
t9
t10
t1
t5
DCLK
t7
DIN
PD0
t2
BUSY
t11
t12
DOUT
t3
DB11
DB10
Figure 10. Detailed Timing Diagram
REV. 0
–13–
AD7843
Sixteen Clocks per Cycle
This will effectively increase the throughput rate of the AD7843
beyond that used for the specifications which are tested using 16
DCLKs per cycle, and DCLK = 2 MHz.
The control bits for the next conversion can be overlapped with
the current conversion to allow for a conversion every 16 DCLK
cycles, as shown in Figure 11. This timing diagram also allows
for the possibility of communication with other serial peripherals
between each (eight DCLK) byte transfer between the processor
and the converter. However, the conversion must be complete
within a short enough time frame to avoid capacitive droop
effects which may distort the conversion result. It should also
be noted that the AD7843 will be fully powered while other
serial communications may be taking place between byte transfers.
8-Bit Conversion
The AD7843 can be set up to operate in an 8-bit rather than
12-bit mode, by setting the MODE bit to 1 in the control regis-
ter. This mode allows a faster throughput rate to be achieved,
assuming 8-bit resolution is sufficient. When using the 8-bit
mode a conversion is complete four clock cycles earlier than in
the 12-bit mode. This could be used with serial interfaces that
provide 12 clock transfers, or two conversions could be com-
pleted with three eight-clock transfers. The throughput rate will
increase by 25% as a result of the shorter conversion cycle, but
the conversion itself can occur at a faster clock rate because the
internal settling time of the AD7843 is not as critical because
settling to 8 bits is all that is required. The clock rate can be as
much as 50% faster. The faster clock rate and fewer clock cycles
combine to provide double the conversion rate.
Fifteen Clocks per Cycle
Figure 12 shows the fastest way to clock the AD7843. This
scheme will not work with most microcontrollers or DSPs as in
general they are not capable of generating a 15-clock cycle per
serial transfer. However, some DSPs will allow the number of
clocks per cycle to be programmed and this method could also
be used with FPGAs (Field Programmable Gate Arrays) or
ASICs (Application Specific Integrated Circuits). As in the 16-
clocks-per-cycle case, the control bits for the next conversion
are overlapped with the current conversion to allow for a con-
version every 15 DCLK cycles, using 12 DCLKs to perform
the conversion and three DCLKs to acquire the analog input.
PEN INTERRUPT REQUEST
The pen interrupt equivalent output circuitry is outlined in
Figure 13. By connecting a pull-up resistor (10 kΩ to 100 kΩ)
between VCC and this CMOS Logic open drain output, the
PENIRQ output will remain high normally. If PENIRQ has
CS
1
8
1
8
1
8
1
DCLK
DIN
S
S
CONTROL BITS
CONTROL BITS
BUSY
11 10
9
8
7
6
5
4
3
1
0
2
11
10
9
DOUT
Figure 11. Conversion Timing, 16 DCLKS per Cycle, 8-Bit Bus Interface. No DCLK Delay Required with Dedicated Serial Port
CS
1
15
15
DCLK
DIN
1
1
SER/
MODE
A2 A1 A0
DFR
SER/
DFR
A2
S
A1
MODE
PD1 PD0
A0
S
5
PD1 PD0
S
5
A2
4
BUSY
DOUT
11
10
9
8
7
6
2
11
10
9
8
7
6
4
3
1
0
Figure 12. Conversion Timing, 15 DCLKS per Cycle, Maximum Throughput Rate
–14–
REV. 0
AD7843
been enabled (see Table III), when the touch screen connected
to the AD7843 is touched via a pen or finger, the PENIRQ output
will go low initiating an interrupt to a microprocessor which may
then instruct a control word to be written to the AD7843 to
initiate a conversion. This output can also be enabled between
conversions during power-down (see Table III) allowing power-
up to be initiated only when the screen is touched. The result of
the first touch screen coordinate conversion after power-up will
be valid assuming any external reference is settled to the 12- or
8-bit level as required.
output will remain low until the fourth falling edge of DCLK
after the START bit has been clocked in, at which point it will
return high as soon as possible, regardless of the touch screen
capacitance. This does not mean the pen interrupt function is
now enabled again as the power-down bits have not yet been
loaded to the control register. So regardless of whether PENIRQ
is to be enabled again or not the PENIRQ output will always
idle high normally. Assuming the PENIRQ is enabled again as
shown in Figure 14, once the conversion is complete, the
PENIRQ output will respond to a screen touch again. The fact
that PENIRQ returns high almost immediately after the fourth
falling edge of DCLK, means the user will avoid any spurious
interrupts on the microprocessor or DSP which could occur if
the interrupt request line on the micro/DSP was unmasked
during or toward the end of conversion with the PENIRQ pin
still low. Once the next START bit is detected by the AD7843
the PENIRQ function is disabled again.
+V
CC
Y+
EXTERNAL
PULL-UP
100k⍀
+V
CC
PENIRQ
X+
TOUCH
If the control register write operation will overlap with the data
read, a START bit will always be detected prior to the end of
conversion, meaning that even if the PENIRQ function has been
enabled in the Control Register it will be disabled by the START
bit again before the end of the conversion is reached, so the
PENIRQ function effectively cannot be used in this mode.
However, as conversions are occurring continuously, the
PENIRQ function is not necessary and, therefore, redundant.
PENIRQ
ENABLE
SCREEN
Y–
ON
Figure 13. PENIRQ Functional Block Diagram
Figure 14 assumes the PENIRQ function has been enabled in
the last write or the part has just been powered up so PENIRQ
is enabled by default. Once the screen is touched, the PENIRQ
output will go low a time tPEN later. This delay is approximately
5 µs, assuming a 10 nF touch screen capacitance, and will vary
with the touch screen resistance actually used. Once the START
bit is detected, the pen interrupt function is disabled and the
PENIRQ will not respond to screen touches. The PENIRQ
GROUNDING AND LAYOUT
For information on grounding and layout considerations for the
AD7843 refer to the “Layout and Grounding Recommendations
for Touch Screen Digitizers” Technical Note.
SCREEN
TOUCHED
HERE
PD1 = 1, PD0 = 0, PENIRQ
tPEN
ENABLED AGAIN
NO RESPONSE TO TOUCH
PENIRQ
INTERRUPT
PROCESSOR
CS
1
8
13
16
1
DCLK
SER/
MODE
DFR
A2 A1 A0
1
0
S
DIN
(START)
Figure 14. PENIRQ Timing Diagram
REV. 0
–15–
AD7843
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead QSOP
(RQ-16)
16-Lead TSSOP
(RU-16)
0.197 (5.00)
0.189 (4.80)
0.201 (5.10)
0.193 (4.90)
9
16
16
9
0.177 (4.50)
0.169 (4.30)
0.244 (6.20)
0.228 (5.79)
0.157 (3.99)
0.150 (3.81)
1
0.256 (6.50)
0.246 (6.25)
8
1
8
PIN 1
PIN 1
0.069 (1.75)
0.053 (1.35)
0.059 (1.50)
MAX
0.006 (0.15)
0.002 (0.05)
0.0433 (1.10)
MAX
8؇
0؇
8؇
0؇
0.012 (0.30)
0.008 (0.20)
0.010 (0.25)
0.004 (0.10)
0.025
(0.64)
BSC
0.050 (1.27)
0.016 (0.41)
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
0.028 (0.70)
0.020 (0.50)
SEATING
PLANE
0.010 (0.20)
0.007 (0.18)
0.0079 (0.20)
0.0035 (0.090)
SEATING
PLANE
BSC
–16–
REV. 0
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