EVAL-AD7176-2SDZ_技术文档

24-Bit, 250 kSPS Sigma-Delta ADC

with 20 µs Settling

Data Sheet

AD7176-2

FEATURES

GENERAL DESCRIPTION

Fast and flexible output rate—5 SPS to 250 kSPS

Fast settling time—20 µs

Channel scan data rate of 50 kSPS/channel

Performance specifications

17 noise free bits at 250 kSPS

20 noise free bits at 2.5 kSPS

The AD7176-2 is a fast settling, highly accurate, high resolution,

multiplexed Σ-Δ analog-to-digital converter (ADC) for low band-

width input signals. Its inputs can be configured as two fully

differential or four pseudo differential inputs via the integrated

crosspoint multiplexer. An integrated precision, 2.5 V, low drift

(2 ppm/°C), band gap internal reference (with an output

reference buffer) adds functionality and reduces the external

component count.

22 noise free bits at 5 SPS

INL 2.5 ppm of FSR

85 dB rejection of 50 Hz and 60 Hz with 50 ms settling

User-configurable input channels

2 fully differential or 4 pseudo differential

Crosspoint multiplexer

On-chip 2.5 V reference (drift 2 ppm/°C)

Internal oscillator, external crystal, or external clock

Power supply

Single supply: 5 V AVDD1, 2 V to 5 V AVDD2 and IOVDD

Optional split supply: AVDD1 and AVSS 2.5 V

Current: 7.8 mA

Temperature range: −40°C to +105°C

3- or 4-wire serial digital interface (Schmitt trigger on SCLK)

CRC error checking

The maximum channel scan data rate is 50 kSPS (with a settling

time of 20 µs), resulting in fully settled data of 17 noise free bits.

User-selectable output data rates range from 5 SPS to 250 kSPS.

The resolution increases at lower speeds.

The AD7176-2 offers three key digital filters. The fast settling filter

maximizes the channel scan rate. The Sinc3 filter maximizes the

resolution for single-channel, low speed applications. For 50 Hz

and 60 Hz environments, the AD7176-2 specific filter minimizes

the settling times or maximizes the rejection of the line frequency.

These enhanced filters enable simultaneous 50 Hz and 60 Hz rejec-

tion with a 27 SPS output data rate (with a settling time of 36 ms).

System offset and gain errors can be corrected on a per channel

basis. This per channel configurability extends to the type of filter

and output data rate used for each channel. All switching of the

crosspoint multiplexer is controlled by the ADC and can be con-

figured to automatically control an external multiplexer via the

GPIO pins.

SPI, QSPI, MICROWIRE, and DSP compatible

APPLICATIONS

Process control: PLC/DCS modules

Temperature and pressure measurement

Medical and scientific multichannel instrumentation

Chromatography

The specified operating temperature range is −40°C to +105°C.

The AD7176-2 is housed in a 24-lead TSSOP package.

FUNCTIONAL BLOCK DIAGRAM

AVDD1 AVDD2 REGCAPA REF– REF+ REFOUT

IOVDD REGCAPD

BUFFERED

PRECISION

REFERENCE

1.8V

LDO

1.8V

LDO

INT

REF

AIN0

AIN1

CS

SCLK

SERIAL

DIGITAL

FILTER

INTERFACE

AND CONTROL

Σ-Δ ADC

DIN

AIN2

DOUT/RDY

SYNC/ERROR

AIN3

XTAL AND INTERNAL

CLOCK OSCILLATOR

CIRCUITRY

I/O

CONTROL

AIN4

AD7176-2

CROSSPOINT

MULTIPLEXER

AVSS

GPIO0 GPIO1

XTAL1 CLKIO/XTAL2

DGND

Figure 1.

Rev. 0

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

AD7176-2

Data Sheet

TABLE OF CONTENTS

Serial Interface Reset (DOUT_RESET) .................................. 41

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications..................................................................................... 4

Timing Characteristics ................................................................ 7

Timing Diagrams.......................................................................... 7

Absolute Maximum Ratings............................................................ 8

Thermal Resistance ...................................................................... 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 11

Noise Performance and Resolution.............................................. 15

Getting Started................................................................................ 16

Power Supplies ............................................................................ 17

Digital Communication............................................................. 17

Configuration Overview ........................................................... 19

Circuit Description......................................................................... 23

Analog Input ............................................................................... 23

Driver Amplifiers ....................................................................... 23

AD7176-2 Reference................................................................... 26

AD7176-2 Clock Source............................................................. 27

Digital Filters................................................................................... 28

Sinc5 + Sinc1 Filter..................................................................... 28

Sinc3 Filter................................................................................... 29

Single Cycle Settling................................................................... 29

Enhanced 50 Hz and 60 Hz Rejection Filters......................... 31

Operating Modes............................................................................ 34

Continuous Conversion Mode ................................................. 34

Continuous Read Mode............................................................. 35

Single Conversion Mode ........................................................... 36

Standby and Power-Down Modes............................................ 37

Calibration Modes...................................................................... 37

Digital Interface .............................................................................. 38

Checksum Protection................................................................. 38

CRC Calculation......................................................................... 39

General-Purpose I/O ................................................................. 41

16-Bit/24-Bit Conversions......................................................... 41

Synchronization (

/

) ........................................... 41

SYNC ERROR

Error Flags................................................................................... 42

DATA_STAT ............................................................................... 42

IOSTRENGTH ........................................................................... 42

Grounding and Layout .................................................................. 43

Register Summary .......................................................................... 44

Register Details ............................................................................... 46

Communications Register......................................................... 46

Status Register............................................................................. 47

ADC Mode Register................................................................... 48

Interface Mode Register ............................................................ 49

Register Check............................................................................ 50

Data Register............................................................................... 50

GPIO Configuration Register................................................... 51

ID Register................................................................................... 52

Channel Map Register 0 ............................................................ 53

Channel Map Register 1 ............................................................ 54

Channel Map Register 2 ............................................................ 55

Channel Map Register 3 ............................................................ 56

Setup Configuration Register 0 ................................................ 57

Setup Configuration Register 1 ................................................ 57

Setup Configuration Register 2 ................................................ 58

Setup Configuration Register 3 ................................................ 58

Filter Configuration Register 0................................................. 59

Filter Configuration Register 1................................................. 60

Filter Configuration Register 2................................................. 61

Filter Configuration Register 3................................................. 62

Offset Register 0 ......................................................................... 63

Offset Register 1 ......................................................................... 63

Offset Register 2 ......................................................................... 63

Offset Register 3 ......................................................................... 63

Gain Register 0............................................................................ 64

Gain Register 1............................................................................ 64

Gain Register 2............................................................................ 64

Gain Register 3............................................................................ 64

Outline Dimensions....................................................................... 65

Ordering Guide .......................................................................... 65

Rev. 0 | Page 2 of 68

Data Sheet

AD7176-2

REVISION HISTORY

11/12—Revision 0—Initial Version

Rev. 0 | Page 3 of 68

AD7176-2

Data Sheet

SPECIFICATIONS

AVDD1 = 4.5 V to 5.5 V, AVDD2 = 2 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS,

internal master clock = 16 MHz, T_A= T_MINto T_MAX, unless otherwise noted.

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

ADC SPEED AND PERFORMANCE

Output Data Rate (ODR)

No Missing Codes¹

Resolution

5

24

250,000

SPS

Bits

See Table 6

Noise

See Table 6

Noise Free Resolution

250 kSPS, REF+ = 5 V

2.5 kSPS, REF+ = 5 V

5 SPS, REF+ = 5 V

17

20

22

Bits

ACCURACY

Integral Nonlinearity (INL)

2.5 V reference

5 V reference

2.5

7

ppm of FSR

µV

Offset Error²

Offset Drift

Offset Drift vs. Time³

Gain Error²

Gain Drift vs. Temperature¹

Gain Drift vs. Time³

40

110

450

10

0.5

3

nV/°C

nV/500 hours

ppm/FSR

ppm/FSR/°C

ppm/FSR/

500 hours

25°C

50

1

REJECTION

Power Supply Rejection

Common-Mode Rejection

At DC

AVDD1, AVDD2 V_IN= 1 V

V_IN= 0.1 V

90

dB

95

130

dB

At 50 Hz and 60 Hz¹

20 SPS ODR (post filter)

(50 Hz 1 Hz and 60 Hz 1 Hz)

50 Hz 1 Hz and 60 Hz 1 Hz

Normal Mode Rejection¹

Internal clock, 20 SPS ODR (post filter)

External clock, 20 SPS ODR (post filter)

71

85

90

dB

ANALOG INPUTS

Differential Input Voltage Range

Absolute AIN Voltage Limits¹

Analog Input Current

Input Current

V_REF

V

AVSS − 0.050

AVDD1 + 0.05

48

0.75

4

µA/V

Input Current Drift

External clock

Internal clock ( 2.5 % clock)

1 kHz input

nA/V/°C

dB

Crosstalk

−120

INTERNAL REFERENCE

100 nF external capacitor on

REFOUT to AVSS

Output Voltage

REFOUT with respect to AVSS

T_A= 25°C

2.5

V

Initial Accuracy¹

− 0.16%

−10

+ 0.16%

Temperature Coefficient

0°C to +105°C

−40°C to +105°C

I_L

2

3

5

10

+10

ppm/°C

mA

Reference Load Current, ILOAD

Power Supply Rejection (Line

Regulation)

AVDD1 and AVDD2

93

dB

Load Regulation

Voltage Noise

Voltage Noise Density

∆V_OUT/∆I_L

e_N, 0.1 Hz to 10 Hz

e_N, 1 kHz

32

4.5

215

ppm/mA

µV rms

nV/√Hz

Rev. 0 | Page 4 of 68

Data Sheet

AD7176-2

Parameter

Test Conditions/Comments

Min

Typ

60

460

25

Max

Unit

µs

ppm

mA

Turn-On Settling Time

Long-Term Stability³

Short Circuit

100 nF capacitor

500 hours

I_SC

EXTERNAL REFERENCE

Reference Input Voltage

Absolute Reference Input

Voltage Limits¹

Reference input = (REF+) – (REF−)

1

2.5

AVDD1

AVDD1 + 0.05

V

AVSS − 0.05

Average Reference Input

Current

Average Reference Input

Current Drift

72

1.2

6

µA/V

External clock

Internal clock

See the Rejection parameter section

of this table

nA/V/°C

Normal Mode Rejection¹

Common-Mode Rejection

83

dB

GENERAL-PURPOSE I/O (GPIO 0,

GPIO 1)

Output High Voltage, V_OH

With respect to AVSS

1

I_SOURCE= 200 µA

I_SINK= 800 µA

AVSS + 4

−10

V

µA

pF

1

Output Low Voltage, V_OL

AVSS + 0.4

+10

Input Mode Leakage Current¹

Floating-State Output

Capacitance

5

1

Input High Voltage, V_IH

AVSS + 3

V

1

Input Low Voltage, V_IL

AVSS + 0.7

CLOCK

Internal Clock

Frequency

Accuracy

16

MHz

%

V

−2.5

+2.5

0.4

Duty Cycle

50:50

Output Low Voltage, V_OL

Output High Voltage, V_OH

Crystal

0.8 × IOVDD

14

Frequency

16

50

16

50:50

16.384

MHz

µs

MHz

%

Start-Up Time

External Clock (CLKIO)

Duty Cycle¹

16.384

70

Typical duty cycle 50:50 (max:min)

30

LOGIC INPUTS

Input High Voltage, V_INH

1

2 V ≤ IOVDD ≤ 2.3 V

2.3 V ≤ IOVDD ≤ 5.5 V

2 V ≤ IOVDD ≤ 2.3 V

2.3 V ≤ IOVDD ≤ 5.5 V

IOVDD > 2.7 V

0.65 × IOVDD

0.7 × IOVDD

V

µA

1

Input Low Voltage, V_INL

0.35 × IOVDD

0.7

0.25

0.2

+10

Hysteresis¹

0.08

0.04

−10

IOVDD < 2.7 V

Leakage Currents

LOGIC OUTPUT (DOUT/RDY)

1

Output High Voltage, V_OH

IOVDD ≥ 4.5 V, I_SOURCE= 1 mA

2.7 V ≤ IOVDD < 4.5 V, I_SOURCE= 500 μA

IOVDD < 2.7 V, I_SOURCE= 200 μA

IOVDD ≥ 4.5 V, I_SINK= 2 mA

2.7 V ≤ IOVDD < 4.5 V, I_SINK= 1 mA

IOVDD < 2.7 V, I_SINK= 400 μA

Floating state

0.8 × IOVDD

V

µA

pF

1

Output Low Voltage, V_OL

0.4

+10

Leakage Current

Output Capacitance

−10

Floating state

10

Rev. 0 | Page 5 of 68

AD7176-2

Data Sheet

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

SYSTEM CALIBRATION¹

Full-Scale Calibration Limit

Zero-Scale Calibration Limit

Input Span

1.05 × FS

2.1 × FS

V

−1.05 × FS

0.8 × FS

POWER REQUIREMENTS

Power Supply Voltage

AVDD1 − AVSS

4.5

2

−2.75

2

5.5

0

5.5

6.35

V

AVDD2 – AVSS

AVSS – DGND

IOVDD − DGND

IOVDD – AVSS

For AVSS < DGND

POWER SUPPLY CURRENTS

All outputs unloaded, digital inputs

connected to IOVDD or DGND

Full Operating Mode

AVDD1 Current

External reference

Internal reference

External reference

Internal reference

External clock

1.5

1.75

4.3

4.5

2

1.75

2.1

4.9

5.1

2.3

2.6

mA

AVDD2 Current

IOVDD Current

Internal clock

External crystal

2.25

2.5

Standby Mode

Standby (LDO On)

Internal reference off, total current

consumption

Internal reference on, total current

consumption

Full power-down, LDO, Internal

reference

22

µA

415

0.5

Power-Down Mode

10

POWER DISSIPATION

Full Operating Mode

AVDD2 = 2 V, IOVDD = 2 V,

external clock and reference

AVDD2 = 5 V, IOVDD = 5 V,

external clock and reference

AVDD2 = 2 V, IOVDD = 2 V,

internal clock and reference

AVDD2 = 5 V, IOVDD = 5 V,

internal clock and reference

20.1

39

23.15

44.75

25.9

49

mW

22.25

42.5

Standby Mode

Internal reference off, all supplies = 5 V

Internal reference on, all supplies = 5 V

Full power-down

110

2.1

2.5

µW

mW

µW

Power-Down Mode

50

¹Specification is not production tested but is supported by characterization data at the initial product release.

²Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. A system full-scale

calibration reduces the gain error to the order of the noise for the programmed output data rate.

³The long-term stability specification is noncumulative.

Rev. 0 | Page 6 of 68

Data Sheet

AD7176-2

TIMING CHARACTERISTICS

IOVDD = 2 V to 5.5 V, DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = IOVDD, C_LOAD= 20 pF, unless otherwise noted.

Table 2.

Parameter

Limit at T_MIN, T_MAX(B Version)

Unit

Test Conditions/Comments^{1, 2}

SCLK high pulse width

t₃

t₄

25

ns min

SCLK low pulse width

READ OPERATION

t₁

0

ns min

ns max

ns min

ns max

ns min

ns max

ns min

CS falling edge to DOUT/RDY active time

IOVDD = 4.5 V to 5.5 V

IOVDD = 2 V to 3.6 V

SCLK active edge to data valid delay⁴

IOVDD = 4.5 V to 5.5 V

IOVDD = 2 V to 3.6 V

Bus relinquish time after CS inactive edge

15

40

0

12

25

2.5

20

0

3

t₂

5

t₅

t₆

t₇

SCLK inactive edge to CS inactive edge

10

SCLK inactive edge to DOUT/RDY high/low

WRITE OPERATION

t₈

0

8

5

ns min

CS falling edge to SCLK active edge setup time⁴

Data valid to SCLK edge setup time

Data valid to SCLK edge hold time

CS rising edge to SCLK edge hold time

t₉

t₁₀

t₁₁

¹Sample tested during initial release to ensure compliance.

²See Figure 2 and Figure 3.

³The time required for the output to cross the V_OLor V_OHlimits.

⁴The SCLK active edge is the falling edge of SCLK.

⁵RDY

RDY

returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while

is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the

digital word can be read only once.

TIMING DIAGRAMS

CS (I)

t₆

t₁

t₅

MSB

LSB

DOUT/RDY (O)

t₇

t₂

t₃

SCLK (I)

t₄

I = INPUT, O = OUTPUT

Figure 2. Read Cycle Timing Diagram

CS (I)

t₁₁

t₈

SCLK (I)

DIN (I)

t₉

t₁₀

MSB

LSB

I = INPUT, O = OUTPUT

Figure 3. Write Cycle Timing Diagram

Rev. 0 | Page 7 of 68

AD7176-2

Data Sheet

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

THERMAL RESISTANCE

θ_JAis specified for a device soldered on a JEDEC test board for

surface-mount packages. The values listed in Table 4 are based

on simulated data.

Table 3.

Parameter

Rating

AVDD1, AVDD2 to AVSS

AVDD1 to DGND

−0.3 V to +6.5 V

−0.3 V to +7.5 V

−3.25 V to +0.3 V

−0.3 V to AVDD1 + 0.3 V

−0.3 V to IOVDD + 0.3 V

10 mA

Table 4. Thermal Resistance

IOVDD to DGND

Package Type

θ_JA

Unit

IOVDD to AVSS

24-Lead TSSOP

JEDEC Board Layer 1

JEDEC Board Layer 2

156

87

°C/W

AVSS to DGND

Analog Input Voltage to AVSS

Reference Input Voltage to AVSS

Digital Input Voltage to DGND

Digital Output Voltage to DGND

ESD CAUTION

AIN[4:0] or Digital Input Current

Operating Temperature Range

−40°C to +105°C

−65°C to +150°C

150°C

Storage Temperature Range

Maximum Junction Temperature

Lead Soldering, Reflow Temperature

260°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. 0 | Page 8 of 68

Data Sheet

AD7176-2

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

24

23

22

21

20

19

1

2

3

4

5

6

7

8

AIN4

REF–

AIN3

AIN2

REF+

AIN1

REFOUT

REGCAPA

AVSS

AIN0

GPIO1

GPIO0

REGCAPD

DGND

IOVDD

SYNC/ERROR

CS

AD7176-2

TOP VIEW

(Not to Scale) 18

AVDD1

17

16

15

14

13

AVDD2

9

XTAL1

10

11

12

CLKIO/XTAL2

DOUT/RDY

DIN

SCLK

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

2

3

AIN4

REF−

REF+

Analog Input 4. Selectable through crosspoint multiplexer.

Reference Input Negative Terminal. REF− can span from AVSS to AVDD1 − 1 V.

Reference Input Positive Terminal. An external reference can be applied between REF+ and REF−. REF+ can

span from AVDD1to AVSS + 1 V. The part functions with a reference from 1 V to AVDD1.

4

5

6

7

8

9

REFOUT

REGCAPA

AVSS

AVDD1

AVDD2

Buffered Output of Internal Reference. The output is 2.5 V with respect to AVSS.

Analog LDO Regulator Output. Decouple this pin to AVSS using a 1 µF capacitor.

Negative Analog Supply. This supply ranges from 0 V to −2.75 V and is nominally set to 0 V.

Analog Supply Voltage 1. This voltage is 5 V 10% with respect to AVSS.

Analog Supply Voltage 2. This voltage ranges from 2 V to AVDD1 with respect to AVSS.

Input 1 for Crystal.

XTAL1

10

CLKIO/XTAL2

Clock Input or Output (Based on the CLOCKSEL Bits in the ADCMODE Register)/Input 2 for Crystal. There

are four options available:

Internal oscillator—no output.

Internal oscillator—output to CLKIO/XTAL2. Operates at IOVDD logic level.

External clock—input to CLKIO/XTAL2. Input should be at IOVDD logic level.

External crystal—connected between XTAL1 and CLKIO/XTAL2.

11

DOUT/RDY

Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data

output pin to access the output shift register of the ADC. The output shift register can contain data from

any of the on-chip data or control registers. The data-word/control word information is placed on the

DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. When CS is high, the

DOUT/RDY output is tristated. When CS is low, DOUT/RDY operates as a data ready pin, going low to

indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high

before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor,

indicating that valid data is available.

12

DIN

Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the

control registers in the ADC, with the register address (RA) bits of the communications register identifying

the appropriate register. Data is clocked in on the rising edge of SCLK.

13

14

SCLK

CS

Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt-

triggered input, making the interface suitable for opto-isolated applications.

Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC

in systems with more than one device on the serial bus. CS can be hardwired low, allowing the ADC to

operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. When CS is high, the

DOUT/RDY output is tristated.

Rev. 0 | Page 9 of 68

AD7176-2

Data Sheet

Pin No.

Mnemonic

SYNC/ERROR

Description

15

Can be switched between a logic input and a logic output in the GPIOCON register. When synchronization

input is enabled, this pin allows for synchronization of the digital filters and analog modulators when

using multiple AD7176-2 devices. When synchronization input is disabled, this pin can be used in one of

three modes:

Active low error input mode: this mode sets the ADC_ERROR bit in the STATUS register.

Active low, open-drain error output mode: the STATUS register error bits are mapped to the ERROR pin.

The ERROR pins of multiple devices can be wired together to a common pull-up resistor so that an error

on any device can be observed.

General-purpose output mode: the status of the pin is controlled by the ERR_DAT bit in the GPIOCON register.

The pin is referenced between IOVDD and DGND, as opposed to the AVDD1 and AVSS levels used by the

GPIO pins. The pin has an active pull-up in this case.

16

IOVDD

Digital I/O Supply Voltage. IOVDD voltage ranges from 2 V to 5 V. IOVDD is independent of AVDD2. For

example, IOVDDcan be operated at 3 V when AVDD2equals 5 V, or vice versa. If AVSS is set to −2.5 V, the

voltage on IOVDD must not exceed 3.6 V.

17

18

DGND

REGCAPD

Digital Ground.

Digital LDO Regulator Output. This pin is for decoupling purposes only. Decouple this pin to DGND using a

1 µF capacitor.

19

20

21

22

23

24

GPIO0

GPIO1

AIN0

AIN1

AIN2

AIN3

General-Purpose Input/Output. The pin is referenced between AVDD1 and AVSS levels.

Analog Input 0. Selectable through the crosspoint multiplexer.

Analog Input 1. Selectable through the crosspoint multiplexer.

Analog Input 2. Selectable through the crosspoint multiplexer.

Analog Input 3. Selectable through the crosspoint multiplexer.

Rev. 0 | Page 10 of 68

Data Sheet

AD7176-2

TYPICAL PERFORMANCE CHARACTERISTICS

8388358

450

400

350

300

250

200

150

100

50

8388357

8388356

8388355

8388354

8388353

0

8388354

8388356

0

100

200

300

SAMPLE

400

500

ADC CODE

Figure 5. Noise (AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V,

_REF= 5 V, Output Data Rate = 5 SPS)

Figure 8. Noise Distribution Histogram (AVDD1 = 5 V, AVDD2 = 5 V,

IOVDD = 3.3 V, V_REF= 5 V, Output Data Rate = 5 SPS)

V

8388375

8388370

8388365

8388360

8388355

8388350

8388345

8388340

8388335

8388330

800

700

600

500

400

300

200

100

0

8388336

8388348

8388360

8388372

0

2000

4000

6000

8000

8388342

8388354

8388366

SAMPLE

ADC CODE

Figure 6. Noise (AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V,

_REF= 5 V, Output Data Rate = 10 kSPS)

Figure 9. Noise Distribution Histogram (AVDD1 = 5 V, AVDD2 = 5 V,

_REF= 5 V, IOVDD = 3.3 V, Output Data Rate = 10 kSPS)

V

8388420

8388400

8388380

8388360

8388340

8388320

8388300

8388280

500

450

400

350

300

250

200

150

100

50

8388260

0

5000

10,000

SAMPLE

15,000

8388282

8388324

8388366

8388408

8388302

8388344

8388386

ADC CODE

Figure 7. Noise (AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V,

_REF= 5 V, Output Data Rate = 250 kSPS)

Figure 10. Noise Distribution Histogram (AVDD1 = 5 V, AVDD2 = 5 V,

_REF= 5 V, IOVDD = 3.3 V, Output Data Rate = 250 kSPS)

V

Rev. 0 | Page 11 of 68

AD7176-2

Data Sheet

12

0

–20

250kSPS

10

–40

8

6

4

2

–60

–80

–100

–120

–140

–160

10kSPS

1kSPS

0

5k

10k

15k

20k

25k

1

2

3

4

5

FREQUENCY (Hz)

V

(V)

CM

Figure 14. 1 kHz Input Tone, −0.5 dBFS Input FFT (AVDD1 = 5 V, AVDD2 = 5 V,

IOVDD = 3.3 V, V_REF= 2.5 V, Output Data Rate = 50 kSPS)

Figure 11. Noise vs. Common-Mode Input Voltage

(AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V, V_REF= 2.5 V)

11.0

0

–20

10.5

10.0

9.5

–40

–60

–80

–100

–120

–140

–160

9.0

8.5

8.0

–180

0

5

10

15

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (Hz)

MASTER CLOCK FREQUENCY (MHz)

Figure 12. Noise vs. Master Clock

(AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V, V_REF= 2.5 V)

Figure 15. 50 Hz Input Tone, −6 dBFS Input FFT (AVDD1 = 5 V, AVDD2 = 5 V,

IOVDD = 3.3 V, V_REF= 2.5 V, Output Data Rate = 1 kSPS)

0

–20

0

–20

–40

–60

–80

–100

–120

–140

–160

–100

–120

–140

–160

–180

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (Hz)

0

5k

10k

15k

20k

25k

FREQUENCY (Hz)

Figure 13. 50 Hz Input Tone, −0.5 dBFS Input FFT (AVDD1 = 5 V, AVDD2 = 5 V,

IOVDD = 3.3 V, V_REF= 2.5 V, Output Data Rate = 1 kSPS)

Figure 16. 1 kHz Input Tone, −6 dBFS Input FFT (AVDD1 = 5 V, AVDD2 = 5 V,

IOVDD = 3.3 V, V_REF= 2.5 V, Output Data Rate = 50 kSPS)

Rev. 0 | Page 12 of 68

Data Sheet

AD7176-2

0

–20

–40

–60

–80

–100

–120

–140

–160

–100

–120

–140

–160

0

20k

40k

60k

80k

100k

120k

10

20

30

40

50

60

70

FREQUENCY (Hz)

Figure 17. 1 kHz Input Tone, −0.5 dBFS Input FFT (AVDD1 = 5 V, AVDD2 = 5 V,

IOVDD = 3.3 V, V_REF= 2.5 V, Output Data Rate = 250 kSPS)

Figure 20. Common-Mode Rejection Ratio (10 Hz to 70 Hz)

(AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V, 20 SPS Enhanced Filter)

0

–20

1.0

–40

0.5

FROM POWER-DOWN

–60

–80

0

FROM STANDBY – REFERENCE OFF

–100

–120

–140

–160

–0.5

–1.0

0.00001

0

20k

40k

60k

80k

100k

120k

0.0001

0.001

0.01

0.1

FREQUENCY (Hz)

TIME (Seconds)

Figure 18. 1 kHz Input Tone, −6 dBFS Input FFT (AVDD1 = 5 V, AVDD2 = 5 V,

IOVDD = 3.3 V, V_REF= 2.5 V, Output Data Rate = 250 kSPS)

Figure 21. Internal Reference Settling Time

(AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V)

0.10

0.05

0

–20

–40

–60

–80

0

–0.05

–0.10

–100

–120

0

10

20

30

40

50

1

10

100

1k

10k

100k

1M

TIME (Seconds)

FREQUENCY (Hz)

Figure 19. Internal Reference Settling Time (Extended)

(AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V)

Figure 22. Common-Mode Rejection Ratio vs. Frequency

(AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V, Output Data Rate = 250 kSPS)

Rev. 0 | Page 13 of 68

AD7176-2

Data Sheet

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–140

–150

–160

1

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 23. Power Supply Rejection Ratio vs. Frequency

(AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V)

Rev. 0 | Page 14 of 68

Data Sheet

AD7176-2

NOISE PERFORMANCE AND RESOLUTION

Table 6 shows the rms noise and the noise free (peak-to-peak)

resolution of the AD7176-2 for various output data rates and

filters. The numbers given are for the bipolar input range with

an external 5 V reference.

on a single channel. It is important to note that the peak-to-

peak resolution is calculated based on the peak-to-peak noise.

The peak-to-peak resolution represents the resolution for which

there is no code flicker.

These numbers are typical and are generated with a differential

input voltage of 0 V when the ADC is continuously converting

Table 6. RMS Noise and Peak-to-Peak Resolution vs. Output Data Rate¹

Sinc5 + Sinc1 Filter (Default)

Sinc3 Filter

Output Data Rate (SPS)

Noise (µV rms)

Peak-to-Peak Resolution (Bits) Noise (µV rms)

Peak-to-Peak Resolution (Bits)

250,000

62,500

10,000

1000

60

50

16.7

5

9.7

5.4

2.5

0.82

0.46

0.42

0.32

17.2

18.2

19

20.8

21.4

21.7

22.2

220

5.1

1.8

0.62

0.32

0.31

0.29

12.8

18.3

19.8

21

22

22.4

¹Selected rates only, 1000 samples.

Rev. 0 | Page 15 of 68

AD7176-2

Data Sheet

GETTING STARTED

The AD7176-2 offers the user a fast settling, high resolution,

multiplexed ADC with high levels of configurability.

The AD7176-2 includes a precision 2.5 V low drift (2 ppm/°C)

band gap internal reference. This reference can be selected to

be used for the ADC conversions, reducing the external com-

ponent count. Alternatively, the reference can be output to the

REFOUT pin to be used as a low noise biasing voltage for the

external circuitry. An example of this is using the REFOUT

signal to set the input common mode for an external driving

amplifier.

•

Two fully differential or four single-ended analog inputs.

Crosspoint multiplexer selects any analog input combina-

tion as the input signals to be converted, routing them to

the modulator positive or negative input.

•

Fully differential input, single-ended relative to any analog

input and pseudo differential configuration available.

Per channel configurability—up to four different setups

can be defined. A separate setup can be mapped to each of

the channels. Each setup allows the user to configure:

The AD7176-2 includes two separate linear regulator blocks for

both the analog and digital circuitry. The analog LDO regulates

the AVDD2 supply to 2 V supplying the ADC core. The user

can tie the AVDD1 and AVDD2 supplies together for easiest

connection. If there is already a clean analog supply rail in the

system in the range of 2 V to 5 V, the user can also choose to

connect this to the AVDD2 input, allowing for lower power

dissipation.

•

Gain and offset correction

Filter type

Output data rate

Reference source selection (internal/external)

GENERAL PURPOSE IO

0 AND 1

GPIO 0

OUTPUT HIGH = AVDD

OUTPUT LOW = AVSS

FOR SINGLE SUPPLY

CASE OUTPUT HIGH = 5V

OUTPUT LOW = GND

GPIO 1

16MHz

20

19

GPIO 0

GPIO 1

CX2

CX1

SEE ANALOG INPUT SECTION FOR FURTHER DETAILS

OPTIONAL EXTERNAL

CRYSTAL CIRCUITRY

CAPACITORS

9

XTAL1

21

AIN0

IN0

CLKI0/XTAL2 10

DOUT/RDY 11

CLKIN

OPTIONAL

EXTERNAL

CLOCK

DOUT/RDY

DIN

22

23

AIN1

AIN2

INPUT

IN1

IN2

12

DIN

13

SCLK

CS

SCLK

14

15

CS

IN3

SYNC/ERROR

IOVDD

24

1

AIN3

AIN4

AD7176-2

AIN4

IN4

16

17

IOVDD

DGND

0.1µF

VIN

1

3

REGCAPD 18

2

4

7

6

V

NC

IN

0.1µF

1µF

AVDD1

4.7µF

0.1µF

ADR445BRZ

AVDD1

AVDD2

7

8

5

0.1µF

3

GND

5

VOUT

8

REF+

REF–

AVDD2

0.1µF

4.7µF

0.1µF

2

4

0.1µF

REFOUT

REGCAPA

2.5V REFERENCE

OUTPUT

0.1µF

1µF

AVSS

6

Figure 24. Typical Connection Diagram

Rev. 0 | Page 16 of 68

Data Sheet

AD7176-2

The linear regulator for the digital IOVDD supply performs a

similar function, regulating the input voltage applied at the

IOVDD pin to 2 V for the internal digital filtering. The serial

interface signals always operate from the IOVDD supply seen at

the pin. This means that if 3.3 V is applied to the IOVDD pin,

the interface logic inputs and outputs operate at this level.

Accessing the ADC Register Map

The communications register controls access to the full register

map of the ADC. This register is an 8-bit write only register. On

power-up or after a reset, the digital interface defaults to a state

where it is expected a write to the communications register;

therefore, all communication begins by writing to the

communications register.

The AD7176-2 can be used across a wide variety of applications,

providing high resolution and accuracy. A sample of these

scenarios is as follows:

The data written to the communications register determines

which register is being accessed and if the next operation is a

read or write. The register address bits (RA[5:0]) determine the

specific register to which the read or write operation applies.

•

Fast scanning of analog input channels using the internal

multiplexer.

Fast scanning of analog input channels using an external

multiplexer.

High resolution at lower speeds in either channel scanning

or ADC per channel applications.

Single ADC per channel: the fast low latency output allows

further application specific filtering in an external micro-

controller, DSP, or FPGA.

When the read or write operation to the selected register is

complete, the interface returns to its defaults state, where it

expects a write operation to the communications register.

In situations where interface synchronization is lost, a write

operation of at least 64 serial clock cycles with DIN high returns

the ADC to its default state by resetting the entire part, including

the register contents. Alternatively, if

is being used with the

CS

high sets the digital interface to

digital interface, returning

CS

POWER SUPPLIES

its default state and aborts any current operation.

The AD7176-2 has three independent power supply pins:

AVDD1, AVDD2, and IOVDD.

Figure 26 and Figure 27 illustrate writing to and reading from a

register by first writing the 8-bit command to the communications

register followed by the data for that register.

8 BITS, 16 BITS,

AVDD1 powers the front-end circuitry, including the crosspoint

multiplexer. AVDD1 is referenced to AVSS and AVDD1 − AVSS

= 5 V only. This can be a single 5 V supply or a 2.5 V split

supply. The split supply operation allows for true bipolar inputs.

When using split supplies, the absolute maximum ratings (see

the Absolute Maximum Ratings section) must be kept in mind.

8-BIT COMMAND

OR 24 BITS OF DATA

CS

AVDD2 powers the internal 1.8 V analog LDO regulator. This

regulator powers the ADC core. AVDD2 is referenced to AVSS,

and AVDD2 – AVSS can range from 5 V to 2 V.

CMD

DATA

DIN

SCLK

IOVDD powers the internal 1.8 V digital LDO regulator. This

regulator powers the digital logic of the ADC. IOVDD sets the

voltage levels for the SPI interface of the ADC. IOVDD is refer-

enced to DGND, and IOVDD − DGND can vary from 5 V to 2 V.

Figure 26. Writing to a Register

(8-Bit Command with Register Address Followed by Data of 8, 16, or 24 Bits;

Data Length Is Dependent on the Register Selected)

DIGITAL COMMUNICATION

8 BITS, 16 BITS,

24 BITS, OR

32 BITS OF DATA

The AD7176-2 has a 3- or 4-wire SPI interface that is compatible

with QSPI™, MICROWIRE®, and DSPs. The interface operates

in SPI Mode 3 and can be operated with

8-BIT COMMAND

CS

tied low. In SPI

CS

Mode 3, the SCLK idles high, the falling edge of SCLK is the

drive edge, and the rising edge of SCLK is the sample edge. This

means that data is clocked out on the falling/drive edge and data

is clocked in on the rising/sample edge.

CMD

DIN

DOUT/RDY

DATA

DRIVE EDGE

SAMPLE EDGE

SCLK

Figure 27. Reading from a Register

(8-Bit Command with Register Address Followed by Data of 8, 16, or 24 Bits;

Data Length on DOUT Is Dependent on the Register Selected)

Figure 25. SPI Mode 3 SCLK Edges

Rev. 0 | Page 17 of 68

AD7176-2

Data Sheet

Reading the ID register is the recommended method for verifying

correct communication with the part. The ID registers is a read

only register and contains the value 0x0C9X for the AD7176-2.

The communication register and ID register details are described

in Table 7 and Table 8.

Table 7. Communications Register

Reg

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

RW

0x00

COMMS

[7:0]

WEN

R/W

RA

0x00

W

Table 8. ID Register

Reg

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

0x0C9X

RW

0x07

ID

[15:8]

[7:0]

ID[15:8]

ID[7:0]

R

Rev. 0 | Page 18 of 68

Data Sheet

AD7176-2

CONFIGURATION OVERVIEW

Figure 28 provides an overview of the configuration flow,

divided into the following three blocks:

•

ADC and interface mode configuration (labeled A in

Figure 28)

•

ADC setups (labeled B in Figure 28)

Channel map configuration (labeled C in Figure 28)

WRITE TO ADC MODE REGISTER AND INTERFACE MODE REGISTER;

A

B

SET UP HIGH LEVEL ADC PERIPHERALS AND INTERFACE

SET UP CONFIGURATION;

FOUR POSSIBLE ADC SETUPS USING DEDICATED

FILTER, OFFSET, AND GAIN REGISTERS

SELECT THE POSITIVEAND NEGATIVE INPUT FOR EACH

ADC CHANNEL AND MAP EACH CHANNEL TO A SETUP

C

Figure 28. Configuration Flow

Rev. 0 | Page 19 of 68

AD7176-2

Data Sheet

ADC and Interface Mode Configuration

enable bits. The reference select bits are contained in the setup

configuration registers (see the ADC Setups section for more

information).

The ADC mode register and the interface mode register (see

Block A in Figure 28) configure the core peripherals to be used

by the AD7176-2 and the mode for the digital interface.

Interface Mode Register

ADC Mode Register

The interface mode register is used to configure the digital interface

operation. This register allows the user to control data-word length,

CRC enable, data + status read and continuous read mode.

The ADC mode register is used primarily to set the conversion

mode of the ADC to either continuous or single conversion.

The user can also select the standby and power-down modes as

well as any of the calibration modes. In addition, this register

contains the clock source select bits and the internal reference

Both register details are shown in Table 9 and Table 10. For

more information, see the Digital Interface section.

Table 9. ADC Mode Register

Reg

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESERVED

Bit 2

CLOCKSEL

Bit 1

DELAY

RESERVED

Bit 0

Reset

RW

0x01 ADCMODE [15:8] REF_EN

RESERVED SING_CYC

MODE

0x8000 RW

[7:0]

RESERVED

Table 10. Interface Mode Register

Reg

Name

Bits

Bit 7

Bit 6

RESERVED

CONTREAD DATA_STAT REG_CHECK RESERVED

Bit 5

Bit 4

ALT_SYNC IOSTRENGTH

CRC_EN

Bit 3

Bit 2

Bit 1

RESERVED

RESERVED WL16

Bit 0

Reset

RW

0x02 IFMODE

[15:8]

[7:0]

DOUT_RESET 0x0000 RW

Rev. 0 | Page 20 of 68

Data Sheet

AD7176-2

reference, an external reference connected between REF+ and

REF− pins, or AVDD1 – AVSS.

ADC Setups

The AD7176-2 has four independent setups (see Block B in

Figure 28). Each setup consists of the following four registers:

Filter Configuration Register

The filter configuration register is used to select which digital

filter is used at the output of the ADC modulator. The order of

the filter and the output data rate is selected by setting the bits

in this register. For more information, see the Digital Filters section.

•

Setup configuration register

Filter configuration register

Offset register

Gain register

Offset Register

For example, Setup 0 consists of Setup Configuration 0, Filter

Configuration 0, Offset 0, and Gain 0. The setup is selectable

from the channel map registers detailed in the Channel Map

Configuration section. This allows each channel to be assigned

to a separate setup; therefore, each channel is fully configurable

because each setup has its own filter, offset, and gain register.

Table 11 through Table 14 show the four registers that are

associated with Setup 0.

The offset register holds the offset calibration coefficient for the

ADC. The power-on reset value of the offset register is 0x800000.

The offset register is a 24-bit read/write register. The power-on

reset value is automatically overwritten if an internal or system

zero-scale calibration is initiated by the user or if the offset register

is written to by the user.

Gain Register

Setup Configuration Register

The gain register is a 24-bit register that holds the gain

calibration coefficient for the ADC. The gain registers are

read/write registers. These registers are configured at power-on

with factory calibrated coefficients. Therefore, every device has

different default coefficients. The default value is automatically

overwritten if a system full-scale calibration is initiated by the

user or if the gain register is written to by the user. For more

information on calibration, see the Operating Modes section.

The setup configuration registers allow the user to select the output

coding of the ADC by selecting between bipolar and unipolar. In

bipolar mode, the ADC accepts negative differential input voltages,

and the output coding is offset binary. In unipolar mode, the ADC

accepts only positive differential voltages, and the coding is straight

binary. In either case, the input voltage must be within the supply

voltages. The user can also select the reference source using this

register. There are three options available—an internal 2.5 V

Table 11. Setup Configuration 0 Register

Reg Name

Bits Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

RESERVED

Bit 0

Reset RW

0x20 SETUPCON0 [15:8]

[7:0]

RESERVED

BI_UNIPOLAR0

0x1020 RW

RESERVED

REF_SEL0

Table 12. Filter Configuration 0 Register

Reg Name

Bits Bit 7

Bit 6

Bit 5

RESERVED

ORDER0

Bit 4

Bit 3

Bit 2

Bit 1

Reset RW

0x28 FILTCON0

[15:8] SINC3_MAP0

[7:0] RESERVED

ENHFILTEN0

ENHFILT0

0x0000 RW

ODR0

Table 13. Offset 0 Register

Reg Name

0x30 OFFSET0

Bits Bit 7

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

RW

[23:16]

[15:8]

[7:0]

OFFSET0[23:16]

OFFSET0[15:8]

OFFSET0[7:0]

0x800000 RW

Table 14. Gain 0 Register

Reg Name

Bits Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

GAIN0[23:16]

GAIN0[15:8]

GAIN0[7:0]

Bit 2

Bit 0

Reset

RW

0x38 GAIN0

[23:16]

[15:8]

[7:0]

0x5XXXX0 RW

Rev. 0 | Page 21 of 68

AD7176-2

Data Sheet

contains a channel enable/disable bit and the setup selection

bits, which are used to pick which of the four available setups

are used for this channel.

Channel Map Configuration

The AD7176-2 has four independent channels (see Block C in

Figure 28). The user can select which of the four setups is used

for each channel. This allows for per channel configuration.

When the AD7176-2 is operating in continuous conversion

mode with more than one channel enabled, the channel

sequencer cycles through the enabled channels in sequential

order, from Channel Map 0 to Channel Map 3. If a channel is

disabled, it is skipped by the sequencer. Details of the channel

map register for Channel 0 are shown in Table 15.

Channel Map Register

The channel map register is used to select which of the five

analog input pins are used as either the positive analog input or

the negative analog input for that channel. This register also

Table 15. Channel Map Register

Reg Name

Bits Bit 7

[15:8] CH_EN0

[7:0]

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset RW

0x10 CHMAP0

RESERVED

AINPOS0[2:0]

SETUP_SEL0

RESERVED

AINPOS0[4:3]

0x8001 RW

AINNEG0

Rev. 0 | Page 22 of 68

Data Sheet

AD7176-2

CIRCUIT DESCRIPTION

ANALOG INPUT

Fully Differential Inputs

Because the AIN0 to AIN4 analog inputs are connected to a

crosspoint multiplexer, any combination of signals can be used

to create an analog input pair. This allows the user to select two

fully differential inputs or four pseudo differential inputs.

The AD7176-2 has five analog input pins: AIN0, AIN1, AIN2,

AIN3, and AIN4. Each of these pins connects to the internal

crosspoint multiplexer. The crosspoint multiplexer enables any of

these inputs to be configured as an input pair, either pseudo

differential or fully differential. The AD7176-2 can have up to four

active channels. When more than one channel is enabled, the

channels are automatically sequenced in order. The output of

the multiplexer is connected directly to the switched-capacitor

input of the ADC. The simplified analog input circuit is shown in

Figure 29.

If two fully differential input paths are connected to the AD7176-2,

using AIN0/AIN1 as one differential input pair and AIN2/AIN3

as the second differential input pair is recommended. This is

due to the relative locations of these pins to each other. All

analog inputs should be decoupled to AVSS.

Pseudo Differential Inputs

AVDD1

The user can also choose to measure four different single-ended

analog inputs. In this case, each of the analog inputs is converted

as being the difference between the single-ended input to be

measured and a set analog input common pin. Because there is

a crosspoint multiplexer, the user can set any of the analog inputs

as the common pin. An example of such a scenario is to connect

the AIN4 pin to AVSS or to the REFOUT voltage (that is, AVSS

+ 2.5 V) and select this input when configuring the crosspoint

multiplexer. When using the AD7176-2 with pseudo differential

inputs, the INL specification is degraded.

AIN0

AVSS

AVDD1

Ø1

+IN

AIN1

CS1

AVSS

AVDD1

Ø2

AIN2

CS2

AVSS

DRIVER AMPLIFIERS

AVDD1

AVSS

–IN

Ø1

To drive the analog input switch capacitor, an external amplifier

is required. Details of three recommended amplifiers for the

AD7176-2 are shown in the Driver Amplifiers section. Each of

the amplifiers can run from a single 5 V voltage rail.

AIN3

AIN4

AVDD1

AVSS

Figure 29. Simplified Analog Input Circuit

The CS1 and CS2 capacitors have a magnitude in the order of a

number of picofarads each. This capacitance is the combination

of both the sampling capacitance and the parasitic capacitance.

The average input current to the AD7176-2 changes linearly with

the differential input voltage at a rate of 48 µA/V. Each of the

analog inputs must be buffered externally not only to provide

the varying input current with differential input amplitude but

also to settle the switched-capacitor input to allow for accurate

sampling.

Recommended amplifiers for this purpose are discussed in the

Driver Amplifiers section.

Rev. 0 | Page 23 of 68

AD7176-2

Data Sheet

AD8475

with a fixed common mode of 2.5 V. The output of the AD8475

amplifier is connected to an RC network. The RC network, as

shown in Figure 30, includes R_IN= 10 Ω; C1, C2 = 270 pF; and

C3 = 680 pF. The RC circuit acts to provide the dynamic charge

required by the AD7176-2 switched sampling capacitors while

isolating the amplifier output from any kickback from the

dynamic switched capacitor input. The configuration of the

AD8475 in Figure 30 shows a fully differential signal source

with a gain of 0.4×.

The AD8475 features an attenuating input stage of 0.8× or 0.4×

(using integrated precision resistors), allowing inputs in the 10 V

range with a single 5 V supply and a 3 mA current consumption

to be used. The AD8475 performs single-ended to differential

conversions, allows easy setting of the common-mode output,

and drives the AD7176-2 with a differential input.

Figure 30 shows a typical connection to the AD7176-2, where

two AD8475 amplifiers attenuate two differential inputs and

then drive the AD7176-2 inputs. The common-mode output of

the AD8475 is set by connecting the internal, buffered 2.5 V

reference of the AD7176-2 to the VOCM pin of the AD8475.

The output of the AD8475 to the AD7176-2 is fully differential

The AD8475 can also be set up to convert single-ended signals

to fully differential inputs. Ground the −IN 0.4× input and

apply the single-ended input to the +IN 0.4× input.

+5V

0.1µF

+5V

0.1µF

6

0.1µF

7

8

AVSS AVDD1 AVDD2*

AIN0

AD8475

R

IN0

IN1

IN

–IN 0.4x

+IN 0.4x

21

±12.5V

LOW IMPEDANCE

VOLTAGE

C1

C2

C3

AD7176-2

SOURCE

22

4

AIN1

VOCM

R

IN

13

12

11

SCLK

DIN

2.5V

REFOUT

AIN2

MICROCONTROLLER

HOST

0.1µF

DOUT/RDY

IN2

IN3

IN

+IN 0.4x

–IN 0.4x

23

24

14

CS

±12.5V

LOW IMPEDANCE

VOLTAGE

C1

C2

C3

SOURCE

AIN3

IN

AD8475

+5V

REF–

REF+

2

3

0.1µF

5.5V TO 18V

0.1µF

4.7µF

ADR445

5V VREF

0.1µF

*AVDD2 CAN BE SUPPLIED BY VOLTAGES RANGING FROM 2V TO 5.5V.

Figure 30. AD8475 Driving Two Differential Inputs of the AD7176-2

Rev. 0 | Page 24 of 68

Data Sheet

AD7176-2

AD8656

To improve accuracy, use precision resistors for R_Gand R_F.

Setting R_G= R_F= 1 kΩ results in a gain of 2 for the circuit. The

matching of the RG and RF resistors directly affects the gain

error of the circuit. The drift and matching of these resistors

affect the gain error drift of the circuit. A 10 Ω source resistor (R_S)

is placed between the feedback resistor (R_F) and the amplifier

output. This resistor acts to isolate the amplifier from any

kickback from the ADC input and does not directly affect the

gain error of the circuit.

The AD8656 is a low noise, dual precision CMOS amplifier. The

AD8656 allows the user to connect a signal of interest directly

to a high impedance, low noise, low offset amplifier input that

can drive the AD7176-2 switched capacitor input. The AD8656

can operate from a single 5 V supply. When using an external

5 V reference such as the ADR445 in conjunction with the

AD7176-2, the AD8656 output can swing to within −1 dBFS

(which equates to a differential input of 4.45 V) of the ADC

input range.

The output of each of the amplifier pairs is connected directly

to a network of decoupling and differential capacitors prior to

being connected to the AD7176-2 analog inputs. The capacitor

network shown in Figure 31 includes C1, C2 = 270 pF and C3 =

680 pF. The capacitor network acts to provide the dynamic charge

required by the AD7176-2 switched sampling capacitors.

A simple configuration for use of the AD8656 is to connect the

amplifiers in a configuration for a gain of more than 1. Each of

the AD7176-2 analog inputs has its own amplifier. This allows

the user to connect either fully differential inputs or single-ended

inputs to the AD7176-2. The example shown in Figure 31 is

configured with two fully differential inputs connecting to the

AIN0/AIN1 pair and the AIN2/AIN3 pair.

The circuit example in Figure 31 requires inclusion of two

precision gain resistors per amplifier (R_Gand R_F). Choose the

value, precision, and matching of such resistors according to the

requirements of the application.

The high impedance input to the amplifier allows the user to

band-limit the input with a suitable passive filter RC combination.

The gain of the configuration used is set by the R_Gand R_Fresistors.

+5V

0.1µF

6

0.1µF

7

8

R

G

F

1

AVSS AVDD1 AVDD2

AIN0

IN0

IN1

0 TO +2.5V

R

21

22

S

INPUT RANGE

C1

C2

AD7176-2

AD8656

R

C3

S

0 TO +2.5V

INPUT RANGE

AIN1

R

G

F

13

12

11

SCLK

DIN

MICROCONTROLLER

HOST

DOUT/RDY

CS

R

G

F

14

IN2

IN3

0 TO +2.5V

S

23

24

INPUT RANGE

AIN2

AIN3

C1

C2

AD8656

C3

R

S

0 TO +2.5V

INPUT RANGE

REF–

REF+

3

2

R

F

G

5.5V TO 18V

0.1µF

4.7µF

0.1µF

ADR445²

5V VREF

0.1µF

+5V

1

2

AVDD2 CAN BE SUPPLIED BY VOLTAGES RANGING FROM 2V TO 5.5V.

USING ADR444 (4.096V REFERENCE) IN PLACE OF THE ADR445 AS SHOWN IN THIS

EXAMPLE WOULD ALLOW THE ENTIRE CCT TO BE OPERATED FROM A SINGLE 5V SUPPLY RAIL.

Figure 31. Dual AD8656 Amplifiers Driving the AD7176-2

Rev. 0 | Page 25 of 68

AD7176-2

Data Sheet

ADA4940

are recommended for use. The external reference should be

applied to the AD7176-2 reference pins as shown in Figure 32.

The output of any external reference should be decoupled to

AVSS. As shown in Figure 32, the ADR445 output is decoupled

with a 0.1 µF capacitor at its output for stability purposes. The

output is then connected to a 4.7 µF capacitor, which acts as a

reservoir for any dynamic charge required by the ADC, and

followed by a 0.1 µF decoupling capacitor at the REF+ input.

This capacitor is placed as close as possible to the REF+ and

REF− pins. The REF− pin is connected directly to the AVSS

potential. On power-up of the AD7176-2, the internal reference

is enabled by default and is output on the REFOUT pin. When

an external reference is used instead of the internal reference to

supply the AD7176-2, attention must be paid to the output of

the REFOUT pin. If the internal reference is not being used

elsewhere in the application, ensure that the REFOUT pin is not

hardwired to AVSS because this will draw a large current on

power-up. On power-up if the internal reference is not being

used, write to the ADC mode register, disabling the internal

reference. This is controlled by the REF_EN bit (Bit 15) in the

ADC mode register and is shown in Table 17.

The ADA4940-1/ADA4940-2 is an alternate option to drive

the AD7176-2. It is a low noise, low distortion fully differential

amplifier with very low power consumption (1.25 mA of quiescent

current). The AD7176-2 REFOUT pin can be used to connect

to the ADA4940-1/ADA4940-2 to set the common-mode output

to 2.5 V. This option requires the use of external resistors to set

the gain of the amplifier.

AD7176-2 REFERENCE

The AD7176-2 offers the user the option of either supplying an

external reference to the REF+ and REF− pins of the device or

allowing the use of the internal 2.5 V, low noise, low drift reference.

Select the reference source to be used by the analog input by setting

the REF_SELx bits (Bits[5:4]) in the setup configuration registers

appropriately. The structure of the Setup Configuration 0 register

is shown in Table 16. The AD7176-2 defaults on power-up to

use the internal 2.5 V reference.

External Reference

The AD7176-2 has a fully differential reference input applied

through the REF+ and REF− pins. Standard low noise, low drift

voltage references, such as the ADR445, ADR444, and ADR441,

AD7176-2

5.5V TO 18V

ADR445²

3

2

REF+

REF–

0.1µF

1

5V VREF

1

0.1µF

4.7µF

0.1µF

1

2

ALL DECOUPLING IS TO AVSS.

ANY OF THE ADR44x FAMILY REFERENCES MAY BE USED.

ADR444 OR ADR441 BOTH ENABLE REUSE OF THE 5V ANALOG SUPPLY

NEEDED FOR AVDD1 TO POWER THE REFERENCE VIN.

Figure 32. External Reference ADR445 Connected to AD7176-2 Reference Pins

Table 16. Setup Configuration 0 Register

Reg Name

Bits Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

RESERVED

Bit 0

Reset RW

0x20 SETUPCON0 [15:8]

[7:0]

RESERVED

BI_UNIPOLAR0

0x1020 RW

RESERVED

REF_SEL0

Table 17. ADC Mode Register

Reg Name

Bits Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Reset RW

0x01 ADCMODE [15:8] REF_EN

[7:0] RESERVED

RESERVED SING_CYC

MODE

RESERVED

DELAY

RESERVED

0x8000 RW

CLOCKSEL

Rev. 0 | Page 26 of 68

Data Sheet

AD7176-2

Internal Reference

introduced by the output driver. The extent to which the

performance is affected depends on the IOVDD voltage supply.

Higher IOVDD voltages create a wider logic output swing from

the driver and affect performance to a greater extent. This is

further exaggerated if the IOSTRENGTH bit is set at higher

IOVDD levels (see Table 25 for more information).

The AD7176-2 includes its own low noise, low drift voltage

reference. The internal reference has a 2.5 V output. The internal

reference is output on the REFOUT pin after the REF_EN bit in

the ADC mode register is set and is decoupled to AVSS with a

0.1 µF capacitor. The AD7176-2 internal reference is enabled by

default on power-up and is selected as the reference source for

the ADC.

External Crystal

If higher precision, lower jitter clock sources are required, the

AD7176-2 has the ability to use an external crystal to generate

the master clock. The crystal is connected to the XTAL1 and

XTAL2 pins. A recommended crystal for use is the FA-20H—a

16 MHz, 10 ppm, 9 pF crystal from Epson-Toyocom—which is

available in a surface-mounted package. As shown in Figure 33,

allow for two capacitors to be inserted from the traces

connecting the crystal to the XTAL1 and XTAL2 pins. These

capacitors allow for circuit tuning. Connect these capacitors to

the DGND pin. The value for these capacitors depends on the

length and capacitance of the trace connections between the

crystal and the XTAL1 and XTAL2 pins. Therefore, the values

of these capacitors differ depending on the PCB layout and the

crystal employed. As a result, empirical testing of the circuit is

required.

The REFOUT signal is buffered prior to being output to the pin.

The signal can be used externally in the circuit as a common-mode

source for external amplifier configurations. This is shown in

Figure 30 in the Driver Amplifiers section, where the REFOUT pin

supplies the VOCM input of the AD8475 amplifier.

AD7176-2 CLOCK SOURCE

The AD7176-2 requires a master clock of 16 MHz. The AD7176-2

can source its sampling clock from one of three scenarios:

•

Internal oscillator

External crystal

External clock source

All output data rates listed in the data sheet relate to a master

clock rate of 16 MHz. Using a lower clock frequency from, for

instance, an external source will scale any listed data rate

proportionally. To achieve the specified data rates, particularly

rates for rejection of 50 Hz and 60 Hz, a 16 MHz clock should

be used. The source of the master clock is selected by setting the

CLOCKSEL bits (Bits[3:2]) in the ADC mode register as shown

in Table 17. The default operation on power-up and reset of the

AD7176-2 is to operate with the internal oscillator.

AD7176-2

Cx1

*

9

XTAL1

CLKIO/XTAL2 10

Cx2

*

*DECOUPLE TO DGND.

Figure 33. External Crystal Connections

Internal Oscillator

External Clock

The internal oscillator runs at 16 MHz and can be used as the

ADC master clock. It is the default clock source for the AD7176-2

and is specified with an accuracy of 2.5%.

The AD7176-2 can also use an externally supplied clock. In

systems where this is desirable, the external clock is routed to

the CLKIO pin. In this configuration, the CLKIO pin accepts

the externally sourced clock and routes it to the modulator. The

logic level of this clock input is defined by the voltage applied to

the IOVDD pin.

There is an option to allow the internal clock oscillator to be

output on the AD7176-2 CLKIO/XTAL2 pin. The clock output

is driven to the IOVDD logic level. Use of this option can affect

the dc performance of the AD7176-2 due to the disturbance

Rev. 0 | Page 27 of 68

AD7176-2

Data Sheet

DIGITAL FILTERS

to control the final ADC output data rate. Figure 35 shows the

frequency domain response of the Sinc5 + Sinc1 filter at a 50 SPS

output data rate. The Sinc5 + Sinc1 filter has a slow roll-off over

frequency and narrow notches.

The AD7176-2 has three flexible filter options to allow for

optimization of noise, settling time, and rejection:

•

Sinc5 + Sinc1 filter

Sinc3 filter

Enhanced 50 Hz and 60 Hz rejection filters

0

–20

–40

50Hz AND 60Hz

POST FILTER

SINC1

SINC5

SINC3

–60

Figure 34. Digital Filter Block Diagram

–80

The filter and output data rate is configured by setting the

appropriate bits in the filter configuration register for the

selected setup. See the Register Details section for more

information.

–100

–120

0

50

100

FREQUENCY (Hz)

150

SINC5 + SINC1 FILTER

Figure 35. Sinc5 + Sinc1 Filter Response at 50 SPS ODR

The Sinc5 + Sinc1 filter is targeted at fast switching multiplexed

applications and achieves single cycle settling at output data rates of

10 kSPS and lower. The Sinc5 block output is fixed at the maximum

rate of 250 kSPS, and the Sinc1 block output data rate can be varied

The output data rates with the accompanying settling time and

rms noise for the Sinc5 + Sinc1 filter are shown in Table 18.

Table 18. AD7176-2 Output Data Rate (ODR), Noise, Settling Time (t_SETTLE), and Rejection Using the Sinc5 + Sinc1 Filter

Output Data

Settling

Switching Rate Notch Frequency Rejection 1 Hz

Noise

Peak-to-Peak Resolution

Rate (SPS)¹

Time¹

(Hz)¹

50,000

41,667

31,250

27,778

20,833

17,857

12,500

10,000

5000

(Hz)

(dB)²

(µV rms) with 5 V Reference (Bits)

250,000

125,000

62,500

50,000

31,250

25,000

15,625

10,000

5000

2500

1000

500

400

200

100

60

50

20

16.667

10

5

20 µs

24 µs

32 µs

36 µs

48 µs

56 µs

80 µs

100 µs

200 µs

400 µs

1.0 ms

2.0 ms

2.516 ms

5.0 ms

10.0 ms

16.68 ms

20.016 ms

50.0 ms

60.02 ms

100.02 ms

200.02 ms

250,000

125,000

62,500

50,000

31,250

25,000

15,625

11,905

5435

9.7

7.4

5.4

5

4

3.6

2.7

2.5

17.25

17.6

18.1

18.2

18.5

18.7

19.1

19.2

19.7

20.2

20.8

21.2

21.6

21.7

21.8

22

1.8

1.3

2500

2604

1000

1016

0.82

0.63

0.62

0.47

0.46

0.43

0.42

500.0

400

200.0

100.0

460

504

400.00

200.64

100.16

60.00

50.00

20.01

16.67

10.00

5.00

34 dB (60 Hz)

34 dB (50 Hz)

50

20.00

16.66

10.00

5.00

34 dB (50 Hz and 60 Hz) 0.38

0.32

22.1

¹The settling time has been rounded to the nearest microsecond. This is reflected in the output data rate and switching rate. Switching rate = 1 ÷ tSETTLE.

²Master clock = 160 MHz.

Rev. 0 | Page 28 of 68

Data Sheet

AD7176-2

For example, an output data rate of 50 SPS can be achieved with

SINC3_MAP enabled by setting the FILTCONx[14:0] bits to a

value of 5000.

SINC3 FILTER

The Sinc3 filter achieves the best single-channel noise performance

at lower rates and is, therefore, most suitable for single-channel

applications. The Sinc3 filter always has a settling time equal to

SINGLE CYCLE SETTLING

t

_SETTLE= 3/Output Data Rate

The AD7176-2 can be configured by setting the SING_CYC bit

in the ADC mode register so that only fully settled data is output,

thus effectively putting the ADC into a single cycle settling mode.

This mode achieves single cycle settling by reducing the output

data rate to be equal to the settling time of the ADC for the selected

output data rate. This bit has no effect with the Sinc5 + Sinc1 at

output data rates of 10 kSPS and lower.

Figure 36 shows the frequency domain filter response for the

Sinc3 filter. The Sinc3 filter has good roll-off over frequency

and has wide notches for good notch frequency rejection.

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

Figure 37 shows a step on the analog input with this mode

disabled and the Sinc3 filter selected. It takes at least three

cycles after the step change for the output to reach the final

settled value.

ANALOG

INPUT

FULLY

SETTLED

ADC

OUTPUT

–120

1/ODR

0

50

100

150

Figure 37. Step Input Without Single Cycle Settling

FREQUENCY (Hz)

Figure 36. Sinc3 Filter Response

Figure 38 shows the same step on the analog input but with

single cycle settling enabled. It takes at least a single cycle for

the output to be fully settled. The output data rate is now

reduced to equal the settling time of the filter at the selected

output data rate.

The output data rates with the accompanying settling time and

rms noise for the Sinc3 filter are shown in Table 19.

It is possible to finely tune the output data rate for the Sinc3 filter by

setting the SINC3_MAP bit in the filter configuration register. If

this bit is set, the mapping of the filter register changes to directly

program the decimation rate of the Sinc3 filter. All other options

are eliminated. The data rate when on a single channel can be

calculated using the following equation:

ANALOG

INPUT

FULLY

SETTLED

ADC

OUTPUT

t_SETTLE

f _MOD

Output Data Rate =

Figure 38. Step Input with Single Cycle Settling

32×FILTCONx[14:0]

where:

f

_MODis the modulator rate and is 8 MHz.

FILTCONx[14:0] are the contents on the filter configuration

register excluding the MSB.

Rev. 0 | Page 29 of 68

AD7176-2

Data Sheet

Table 19. AD7176-2 Output Data Rate (ODR), Noise, Settling Time (t_SETTLE), and Rejection Using the Sinc3 Filter

Output Data

Settling

Switching Rate¹

(Hz)

Notch Frequency Rejection 1 Hz

(Hz)

Noise

Peak-to-Peak Resolution

Rate (SPS)¹

Time (ms)¹

(dB)²

(µV rms) with 5 V Reference (Bits)

250,000

125,000

62,500

50,000

31,250

25,000

15,625

10,000

5000

2500

1000

500

400

200

100

59.94

49.96

20

16.667

10

0.012

0.024

0.048

0.060

0.096

0.120

0.192

0.300

0.600

1.200

3.000

6.000

83,333

41,667

20,833

16,667

10,417

8333

5208

3333

1667

833

250,000

125,000

62,500

50,000

31,250

25,000

15,625

10,000

5000

2500

1000

500

400

200

100

59.94

49.96

20

16.667

10

220

27

5.1

4.3

3.2

2.7

2.3

1.8

1.3

0.91

0.62

0.49

0.45

0.37

0.33

0.32

0.31

0.29

12.8

15.9

18.3

18.5

18.8

19

19.4

19.8

20.2

20.5

21

21.4

21.7

22

333.3

166.7

133.3

66.7

7.500

15.000

30.000

50.004

60.000

150.000

180.000

300.000

600.000

33.3

20.00

16.67

6.67

5.56

3.33

100 (60 Hz)

100 (50 Hz)

22

22.4

100 (50 Hz and 60 Hz) 0.29

0.29

5

1.67

5

¹The settling time has been rounded to the nearest microsecond. This is reflected in the output data rate and switching rate. Switching rate = 1 ÷ t_SETTLE

²Master clock = 160 MHz.

.

Rev. 0 | Page 30 of 68

Data Sheet

AD7176-2

+ Sinc1 filter must be selected when using the enhanced filters.

Table 20 shows the output data rates with the accompanying

settling time, rejection, and rms noise. Figure 39 to Figure 46

show the frequency domain plots of the responses from the

enhanced filters.

ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS

The enhanced filters are designed to provide rejection of 50 Hz

and 60 Hz simultaneously and to allow the user to trade off

settling time and rejection. These filters can operate up to

27.27 SPS or can reject up to 90 dB of 50 Hz 1 Hz and 60 Hz

1 Hz interference. These filters are realized by post filtering

the output of the Sinc5 + Sinc1 filter. For this reason, the Sinc5

Table 20. AD7176-2 Enhanced Filters Output Data Rate, Noise, Settling Time (t_SETTLE), and Rejection Using the Enhanced Filters

Simultaneous Rejection of

50 Hz 1 Hz and 60 Hz 1 Hz

Output Data Rate

(SPS)

Settling Time

(ms)

Noise

(µV rms)

Peak-to-Peak Resolution

(Bits)

(dB)¹

Comments

27.27

25

20

36.67

40.0

50.0

60.0

47

62

85

90

0.15

0.14

0.125

23.26

23.36

23.53

See Figure 39 and Figure 40

See Figure 41 and Figure 42

See Figure 43 and Figure 44

See Figure 45 and Figure 46

16.667

¹Master clock = 160 MHz.

Rev. 0 | Page 31 of 68

AD7176-2

Data Sheet

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–100

100

200

300

400

500

600

40

45

50

55

60

65

70

FREQUENCY (Hz)

Figure 39. DC to 600 Hz, 27.27 SPS ODR, 36.67 ms Settling Time

Figure 42. Zoom in 40 Hz to 70 Hz, 25 SPS ODR, 40 ms Settling Time

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

40

45

50

55

60

65

70

0

100

200

300

400

500

600

FREQUENCY (Hz)

Figure 40. Zoom in 40 Hz to 70 Hz, 27.27 SPS ODR, 36.67 ms Settling Time

Figure 43. DC to 600 Hz, 20 SPS ODR, 50 ms Settling Time

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

40

100

200

300

400

500

600

40

45

50

55

60

65

70

FREQUENCY (Hz)

Figure 41. DC to 600 Hz, 25 SPS ODR, 40 ms Settling Time

Figure 44. Zoom in 40 Hz to 70 Hz, 20 SPS ODR, 50 ms Settling Time

Rev. 0 | Page 32 of 68

Data Sheet

AD7176-2

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

100

200

300

400

500

600

40

45

50

55

60

65

70

FREQUENCY (Hz)

Figure 45. DC to 600 Hz,16.667 SPS ODR, 60 ms Settling Time

Figure 46. Zoom in 40 Hz to 70 Hz, 16.667 SPS ODR, 60 ms Settling Time

Rev. 0 | Page 33 of 68

AD7176-2

Data Sheet

OPERATING MODES

When several channels are enabled, the ADC automatically

CONTINUOUS CONVERSION MODE

sequences through the enabled channels, performing one

conversion on each channel. When all channels have been

converted, the sequence starts again with the first channel. The

channels are converted in order from lowest enabled channel to

highest enabled channel. The data register is updated as soon as

Continuous conversion is the default power-up mode. The

RDY

AD7176-2 converts continuously, and the

register goes low each time a conversion is complete. If

RDY

bit in the status

CS

is low,

line also goes low when a conversion is complete.

the DOUT/

To read a conversion, the user writes to the communications

register, indicating that the next operation is a read of the data

register. When the data-word has been read from the data register,

RDY

each conversion is available. The DOUT/

pin pulses low

each time a conversion is available. The user can then read the

conversion while the ADC converts the next enabled channel.

RDY

DOUT/

goes high. The user can read this register additional

If the DATA_STAT bit in the interface mode register is set to 1,

the contents of the status register, along with the conversion data,

are output each time the data register is read. The status register

indicates the channel to which the conversion corresponds.

times, if required. However, the user must ensure that the data

register is not being accessed at the completion of the next con-

version; otherwise the new conversion word will be lost.

CS

0x44

DIN

DATA

DOUT/RDY

SCLK

Figure 47. Continuous Conversion Mode

Rev. 0 | Page 34 of 68

Data Sheet

AD7176-2

To enable continuous read mode, set the CONTREAD bit in the

interface mode register. When this bit is set, the only serial interface

operations possible are reads from the data register. To exit con-

tinuous read mode, issue a dummy read of the ADC data register

CONTINUOUS READ MODE

In continuous read mode, it is not required to write to the

communications register before reading ADC data; just apply

the required number of SCLKs after DOUT/

RDY

goes low to

RDY

command (0x44) while

is low. Alternatively, apply a software

CS

indicate the end of a conversion. When the conversion is read,

RDY

reset, that is, 64 SCLKs with

= 0 and DIN = 1. This resets the

DOUT/

returns high until the next conversion is available.

ADC and all register contents. These are the only commands

that the interface recognizes after it is placed in continuous read

mode. DIN should be held low in continuous read mode until

an instruction is to be written to the device.

In this mode, the data can be read only once. The user must also

ensure that the data-word is read before the next conversion is

complete. If the user has not read the conversion before the

completion of the next conversion or if insufficient serial clocks

are applied to the AD7176-2 to read the word, the serial output

register is reset when the next conversion is complete, and the

new conversion is placed in the output serial register. The ADC

must be configured for continuous conversion mode to use

continuous read mode.

If multiple ADC channels are enabled, each channel is output

in turn, with the status bits being appended to the data if

DATA_STAT is set in the interface mode register. The status

register indicates the channel to which the conversion corresponds.

CS

0x02

0x0800

DIN

DATA

DOUT/RDY

SCLK

Figure 48. Continuous Read Mode

Rev. 0 | Page 35 of 68

AD7176-2

Data Sheet

RDY

DOUT/

goes low. The ADC then selects the next channel and

SINGLE CONVERSION MODE

begins a conversion. The user can read the present conversion

while the next conversion is being performed. As soon as the next

conversion is complete, the data register is updated; therefore,

the user has a limited period in which to read the conversion.

When the ADC has performed a single conversion on each of

the selected channels, it returns to standby mode.

In single conversion mode, the AD7176-2 performs a single

conversion and is placed in standby mode after the conversion

RDY

is complete. DOUT/

goes low to indicate the completion of a

conversion. When the data-word has been read from the data

RDY

register, DOUT/

several times, if required, even when DOUT/

goes high. The data register can be read

RDY

has gone high.

If the DATA_STAT bit in the interface mode register is set to 1,

the contents of the status register, along with the conversion, are

output each time the data register is read. The two LSBs of the

status register indicate the channel to which the conversion

corresponds.

If several channels are enabled, the ADC automatically

sequences through the enabled channels and performs a

conversion on each channel. When a conversion is started,

RDY

DOUT/

goes high and remains high until a valid conversion

CS

is available and

is low. As soon as the conversion is available,

CS

0x01

0x8010

0x44

DIN

DATA

DOUT/RDY

SCLK

Figure 49. Single Conversion Mode

Rev. 0 | Page 36 of 68

Data Sheet

AD7176-2

To start a calibration, write the relevant value to the MODE bits

STANDBY AND POWER-DOWN MODES

RDY

in the ADC mode register. The DOUT/

pin and the RDY bit

In standby mode, most blocks are powered down. The LDOs

remain active so that registers maintain their contents. The

internal reference remains active if enabled, and the crystal

oscillator remains active if selected. To power down the

reference in standby mode, set the REF_EN bit in the ADC

mode regsiter to 0. To power down the clock in standby mode,

set the CLOCKSEL bits in the ADC mode register to 00

(internal oscillator).

in the status register go high when the calibration initiates. When

the calibration is complete, the contents of the corresponding

RDY

offset or gain register are updated, the

bit in the status

RDY

CS

is low),

register is reset, the DOUT/

pin returns low (if

and the AD7176-2 reverts to standby mode.

During an internal offset calibration, the selected positive

analog input pin is disconnected, and both modulator inputs

are connected internally to the selected negative analog input

pin. For this reason, it is necessary to ensure that the voltage on

the selected negative analog input pin does not exceed the

allowed limits and is free from excessive noise and interference.

In power-down mode, all blocks are powered down, including

the LDOs. All registers lose their contents, and the GPIO outputs

are placed in tristate. To prevent accidental entry to power-down

mode, the ADC must first be placed into standby mode. Exiting

CS

power-down mode requires 64 SCLKs with

= 0 and DIN = 1,

System calibrations, however, expect the system zero-scale

(offset) and system full-scale (gain) voltages to be applied to the

ADC pins before initiating the calibration modes. As a result,

errors external to the ADC are removed.

that is, a serial interface reset. A delay of 500 µs is recommended

before issuing a subsequent serial interface command to allow

the LDO to power up.

CALIBRATION MODES

From an operational point of view, treat a calibration like

another ADC conversion. An offset calibration, if required,

must always be performed before a full-scale calibration. Set the

system software to monitor the RDY bit in the status register or

The AD7176-2 provides three calibration modes that can be

used to eliminate the offset and gain errors on a per setup basis:

•

Internal zero-scale calibration mode

System zero-scale calibration mode

System full-scale calibration mode

RDY

the DOUT/

pin to determine the end of a calibration via a

polling sequence or an interrupt-driven routine. All calibrations

require a time equal to the settling time of the selected filter and

output data rate to be completed.

Only one channel can be active during calibration. After each

conversion, the ADC conversion result is scaled using the ADC

calibration registers before being written to the data register.

An internal offset calibration, system zero-scale calibration, and

system full-scale calibration can be performed at any output data

rate. Using lower output data rates results in better calibration

accuracy and is accurate for all output data rates. A new calibration

is required for a given channel if the reference source for that

channel is changed.

The default value of the offset register is 0x800000, and the

nominal value of the gain register is 0x555555. The calibration

range of the ADC gain is from 0.4 × V_REFto 1.05 × V_REF. The

following equations show the calculations that are used. In

unipolar mode, the ideal relationship—that is, not taking into

account the ADC gain error and offset error—is as follows:

The offset error is typically 40 µV and an offset calibration

reduces the offset error to the order of the noise. The gain error

is factory calibrated at ambient temperature. Following this

calibration, the gain error is typically 0.001%.









0.75×V_IN

V_REF

Gain

0x400000

Data =

×2²³−(Offset −0x800000) ×

×2





The AD7176-2 provides the user with access to the on-chip

calibration registers, allowing the microprocessor to read the

calibration coefficients of the device and to write its own

calibration coefficients. A read or write of the offset and gain

registers can be performed at any time except during an internal

or self-calibration.

In bipolar mode, the ideal relationship—that is, not taking into

account the ADC gain error and offset error—is as follows:









0.75×V_IN

V_REF

Gain

0x400000

Data =

×2²³−(Offset − 0x800000) ×

+ 0x800000





Rev. 0 | Page 37 of 68

AD7176-2

Data Sheet

DIGITAL INTERFACE

The programmable functions of the AD7176-2 are via the SPI

serial interface. The serial interface of the AD7176-2 consists of

For CRC checksum calculations during a write operation, the

following polynomial is always used:

CS

RDY

x⁸+ x²+ x + 1

four signals: , DIN, SCLK, and DOUT/

. The DIN line is

RDY

used to transfer data into the on-chip registers, and DOUT/

is

During read operations, the user can select between this

polynomial and a similar XOR function. The XOR function

requires less time to process on the host microcontroller than

the polynomial-based checksum. The CRC_EN bits in the

interface mode register enable and disable the checksum and

allow the user to select between the polynomial check and the

simple XOR check.

used to access data from the on-chip registers. SCLK is the serial

clock input for the device, and all data transfers (either on DIN or

RDY

on DOUT/

) occur with respect to the SCLK signal.

RDY

The DOUT/

pin also functions as a data-ready signal, with

CS

the line going low if

is low when a new data-word is available

in the data register. The pin is reset high when a read operation

RDY

from the data register is complete. The DOUT/

pin also

The checksum is appended to the end of each read and write

transaction. The checksum calculation for the write transaction

is calculated using the 8-bit command word and the 8- to 24-bit

data. For a read transaction, the checksum is calculated using

the command word and the 8- to 32-bit data output. Figure 50

and Figure 51 show SPI write and read transactions, respectively.

goes high before updating the data register to indicate when not

to read from the device to ensure that a data read is not attempted

CS

while the register is being updated.

is used to select a device.

It can be used to decode the AD7176-2 in systems where several

components are connected to the serial bus.

8-BIT COMMAND

UP TO 24-BIT INPUT

8-BIT CRC

Figure 2 and Figure 3 show timing diagrams for interfacing to

CS

the AD7176-2 using

to decode the part. Figure 2 shows the

timing for a read operation from the AD7176-2, and Figure 3

shows the timing for a write operation to the AD7176-2. It is

possible to read from the data register several times even though

CS

DATA

CRC

DIN

RDY

the DOUT/

line returns high after the first read operation.

SCLK

However, care must be taken to ensure that the read operations are

completed before the next output update occurs. In continuous

read mode, the data register can be read only once.

Figure 50. SPI Write Transaction with CRC

8-BIT COMMAND

UP TO 32-BIT INPUT

8-BIT CRC

CS

The serial interface can operate in 3-wire mode by tying

low.

lines are used to

communicate with the AD7176-2. The end of the conversion

RDY

CS

RDY

In this case, the SCLK, DIN, and DOUT/

CMD

DIN

can also be monitored using the

bit in the status register.

CS

The serial interface can be reset by writing 64 SCLKs with

=

DOUT/

RDY

DATA

CRC

0 and DIN = 1. A reset returns the interface to the state in which it

expects a write to the communications register. This operation

resets the contents of all registers to their power-on values.

Following a reset, allow a period of 500 µs before addressing the

serial interface.

SCLK

Figure 51. SPI Read Transaction with CRC

CHECKSUM PROTECTION

If checksum protection is enabled when continuous read mode

is active, there is an implied read data command of 0x44 before

every data transmission that needs to be accounted for when

calculating the checksum value. This ensures a nonzero checksum

value even if the ADC data equals 0x000000.

The AD7176-2 has a checksum mode, which can be used to

improve interface robustness. Using the checksum ensures that

only valid data is written to a register and allows data read from

a register to be validated. If an error occurs during a register

write, the CRC_ERROR bit is set in the status register. However,

to ensure that the register write was successful, the register

should be read back and checksum verified.

Rev. 0 | Page 38 of 68

Data Sheet

AD7176-2

CRC CALCULATION

Polynomial

The checksum, which is 8-bits wide, is generated using the polynomial

x⁸+ x²+ x + 1

To generate the checksum, the data is left shifted by eight bits to create a number ending in eight Logic 0s. The polynomial is aligned so that

its MSB is adjacent to the leftmost Logic 1 of the data. An XOR (exclusive OR) function is applied to the data to produce a new, shorter

number. The polynomial is again aligned so that its MSB is adjacent to the leftmost Logic 1 of the new result, and the procedure is repeated. This

process is repeated until the original data is reduced to a value less than the polynomial. This is the 8-bit checksum.

Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data)

An example of generating the 8-bit checksum using the polynomial based checksum is as follows:

Initial value

011001010100001100100001

01100101010000110010000100000000

left shifted eight bits

polynomial

x⁸+ x²+ x + 1

=

100000111

100100100000110010000100000000

100000111

XOR result

polynomial

XOR result

polynomial

XOR result

polynomial value

XOR result

polynomial value

XOR result

polynomial value

XOR result

polynomial value

XOR result

polynomial value

XOR result

polynomial value

XOR result

polynomial value

XOR result

polynomial value

XOR result

polynomial value

XOR result

polynomial value

checksum = 0x86.

100011000110010000100000000

100000111

11111110010000100000000

100000111

1111101110000100000000

100000111

111100000000100000000

100000111

11100111000100000000

100000111

1100100100100000000

100000111

100101010100000000

100000111

101101100000000

100000111

1101011000000

100000111

101010110000

100000111

1010001000

100000111

10000110

Rev. 0 | Page 39 of 68

AD7176-2

Data Sheet

XOR Calculation

The checksum, which is 8-bits wide, is generated by splitting the data into bytes and then performing an XOR of the bytes.

Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data)

Using the previous example,

Divide into three bytes: 0x65, 0x43, and 0x21

01100101

01000011

00100110

00100001

00000111

0x65

0x43

XOR result

0x21

CRC

Rev. 0 | Page 40 of 68

Data Sheet

AD7176-2

SYNC

input allows the user to reset the modulator and the

GENERAL-PURPOSE I/O

digital filter without affecting any of the setup conditions on

the part. This allows the user to start gathering samples of the

analog input from a known point in time, that is, the rising

The AD7176-2 has two general-purpose digital input/output pins:

GPIO0 and GPIO1. These are enabled using the IP_EN0/IP_EN1

or OP_EN0/OP_EN1 bits in the GPIOCON register. When the

GPIO0 or GPIO1 pin is enabled as an input, the logic level at

the pin is contained in the DATA0 or DATA1 bit, respectively.

When the GPIO0 or GPIO1 pin is enabled as an output, the

GP_DATA0 or GP_DATA1 bits, respectively, determine the

logic level output at the pin. The logic levels for these pins are

referenced to AVDD1 and AVSS; therefore, outputs have an

amplitude of 5 V.

SYNC

edge of

. This pin must be low for at least one master

clock cycle to ensure that synchronization occurs.

If multiple AD7176-2 devices are operated from a common

master clock, they can be synchronized so that their data registers

are updated simultaneously. This is normally done after each

AD7176-2 has performed its own calibration or has calibration

coefficients loaded into its calibration registers. A falling edge

SYNC

on the

and places the AD7176-2 into a consistent known state. While

SYNC

pin resets the digital filter and the analog modulator

If an external multiplexer is used to increase the channel count,

the multiplexer logic pins can be controlled via the AD7176-2

GPIO pins. With the MUX_IO bit, the GPIOs timing is controlled

by the ADC; therefore, the channel change is synchronized with

the ADC, eliminating any need for external synchronization.

the

On the

pin is low, the AD7176-2 is maintained in this state.

SYNC

rising edge, the modulator and filter are taken

out of this reset state, and on the next master clock edge, the

part starts to gather input samples again.

SYNC ERROR

pin can also be used as a general-purpose

The

output. When ERR_EN bits in the GPIOCON register are set to

SYNC ERROR

pin operates as a general-purpose output.

/

The part is taken out of reset on the master clock falling edge

following the

multiple devices are being synchronized, the

be taken high on the master clock rising edge to ensure that all

devices begin sampling on the master clock falling edge. If the

SYNC

low-to-high transition. Therefore, when

SYNC

11, the

/

In this configuration, the ERR_DAT bit in the GPIOCON register

determines the logic level output at the pin. The logic level for the

pin should

SYNC ERROR

pin is referenced to IOVDD and DGND, and the

pin has an active pull-up.

/

SYNC

pin is not taken high in sufficient time, it is possible to

have a difference of one master clock cycle between the devices;

that is, the instant at which conversions are available differs

from part to part by a maximum of one master clock cycle.

16-BIT/24-BIT CONVERSIONS

By default, the AD7176-2 generates 24-bit conversions. However,

the width of the conversions can be reduced to 16 bits. Setting

Bit WL16 in the interface mode register to 1 rounds all data

conversions to 16 bits. Clearing this bit sets the width of the

data conversions to 24 bits.

SYNC

The

In this mode, the rising edge of

RDY

pin can also be used as a start conversion command.

SYNC

starts a conversion, and

indicates when the conversion is complete.

the falling edge of

The settling time of the filter has to be allowed for each data

register update.

SERIAL INTERFACE RESET (DOUT_RESET)

The serial interface is reset when each read operation is

complete. The instant at which the serial interface is reset is

programmable. By default, the serial interface is reset after a

period of time following the last SCLK rising edge, the SCLK

edge on which the LSB is read by the processor. By setting Bit

DOUT_RESET in the interface mode register to 1, the instant at

Alternate Synchronization

Setting Bit ALT_SYNC in the interface mode register to 1 enables

an alternate synchronization scheme. The SYNC_EN bit in the

GPIOCON register must be set to 1 to enable this alternate scheme.

SYNC

In this mode, the

mand when several channels of the AD7176-2 are enabled. When

SYNC

pin operates as a start conversion com-

CS

which the interface is reset is controlled by the

rising edge.

pin continues to output the LSB of

CS CS

is taken low, the ADC completes the conversion on the

current channel, selects the next channel in the sequence, and

SYNC

RDY

In this case, the DOUT/

the register being read until

rising edge is the interface reset. This configuration is useful if

CS CS

is taken high. Only on the

then waits until

is taken high to commence the conversion.

pin goes low when the conversion is complete on

the current channel, and the data register is updated with the

SYNC

RDY

The

the

signal is used to frame all read operations. If

is not

used to frame all read operations, DOUT_RESET should be set

to 0 so that the interface is reset following the last SCLK edge in

the read operation.

corresponding conversion. Therefore, the

command

does not interfere with the sampling on the currently selected

channel but allows the user to control the instant at which the

conversion begins on the next channel in the sequence.

SYNCHRONIZATION (

/

)

SYNC ERROR

Normal Synchronization

The mode can be used only when several channels are enabled.

It is not recommended to use this mode when a single channel

is enabled.

When the SYNC_EN bit in the GPIOCON register is set to 0,

SYNC ERROR

pin functions as a synchronization pin. The

the

/

Rev. 0 | Page 41 of 68

AD7176-2

Data Sheet

With ERR_EN bits are set to 10, the pin functions as an open-

drain error output pin. The three error bits in the status register

(ADC_ERROR, CRC_ERROR, and REG_ERROR) are OR’ed,

ERROR FLAGS

The status register contains three error bits—ADC_ERROR,

CRC_ERROR, and REG_ERROR—that flag errors with the

ADC conversion, errors with the CRC check, and errors due to

changes in the registers, respectively. In addition, the

pin can indicate that an error has occurred.

ERROR

inverted, and mapped to the

ERROR

pin. Therefore, the

pin indicates that an error has occurred. The status

register must be read to identify the error source.

ERROR

When ERR_EN bits are set to 01, the

an error input pin. The error pin of another component can be

ERROR

pin functions as

ADC_ERROR

The ADC_ERROR bit in the status register flags any errors that

occur during the conversion process. The flag is set when an over-

voltage or undervoltage occurs on the analog inputs. The ADC

also outputs all 0s or all 1s when an undervoltage or overvoltage

occurs. This flag is reset only when the overvoltage/undervoltage is

removed. It is not reset by a read of the data register.

connected to the AD7176-2

indicates when an error occurs on either itself or the external

ERROR

pin so that the AD7176-2

component. The value on the

pin is inverted and OR’ed

with the errors from the ADC conversion, and the result is

indicated via the ADC_ERROR bit in the status register. The value

ERROR

of the

register.

pin is reflected in the ERR_DAT bit in the status

CRC_ERROR

If the CRC value that accompanies a write operation does not

correspond with the information sent, the CRC_ERROR flag is

set. The flag is reset as soon as the status register is explicitly read.

ERROR

The

pin is disabled when the ERR_EN bits are set to 00.

ERROR

When the ERR_EN1 bits are set to 11, the

as a general-purpose output.

pin operates

REG_ERROR

DATA_STAT

This flag is used in conjunction with the REG_CHECK bit in

the interface mode register. When the REG_CHECK bit is set,

the AD7176-2 monitors the values in the on-chip registers. If a

bit changes, the REG_ERROR bit is set. Therefore, for writes to

the on-chip registers, REG_CHECK should be set to 0. When

the registers have been updated, the REF_CHK bit can be set to 1.

The AD7176-2 calculates a checksum of the on-chip registers. If

one of the register values has changed, the REG_ERROR bit is

set. If an error is flagged, the REG_CHECK bit must be set to 0

to clear the REG_ERROR bit in the status register. The register

check function does not monitor the data register, status

register, or interface mode register.

The contents of the status register can be appended to each con-

version on the AD7176-2. This is a useful function if several

channels are enabled. Each time a conversion is output, the

contents of the status register are appended. The two LSBs of

the status register indicate to which channel the conversion

corresponds. In addition, the user can determine if any errors

are being flagged by the error bits.

IOSTRENGTH

The serial interface can operate with a power supply as low as

RDY

2 V. However, at this low voltage, the DOUT/

pin may not

have sufficient drive strength if there is moderate parasitic

capacitance on the board or the SCLK frequency is high. The

IOSTRENGTH bit in the interface mode register increases the

ERROR

When the SYNC_EN bit in the GPIOCON register is set to 1

and Bit ALT_SYNC in the interface mode register is set to 0, the

RDY

drive strength of the DOUT/

pin.

SYNC ERROR

/

pin functions as an error input/output pin or a

general-purpose output pin. The ERR_EN bits in the GPIOCON

register determine the function of the pin.

Rev. 0 | Page 42 of 68

Data Sheet

AD7176-2

GROUNDING AND LAYOUT

The analog inputs and reference inputs are differential and,

therefore, most of the voltages in the analog modulator are

common-mode voltages. The high common-mode rejection of

the part removes common-mode noise on these inputs. The

analog and digital supplies to the AD7176-2 are independent

and separately pinned out to minimize coupling between the

analog and digital sections of the device. The digital filter

provides rejection of broadband noise on the power supplies,

except at integer multiples of the master clock frequency.

the power supply line. Shield fast switching signals like clocks

with digital ground to prevent radiating noise to other sections

of the board and never run clock signals near the analog inputs.

Avoid crossover of digital and analog signals. Run traces on

opposite sides of the board at right angles to each other. This

reduces the effects of feedthrough on the board. A microstrip

technique is by far the best but is not always possible with a

double-sided board. In this technique, the component side of

the board is dedicated to ground planes, whereas signals are

placed on the solder side.

The digital filter also removes noise from the analog and

reference inputs, provided that these noise sources do not

saturate the analog modulator. As a result, the AD7176-2 is

more immune to noise interference than a conventional high

resolution converter. However, because the resolution of the

AD7176-2 is high and the noise levels from the converter are so

low, care must be taken with regard to grounding and layout.

Good decoupling is important when using high resolution ADCs.

The AD7176-2 has three power supply pins—AVDD1, AVDD2,

and IOVDD. The AVDD1 and AVDD2 pins are referenced to

AVSS, and the IOVDD pin is referenced to DGND. AVDD1 and

AVDD2 should be decoupled with a 10 µF tantalum capacitor

in parallel with a 0.1 µF capacitor to AVSS on each pin. The

0.1 µF capacitor should be placed as close as possible to the

device on each supply, ideally right up against the device.

IOVDD should be decoupled with a 10 µF tantalum capacitor

in parallel with a 0.1 µF capacitor to DGND. All analog inputs

should be decoupled to AVSS. If an external reference is used,

the REF+ and REF− pins should be decoupled to AVSS.

The printed circuit board (PCB) that houses the ADC must be

designed so that the analog and digital sections are separated

and confined to certain areas of the board. A minimum etch

technique is generally best for ground planes because it results

in the best shielding.

In any layout, the user must keep in mind the flow of currents

in the system, ensuring that the paths for all return currents are as

close as possible to the paths the currents took to reach their

destinations.

The AD7176-2 also has two on-board LDO regulators—one that

regulates the AVDD2 supply and one that regulates the IOVDD

supply. For the REGCAPA pin, it is recommended that 1 µF and

0.1 µF capacitors to AVSS be used. Similarly, for the REGCAPD

pin, it is recommended that 1 µF and 0.1 µF capacitors to

DGND be used.

Avoid running digital lines under the device because this

couples noise onto the die and allows the analog ground plane

to run under the AD7176-2 to prevent noise coupling. The

power supply lines to the AD7176-2 must use as wide a trace as

possible to provide low impedance paths and reduce glitches on

If using the AD7176-2 for split supply operation, a separate

plane must be used for AVSS.

Rev. 0 | Page 43 of 68

AD7176-2

Data Sheet

REGISTER SUMMARY

Table 21. AD7176-2 Register Summary

Reg Name

Bits

[7:0]

Bit 7

WEN

RDY

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

RA

Bit 1

Bit 0

Reset

0x00

RW

W

0x00 COMMS

0x00 STATUS

0x01 ADCMODE

W

R/

ADC_ERROR

RESERVED

CRC_ERROR

REG_ERROR

RESERVED

CHANNEL

0x80

R

[15:8] REF_EN

SING_CYC

MODE

RESERVED

DELAY

RESERVED

DOUT_RESET 0x0000

0x8000

RW

[7:0]

RESERVED

CLOCKSEL

0x02 IFMODE

[15:8]

[7:0]

RESERVED

ALT_SYNC

RESERVED

IOSTRENGTH

CRC_EN

RESERVED

RW

R

CONTREAD

DATA_STAT

REG_CHECK

RESERVED WL16

0x03 REGCHECK

[23:16]

[15:8]

REGISTER_CHECK[23:16]

REGISTER_CHECK[15:8]

0x000000

[7:0]

REGISTER_CHECK[7:0]

0x04 DATA

[23:16]

[15:8]

DATA[23:16]

DATA[15:8]

0x000000

R

[7:0]

DATA[7:0]

0x06 GPIOCON

0x07 ID

[15:8]

[7:0]

RESERVED

MUX_IO

IP_EN0

SYNC_EN

OP_EN1

ERR_EN

GP_DATA1

ERR_DAT

0x0800

0x0C9X

0x8001

0x0001

0x1020

0x0000

RW

R

RESERVED

IP_EN1

OP_EN0

GP_DATA0

[15:8]

[7:0]

ID[15:8]

ID[7:0]

0x10 CHMAP0

0x11 CHMAP1

0x12 CHMAP2

0x13 CHMAP3

0x20 SETUPCON0

0x21 SETUPCON1

0x22 SETUPCON2

0x23 SETUPCON3

0x28 FILTCON0

0x29 FILTCON1

0x2A FILTCON2

0x2B FILTCON3

0x30 OFFSET0

[15:8] CH_EN0

[7:0]

RESERVED

SETUP_SEL0

SETUP_SEL1

SETUP_SEL2

SETUP_SEL3

RESERVED

AINNEG0

RESERVED

AINNEG1

RESERVED

AINNEG2

RESERVED

AINNEG3

AINPOS0[4:3]

RW

AINPOS0[2:0]

[15:8] CH_EN1

[7:0]

RESERVED

AINPOS1[4:3]

AINPOS2[4:3]

AINPOS3[4:3]

AINPOS1[2:0]

[15:8] CH_EN2

[7:0]

RESERVED

AINPOS2[2:0]

[15:8] CH_EN3

[7:0]

RESERVED

AINPOS3[2:0]

[15:8]

[7:0]

RESERVED

BI_UNIPOLAR0

REF_SEL0

BI_UNIPOLAR1

REF_SEL1

BI_UNIPOLAR2

REF_SEL2

BI_UNIPOLAR3

REF_SEL3

RESERVED

ORDER0

RESERVED

ORDER1

RESERVED

ORDER2

RESERVED

ORDER3

RESERVED

[15:8]

[7:0]

RESERVED

[15:8]

[7:0]

RESERVED

[15:8]

[7:0]

RESERVED

[15:8] SINC3_MAP0

[7:0] RESERVED

[15:8] SINC3_MAP1

[7:0] RESERVED

[15:8] SINC3_MAP2

[7:0] RESERVED

[15:8] SINC3_MAP3

ENHFILTEN0

ENHFILT0

ODR0

ODR1

ODR2

ODR3

ENHFILTEN1

ENHFILTEN2

ENHFILTEN3

ENHFILT1

ENHFILT2

ENHFILT3

[7:0]

RESERVED

[23:16]

[15:8]

OFFSET0[23:16]

0x800000 RW

OFFSET0[15:8]

OFFSET0[7:0]

[7:0]

0x31 OFFSET1

0x32 OFFSET2

0x33 OFFSET3

[23:16]

[15:8]

OFFSET1[23:16]

OFFSET1[15:8]

[7:0]

OFFSET1[7:0]

[23:16]

[15:8]

OFFSET2[23:16]

OFFSET2[15:8]

[7:0]

OFFSET2[7:0]

[23:16]

[15:8]

OFFSET3[23:16]

OFFSET3[15:8]

[7:0]

OFFSET3[7:0]

Rev. 0 | Page 44 of 68

Data Sheet

AD7176-2

Reg Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

GAIN0[23:16]

GAIN0[15:8]

Bit 2

Bit 1

Bit 0

Reset

RW

0x38 GAIN0

[23:16]

[15:8]

0x5XXXX0 RW

[7:0]

GAIN0[7:0]

0x39 GAIN1

0x3A GAIN2

0x3B GAIN3

[23:16]

[15:8]

GAIN1[23:16]

GAIN1[15:8]

[7:0]

GAIN1[7:0]

[23:16]

[15:8]

GAIN2[23:16]

GAIN2[15:8]

[7:0]

GAIN2[7:0]

[23:16]

[15:8]

GAIN3[23:16]

GAIN3[15:8]

[7:0]

GAIN3[7:0]

Rev. 0 | Page 45 of 68

AD7176-2

Data Sheet

REGISTER DETAILS

COMMUNICATIONS REGISTER

Address: 0x00, Reset: 0x00, Name: COMMS

Table 22. Bit Descriptions for COMMS

Bits

Bit Name

Settings

Description

Reset

0x0

Access

W

7

WEN

This bit must be low to begin communications with the ADC.

6

R/W

This bit determines if the command is a read or write operation.

0x0

W

0

1

Write command

Read command

[5:0]

RA

The register address bits determine which register is to be read from or

written to as part of the current communication.

0x00

W

000000 Status Register

000001 ADC Mode Register

000010 Interface Mode Register

000011 Register Checksum Register

000100 Data Register

000110 GPIO Configuration Register

000111 ID Register

010000 Channel Map 1 Register

010001 Channel Map 2 Register

010010 Channel Map 3 Register

010011 Channel Map 4 Register

100000 Setup Configuration 1 Register

100001 Setup Configuration 2 Register

100010 Setup Configuration 3 Register

100011 Setup Configuration 4 Register

101000 Filter Configuration 1 Register

101001 Filter Configuration 2 Register

101010 Filter Configuration 3 Register

101011 Filter Configuration 4 Register

110000 Offset 1 Register

110001 Offset 2 Register

110010 Offset 3 Register

110011 Offset 4 Register

111000 Gain 1 Register

111001 Gain 2 Register

111010 Gain 3 Register

Rev. 0 | Page 46 of 68

Data Sheet

AD7176-2

STATUS REGISTER

Address: 0x00, Reset: 0x80, Name: STATUS

The Status Register is an 8-bit register that contains ADC and serial interface status information. It can optionally be appended to the

Data Register by setting the DATA_STAT bit in the Interface Mode Register.

Table 23. Bit Descriptions for STATUS

Bits

Bit Name

Settings

Description

Reset

Access

7

RDY

The status of RDY is output to the DOUT/RDYpin whenever CS is low and a 0x1

register is not being read. This bit goes low when the ADC has written a

new result to the Data Register. In ADC calibration modes, this bit goes

low when the ADC has written the calibration result. RDY is brought high

automatically by a read of the Data Register.

R

0

1

New data result available

Awaiting new data result

6

ADC_ERROR

This bit by default indicates if an ADC overrange or underrange has

occurred. The ADC result will be clamped to full scale if this happens.

This bit is updated when the ADC result is written and is cleared by

removing the overrange or underrange condition on the analog inputs.

0x0

R

0

1

No Error

Error

5

4

CRC_ERROR

REG_ERROR

This bit indicates if a CRC error has taken place during a register write. For

register reads, the host microcontroller determines if a CRC error has

occurred. This bit is cleared by a read of this register.

No Error

CRC Error

0x0

R

0

1

This bit indicates if the content of one of the internal registers has

changed from the value calculated when the register integrity check was

activated. The check is activated by setting the REG_CHECK bit in the

Interface Mode Register. This bit is cleared by clearing the REG_CHECK bit.

0

1

No Error

Error

[3:2]

[1:0]

RESERVED

CHANNEL

These bits are reserved.

0x0

R

These bits indicate which channel was active for the ADC conversion

whose result is currently in the Data Register. This may be different from

the channel currently being converted. The mapping is a direct map from

the Channel Map Register; therefore, Channel 0 results in 0x0 and Channel

3 results in 0x3.

00 Channel 0

01 Channel 1

10 Channel 2

11 Channel 3

Rev. 0 | Page 47 of 68

AD7176-2

Data Sheet

ADC MODE REGISTER

Address: 0x01, Reset: 0x8000, Name: ADCMODE

The ADC Mode Register controls the operating mode of the ADC and the master clock selection. A write to the ADC Mode Register

resets the filter and the bits and starts a new conversion or calibration.

RDY

Table 24. Bit Descriptions for ADCMODE

Bits

Bit Name

Settings

Description

Reset

Access

15

REF_EN

Enables internal reference and outputs a buffered 2.5 V to the REFOUT pin. 0x1

RW

0

1

Disabled

Enabled

14

13

RESERVED

SING_CYC

This bit is reserved and should be set to 0.

0x0

R

This bit can be used when only a single channel is active to set the ADC to 0x0

only output at the settled filter data rate.

RW

0

1

Disabled

Enabled

[12:11] RESERVED

These bits are reserved and should be set to 0.

0x0

R

[10:8]

DELAY

These bits allow a programmable delay to be added after a channel switch 0x0

to allow for settling of external circuitry before the ADC starts processing

its input.

RW

000

0

001 4 µs

010 16 µs

011 40 µs

100 100 µs

101 200 µs

110 500 µs

111 1 ms

7

RESERVED

MODE

This bit is reserved and should be set to 0.

0x0

R

[6:4]

These bits control the operating mode of the ADC. Details can be found in 0x0

the Operating Modes section.

RW

000 Continuous Conversion Mode

001 Single Conversion Mode

010 Standby Mode

011 Power-Down Mode

100 Internal Offset Calibration

110 System Offset Calibration

111 System Gain Calibration

[3:2]

[1:0]

CLOCKSEL

RESERVED

This bit is used to select the ADC clock source. Selecting internal oscillator 0x0

also enables the internal oscillator.

00 Internal oscillator

01 Internal oscillator output on XTAL2 pin

10 External clock input on XTAL2 pin

11 External crystal on XTAL1 and XTAL2 pins

RW

These bits are reserved and should be set to 0.

0x0

R

Rev. 0 | Page 48 of 68

Data Sheet

AD7176-2

INTERFACE MODE REGISTER

Address: 0x02, Reset: 0x0000, Name: IFMODE

The Interface Mode Register configures various serial interface options.

Table 25. Bit Descriptions for IFMODE

Bits

Bit Name

Settings

Description

Reset

Access

R

[15:13] RESERVED

These bits are reserved and should be set to 0.

0x0

12

11

ALT_SYNC

This bit enables a different behavior of the ERROR\SYNC pin to allow the

use of ERROR\SYNC as a control for conversions when cycling channels

(see the description of the SYNC_EN bit in the GPIO Configuration Register

for details).

Disabled

Enabled

RW

0

1

IOSTRENGTH

This bit controls the drive strength of the DOUT pin. This bit should be set

when reading from the serial interface at high speed with low IOVDD

supply and moderate capacitance.

0x0

RW

0

1

Disabled (default)

Enabled

[10:9]

8

RESERVED

These bits are reserved and should be set to 0.

0x0

R

DOUT_RESET

This bit prevents the DOUT/RDY pin from switching from outputting

DOUT to outputting RDY soon after the last rising edge of SCLK during a

read operation. Instead, the DOUT/RDY pin will continue to output the

LSB of the data until CS goes high. This allows for longer hold times for the

SPI master to sample the LSB of the data. When this bit is set, CS must not

be tied low.

RW

0

1

Disabled

Enabled

7

6

CONTREAD

DATA_STAT

This enables continuous read of the ADC data register. The ADC should be 0x0

configured in continuous conversion mode to use continuous read. For

more details, see the Operating Modes section.

Disabled

Enabled

RW

0

1

This enables the Status Register to be appended to the Data Register

when read so that channel and status information are transmitted with

the data. This is the only way to be sure that the channel bits read from

the Status Register correspond to the data in the Data Register.

0x0

0

1

Disabled

Enabled

5

REG_CHECK

This bit enables a register integrity checker, which can be used to monitor 0x0

any change in the value of the user registers. To use this feature, all other

registers should be configured as desired, with this bit cleared. Then write

to this register to set the REG_CHECK bit to 1. If the contents of any of the

registers change, the REG_ERROR bit is set in the Status Register. To clear

the error, the REG_CHECK bit should be set to 0. Neither the Interface

Mode Register nor the ADC Data or Status Register is included in the

registers that are checked. If a register needs to have a new value written,

this bit should first be cleared; otherwise, an error will be flagged falsely

when the new register contents are written.

RW

0

1

Disabled

Enabled

4

RESERVED

This bit is reserved and should be set to 0.

0x0

R

Rev. 0 | Page 49 of 68

AD7176-2

Data Sheet

Bits

Bit Name

Settings

Description

Reset

Access

[3:2]

CRC_EN

Enables CRC protection of register reads/writes. CRC increases the

number of bytes in a serial interface transfer by one. See the CRC

Calculation section for more details.

0x00

RW

00 Disabled.

01 XOR checksum enabled for register read transactions. Register writes will

still use CRC with these bits set.

10 CRC checksum enabled for read and write transactions.

This bit is reserved and should be set to 0.

1

0

RESERVED

WL16

0x0

R

Changes the ADC Data Register to 16 bits. The ADC is not reset by a write

to the Interface Mode Register; therefore, the ADC result will not be

rounded to the correct word length immediately after writing to these

bits. The first new ADC result will be correct.

RW

0

1

24-bit data

16-bit data

REGISTER CHECK

Address: 0x03, Reset: 0x000000, Name: REGCHECK

This Register Check Register is a 24-bit checksum calculated by exclusively OR'ing the contents of the user registers. The REG_CHECK

bit in the Interface Mode Register must be set for this to operate; otherwise, the register reads 0.

Table 26. Bit Descriptions for REGCHECK

Bits

Bit Name

Settings

Description

Reset

Access

[23:0]

REGISTER_CHECK

This register contains the 24-bit checksum of user registers when the

REG_CHECK bit is set in the Interface Mode Register.

0x000000

R

DATA REGISTER

Address: 0x04, Reset: 0x000000, Name: DATA

The Data Register contains the ADC conversion result. The encoding is offset binary, or it can be changed to unipolar by the

BI_UNIPOLAR bit in the Setup Configuration Register. Reading the Data Register brings the bit and pin high if they had been low.

RDY

has been brought high, it is not possible to know if another ADC

The ADC result can be read multiple times; however, because

RDY

result is imminent. The ADC will not write a new result into the data register if the register is currently being read.

Table 27. Bit Descriptions for DATA

Bits

Bit Name

Settings

Description

Reset

Access

[23:0]

DATA

This register contains the ADC conversion result. If DATA_STAT is set in

the Interface Mode Register, then the Status Register is appended to this

register when read, making this a 32-bit register. If WL16 is set in the

Interface Mode Register, then this register is rounded to 16 bits.

0x000000

R

Rev. 0 | Page 50 of 68

Data Sheet

AD7176-2

GPIO CONFIGURATION REGISTER

Address: 0x06, Reset: 0x0800, Name: GPIOCON

The GPIO Configuration Register controls the general-purpose I/O pins of the ADC.

Table 28. Bit Descriptions for GPIOCON

Bits

Bit Name

Settings

Description

Reset

Access

R

[15:13] RESERVED

These bits are reserved and should be set to 0.

0x0

12

11

MUX_IO

This bit allows the ADC to control an external multiplexer, using GPIO0/GPIO1

in sync with the internal channel sequencing. The analog input pins used

for a channel can still be selected on a per channel basis. Therefore, it is

possible to have a 4-channel multiplexer in front of AIN0/AIN1 and another

in front of AIN2/AIN3, giving a total of eight differential channels with the

AD7175-2. However, only four channels at a time can be automatically

sequenced. A delay can be inserted after switching an external multiplexer

(see the DELAY bits in the ADC Mode Register).

RW

SYNC_EN

This bit enables the SYNC/ERROR pin as a sync input. When set low, the

SYNC/ERROR pin holds the ADC and filter in reset until SYNC/ERROR goes

high. An alternative operation of the SYNC/ERROR pin is available when

the ALT_SYNC bit in the Interface Mode Register is set. This mode only

works when multiple channels are enabled. In this case, a low on the SYNC

/ERROR pin does not immediately reset the filter/modulator. Instead, if the

SYNC/ERROR pin is low when the channel is due to be switched, the

modulator and filter are prevented from starting a new conversion.

Bringing SYNC/ERROR high begins the next conversion. This alternative

sync mode allows SYNC/ERROR to be used while cycling through channels.

0x1

RW

0

1

Disabled

Enabled

[10:9]

ERR_EN

These bits enable the SYNC/ERROR pin as an error input/output.

0x0

RW

00 Disabled

01 SYNC/ERROR is an error input. The (inverted) readback state is OR'ed with

other error sources and is available in the ADC_ERROR bit in the Status

Register. The SYNC/ERROR pin state can also be read from the ERR_DAT bit

in this register.

10 SYNC/ERROR is an open-drain error output. The Status Register error bits

are OR'ed, inverted, and mapped to the SYNC/ERROR pin. SYNC/ERROR

pins of multiple devices can be wired together to a common pull-up

resistor so that an error on any device can be observed.

11 SYNC/ERROR is a general-purpose output. The status of the pin is

controlled by the ERR_DAT bit in this register. This is referenced between

IOVDD and DGND, as opposed to the AVDD1 and AVSS levels used by the

general-purpose I/O pins. It has an active pull-up in this case.

8

ERR_DAT

This bit determines the logic level at the ERROR pin if the pin is enabled as 0x0

a general-purpose output. It reflects the readback status of the pin if the

pin is enabled as an input.

RW

[7:6]

5

RESERVED

IP_EN1

These bits are reserved and should be set to 0.

0x0

R

This bit turns GPIO1 into an input. Input should equal AVDD5 or AVSS.

RW

0

1

Disabled

Enabled

4

3

IP_EN0

This bit turns GPIO0 into an input. Input should equal AVDD5 or AVSS.

Disabled

Enabled

0x0

RW

0

1

OP_EN1

This bit turns GPIO1 into an output. Outputs are referenced between

AVDD1 and AVSS.

0

1

Disabled

Enabled

2

OP_EN0

This bit turns GPIO0 into an output. Outputs are referenced between

AVDD1 and AVSS.

0x0

RW

Rev. 0 | Page 51 of 68

AD7176-2

Data Sheet

Bits

Bit Name

Settings

Description

Reset

Access

0

1

Disabled

Enabled

1

0

GP_DATA1

GP_DATA0

This bit is the readback or write data for GPIO1.

This bit is the readback or write data for GPIO0.

0x0

RW

ID REGISTER

Address: 0x07, Reset: 0x0C9X, Name: ID

The ID register returns a 16-bit ID. For the AD7176-2, this should be 0x0C94.

Table 29. Bit Descriptions for ID

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

ID

The ID register returns a 16-bit ID code that is specific to the ADC.

0x0C9X

R

0x0C9X AD7176-2

Rev. 0 | Page 52 of 68

Data Sheet

AD7176-2

CHANNEL MAP REGISTER 0

Address: 0x10, Reset: 0x8001, Name: CHMAP0

The Channel Map Registers are 16-bit registers that are used to select which channels are currently active, which inputs are selected for

each channel, and which setup should be used to configure the ADC for that channel.

Table 30. Bit Descriptions for CHMAP0

Bits

Bit Name

Settings

Description

Reset

Access

15

CH_EN0

This bit enables Channel 0. If more than one channel is enabled, the ADC

will automatically sequence between them.

0x1

RW

0

1

Disabled

Enabled (default)

14

RESERVED

This bit is reserved and should be set to 0.

0x0

R

[13:12] SETUP_SEL0

These bits identify which of the four setups are used to configure the ADC 0x0

for this channel. A setup comprises a set of four registers: Setup Configuration

Register, Filter Configuration Register, Offset Register, Gain Register. All

channels can use the same setup, in which case the same 3-bit value should

be written to these bits on all active channels, or up to four channels can

be configured differently.

RW

000 Setup 0

001 Setup 1

010 Setup 2

011 Setup 3

[11:10] RESERVED

[9:5] AINPOS0

These bits are reserved and should be set to 0.

0x0

R

These bits select which of the analog inputs is connected to the positive

input of the ADC for this channel.

RW

00000 AIN0 (default)

00001 AIN1

00010 AIN2

00011 AIN3

00100 AIN4

10101 REF+

10110 REF−

[4:0]

AINNEG0

These bits select which of the analog inputs is connected to the negative

input of the ADC for this channel.

00000 AIN0

0x1

RW

00001 AIN1 (default)

00010 AIN2

00011 AIN3

00100 AIN4

10101 REF+

10110 REF−

Rev. 0 | Page 53 of 68

AD7176-2

Data Sheet

CHANNEL MAP REGISTER 1

Address: 0x11, Reset: 0x0001, Name: CHMAP1

The Channel Map Registers are 16-bit registers that are used to select which channels are currently active, which inputs are selected for

each channel, and which setup should be used to configure the ADC for that channel.

Table 31. Bit Descriptions for CHMAP1

Bits

Bit Name

Settings

Description

Reset

Access

15

CH_EN1

This bit enables Channel 1. If more than one channel is enabled, the ADC

will automatically sequence between them.

0x0

RW

0

1

Disabled (default)

Enabled

14

RESERVED

This bit is reserved and should be set to 0.

0x0

R

[13:12] SETUP_SEL1

These bits identify which of the four setups are used to configure the ADC 0x0

for this channel. A setup comprises a set of four registers: Setup Configuration

Register, Filter Configuration Register, Offset Register, Gain Register. All

channels can use the same setup, in which case the same 3-bit value should

be written to these bits on all active channels, or up to four channels can

be configured differently.

RW

000 Setup 0

001 Setup 1

010 Setup 2

011 Setup 3

[11:10] RESERVED

[9:5] AINPOS1

These bits are reserved and should be set to 0.

0x0

R

These bits select which of the analog inputs is connected to the positive

input of the ADC for this channel.

RW

00000 AIN0 (default)

00001 AIN1

00010 AIN2

00011 AIN3

00100 AIN4

10101 REF+

10110 REF−

[4:0]

AINNEG1

These bits select which of the analog inputs is connected to the negative

input of the ADC for this channel.

00000 AIN0

0x1

RW

00001 AIN1 (default)

00010 AIN2

00011 AIN3

00100 AIN4

10101 REF+

10110 REF−

Rev. 0 | Page 54 of 68

Data Sheet

AD7176-2

CHANNEL MAP REGISTER 2

Address: 0x12, Reset: 0x0001, Name: CHMAP2

The Channel Map Registers are 16-bit registers that are used to select which channels are currently active, which inputs are selected for

each channel, and which setup should be used to configure the ADC for that channel.

Table 32. Bit Descriptions for CHMAP2

Bits

Bit Name

Settings

Description

Reset

Access

15

CH_EN2

This bit enables Channel 2. If more than one channel is enabled, the ADC

will automatically sequence between them.

0x0

RW

0

1

Disabled (default)

Enabled

14

RESERVED

This bit is reserved and should be set to 0.

0x0

R

[13:12] SETUP_SEL2

These bits identify which of the four setups are used to configure the ADC 0x0

for this channel. A setup comprises a set of four registers: Setup Configuration

Register, Filter Configuration Register, Offset Register, Gain Register. All

channels can use the same setup, in which case the same 3-bit value should

be written to these bits on all active channels, or up to four channels can

be configured differently.

RW

000 Setup 0

001 Setup 1

010 Setup 2

011 Setup 3

[11:10] RESERVED

[9:5] AINPOS2

These bits are reserved and should be set to 0.

0x0

R

These bits select which of the analog inputs is connected to the positive

input of the ADC for this channel.

RW

00000 AIN0 (default)

00001 AIN1

00010 AIN2

00011 AIN3

00100 AIN4

10101 REF+

10110 REF−

[4:0]

AINNEG2

These bits select which of the analog inputs is connected to the negative

input of the ADC for this channel.

00000 AIN0

0x1

RW

00001 AIN1 (default)

00010 AIN2

00011 AIN3

00100 AIN4

10101 REF+

10110 REF−

Rev. 0 | Page 55 of 68

AD7176-2

Data Sheet

CHANNEL MAP REGISTER 3

Address: 0x13, Reset: 0x0001, Name: CHMAP3

The Channel Map Registers are 16-bit registers that are used to select which channels are currently active, which inputs are selected for

each channel, and which setup should be used to configure the ADC for that channel.

Table 33. Bit Descriptions for CHMAP3

Bits

Bit Name

Settings

Description

Reset

Access

15

CH_EN3

This bit enables Channel 3. If more than one channel is enabled, the ADC

will automatically sequence between them.

0x0

RW

0

1

Disabled (default)

Enabled

14

RESERVED

This bit is reserved and should be set to 0.

0x0

R

[13:12] SETUP_SEL3

These bits identify which of the four setups are used to configure the ADC 0x0

for this channel. A setup comprises a set of four registers: Setup Configuration

Register, Filter Configuration Register, Offset Register, Gain Register. All

channels can use the same setup, in which case the same 3-bit value should

be written to these bits on all active channels, or up to four channels can

be configured differently.

RW

000 Setup 0

001 Setup 1

010 Setup 2

011 Setup 3

[11:10] RESERVED

[9:5] AINPOS3

These bits are reserved and should be set to 0.

0x0

R

These bits select which of the analog inputs is connected to the positive

input of the ADC for this channel.

RW

00000 AIN0 (default)

00001 AIN1

00010 AIN2

00011 AIN3

00100 AIN4

10101 REF+

10110 REF−

[4:0]

AINNEG3

These bits select which of the analog inputs is connected to the negative

input of the ADC for this channel.

00000 AIN0

0x1

RW

00001 AIN1 (default)

00010 AIN2

00011 AIN3

00100 AIN4

10101 REF+

10110 REF−

Rev. 0 | Page 56 of 68

Data Sheet

AD7176-2

SETUP CONFIGURATION REGISTER 0

Address: 0x20, Reset: 0x1020, Name: SETUPCON0

The Setup Configuration Registers are 16-bit registers that configure the reference selection and output coding of the ADC.

Table 34. Bit Descriptions for SETUPCON0

Bits

Bit Name

Settings

Description

Reset

0x0

Access

R

[15:13] RESERVED

These bits are reserved and should be set to 0.

This bit sets the output coding of the ADC for Setup 0.

Unipolar coded output

12

BI_UNIPOLAR0

0x1

RW

0

1

Offset binary coded output

[11:6]

[5:4]

RESERVED

REF_SEL0

These bits are reserved and should be set to 0.

0x00

0x2

R

These bits allow you to select the reference source for ADC conversion on

Setup 0.

RW

00 External Reference.

10 Internal 2.5 V Reference. This must also be enabled in the ADC Mode Register.

11 AVDD1 − AVSS. This can be used to as a diagnostic to validate other

reference values.

[3:0]

RESERVED

These bits are reserved and should be set to 0.

0x0

R

SETUP CONFIGURATION REGISTER 1

Address: 0x21, Reset: 0x1020, Name: SETUPCON1

The Setup Configuration Registers are 16-bit registers that configure the reference selection and output coding of the ADC.

Table 35. Bit Descriptions for SETUPCON1

Bits

Bit Name

Settings

Description

Reset

0x0

Access

R

[15:13] RESERVED

These bits are reserved and should be set to 0.

This bit sets the output coding of the ADC for Setup 1.

Unipolar coded output

12

BI_UNIPOLAR1

0x1

RW

0

1

Offset binary coded output

[11:6]

[5:4]

RESERVED

REF_SEL1

These bits are reserved and should be set to 0.

0x00

0x2

R

These bits allow you to select the reference source for ADC conversion on

Setup 1.

RW

00 External Reference

10 Internal 2.5 V Reference. This must also be enabled in the ADC Mode Register.

11 AVDD1 − AVSS. This can be used to as a diagnostic to validate other

reference values.

[3:0]

RESERVED

These bits are reserved and should be set to 0.

0x0

R

Rev. 0 | Page 57 of 68

AD7176-2

Data Sheet

SETUP CONFIGURATION REGISTER 2

Address: 0x22, Reset: 0x1020, Name: SETUPCON2

The Setup Configuration Registers are 16-bit registers that configure the reference selection and output coding of the ADC.

Table 36. Bit Descriptions for SETUPCON2

Bits

Bit Name

Settings

Description

Reset

0x0

Access

R

[15:13] RESERVED

These bits are reserved and should be set to 0.

This bit sets the output coding of the ADC for Setup 2.

Unipolar coded output

12

BI_UNIPOLAR2

0x1

RW

0

1

Offset binary coded output

[11:6]

[5:4]

RESERVED

REF_SEL2

These bits are reserved and should be set to 0.

0x00

0x2

R

These bits allow you to select the reference source for ADC conversion on

Setup 2.

RW

00 External Reference

10 Internal 2.5 V Reference. This must also be enabled in the ADC Mode Register.

11 AVDD1 − AVSS. This can be used to as a diagnostic to validate other

reference values.

[3:0]

RESERVED

These bits are reserved and should be set to 0.

0x0

R

SETUP CONFIGURATION REGISTER 3

Address: 0x23, Reset: 0x1020, Name: SETUPCON3

The Setup Configuration Registers are 16-bit registers that configure the reference selection and output coding of the ADC.

Table 37. Bit Descriptions for SETUPCON3

Bits

Bit Name

Settings

Description

Reset

0x0

Access

R

[15:13] RESERVED

These bits are reserved and should be set to 0.

This bit sets the output coding of the ADC for Setup 3.

Unipolar coded output

12

BI_UNIPOLAR3

0x1

RW

0

1

Offset binary coded output

[11:6]

[5:4]

RESERVED

REF_SEL3

These bits are reserved and should be set to 0.

0x00

0x2

R

These bits allow you to select the reference source for ADC conversion on

Setup 3.

RW

00 External Reference

10 Internal 2.5 V Reference. This must also be enabled in the ADC Mode Register.

11 AVDD1 − AVSS. This can be used to as a diagnostic to validate other

reference values.

[3:0]

RESERVED

These bits are reserved and should be set to 0.

0x0

R

Rev. 0 | Page 58 of 68

Data Sheet

AD7176-2

FILTER CONFIGURATION REGISTER 0

Address: 0x28, Reset: 0x0000, Name: FILTCON0

The Filter Configuration Registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers

resets any active ADC conversion and restarts converting at the first channel in the sequence.

Table 38. Bit Descriptions for FILTCON0

Bits

Bit Name

Settings

Description

Reset

Access

15

SINC3_MAP0

If this bit is set, the mapping of the Filter Register changes to directly

program the decimation rate of the Sinc3 filter for Setup 0. All other

options are eliminated. This allows for fine tuning of the output data rate

and filter notch for rejection of specific frequencies. The data rate when on

a single channel equals FMOD/(32 × FILTCON0[14:0]).

0x0

RW

[14:12] RESERVED

These bits are reserved and should be set to 0.

0x0

R

11

ENHFILTEN0

This bit enables various post filters for enhanced 50 Hz/60 Hz rejection for 0x0

Setup 0. The ORDER bits must be set to 00 to select the Sinc5 + Sinc1 filter

for this to work.

RW

0

1

Disabled

Enabled

[10:8]

ENHFILT0

These bits select between various post filters for enhanced 50 Hz/60 Hz

rejection for Setup 0.

0x0

RW

010 27 SPS, 47 dB rejection, 36.7 ms settling

011 25 SPS, 62 dB rejection, 40 ms settling

101 20 SPS, 86 dB rejection, 50 ms settling

110 16.67 SPS, 92 dB rejection, 60 ms settling

This bit is reserved and should be set to 0.

7

RESERVED

ORDER0

0x0

R

[6:5]

These bits control the order of the digital filter that processes the

modulator data for Setup 0.

RW

00 Sinc5 + Sinc1 (default)

11 Sinc3

[4:0]

ODR0

These bits control the output data rate of the ADC and, therefore, the

settling time and noise for Setup 0.

0x0

RW

00000 250,000

00001 125,000

00010 62,500

00011 50,000

00100 31,250

00101 25,000

00110 15,625

00111 10,000

01000 5000

01001 2500

01010 1000

01011 500

01100 397.5

01101 200

01110 100

01111 59.94

10000 49.96

10001 20

10010 16.667

10011 10

10100

5

Rev. 0 | Page 59 of 68

AD7176-2

Data Sheet

FILTER CONFIGURATION REGISTER 1

Address: 0x29, Reset: 0x0000, Name: FILTCON1

The Filter Configuration Registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers

resets any active ADC conversion and restarts converting at the first channel in the sequence.

Table 39. Bit Descriptions for FILTCON1

Bits

Bit Name

Settings

Description

Reset

Access

15

SINC3_MAP1

If this bit is set, the mapping of the Filter Register changes to directly

program the decimation rate of the Sinc3 filter for Setup 1. All other

options are eliminated. This allows for fine tuning of the output data rate

and filter notch for rejection of specific frequencies. The data rate when on

a single channel equals FMOD/(32 × FILTCON1[14:0]).

0x0

RW

[14:12] RESERVED

These bits are reserved and should be set to 0.

0x0

R

11

ENHFILTEN1

This bit enables various post filters for enhanced 50 Hz/60 Hz rejection for 0x0

Setup 1. The ORDER bits must be set to 00 to select the Sinc5 + Sinc1 filter

for this to work.

RW

0

1

Disabled

Enabled

[10:8]

ENHFILT1

These bits select between various post filters for enhanced 50 Hz/60 Hz

rejection for Setup 1.

0x0

RW

010 27 SPS, 47 dB rejection, 36.7 ms settling

011 25 SPS, 62 dB rejection, 40 ms settling

101 20 SPS, 86 dB rejection, 50 ms settling

110 16.67 SPS, 92 dB rejection, 60 ms settling

This bit is reserved and should be set to 0.

7

RESERVED

ORDER1

0x0

R

[6:5]

These bits control the order of the digital filter that processes the

modulator data for Setup 1.

RW

00 Sinc5 + Sinc1 (default)

11 Sinc3

[4:0]

ODR1

These bits control the output data rate of the ADC and, therefore, the

settling time and noise for Setup 1.

0x0

RW

00000 250,000

00001 125,000

00010 62,500

00011 50,000

00100 31,250

00101 25,000

00110 15,625

00111 10,000

01000 5000

01001 2500

01010 1000

01011 500

01100 397.5

01101 200

01110 100

01111 59.94

10000 49.96

10001 20

10010 16.667

10011 10

10100

5

Rev. 0 | Page 60 of 68

Data Sheet

AD7176-2

FILTER CONFIGURATION REGISTER 2

Address: 0x2A, Reset: 0x0000, Name: FILTCON2

The Filter Configuration Registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers

resets any active ADC conversion and restarts converting at the first channel in the sequence.

Table 40. Bit Descriptions for FILTCON2

Bits

Bit Name

Settings

Description

Reset

Access

15

SINC3_MAP2

If this bit is set, the mapping of the Filter Register changes to directly

program the decimation rate of the Sinc3 filter for Setup 2. All other

options are eliminated. This allows for fine tuning of the output data rate

and filter notch for rejection of specific frequencies. The data rate when on

a single channel equals FMOD/(32 × FILTCON2[14:0]).

0x0

RW

[14:12] RESERVED

These bits are reserved and should be set to 0.

0x0

R

11

ENHFILTEN2

This bit enables various post filters for enhanced 50 Hz/60 Hz rejection for 0x0

Setup 2. The ORDER bits must be set to 00 to select the Sinc5 + Sinc1 filter

for this to work.

RW

0

1

Disabled

Enabled

[10:8]

ENHFILT2

These bits select between various post filters for enhanced 50 Hz/60 Hz

rejection for Setup 2.

0x0

RW

010 27 SPS, 47dB rejection, 36.7 ms settling

011 25 SPS, 62 dB rejection, 40 ms settling

101 20 SPS, 86 dB rejection, 50 ms settling

110 16.67 SPS, 92 dB rejection, 60 ms settling

This bit is reserved and should be set to 0.

7

RESERVED

ORDER2

0x0

R

[6:5]

These bits control the order of the digital filter that processes the

modulator data for Setup 2.

RW

00 Sinc5 + Sinc1 (default)

11 Sinc3

[4:0]

ODR2

These bits control the output data rate of the ADC and, therefore, the

settling time and noise for Setup 2.

0x0

RW

00000 250,000

00001 125,000

00010 62,500

00011 50,000

00100 31,250

00101 25,000

00110 15,625

00111 10,000

01000 5000

01001 2500

01010 1000

01011 500

01100 397.5

01101 200

01110 100

01111 59.94

10000 49.96

10001 20

10010 16.667

10011 10

10100

5

Rev. 0 | Page 61 of 68

AD7176-2

Data Sheet

FILTER CONFIGURATION REGISTER 3

Address: 0x2B, Reset: 0x0000, Name: FILTCON3

The Filter Configuration Registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers

resets any active ADC conversion and restarts converting at the first channel in the sequence.

Table 41. Bit Descriptions for FILTCON3

Bits

Bit Name

Settings

Description

Reset

Access

15

SINC3_MAP3

If this bit is set, the mapping of the Filter Register changes to directly

program the decimation rate of the Sinc3 filter for Setup 3. All other

options are eliminated. This allows for fine tuning of the output data rate

and filter notch for rejection of specific frequencies. The data rate when on

a single channel equals FMOD/(32 × FILTCON3[14:0]).

0x0

RW

[14:12] RESERVED

These bits are reserved and should be set to 0.

0x0

R

11

ENHFILTEN3

This bit enables various post filters for enhanced 50 Hz/60 Hz rejection for 0x0

Setup 3. The ORDER bits must be set to 00 to select the Sinc5 + Sinc1 filter

for this to work.

RW

0

1

Disabled

Enabled

[10:8]

ENHFILT3

These bits select between various post filters for enhanced 50 Hz/60 Hz

rejection for Setup 3.

0x0

RW

010 27 SPS, 47 dB rejection, 36.7 ms settling

011 25 SPS, 62 dB rejection, 40 ms settling

101 20 SPS, 86 dB rejection, 50 ms settling

110 16.67 SPS, 92 dB rejection, 60 ms settling

This bit is reserved and should be set to 0.

7

RESERVED

ORDER3

0x0

R

[6:5]

These bits control the order of the digital filter that processes the

modulator data for Setup 3.

RW

00 Sinc5 + Sinc1 (default)

11 Sinc3

[4:0]

ODR3

These bits control the output data rate of the ADC and, therefore, the

settling time and noise for Setup 3.

0x0

RW

00000 250,000

00001 125,000

00010 62,500

00011 50,000

00100 31,250

00101 25,000

00110 15,625

00111 10,000

01000 5000

01001 2500

01010 1000

01011 500

01100 397.5

01101 200

01110 100

01111 59.94

10000 49.96

10001 20

10010 16.667

10011 10

10100

5

Rev. 0 | Page 62 of 68

Data Sheet

AD7176-2

OFFSET REGISTER 0

Address: 0x30, Reset: 0x800000, Name: OFFSET0

The Offset (Zero-Scale) Registers are 24-bit registers that can be used to compensate for any offset error in the ADC or in the system.

Table 42. Bit Descriptions for OFFSET0

Bits

Bit Name

Settings

Description

Reset

Access

[23:0]

OFFSET0

Offset calibration coefficient for Setup 0.

0x800000 RW

OFFSET REGISTER 1

Address: 0x31, Reset: 0x800000, Name: OFFSET1

The Offset (Zero-Scale) Registers are 24-bit registers that can be used to compensate for any offset error in the ADC or in the system.

Table 43. Bit Descriptions for OFFSET1

Bits

Bit Name

Settings

Description

Reset

Access

[23:0]

OFFSET1

Offset calibration coefficient for Setup 1.

0x800000 RW

OFFSET REGISTER 2

Address: 0x32, Reset: 0x800000, Name: OFFSET2

The Offset (Zero-Scale) Registers are 24-bit registers that can be used to compensate for any offset error in the ADC or in the system.

Table 44. Bit Descriptions for OFFSET2

Bits

Bit Name

Settings

Description

Reset

Access

[23:0]

OFFSET2

Offset calibration coefficient for Setup 2.

0x800000 RW

OFFSET REGISTER 3

Address: 0x33, Reset: 0x800000, Name: OFFSET3

The Offset (Zero-Scale) Registers are 24-bit registers that can be used to compensate for any offset error in the ADC or in the system.

Table 45. Bit Descriptions for OFFSET3

Bits

Bit Name

Settings

Description

Reset

Access

[23:0]

OFFSET3

Offset calibration coefficient for Setup 3.

0x800000 RW

Rev. 0 | Page 63 of 68

AD7176-2

Data Sheet

GAIN REGISTER 0

Address: 0x38, Reset: 0x5xxxx0, Name: GAIN0

The Gain (Full-Scale) Registers are 24-bit registers that can be used to compensate for any gain error in the ADC or in the system.

Table 46. Bit Descriptions for GAIN0

Bits

Bit Name

Settings

Description

Reset

Access

[23:0]

GAIN0

Gain calibration coefficient for Setup 0.

0x5XXXX0 RW

GAIN REGISTER 1

Address: 0x39, Reset: 0x5xxxx0, Name: GAIN1

The Gain (Full-Scale) Registers are 24-bit registers that can be used to compensate for any gain error in the ADC or in the system.

Table 47. Bit Descriptions for GAIN1

Bits

Bit Name

Settings

Description

Reset

Access

[23:0]

GAIN1

Gain calibration coefficient for Setup 1.

0x5XXXX0 RW

GAIN REGISTER 2

Address: 0x3A, Reset: 0x5xxxx0, Name: GAIN2

The Gain (Full-Scale) Registers are 24-bit registers that can be used to compensate for any gain error in the ADC or in the system.

Table 48. Bit Descriptions for GAIN2

Bits

Bit Name

Settings

Description

Reset

Access

[23:0]

GAIN2

Gain calibration coefficient for Setup 2.

0x5XXXX0 RW

GAIN REGISTER 3

Address: 0x3B, Reset: 0x5xxxx0, Name: GAIN3

The Gain (Full-Scale) Registers are 24-bit registers that can be used to compensate for any gain error in the ADC or in the system.

Table 49. Bit Descriptions for GAIN3

Bits

Bit Name

Settings

Description

Reset

Access

[23:0]

GAIN3

Gain calibration coefficient for Setup 3.

0x5XXXX0 RW

Rev. 0 | Page 64 of 68

Data Sheet

AD7176-2

OUTLINE DIMENSIONS

7.90

7.80

7.70

24

13

12

4.50

4.40

4.30

6.40 BSC

1

PIN 1

0.65

BSC

1.20

MAX

0.15

0.05

0.75

0.60

0.45

8°

0°

0.30

0.19

0.20

0.09

SEATING

PLANE

0.10 COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-AD

Figure 52. 24-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-24)

Dimensions shown in millimeters

ORDERING GUIDE

Models¹

Temperature Range

Package Description

24-Lead TSSOP

Evaluation Board

Evaluation Controller Board

Package Option

RU-24

AD7176-2BRUZ

AD7176-2BRUZ-RL

EVAL-AD7176-2SDZ

EVAL-SDP-CB1Z

–40°C to +105°C

¹Z = RoHS Compliant Part.

Rev. 0 | Page 65 of 68

AD7176-2

NOTES

Data Sheet

Rev. 0 | Page 66 of 68

Data Sheet

NOTES

AD7176-2

Rev. 0 | Page 67 of 68

AD7176-2

NOTES

Data Sheet

registered trademarks are the property of their respective owners.

D11037-0-11/12(0)

Rev. 0 | Page 68 of 68


型号：	EVAL-AD7176-2SDZ
厂家：	ADI
描述：	The AD7176-2 is a fast settling, highly accurate, high resolution, multiplexed Î£-Î analog-to-digital converter (ADC) for low band-width input signals. 该AD7176-2是一个快速稳定，高精确度，高解析度，复用I -I英镑？模拟 - 数字转换器（ADC ），用于低频段宽的输入信号。转换器
文件：	总68页 (文件大小：959K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EVAL-AD7176-2SDZ [ADI]

相关型号：

EVAL-AD7262EDZ

EVAL-AD7264EDZ

EVAL-AD7265CB

EVAL-AD7265CB1

EVAL-AD7266CB1

EVAL-AD7266EDZ

EVAL-AD7273CB

EVAL-AD7273CB3

EVAL-AD7274CB

EVAL-AD7274CB3

EVAL-AD7276CBZ

EVAL-AD7291SDZ