DAC8512 [ADI]
% V, Serial Input Complete 12-Bit DAC; ％V ，串行输入完整的12位DAC
| 型号： | DAC8512 |
| 厂家： | 
ADI |
| 描述： | % V, Serial Input Complete 12-Bit DAC |
| 文件： | 总20页 (文件大小：759K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
+5 V, Serial Input
Complete 12-Bit DAC
a
DAC8512
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Space Saving SO-8 or Mini-DIP Packages
Complete, Voltage Output with Internal Reference
1 mV/Bit with 4.095 V Full Scale
Single +5 Volt Operation
V
V
1
8
DD
REF
12-BIT DAC
12
OUT
No External Components
3-Wire Serial Data Interface, 20 MHz Data Loading Rate
Low Power: 2.5 mW
6
5
CLR
LD
DAC REGISTER
12
GND
7
APPLICATIONS
2
3
4
CS
CLK
SDI
SERIAL REGISTER
Portable Instrumentation
Digitally Controlled Calibration
Servo Controls
Process Control Equipment
PC Peripherals
Serial interface is high speed, three-wire, DSP compatible with
data in (SDI), clock (CLK) and load strobe (LD). There is also
a chip-select pin for connecting multiple DACs.
GENERAL DESCRIPTION
The DAC8512 is a complete serial input, 12-bit, voltage output
digital-to-analog converter designed to operate from a single
+5 V supply. It contains the DAC, input shift register and
latches, reference and a rail-to-rail output amplifier. Built using
a CBCMOS process, these monolithic DACs offer the user low
cost, and ease of use in +5 V only systems.
A CLR input sets the output to zero scale at power on or upon
user demand.
The DAC8512 is specified over the extended industrial (–40°C
to +85°C) temperature range. DAC8512s are available in plas-
tic DIPs and SO-8 surface mount packages.
Coding for the DAC8512 is natural binary with the MSB loaded
first. The output op amp can swing to either rail and is set to a
range of 0 V to +4.095 V—for a one-millivolt-per-bit resolution.
It is capable of sinking and sourcing 5 mA. An on-chip reference
is laser trimmed to provide an accurate full-scale output voltage
of 4.095 V.
1.0
0.75
0.5
0.25
0
–0.25
–0.5
–0.75
–1.0
0
1024
2048
3072
4096
DIGITAL INPUT CODE – Decimal
Linearity Error vs. Digital Input Code
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1996
DAC8512–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ VDD = +5.0 V ؎ 5%, –40؇C ≤ TA ≤ +85؇C, unless otherwise noted)
Parameter
Symbol
Condition
Min
Typ
Max
Units
STATIC PERFORMANCE
Resolution
Relative Accuracy
N
INL
Note 2
12
–1
–2
–1
Bits
LSB
LSB
LSB
LSB
V
E Grade
F Grade
±1/4
±3/4
±3/4
+1/2
4.095
4.095
16
+1
+2
+1
+3
4.103
4.111
Differential Nonlinearity
Zero-Scale Error
Full-Scale Voltage
DNL
VZSE
VFS
No Missing Codes
Data = 000H
Data = FFFH
3
E Grade
F Grade
4.087
4.079
V
Full-Scale Tempco
TCVFS
Notes 3, 4
ppm/°C
ANALOG OUTPUT
Output Current
Load Regulation at Full Scale
Capacitive Load
IOUT
LREG
CL
Data = 800H
±5
±7
1
500
mA
LSB
pF
RL = 402 Ω to ∞, Data = 800H
3
No Oscillation4
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance
VIL
VIH
IIL
0.8
V
V
µA
pF
2.4
10
10
CIL
INTERFACE TIMING SPECIFICATIONS1, 4
Clock Width High
Clock Width Low
Load Pulse Width
Data Setup
Data Hold
Clear Pulse Width
Load Setup
Load Hold
Select
Deselect
tCH
tCL
tLDW
tDS
tDH
tCLRW
tLD1
tLD2
tCSS
tCSH
30
30
20
15
15
30
15
10
30
20
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
5
20
AC CHARACTERISTICS4
Voltage Output Settling Time
DAC Glitch
tS
To ±1 LSB of Final Value5
16
15
15
µs
nV s
nV s
Digital Feedthrough
SUPPLY CHARACTERISTICS
Positive Supply Current
IDD
VIH = 2.4 V, VIL = 0.8 V, No Load
DD = 5 V, VIL = 0 V, No Load
VIH = 2.4 V, VIL = 0.8 V, No Load
DD = 5 V, VIL = 0 V, No Load
∆VDD = ±5%
1.5
0.5
7.5
2.5
2.5
1
12.5
5
mA
mA
mW
mW
V
Power Dissipation
PDISS
PSS
V
Power Supply Sensitivity
0.002
0.004 %/%
NOTES
1All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
21 LSB = 1 mV for 0 V to +4.095 V output range.
3Includes internal voltage reference error.
4These parameters are guaranteed by design and not subject to production testing.
5The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in
this 6 LSB region.
Specifications subject to change without notice.
–2–
REV. A
DAC8512
WAFER TEST LIMITS
Parameter
(@ VDD = +5.0 V ؎ 5%, TA = +25؇C, applies to part number DAC8512GBC only, unless otherwise noted)
Symbol
Condition
Min
Typ
Max
Units
STATIC PERFORMANCE
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
INL
DNL
VZSE
VFS
–2
–1
±3/4
±0.7
+1/2
+2
+1
+3
LSB
LSB
LSB
V
No Missing Codes
Data = 000H
Data = FFFH
Full-Scale Voltage
4.085 4.095 4.105
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
VIL
VIH
IIL
0.8
V
V
µA
2.4
10
SUPPLY CHARACTERISTICS
Positive Supply Current
IDD
VIH = 2.4 V, VIL= 0.8 V, No Load
1.5
0.5
7.5
2.5
2.5
1
12.5
5
mA
mA
mW
mW
%/%
V
DD = 5 V, VIL = 0 V, No Load
VIH = 2.4 V, VIL = 0.8 V, No Load
DD = 5 V, VIL = 0 V, No Load
∆VDD = ±5%
Power Dissipation
PDISS
PSS
V
Power Supply Sensitivity
0.002 0.004
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
ABSOLUTE MAXIMUM RATINGS*
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +10 V
Logic Inputs to GND . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
Operating Temperature Range . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C
V
OUT to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
I
OUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability .
Package Power Dissipation . . . . . . . . . . . . . .(TJ max – TA)/θJA
Thermal Resistance θJA
8-Pin Plastic DIP Package (P) . . . . . . . . . . . . . . . . 103°C/W
8-Lead SOIC Package (S) . . . . . . . . . . . . . . . . . . . 158°C/W
Maximum Junction Temperature (TJ max) . . . . . . . . . +150°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the DAC8512 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
INL
Temperature
Package
Package
Model
(LSB) Range
Description Option
DAC8512EP
DAC8512FP
DAC8512FS
±1
±2
±2
–40°C to +85°C 8-Pin P-DIP N-8
–40°C to +85°C 8-Pin P-DIP N-8
–40°C to +85°C 8-Lead SOIC SO-8
DAC8512GBC ±2
+25°C
Dice
REV. A
–3–
DAC8512
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDI
CLK
CS
tcss
tcsh
tld1
tld2
LD
SDI
tds
tdh
tcl
CLK
tch
tldw
LD
tclrw
ts
CLR
FS
±1 LSB
ERROR BAND
V
OUT
ZS
tS
Figure 1. Timing Diagram
ESD PROTECTION DIODES TO VDD AND GND
CS
SHIFT
REGISTER
CLK
DATA
SDI
Figure 2. Equivalent Clock Input Logic
Table I. Control-Logic Truth Table
CS2
CLK2 CLR LD
Serial Shift Register Function
DAC Register Function
H
L
L
X
L
H
↑+
L
X
X
X
X
H
H
H
H
H
H
↓–
L
No Effect
No Effect
No Effect
Shift-Register-Data Advanced One Bit
Latched
Latched
Latched
Latched
Latched
H
H
H
H
H
H
L
L
↑+
H
H
H
H
Shift-Register-Data Advanced One Bit
No Effect
No Effect
No Effect
No Effect
Updated with Current Shift Register Contents
Transparent
Loaded with All Zeros
X
H
↑+
Latched All Zeros
NOTES
l ↑+ positive logic transition; ↓– negative logic transition; X = Don’t Care.
2CS and CLK are interchangeable.
3Returning CS HIGH avoids an additional “false clock” of serial data input.
4Do not clock in serial data while LD is LOW.
REV. A
–4–
DAC8512
PIN CONFIGURATIONS
P-DIP-8 & Cerdip-8
OPERATION
The DAC8512 is a complete ready to use 12-bit digital-to-analog
converter. It contains a voltage-switched, 12-bit, laser-trimmed
DAC, a curvature-corrected bandgap reference, a rail-to-rail
output op amp, a DAC register, and a serial data input register.
The serial data interface consists of a CLK, serial data in (SDI),
and a load strobe (LD). This basic 3-wire interface offers maxi-
mum flexibility for interface to the widest variety of serial data
input loading requirements. In addition a CS select is provided
for multiple packaging loading and a power on reset CLR pin to
simplify start or periodic resets.
SO-8
V
V
DD
OUT
1
2
3
4
8
7
6
5
V
1
8
7
6
5
V
DD
OUT
GND
CLR
LD
DAC8512
TOP VIEW
(Not to Scale)
CS
GND
CLR
LD
2
3
4
CS
DAC8512
TOP VIEW
(Not to Scale)
CLK
CLK
SDI
SDI
PIN DESCRIPTIONS
Pin Name Description
D/A CONVERTER SECTION
The DAC is a 12-bit voltage mode device with an output that
swings from GND potential to the 2.5 volt internal bandgap
voltage. It uses a laser trimmed R-2R ladder which is switched
by N channel MOSFETs. The output voltage of the DAC has a
constant resistance independent of digital input code. The DAC
output is internally connected to the rail-to-rail output op amp.
1
2
3
4
VDD
CS
CLK
SDI
Positive Supply. Nominal value +5 V, ± 5%.
Chip Select. Active low input.
Clock input for the internal serial input shift register.
Serial Data Input. Data on this pin is clocked into the
internal serial register on positive clock edges of the
CLK pin. The Most Significant Bit (MSB) is loaded
first.
AMPLIFIER SECTION
The DAC’s output is buffered by a low power consumption pre-
cision amplifier. This amplifier contains a differential PNP pair
input stage which provides low offset voltage and low noise, as
well as the ability to amplify the zero-scale DAC output volt-
ages. The rail-to-rail amplifier is configured in a gain of 1.6384
(= 4.095 V/2.5 V) in order to set the 4.095 volt full-scale output
(1 mV/LSB). See Figure 3 for an equivalent circuit schematic of
the analog section.
5
6
LD
Active low input which writes the serial register data
into the DAC register. Asynchronous input.
CLR Active low digital input that clears the DAC register to
zero, setting the DAC to minimum scale. Asynchronous
input.
GND Analog ground for the DAC. This also serves as the
digital logic ground reference voltage.
VOUT Voltage output from the DAC. Fixed output voltage
range of 0 V to 4.095 V with 1 mV/LSB. An internal
temperature stabilized reference maintains a fixed
full-scale voltage independent of time, temperature and
power supply variations.
7
8
VOLTAGE SWITCHED 12-BIT
RAIL-TO-RAIL
R-2R D/A CONVERTER
BANDGAP
REFERENCE
OUTPUT
AMPLIFIER
2R
R
V
OUT
BUFFER
R2
2R
DICE CHARACTERISTICS
R1
R
2.5V
V
V
DD
OUT
2R
AV = 4.095/2.5
= 1.638V/V
1
8
GND
GND
CLR
7
7
6
2R
SPDT
N-CH FET
SWITCHES
2R
2
3
CS
Figure 3. Equivalent DAC8512 Schematic of Analog
Portion
CLK
The op amp has a 16 µs typical settling time to 0.01%. There
are slight differences in settling time for negative slowing signals
vs. positive. See the oscilloscope photos in the typical perfor-
mances section of this data sheet.
5
4
SDI
LD
SUBSTRATE IS COMMON WITH V
.
DD
NUMBER OF TRANSISTORS: 642
DIE SIZE: 0.055 inch × 0.106 inch; 5830 sq mils
REV. A
–5–
DAC8512
OUTPUT SECTION
As with any analog system, it is recommended that the DAC8512
power supply be bypassed on the same PC card that contains the
chip. Figure 10 shows the power supply rejection versus frequen-
cy performance. This should be taken into account when using
higher frequency switched mode power supplies with ripple fre-
quencies of 100 kHz and higher.
The rail-to-rail output stage of this amplifier has been designed
to provide precision performance while operating near either
power supply.
VDD
P-CH
One advantage of the rail-to-rail output amplifier used in the
DAC8512 is the wide range of usable supply voltage. The part
is fully specified and tested over temperature for operation from
+4.75 V to +5.25 V. If reduced linearity and source current ca-
pability near full scale can be tolerated, operation of the DAC8512
is possible down to +4.3 volts. The minimum operating supply
voltage versus load current plot, in Figure 11, provides informa-
tion for operation below VDD = +4.75 V.
VOUT
N-CH
AGND
TIMING AND CONTROL
Figure 4. Equivalent Analog Output Circuit
The DAC8512 has a separate serial input register from the
12-bit DAC register that allows preloading of a new data value
into the serial register without disturbing the present DAC out-
put voltage. After the new value is fully loaded in the serial in-
put register it can be asynchronously transferred to the DAC
register by strobing the LD pin. The DAC register uses a level
sensitive LD strobe that should be returned high before any
new data is loaded into the serial input register. At any time the
contents of the DAC register can be reset to zero by strobing
the CLR pin which causes the DAC output voltage to go to
zero volts. All of the timing requirements are detailed in Figure
1 along with the Table I Control-Logic Truth Table.
Figure 4 shows an equivalent output schematic of the rail-to-rail
amplifier with its N channel pull down FETs that will pull an
output load directly to GND. The output sourcing current is
provided by a P channel pull up device that can supply GND
terminated loads, especially at the low supply tolerance values of
4.75 volts. Figures 5 and 6 provide information on output swing
performance near ground and full-scale as a function of load. In
addition to resistive load driving capability the amplifier has also
been carefully designed and characterized for up to 500 pF ca-
pacitive load driving capability.
POWER SUPPLY
The very low power consumption of the DAC8512 is a direct
result of a circuit design optimizing use of the CBCMOS pro-
cess. By using the low power characteristics of the CMOS for
the logic, and the low noise, tight matching of the complemen-
tary bipolar transistors good analog accuracy is achieved.
For power consumption sensitive applications it is important to
note that the internal power consumption of the DAC8512 is
strongly dependent on the actual logic input voltage levels
present on the SDI, CS, LD, and CLR pins. Since these inputs
are standard CMOS logic structures they contribute static
power dissipation dependent on the actual driving logic VOH and
V
OL voltage levels. The graph in Figure 9 shows the effect on to-
tal DAC8512 supply current as a function of the actual value of
input logic voltage. Consequently use of CMOS logic vs. TTL
minimizes power dissipation in the static state. A VIL = 0 V on
the SDI, CS and CLR pins provides the lowest standby power
dissipation of 2.5 mW (500 µA × 5 V).
REV. A
–6–
Typical Performance Characteristics — DAC8512
100
10
80
5
4
POS0
VDD = +5V
A = +25؇C
VDD = +5V
CURRENT0
LIMIT0
60
40
20
T
DATA = 000H
RL TIEDTOAGND
DATA=FFFH
3
2
DATA = 800H
RL TIED TO +2V
0
TA = +85؇C
1
–20
–40
–60
TA = +25
TA = –40
؇C
0.1
0.01
1
0
؇
C
RL TIED TO +5V
DATA = 000H
NEG
CURRENT
LIMIT
–80
–100
1
10
100
1000
1
2
3
10
100
1k
10k
100k
OUTPUT SINK CURRENT – A
OUTPUT VOLTAGE – Volts
LOAD RESISTANCE – ⍀
Figure 7. Short Circuit Current
Figure 5. Output Swing vs. Load
Figure 6. Pull-Down Voltage vs. Out-
put Sink Current Capability
100
4.0
50mV
V
T
= +5V ؎200mV AC
DD
V
T
= +5V
DD
= +25؇C
100
90
A
80
60
40
3.2
2.4
1.6
0.8
0.0
= +25
؇
C
DATA = FFF
A
H
NO LOAD
CODE = FFF = 4095
BW = 630kHz
SCALE = 100X
H
10
10
0%
20
0
T
= +25؇C
2mS
A
TIME = 2ms/DIV
0
1
2
3
4
5
10
100
1k
FREQUENCY – Hz
10k
100k
LOGIC VOLTAGE VALUE – Volts
Figure 8. Broadband Noise
Figure 9. Supply Current vs. Logic
Input Voltage
Figure 10. Power Supply Rejection
vs. Frequency
5.0
1V
5
∆VFS ≤ 1 LSB
100
90
4.8
DATA = FFFH
TA = +25؇C
0
2048 TO 2047
10
10
4.6
4.4
4.2
4.0
2.048
2.038
2.028
2.018
RL = NO LOAD
PROPER OPERATION
WHEN VDD SUPPLY
VOLTAGE ABOVE
CURVE
CL = 110pF
10
TA = +25؇C
0%
V
= 5V
20µs
DD
T
= +25؇C
A
TIME = 20µs/DIV
0.01
0.04 0.1
0.4
1.0
4.0
10
TIME – 200ns/DIV
OUTPUT LOAD CURRENT – mA
Figure 11. Minimum Supply Voltage
vs. Load
Figure 12. Midscale DAC Glitch
Performance
Figure 13. Large Signal Settling Time
REV. A
–7–
DAC8512 — Typical Performance Characteristics
2.0
1.5
V
T
= +5V
DD
= –40؇C, +25؇C, +85؇C
A
5
0
5
0
1.0
–40؇C
16µs
0.5
0.0
–0.5
–1.0
–1.5
–2.0
+25؇C & +85؇C
V
T
R
= +5V
VDD = +5V
TA = +25؇C
RL = NO LOAD
DD
= +25
؇C
A
= NO LOAD
L
TIME – 10µs/DIV
TIME – 10µs/DIV
0
512 1024 1536 2048 2560 3072 3584 4096
DIGITAL INPUT CODE – Decimal
Figure 14. Rise Time Detail
Figure 15. Fall Time Detail
Figure 16. Linearity Error vs. Digital
Code
60
4.115
3
TUE = ∑INL + ZS + FS
VDD = +5V
SS = 300 UNITS
DATA = 000H
NO LOAD
VDD = +5.0V
NO LOAD
SS = 300 PCS
4.110
4.105
4.100
4.095
4.090
4.085
4.080
4.075
T
= +25
؇
C
50
40
30
20
10
0
A
2
AVG + 3σ
1
0
AVG
AVG – 3σ
–1
–50
–50
–25
0
25
50
75
100 125
–12
–8
–4
0
+4
+8
+12
–25
0
25
50
75
100 125
TEMPERATURE – ؇C
TEMPERATURE – ؇C
TOTAL UNADJUSTED ERROR – mV
Figure 18. Full-Scale Voltage vs.
Temperature
Figure 19. Zero-Scale Voltage vs.
Temperature
Figure 17. Total Unadjusted Error
Histogram
4
5
10
135 UNITS TESTED
4
VLOGIC = 2.4V
DATA = FFFH
V
T
= +5V
DD
= +25؇C
A
3
2
1
NO LOAD
DATA = FFF
3
H
1
VDD = +5.0V
0
2
AVERAGE
–1
–2
VDD = +5.25V
0.1
1
VDD = +4.75V
–3
READINGS NORMALIZED
TO ZERO HOUR TIME POINT
–4
–5
0.01
0
–50
10
100
1k
10k
100k
200
400
600
800
1000 1200
0
–25
0
25
50
75
100 125
FREQUENCY – Hz
HOURS OF OPERATION AT +125؇C
TEMPERATURE – ؇C
Figure 20. Output Voltage Noise vs.
Frequency
Figure 22. Supply Current vs.
Temperature
Figure 21. Long Term Drift Acceler-
ated by Burn-In
REV. A
–8–
DAC8512
Typical Performance Characteristics—
the ground connection of the DAC8512 be connected to a high
quality analog ground, such as the one described above. Gener-
ous bypassing of the DAC’s supply goes a long way in reducing
supply line-induced errors. Local supply bypassing consisting of
a 10 µF tantalum electrolytic in parallel with a 0.1 µF ceramic is
recommended. The decoupling capacitors should be connected
between the DAC’s supply pin (Pin 1) and the analog ground
(Pin 7). Figure 24 shows how the ground and bypass connec-
tions should be made to the DAC8512.
APPLICATIONS SECTION
Power Supplies, Bypassing, and Grounding
All precision converter products require careful application of
good grounding practices to maintain full rated performance.
Because the DAC8512 has been designed for +5 V applications,
it is ideal for those applications under microprocessor or micro-
computer control. In these applications, digital noise is preva-
lent; therefore, special care must be taken to assure that its
inherent precision is maintained. This means that particularly
good engineering judgment should be exercised when address-
ing the power supply, grounding, and bypassing issues using the
DAC8512.
+5V
1
The power supply used for the DAC8512 should be well filtered
and regulated. The device has been completely characterized for
a +5 V supply with a tolerance of ±5%. Since a +5 V logic sup-
ply is almost universally available, it is not recommended to
connect the DAC directly to an unfiltered logic supply without
careful filtering. Because it is convenient, a designer might be
inclined to tap a logic circuit’s supply for the DAC’s supply.
Unfortunately, this is not wise because fast logic with nanosec-
ond transition edges induce high current pulses. The high tran-
sient current pulses can generate glitches hundreds of millivolts
in amplitude due to wiring resistances and inductances. This
high frequency noise will corrupt the analog circuits internal to
the DAC and cause errors. Even though their spike noise is
lower in amplitude, directly tapping the output of a +5 V system
supply can cause errors because these supplies are of the switch-
ing regulator type that can and do generate a great deal of high
frequency noise. Therefore, the DAC and any associated analog
circuitry should be powered directly from the system power sup-
ply outputs using appropriate filtering. Figure 23 illustrates how
a clean, analog-grade supply can be generated from a +5 V logic
supply using a differential LC filter with separate power supply
and return lines. With the values shown, this filter can easily
handle 100 mA of load current without saturating the ferrite
cores. Higher current capacity can be achieved with larger ferrite
cores. For lowest noise, all electrolytic capacitors should be low
ESR (Equivalent Series Resistance) type.
10µF
0.1µF
V
CS
2
6
5
3
4
DD
CLR
LD
DAC8512
V
8
V
OUT
OUT
SCLK
SDI
GND
7
TO ANALOG GROUND
Figure 24. Recommended Grounding and Bypassing
Scheme for the DAC8512
Unipolar Output Operation
This is the basic mode of operation for the DAC8512. As shown
in Figure 24, the DAC8512 has been designed to drive loads as
low as 2 kΩ in parallel with 500 pF. The code table for this op-
eration is shown in Table II.
+5V
10µF
0.1µF
1
V
CS
2
6
5
3
4
DD
CLR
LD
DAC8512
0V ≤ V
≤ 4.095V
OUT
V
8
OUT
FERRITE BEADS:
2 TURNS, FAIR-RITE
2kΩ
500pF
+5V
SCLK
SDI
#2677006301
TTL/CMOS
LOGIC
GND
7
CIRCUITS
100µF
ELECT
.
10-22µF
TANT.
0.1µF
CER.
+5V
RETURN
Figure 25. Unipolar Output Operation
+5V
POWER SUPPLY
Table II. Unipolar Code Table
Hexadecimal Number Decimal Number Analog Output
Figure 23. Properly Filtering a +5 V Logic Supply Can Yield
a High Quality Analog Supply
in DAC Register
in DAC Register
Voltage (V)
FFF
801
800
7FF
000
4095
2049
2048
2047
0
+4.095
+2.049
+2.048
+2.047
0
In order to fit the DAC8512 in an 8-pin package, it was neces-
sary to use only one ground connection to the device. The
ground connection of the DAC serves as the return path for
supply currents as well as the reference point for the digital in-
put thresholds. The ground connection also serves as the supply
rail for the internal voltage reference and the output amplifier.
Therefore, to minimize any errors, it is recommended that
REV. A
–9–
DAC8512
Operating the DAC8512 on +12 V or +15 V Supplies Only
Although the DAC8512 has been specified to operate on a
single, +5 V supply, a single +5 V supply may not be available in
many applications. Since the DAC8512 consumes no more than
2.5 mA, maximum, then an integrated voltage reference, such as
the REF02, can be used as the DAC8512 +5 V supply. The
configuration of the circuit is shown in Figure 26. Notice that
the reference’s output voltage requires no trimming because of
the REF02’s excellent load regulation and tight initial output
voltage tolerance. Although the maximum supply current of the
DAC8512 is 2.5 mA, local bypassing of the REF02’s output
with at least 0.1 µF at the DAC’s voltage supply pin is recom-
mended to prevent the DAC’s internal digital circuits from af-
fecting the DAC’s internal voltage reference.
By adding a pull-down resistor from the output of the DAC8412
to a negative supply as shown in Figure 27, offset errors can
now be read at zero code. This configuration forces the output
p-channel MOSFET to source current to the negative supply
thereby allowing the designer to determine in which direction the
offset error appears. The value of the resistor should be such that,
at zero code, current through the resistor is 200 µA, maximum.
Bipolar Output Operation
Although the DAC8512 has been designed for single-supply op-
eration, bipolar operation is achievable using the circuit illus-
trated in Figure 28. The circuit uses a single-supply, rail-to-rail
OP295 op amp and the REF03 to generate the –2.5 V reference
required to level-shift the DAC output voltage. Note that the –
2.5 V reference was generated without the use of precision resis-
tors. The circuit has been configured to provide an output
voltage in the range –5 V ≤ VOUT ≤ +5 V and is coded in com-
plementary offset binary. Although each DAC LSB corresponds
to 1 mV, each output LSB has been scaled to 2.44 mV. Table
III provides the relationship between the digital codes and out-
put voltage.
+12V OR +15V
0.1µF
2
6
REF02
0.1µF
4
The transfer function of the circuit is given by:
1
CS
2
6
5
3
4
VDD
R4
R1
R4
R2
VO = –1 mV × Digital Code ×
+ 2.5 ×
CLR
LD
DAC8512
8
VOUT
and, for the circuit values shown, becomes:
SCLK
SDI
VO = –2.44 mV × Digital Code + 5 V
GND
7
+5V
0.1µF
10µF
+
FULL SCALE
ADJUST
R4
23.7kΩ
Figure 26. Operating the DAC8512 on +12 V or +15 V
Supplies Using a REF02 Voltage Reference
1
P3
V
6
CLR
LD
DD
500Ω
+5V
Measuring Offset Error
One of the most commonly specified endpoint errors associated
with real world nonideal DACs is offset error.
R1
5
2
3
4
DAC8512
10kΩ
8
4
6
8
CS
SCLK
SDI
R3
7
A2
R2
12.7k
247kΩ
–5V ≤ V ≤ +5V
5
In most DAC testing, the offset error is measured by applying
the zero-scale code and measuring the output deviation from 0
volt. There are some DACs where offset errors may be present
but not observable at the zero scale because of other circuit limi-
tations (for example, zero coinciding with single-supply ground).
In these DACs, nonzero output at zero code cannot be read as
the offset error. In the DAC8512, for example, the zero-scale
error is specified to be ±3 LSBs. Since zero scale coincides with
zero volt, it is not possible to measure negative offset error.
O
GND
7
–5V
P2
10kΩ
–2.5V
ZERO SCALE
ADJUST
+5V
0.1µF
0.01µF
2
2.5V
TRIM
100Ω
6
5
2
3
+5V
0.1µF
REF03
A1
–2.5V
1
P1
10kΩ
4
1
V
CS
2
6
5
3
4
DD
A1, A2 = 1/2 OP295
CLR
LD
DAC8512
Figure 28. Bipolar Output Operation
8
V
OUT
200µA, MAX
R
SCLK
SDI
GND
7
V–
SET CODE = 000 AND MEASURE V
H
OUT
Figure 27. Measuring Zero-Scale or Offset Error
REV. A
–10–
DAC8512
Generating a Negative Supply Voltage
Table III. Bipolar Code Table
Some applications may require bipolar output configuration but
only have a single power supply rail available. This is very com-
mon in data acquisition systems using microprocessor-based
systems. In these systems, +12 V, +15 V, and/or +5 V are only
available. Shown in Figure 30 is a method of generating a nega-
tive supply voltage using one CD4049, a CMOS hex inverter,
operating on +12 V or +15 V. The circuit is essentially a charge
pump where two of the six are used as an oscillator. For the val-
ues shown, the frequency of oscillation is approximately 3.5 kHz
and is fairly insensitive to supply voltage because R1 > 2 × R2.
The remaining four inverters are wired in parallel for higher out-
put current. The square wave output is level translated by C2 to
a negative-going signal, rectified using a pair of 1N4001s, and
then filtered by C3. With the values shown, the charge pump
will provide an output voltage of –5 V for current loadings in the
range 0.5 mA ≤ IOUT ≤ 10 mA with a +15 V supply and 0.5 mA
≤ IOUT ≤ 7 mA with a +12 V supply.
Hexadecimal Number Decimal Number
Analog Output
Voltage (V)
in DAC Register
in DAC Register
F
FF
4095
2049
2048
2047
0
–4.9976
–2.44E–3
0
+2.44E–3
+5
801
800
7FF
000
To maintain monotonicity and accuracy, R1, R2, and R4 should
be selected to match within 0.01% and must all be of the same
(preferably metal foil) type to assure temperature coefficient
matching. Mismatching between R1 and R2 causes offset and gain
errors while an R4 to R1 and R2 mismatch yields gain errors.
For applications that do not require high accuracy, the circuit
illustrated in Figure 29 can also be used to generate a bipolar
output voltage. In this circuit, only one op amp is used and no
potentiometers are used for offset and gain trim. The output
voltage is coded in offset binary and is given by:
6
7
INVERTERS = CD4049
C2
47µF
9
10
R3
470Ω
D2
1N4001
3
2
5
4
R4
R3+ R4
R2
R1
–5V
1+
×
VO = 1 mV × Digital Code ×
11
14
12
15
R2
5.1kΩ
R1
510kΩ
D1
C3
1N5231
1N4001 47µF
5.1V
R2
–2.5 ×
R1
ZENER
C1
0.02µF
+5V
0.1µF
Figure 30. Generating a –5 V Supply When Only +12 V
or +15 V Is Available
2
R2
A High-Compliance, Digitally Controlled Precision Current
Source
R1
6
REF03
+2.5V
+5V
4
The circuit in Figure 31 shows the DAC8512 controlling a
high-compliance precision current source using an AMP05 in-
strumentation amplifier. The AMP05’s reference pin becomes
the input, and the “old” inputs now monitor the voltage across a
precision current sense resistor, RCS. Voltage gain is set to unity,
so the transfer function is given by the following equation:
8
2
3
+5V
1
A1
V
O
0.1µF
4
1
CS
–5V
A1 = 1/2 OP295
2
V
DD
CLR
LD
6
5
3
4
DAC8512
R3
VIN
RCS
8
IOUT
=
SCLK
SDI
R4
GND
7
If RCS equals 100 Ω, the output current is limited to +10 mA
with a 1 V input. Therefore, each DAC LSB corresponds to
2.4 µA. If a bipolar output current is required, then the circuit
in Figure 28 can be modified to drive the AMP05’s reference
pin with a ±1 V input signal.
V
RANGE R1 R2 R3
R4
OUT
؎2.5V
؎5V
10k 10k 10k 15.4k + 274
10k 20k 10k 43.2k + 499
Potentiometer P1 trims the output current to zero with the in-
put at 0 V. Fine gain adjustment can be accomplished by adjust-
ing R1 or R2.
Figure 29. Bipolar Output Operation without Trim
For the ±2.5 V output range and the circuit values shown in the
table, the transfer equation becomes:
VO = 1.22 mV × Digital Code – 2.5 V
Similarly, for the ±5 V output range, the transfer equation
becomes:
VO = 2.44 mV × Digital Code – 5 V
REV. A
–11–
DAC8512
OP295’s feedback loop. For the circuit values shown, the full-
scale output current is 1 mA which is given by the following
equation:
R2
5kΩ
+15V
7
0.1µF
17
18
DW × 4.095V
6
IOUT
=
R1
12
RCS
100Ω
R1
100k
where DW = DAC8512’s binary digital input code.
10
AMP05
0mA ≤ IOUT ≤ 10mA
2.4µA/ BIT
8
+5V
9
1
2
0.1µF
11
VS
5
1
4
CS
CLR
LD
2
6
5
3
4
LOAD
P1
100kΩ
DAC8512FP
+5V
0.1µF
3
2
8
A1
1
2N2222
SCLK
SDI
–15V
7
+15V
0.1µF
R1
4.02kΩ
A1 = 1/2 OP295
2
REF02
4
P1
200Ω
0.1µF
6
FULL-SCALE
ADJUST
1
CS
2
6
5
3
4
Figure 32. A Single-Supply, Programmable Current
Source
R3
3k
CLR
LD
DAC8512FZ
8
The usable output voltage range of the current sink is +5 V to
+60 V. The low limit of the range is controlled by transistor
saturation, and the high limit is controlled by the collector-base
breakdown voltage of the 2N2222.
R4
1k
SCLK
SDI
7
A Digitally Programmable Window Detector
A digitally programmable, upper/lower limit detector using two
DAC8512s is shown in Figure 33. The required upper and
lower limits for the test are loaded into each DAC individually
by controlling HDAC/LDAC. If a signal at the test input is not
within the programmed limits, the output will indicate a logic
zero which will turn the red LED on.
Figure 31. A High-Compliance, Digitally Controlled
Precision Current Source
A Single-Supply, Programmable Current Source
The circuit in Figure 32 shows how the DAC8512 can be used
with an OP295 single-supply, rail-to-rail output op amp to pro-
vide a digitally programmable current sink from VSOURCE that
consumes less than 3.8 mA, maximum. The DAC’s output volt-
age is applied across R1 by placing the 2N2222 transistor in the
+5V
0.1µF
+5V
V
IN
+5V
+5V
1
6
2
5
3
4
1kΩ
R1
R2
604Ω
604Ω
DAC8512
+5V
0.1µF
8
RED LED
T1
GREEN LED
T1
3
7
2
5
4
+5V
1/6
2
1
PASS/FAIL
C1
74HC05
0.1µF
1
1
7
6
3
4
CLR
6
2
5
3
4
C2
12
HDAC/LDAC
1/6
74HC05
DAC8512
LD
SCLK
SDI
8
C1, C2 = 1/4 CMP-404
7
Figure 33. A Digitally Programmable Window Detector
–12–
REV. A
DAC8512
Opto-Isolated Interfaces for Process Control Environments
In many process control type applications, it is necessary to pro-
vide an isolation barrier between the controller and the unit be-
ing controlled. Opto-isolators can provide isolation in excess of
3 kV. The serial loading structure of the DAC8512 makes it
ideal for opto-isolated interfaces as the number of interface lines
is kept to a minimum.
HIGH VOLTAGE
ISOLATION
+5V
REG
+5V
POWER
+5V
Illustrated in Figure 34 is an opto-isolated interface using the
DAC8512. In this circuit, the CS line is always LOW to enable
the DAC, and the 10 kΩ/1 µF combination connected to the
DAC’s CLR pin sets a turn-on time constant of 10 ms to reset
the DAC upon application of power. Three opto-couplers are
then used for the SDI, SCLK, and LD lines.
10kΩ
LD
LD
+5V
+5V
0.1µF
10kΩ
Often times reducing the number of interface lines to two lines
is required in many control environments. The circuit illustrated
in Figure 35 shows how to convert a two-line interface into the
three control lines required to control the DAC8512 without us-
ing one shots. This technique uses a counter to keep track of the
clock cycles and, when all the data has been input to the DAC,
the external logic generates the LD pulse.
1
0.1µF
+5V
6
10kΩ
SCLK
5
3
4
DAC8512
SCLK
V
8
OUT
2
CS
7
+5V
10kΩ
SDI
SDI
Figure 34. An Opto-Isolated DAC Interface
HIGH VOLTAGE
ISOLATION
+5V
+5V
REG
+5V
POWER
10kΩ
1µF
+5V
+5V
74HC161
0.1µF
10kΩ
1
2
3
4
5
6
VCC 16
15
CLR
CLK
A
1/4 74HCOO
RCO
1
2
NC
NC
NC
SCLK
3
X
QA 14
+5V
13
QB
B
+5V
+5V
0.1µF
QC
C
12
10kΩ
10kΩ
QD 11
D
ENT
7
8
ENP
GND
10
9
6
1
+5V
LOAD
VDD
5
3
1/4 74HCOO
LD
CLR
4
5
6
8
10kΩ
SCLK
Y
VOUT
DAC8512
4
2
SDI
CS
SDI
GND
7
Figure 35. A Two-Wire, Opto-lsolated DAC Interface
–13–
REV. A
DAC8512
LOAD DAC
COUNTER
CLK
Q
D
Q
C
Q
B
Q
A
LOAD
(X)
DAC8512
CLK (Y)
LOAD = Q
· Q
D
C
DAC8512 CLK = LOAD · SCLK
Figure 36. Opto-lsolated Two-Wire Serial Interface Timing Diagram
The timing diagram of Figure 36 can be used to understand the
ENABLE input while the coded address inputs are changing. A
simple timing circuit, R1 and C1, connected to the DACs’ CLR
pins resets all DAC outputs to zero during power-up.
operation of the circuit. Only two opto-couplers are used in the
circuit; one for SCLK and one for SDI. The 74HC161 counter
in incremented on every rising edge of the clock. Additionally,
the data is loaded into the DAC8512 on the falling edge of the
clock by inverting the serial clock using gate “Y.” The timing
diagram shows that after the twelfth bit has been clocked the
output of the counter is binary 1011. On the very next rising
clock edge, the output of the counter changes to binary 1100
upon which the output of gate “X” goes LOW to generate the
LD pulse. The LD signal is connected to both the DAC’s LD
and the counter’s LOAD pins to prevent the thirteenth rising
clock edge from advancing the DAC’s internal shift register.
This prevents false loading of data into the DAC8512. Inverting
the DAC’s serial clock allows sufficient time from the CLK edge
to the LD edge, and from the LD edge to the next clock pulse
all of which satisfies the timing requirements for loading the
DAC8512.
+5V
C1
0.1µF
R1
1k
6
SCLK
SDI
3
4
5
2
DAC8512
#1
V
V
V
OUT1
OUT2
OUT3
LD
8
8
8
After loading one address of the DAC, the entire process can re-
peated to load another address. If the loading is complete, then
the clock must stop after the thirteenth pulse of the final load.
The DAC’s clock input will be pulled high and the counter reset
to zero. As was shown in Figure 35, both the 74HC161’s and
the DAC8512’s CLR pins are connected to a simple R-C timing
circuit that resets both ICs when the power in turned on. The
circuit’s time constant should be set longer than the power sup-
ply turn-on time and, in this circuit, is set to 10 ms, which
should be adequate for most systems. This same two-wire inter-
face can be used for other three-wire serial input DACs.
6
3
4
5
2
+5V
DAC8512
#2
74HC139
16
4
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
V
CC
1
2
5
6
ENABLE
1G
1A
1B
2G
2A
2B
6
CODED
ADDRESS
3
7
3
4
5
2
DAC8512
#3
15
14
13
8
12
11
10
9
+5V
NC
NC
NC
NC
1kΩ
Decoding Multiple DAC8512s
The CS function of the DAC8512 can be used in applications
to decode a number of DACs. In this application, all DACs re-
ceive the same input data; however, only one of the DAC’s CS
input is asserted to transfer its serial input register contents into
the destination DAC register. In this circuit, shown in Figure 37,
the CS timing is generated by a 74HC139 decoder and should
follow the DAC8512’s standard timing requirements. To pre-
vent timing errors, the 74HC139 should not be activated by its
GND 2Y3
6
3
4
5
2
DAC8512
#4
V
OUT4
8
Figure 37. Decoding Multiple DAC8512s Using the CS Pin
REV. A
–14–
DAC8512
R1
619Ω
R2
4.32kΩ
V+
AD600JN
1
2
3
16
15
14
+625mV
R3
402Ω
R5
806Ω
0.1µF
V+
0.1µF
4
5
13
12
V+
V
IN
REF
R4
V–
0.1µF
2
3
49.9Ω
V
OUT
6
AD844
R4
402Ω
0.01dB/BIT
6
11
0.1µF
10
9
7
8
V–
V+
SUPPLY DECOUPLING NETWORK
0.1µF
+5V
10µF
1
FB = FAIR RITE
CS
2
6
5
3
4
#2743001111
V+
R6
2.26kΩ
CLR
LD
V–
0 ≤ V ≤ 1.25V
8
G
DAC8512FZ
R7
1kΩ
10µF
1µF
SCLK
SDI
–5V
7
Figure 38. A Digitally Controlled, Ultralow Noise VCA
A Digitally Controlled, Ultralow Noise VCA
+70
+60
+50
+40
+30
+20
The circuit in Figure 38 illustrates how the DAC8512 can be
used to control an ultralow noise VCA, using the AD600/
AD602. The AD600/AD602 is a dual, low noise, wideband,
variable gain amplifier based on the X-AMP topology.* Both
channels of the AD600 are wired in parallel to achieve a
wideband VCA which exhibits an RTI (Referred To Input)
noise voltage spectral density of approximately 1 nV/√Hz. The
output of the VCA requires an AD844 configured in a gain of 4
to account for signal loss due to input and output 50 Ω termina-
tions. As configured, the total gain in the circuit is 40 dB.
4095
3072
2048
1024
0
+10
0
–10
–20
–30
Since the output of the DAC8512 is single quadrant, it was nec-
essary to offset the AD600’s gain control voltage so that the gain
of the circuit is 0 dB for zero scale and 40 dB at full scale. This
was achieved by setting C1LO and C2LO to +625 mV using R1
and R2. Next, the output of the DAC8512 was scaled so that
the gain of the AD600 equaled 20 dB when the digital input
code equaled 800H. The frequency response of the VCA as a
function of digital code is shown in Figure 39.
10k
100k
1M
10M
100M
FREQUENCY – Hz
Figure 39. VCA Frequency Response vs. Digital Code
*For more details regarding the AD600 or AD602, please consult the AD600/
AD602 data sheet.
REV. A
–15–
DAC8512
Table IV. SSM-2018 VCA Attenuation vs.
DAC8512 Input Code
A Serial DAC, Audio Volume Control
The DAC8512 is well suited to control digitally the gain or at-
tenuation of a voltage controlled amplifier. In professional audio
mixing consoles, music synthesizers, and other audio processors,
VCAs, such as the SSM2018, adjust audio channel gain and at-
tenuation from front panel potentiometers. The VCA provides a
clean gain transition control of the audio level when the slew
rate of the analog input control voltage, VC, is properly chosen.
The circuit in Figure 40 illustrates a volume control application
using the DAC8512 to control the attenuation of the SSM2018.
Hexadecimal Number
in DAC Register
Control
Voltage (V)
VCA
Attenuation (dB)
000
400
800
C00
FFF
0
0
+0.56
+1.12
+1.68
+2.24
20
40
60
80
+15V
digital code equals FFFH. Therefore, every DAC LSB corre-
sponds to 0.02 dB of attenuation. Table IV illustrates the at-
tenuation vs. digital code of the volume control circuit.
10MΩ
P1
100kΩ
SYMMETRY
TRIM
470kΩ
OFFSET
TRIM
P2
500kΩ
10pF
To compensate for the SSM2018’s gain constant temperature
coefficient of –3300 ppm/°C, a 1 kΩ, temperature-sensitive re-
sistor (R7) manufactured by the Precision Resistor Company
with a temperature coefficient of +3500 ppm/°C is used. A
–15V
18kΩ
V
OUT
16
15
14
13
1
2
3
4
C
CON of 1 µF provides a control transition time of 1 ms which
+15V
yields a click-free change in the audio channel attenuation. Sym-
metry and offset trimming details of the VCA can be found in
the SSM2018 data sheet.
0.1µF
30kΩ
SSM2018
5
6
12
11
+15V
–15V
18kΩ
Information regarding the PT146 1 kΩ “Compensator” can be
obtained by contacting:
V
IN
7
8
10
9
+15V
0.1µF
0.1µF
Precision Resistor Company, Incorporated
10601 75th Street North
Largo, Fl 34647
47pF
2
0.1µF
+5V
(813) 541-5771
6
REF02
An Isolated, Programmable, 4-20 mA Process Controller
In many process control system, applications, two-wire current
transmitters are used to transmit analog signals through noisy
environments. These current transmitters use a “zero-scale” sig-
nal current of 4 mA that can be used to power the transmitter’s
signal conditioning circuitry. The “full-scale” output signal in
these transmitters is 20 mA. The converse approach to process
control can also be used; a low-power, programmable current
source can be used to control remotely located sensors or de-
vices in the loop.
4
1
CS
2
6
5
3
4
R6
825Ω
0V
≤ V ≤ +2.24V
C
CLR
LD
8
DAC8512
R7
1kΩ
C
CON
1µF
SCLK
SDI
*
7
* – PRECISION RESISTOR
PT146
1kΩ COMPENSATOR
A circuit that performs this function is illustrated in Figure 41.
Using the DAC8512 as the controller, the circuit provides a
programmable output current of 4 mA to 20 mA, proportional
to the DAC’s digital code. Biasing for the controller is provided
by the REF02 and requires no external trim for two reasons:
Figure 40. A Serial DAC, Audio Volume Control
Since the supply voltage available in these systems is typically
±15 V or ±18 V, a REF02 is used to supply the +5 V required
to power the DAC. No trimming of the reference is required be-
cause of the reference’s tight initial tolerance and low supply
current consumption of the DAC8512. The SSM2018 is config-
ured as a unity-gain buffer when its control voltage equals 0
volt. This corresponds to a 000H code from the DAC8512.
Since the SSM2018 exhibits a gain constant of –28 mV/dB
(typical), the DAC’s full-scale output voltage has to be scaled
down by R6 and R7 to provide 80 dB of attenuation when the
(1) the REF02’s tight initial output voltage tolerance and (2) the
low supply current consumption of both the OP90 and the
DAC8512. The entire circuit, including opto-couplers, con-
sumes less than 3 mA from the total budget of 4 mA. The OP90
regulates the output current to satisfy the current summation at
the noninverting node of the OP-90. The KCL equation at
Pin 3 is given by:
1
R7
1 mV × Digital Code × R3 VREF × R3
×
+
IOUT
=
R1
R2
REV. A
–16–
DAC8512
6
2
R2
REF02
4
976kΩ
V
LOOP
P2
50Ω
4mA
ADJUST
+12 TO +40V
1
6
5
3
4
CLR
LD
R1
200kΩ
R6
7
8
DAC8512
3
2
150Ω
Q1
2N1711
P1
D1
SCLK
SCI
6
OP90
10kΩ
4
20mA
ADJUST
4–20mA
7
R5
100k
R4
54.9k
R3
R
L
80.6k
100Ω
R7
100Ω
D1 = HP5082-2810
+5V
10kΩ
SCLK
REPEAT FOR SDI, LD, & CLR
360Ω
ILQ-1
CLK
Figure 41. An Isolated, Programmable, 4-20 mA Process Controller
For the values shown in Figure 41,
IOUT = 3.9 µA × Digital Code + 4 mA
MC68HC11*
DAC8512*
CLR
PC1
PC0
SS
CS
giving a full-scale output current of 20 mA when the
DAC8512’s digital code equals FFFH. Offset trim at 4 mA is
provided by P2, and P1 provides the circuit’s gain trim at 20 mA.
These two trims do not interact because the noninverting input
of the OP90 is at virtual ground. The Schottky diode, D1, is re-
quired in this circuit to prevent loop supply power-on transients
from pulling the noninverting input of the OP90 more than
300 mV below its inverting input. Without this diode, such tran-
sients could cause phase reversal of the OP90 and possible
latchup of the controller. The loop supply voltage compliance of
the circuit is limited by the maximum applied input voltage to
the REF02 and is from +12 V to +40 V.
LD
SCK
MOSI
CLK
SDI
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 42. DAC8512–MC68HC11 Interface
MOSI is valid on the rising edge of SCLK. The 68HC11 trans-
mits its serial data in 8-bit bytes (MSB first), with only eight ris-
ing clock edges occurring in the transmit cycle. To load data to
the DAC8512’s input serial register, PC0 is left low after the
first eight bits are transferred, and a second byte of data is then
transferred serially to the DAC8512. During the second byte
load, the first four most significant bits of the first byte are
pushed out of the DAC’s input shift register. At the end of the
second byte load, PC0 is then taken high. To prevent an acci-
dental advancing of the internal shift register, SCLK must al-
ready be asserted before PC0 is taken high. To transfer the
contents of the input shift register to the DAC register, PD5 is
taken low, asserting the DAC’s LD input. The DAC’s CLR in-
put, controlled by the 68HC11’s PC1 port, provides an asyn-
chronous clear function, setting the DAC output to zero.
Included in this section is the source code for operating the
DAC8512—M68HC11 interface.
MICROPROCESSOR INTERFACING
DAC8512–MC68HC11 Interface
The circuit illustrated in Figure 42 shows a serial interface be-
tween the DAC8512 and the MC68HC11 8-bit microcontrol-
ler. SCK of the 68HC11 drives SCLK of the DAC8512, while
the MOSI output drives the serial data line, SDI, of the
DAC8512. The DAC’s CLR, LD, and CS signals are derived
from port lines PC1, PD5, and PC0, respectively, as shown.
For correct operation of the serial interface, the 68HC11 should
be configured such that its CPOL bit is set to 1 and its CPHA
bit is also set to 1. When the serial data is to be transmitted to
the DAC, PC0 is taken low, asserting the DAC’s CS input.
When the 68HC11 is configured in this manner, serial data on
REV. A
–17–
DAC8512
DAC8512–M68HC11 Interface Program Source Code
*
PORTC
EQU
$1003
Port C control register
*
“0,0,0,0;0,0,CLR/,CS/”
DDRC
PORTD
*
DDRD
SPCR
*
SPSR
*
SPDR
*
EQU
EQU
$1007
$1008
Port C data direction
Port D data register
“0,0,LD/,SCLK;SDI,0,0,0
Port D data direction
SPI control register
“SPIE,SPE,DWOM,MSTR;CPOL,CPHA,SPRl,SPR0”
SPI status register
“SPIF,WCOL,0,MODF;0,0,0,0”
SPI data register; Read-Buffer; Write-Shifter
EQU
EQU
$1009
$1028
EQU
EQU
$1029
$102A
* SDI RAM variables:
SDI1 is encoded from 0 (Hex) to F (Hex)
SDI2 is encoded from 00 (Hex) to FF (Hex)
DAC requires two 8-bit loads; upper 4 bits of SDI1
are ignored.
*
*
*
*
SDI1
SDI2
*
EQU
EQU
$00
$01
SDI packed byte 1 “0,0,0,0;MSB,DB10,DB9,DB8”
SDI packed byte 2 “DB7,DB6,DB5,DB4;DB3,DB2,DB1,DB0”
ORG
LDS
$C000
#$CFFF
Start of user’s RAM in EVB
Top of C page RAM
INIT
*
LDAA
#$03
0,0,0,0;0,0,1,1
*
CLR/-Hi, CS/-Hi
STAA
LDAA
STAA
PORTC
#$03
DDRC
Initialize Port C Outputs
0,0,0,0;0,0,1,1
CLR/ and CS/ are now enabled as outputs
*
*
LDAA
#$30
0,0,1,1;0,0,0,0
LDI-Hi,SCLK-Hi,SDI-Lo
Initialize Port D Outputs
0,0,1,1;1,0,0,0
STAA
LDAA
STAA
PORTD
#$38
DDRD
LD/,SCLK, and SDI are now enabled as outputs
*
*
LDAA
STAA
#$5F
SPCR
SPI is Master,CPHA=1,CPOL=1,Clk rate=E/32
BSR
JMP
UPDATE
$E000
Xfer 2 8-bit words to DAC8512
Restart BUFFALO
*
UPDATE
PSHX
PSHY
PSHA
Save registers X, Y, and A
*
*
*
*
LDAA
STAA
#$0A
SDI1
0,0,0,0;1,0,1,0
SDI1 is set to 0A (Hex)
LDAA
STAA
#$AA
SDI2
1,0,1,0;1,0,1,0
SDI2 is set to AA (Hex)
LDX
LDY
#SDI1
#$1000
Stack pointer at 1st byte to send via SDI
Stack pointer at on-chip registers
BCLR
PORTC,Y
$02 Assert CLR/
BSET
PORTC,Y
$02 De-assert CLR/
*
BCLR
PORTC,Y
$01 Assert CS/
*
REV. A
–18–
DAC8512
TFRLP
LDAA
STAA
0,X
SPDR
Get a byte to transfer via SPI
Write SDI data reg to start xfer
*
WAIT
LDAA
BPL
SPSR
WAIT
Loop to wait for SPIF
SPIF is the MSB of SPSR
(when SPIF is set, SPSR is negated)
Increment counter to next byte for xfer
Are we done yet ?
*
INX
CPX
BNE
#SDI2+1
TFRLP
If not, xfer the second byte
*
*Update DAC output with contents of DAC register
*
BCLR
BSET
PORTD,Y
PORTD,Y
$20 Assert LD/
$20 Latch DAC register
*
BSET
PORTC,Y
$01 De-assert CS/
PULA When done, restore registers X, Y & A
PULY
PULX
RTS
** Return to Main Program **
REV. A
–19–
DAC8512
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Pin Plastic DIP (P Suffix)
8
1
5
0.280 (7.11)
0.240 (6.10)
4
0.070 (1.77)
0.045 (1.15)
0.325 (8.25)
0.300 (7.62)
0.430 (10.92)
0.348 (8.84)
0.015
0.210
(5.33)
MAX
0.195 (4.95)
0.115 (2.93)
(0.381) TYP
0.130
(3.30)
MIN
0.015 (0.381)
0.008 (0.204)
0.160 (4.06)
0.115 (2.93)
SEATING
0°- 15°
0.022 (0.558)
0.014 (0.356)
0.100
(2.54)
BSC
PLANE
8-Pin Cerdip (Z Suffix)
0.005 (0.13) MIN
0.055 (1.4) MAX
8
5
0.310 (7.87)
0.220 (5.59)
4
1
0.070 (1.78)
0.030 (0.76)
0.320 (8.13)
0.290 (7.37)
0.405 (10.29) MAX
0.200
0.060 (1.52)
0.015 (0.38)
(5.08)
MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
0°-15°
SEATING PLANE
0.023 (0.58)
0.014 (0.36)
0.100 (2.54)
BSC
8-Lead SOIC (S Suffix)
8
1
5
0.1574 (4.00)
0.1497 (3.80)
0°- 8°
PIN 1
0.2440 (6.20)
0.2284 (5.80)
4
0.0500 (1.27)
0.0160 (0.41)
0.1968 (5.00)
0.1890 (4.80)
0.0196 (0.50)
0.0099 (0.25)
× 45°
0.0098 (0.25)
0.0040 (0.10)
0.0688 (1.75)
0.0532 (1.35)
SEE DETAIL
ABOVE
0.0098 (0.25)
0.0075 (0.19)
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
SEATING
PLANE
REV. A
–20–
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