DAC8426AR/883 [ADI]
IC SERIAL INPUT LOADING, 3 us SETTLING TIME, 8-BIT DAC, CDIP20, CERAMIC, DIP-20, Digital to Analog Converter;型号: | DAC8426AR/883 |
厂家: | ADI |
描述: | IC SERIAL INPUT LOADING, 3 us SETTLING TIME, 8-BIT DAC, CDIP20, CERAMIC, DIP-20, Digital to Analog Converter CD 输入元件 转换器 |
文件: | 总12页 (文件大小:261K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Quad 8-Bit Voltage Out CMOS DAC
Complete with Internal 10 V Reference
a
DAC8426
FEATURES
offering a 25 ppm/°C temperature coefficient and 5 mA of exter-
No Adjustm ents Required, Total Error ؎1 LSB Max
Over Tem perature
Four Voltage-Output DACs on a Single Chip
Internal 10 V Bandgap Reference
Operates from Single ؉15 V Supply
Fast 50 ns Data Load Tim e, All Tem peratures
Pin-for-Pin Replacem ent for PM-7226 and AD7226,
Elim inates External Reference
nal load driving capability.
T he DAC8426 contains four 8-bit voltage-output CMOS D/A
converters on a single chip. A 10 V output bandgap reference
sets the output full-scale voltage. T he circuit also includes four
input latches and interface control logic.
One of the four latches, selected by the address inputs, is loaded
from the 8-bit data bus input when the write strobe is active
low. All digital inputs are T T L/CMOS (5 V) compatible. T he
on-board amplifiers can drive up to 10 mA from either a single
or dual supply. T he on-board reference that is always connected
to the internal DACs has 5 mA available to drive external devices.
APPLICATIONS
Process Controls
Multichannel Microprocessor Controlled:
System Calibration
Op Am p Offset and Gain Adjust
Level and Threshold Setting
Its compact size, low power, and economical cost-per-channel,
make the DAC8426 attractive for applications requiring mul-
tiple D/A converters without sacrificing circuit-board space. Sys-
tem reliability is also increased due to reduced parts count.
PMI’s advanced oxide-based, silicon-gate, CMOS process al-
lows the DAC8426’s analog and digital circuitry to be manufac-
tured on the same chip. T his, coupled with PMI’s highly stable
thin-film R-2R resistor ladder, aids in matching and tempera-
ture tracking between DACs.
GENERAL D ESCRIP TIO N
T he DAC8426 is a complete quad voltage output D/A converter
with internal reference. T his product fits directly into any exist-
ing 7226 socket where the user currently has a 10 V external
reference. T he external reference is no longer necessary. T he
internal reference of the DAC8426 is laser-trimmed to ±0.4%
FUNCTIO NAL BLO CK D IAGRAM
REV. C
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
(V = +15 V ؎ 10%, AGND = DGND = 0 V, V = 0 V, T = –55؇C to +125؇C
applies for DAC8426AR/BR, T = –40؇C to +85؇C applies for DAC8426ER/EP/FR/FP/FS, unless otherwise noted.)
DAC8426–SPECIFICATIONS
DD
SS
A
A
P aram eter
Sym bol
Conditions
Min Typ
Max
Units
ST AT IC PERFORMANCE
Resolution
N
T UE
8
Bits
T otal Unadjusted Error1
Includes Reference
A, E
B, F
A, E
B, F
±1
±2
±1/2
±1
±1
LSB
LSB
LSB
LSB
LSB
ppm/°C
mV
Relative Accuracy
INL
Differential Nonlinearity2
Full-Scale T emperature Coefficient
Zero Scale Error
Zero Scale Error
T emperature Coefficient
DNL
T CGFS
VZSE
Includes Reference
25
10
20
T CVZS
Dual Supply
No Load
VSS = –5 V
µV/°C
REFERENCE OUT PUT
Output Voltage
VREFOUT
A, E
B, F
9.96
9.92
20
10.04
10.08
V
V
T emperature Coefficient
Load Regulation
Line Regulation
T CVREFOUT
LDREG
LNREG
en rms
IREFOUT
ppm/°C
%/mA
%/V
µV p-p
mA
∆IL = 5 mA
∆VDD ±10%
f = 0.1 Hz to 10 Hz
∆VREFOUT < 40 mV
0.02
0.008
3
0.1
0.04
10
Output Noise3
Output Current
5
7
DIGIT AL INPUT S
Logic Input “0”
Logic Input “1”
Input Current
VINL
VINH
IIN
0.8
V
V
µA
pF
2.4
VIN = 0 V or VDD
0.1
4
10
8
Input Capacitance3
CIN
POWER SUPPLIES
Positive Supply Current4
Negative Supply Current4
Power Dissipation5
IDD
ISS
PDISS
PSS
6
4
90
14
10
210
mA
mA
mW
%/%
Dual Supply
VSS = –5 V
Power Supply Sensitivity
∆VDD = ±5%
0.0002 0.01
V = +15 V ؎ 10%, AGND = DGND = 0 V, V = 0 V, T = –55؇C to +125؇C applies for
DAC8426AR/BR, T = –40؇C to +85؇C applies for DAC8426ER/EP/FR/FP/FS, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
DD
SS
A
A
P aram eter
Sym bol
Conditions
Min
Typ6 Max
Units
DAC OUT PUT
Output Current (Source)3
Output Current (Sink)3
Minimum Load Resistance
IOUTSOURCE
IOUTSINK
RL(MIN)
Digital In = All Ones
Digital In = All Zeroes VSS = –5 V
Digital In = All Ones
10
350
2
mA
µA
kΩ
450
DYNAMIC PERFORMANCE3
VOUT Slew Rate
VOUT Settling T ime
(Positive or Negative)
Digital Crosstalk
SR
tS
4
3
V/µs
µs
T o ±1/2 LSB, RL = 2 kΩ
Q
10
nVs
SWIT CHING CHARACT ERIST ICS3
Address T o Write Setup T ime
Address T o Write Hold T ime
Data Valid T o Write Setup T ime
Data Valid T o Write Hold T ime
Write Pulse Width
tAS
0
0
70
10
50
ns
ns
ns
ns
ns
tAH
tDS
tDH
tWR
NOT ES
1Includes Full-Scale Error, Relative Accuracy, and Zero Code Error. Note ±1 LSB = ±0.39% error.
2All devices guaranteed monotonic over the full operating temperature range.
3Guaranteed and not subject to production test.
4Digital inputs VIN = VINL or VINH ; VOUT and VREFOUT unloaded.
5PDISS calculated by IDD × VDD
.
6T ypicals represent measured characteristics at T A = +25°C.
Specifications subject to change without notice.
–2–
REV. C
DAC8426
ABSO LUTE MAXIMUM RATINGS
CAUTIO N
VDD to AGND or DGND . . . . . . . . . . . . . . . . . –0.3 V, +17 V
VSS to AGND or DGND . . . . . . . . . . . . . . . . . . . . . –7 V, VDD
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +24 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +5 V
Digital Input Voltage to DGND . . . . . . . . . . . . . –0.3 V, VDD
VREFOUT to AGND1 . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD
VOUT to AGND1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
Operating T emperature
Military AR/BR . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Extended Industrial ER/EP/FR/FP/FS . . . . –40°C to +85°C
Maximum Junction T emperature . . . . . . . . . . . . . . . . +150°C
Storage T emperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C
1. Do not apply voltages higher than VDD or less than VSS po-
tential on any terminal.
2. T he digital control inputs are zener-protected; however,
permanent damage may occur on unprotected units from
high-energy electrostatic fields. Keep units in conductive
foam at all times until ready to use.
3. Do not insert this device into powered sockets. Remove
power before insertion or removal.
4. Stresses above those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to device.
P IN CO NNECTIO NS
TH ERMAL RESISTANCE
20-P in Cer dip
(R Suffix)
2
P ackage Type
JA
JC
Units
20-P in Epoxy D IP
(P Suffix)
20-Pin Cerdip (R)
20-Pin Plastic DIP (P)
20-Pin SOL(S)
70
61
80
7
24
22
°C/W
°C/W
°C/W
20-P in SO L
(S Suffix)
NOT ES
1Outputs may be shorted to any terminal provided the package power dissipation
is not exceeded. T ypical output short-circuit current to AGND is 50 mA.
2θJA is specified for worst case mounting conditions, i.e., θJA is specified for de-
vice in socket for cerdip and P-DIP packages; θJA is specified for device sol-
dered to printed circuit board for SOL package.
O RD ERING GUID E 1
Tem perature Range
Model
Total Unadjusted Error
P ackage D escription
DAC8426AR2
DAC8426ER
DAC8426EP
DAC8426BR2
DAC8426FR
DAC8426FP
DAC8426FS3
±1 LSB
±1 LSB
±1 LSB
±2 LSB
±2 LSB
±2 LSB
±2 LSB
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
20-Pin Cerdip (Q-20)
20-Pin Cerdip (Q-20)
20-Pin Plastic DIP (N-20)
20-Pin Cerdip (Q-20)
20-Pin Cerdip (Q-20)
20-Pin Plastic DIP (N-20)
20-Lead SOL (R-20)
NOT ES
1Burn-in is available on commercial and industrial temperature range parts in cerdip, plastic DIP, and T O-can packages.
2For devices processed in total compliance to MIL-ST D-883, add /883 after part number. Consult factory for 883 data sheet.
3For availability and burn-in information on SO and PLCC packages, contact your local sales office.
Burn-In Circuit
REV. C
–3–
DAC8426
D ICE CH ARACTERISTICS
1. VOUT B
2. VOUT A
3. VSS
4. VREF OUT
5. AGND
6. DGND
7. DB7 (MSB)
8. DB6
11. DB3
12. DB2
13. DB1
14. DB0 (LSB)
15. WR
16. A1
17. A0
18. VDD
9. DB5
10. DB4
19. VOUT D
20. VOUT C
DIE SIZE 0.129 × 0.152 inch, 19,608 sq. m ils
(3.28 × 3.86 m m , 12.65 sq. m m )
at V = +15 V ؎ 5%; V = AGND = DGND = 0 V; unless otherwise specified. T = +25؇C. All specifications
WAFER TEST LIMITS
DD
SS
A
apply for DACs A, B, C, and D.
D AC8426GBC
Lim its
P aram eter
Sym bol
Conditions
Units
T otal Unadjusted Error
Relative Accuracy
Differential Nonlinearity
Full-Scale Error
T UE
INL
DNL
GFSE
VZSE
±2
±1
±1
±1
±20
10
10.04
0.1
0.04
5
2.4
0.8
±1
LSB max
LSB max
LSB max
LSB max
mV max
mA min
V max
%/mA max
%/V max
mA min
V min
Zero Code Error
DAC Output Current
Reference Output Voltage
Load Regulation
Line Regulation
Reference Output Current
Logic Inputs High
I
V
OUT SOURCE
REFOUT
Digital In = All Ones
No Load
∆IL = 5 mA
∆VDD = ±10 V
∆VREFOUT < 40 mV
LDREG
LNREG
IREFOUT
VINH
VINL
IIN
IDD
ISS
Logic Inputs Low
V max
Logic Input Current
Positive Supply Current
Negative Supply Current
VIN = 0 V or VDD
VIN = VINL or VINH
VIN = VINL or VINH’ VSS = –5 V
µA max
mA max
mA max
14
10
NOT E
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the DAC8426 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. C
–4–
Typical Performance Characteristics–DAC8426
Channel-to-Channel Matching (DACs
A, B, C, D, Superim posed)
Relative Accuracy vs. Code
at TA = –55°C, +25°C, +125°C
(All Superim posed)
Zero Code Error vs. Tem perature
Broadband Noise (DC to 200 kHz)
Long Term Drift Accelerated by
Burn-In
VOUT Noise Density vs. Frequency
V
(0)
OUT
⌬V
PSRR(+) = –20 LOG
VDD = +15 V ؎1 VP, VSS = 0 V
(0)
,
DD
V
OUT
⌬V
PSRR(–) = –20 LOG
,
SS
VDD = +15 V, VSS = –4 V ؎1 VP
Power Supply Current vs.
Tem perature
PSRR vs. Frequency
REV. C
–5–
DAC8426–Typical Performance Characteristics
Output Im pedance (VREFOUT)
vs. Frequency
VREFOUT Load Regulation
vs. Tem perature
VREFOUT Error from 10.000 V
vs. Tem perature
VREFOUT Start Up
VREFOUT Line Regulation vs. Tem perature
REV. C
–6–
DAC8426
P ARAMETER D EFINITIO NS
TO TAL UNAD JUSTED ERRO R (TUE)
Table I. D AC Control Logic Truth Table
T his specification includes the Full-Scale-Error, Relative Accu-
racy Zero-Code-Error and the internal reference voltage. T he
ideal Full-Scale output voltage is 10 V minus 1 LSB which
equals 9.961 volts. Each LSB equals 10 V × (1/256) = 0.039 volts.
Logic Control
A1
D AC8426
O peration
WR
A0
H
X
X
No Operation
Device Not Selected
DAC A T ransparent
DAC A Latched
DAC B T ransparent
DAC B Latched
DAC C T ransparent
DAC C Latched
DAC D T ransparent
DAC D Latched
D IGITAL CRO SSTALK
L
g
L
g
L
g
L
g
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
Digital crosstalk is the signal coupled to the output of a DAC
due to a changing digital input from adjacent DACs being up-
dated. It is specified in nano-Volt-seconds (nVs).
CIRCUIT D ESCRIP TIO N
T he DAC8426 is a complete quad 8-bit D/A converter. It con-
tains an internal bandgap reference, four voltage switched R-2R
ladder DACs, four DAC latches, four output buffer amplifiers,
and an address decoder. All four DACs share the internal ten
volt reference and analog ground(AGND). Figure 1 provides an
equivalent DAC plus buffer schematic.
L = Low State, H = High State, X = Don’t Care
Figure 1. Sim plified Circuit Configuration for One DAC.
(Switches Are Shown for All “1s” on the Digital Inputs.)
T he eleven digital inputs are compatible with both T T L and 5 V
(or higher) CMOS logic. T able I shows the DAC control logic
truth table for WR, A1, and A0 operation. When WR is active
low the input latch of the selected DAC is transparent, and the
DAC’s output responds to the data present on the eight digital
data inputs (DBx). T he data (DBx) is latched into the ad-
dressed DAC’s latch on the positive edge of the WR control sig-
nal. T he important timing requirements are shown in the Write
Cycle T iming Diagram, Figure 2.
Figure 2. Write Cycle Tim ing Diagram
the design of the internal DAC switching to minimize transients
on the reference voltage terminal (VREFOUT ). Other devices
connected to this reference terminal should have well behaved
input loading characteristics. D/A converters such as the PMI
PM7226A have been designed to minimize reference input tran-
sient currents and can be directly connected to the DAC8426
10 V reference. Devices exhibiting large current transients due
to internal switching should be buffered with an op amp to
maintain good overall system noise performance. A 10 µF refer-
ence output bypass capacitor is required.
INTERNAL 10 VO LT REFERENCE
T he internal 10 V bandgap reference of the DAC8426 is trimm-
ed to the output voltage and temperature drift specifications.
T his internal reference is connected to the reference inputs of
the four internal 8-bit D/A converters. T he output terminal of
the internal 10 V reference is available on pin 4. T he 10 V out-
put of the reference is produced with respect to the AGND pin.
T his reference output can be used to supply as much as 5 mA of
additional current to external devices. Care has been taken in
BUFFER AMP LIFIER SECTIO N
T he four internal unity-gain voltage buffers provide low output
impedance capable of sourcing 5 mA or sinking 350 µA. Typical
output slew rates of ±4 V/µs are achieved with 10 V full-scale out-
put changes and RL = 2 kΩ. Figure 3 photographs show large sig-
nal and settling time response. Capacitive loads to 3300 pF
maximum, and resistive loads to 2 kΩ minimum can be applied.
REV. C
–7–
DAC8426
a) Large Signal
b) Settling Tim e Response (Negative Transition)
Test Conditions, All Photos:
DD = +15 V
V
CREFOUT = 10 F
RL = 2 k⍀
Digital Input Sequence 0, 255, 0
c) Settling Tim e Response (Positive Transition)
Figure 3. Dynam ic Response
four output buffer amplifiers are connected to VSS. Operating
the DAC8426 from dual supplies (VDD = +15 V and VSS = –5 V)
improves negative going output settling time near zero volts.
T he outputs can withstand an indefinite short-circuit to AGND
to typically 50 mA. T he output may also be shorted to any volt-
age between VDD and VSS; however, care must be taken to not
exceed the device maximum power dissipation.
When operating single supply (VDD = +15 V and VSS = 0 V) the
output sink current decreases as the output approaches zero
voltage. Within 200 mV of AGND (single-supply operation) the
internal sinking capability appears resistive at a value of approxi-
mately 1200 Ω. T he buffer amplifier output current and voltage
characteristics are plotted in Figure 5.
T he amplifier’s emitter follower output stage consists of an in-
trinsic NPN bipolar transistor with a 400 µA NMOS pull-down
current-source load connected to VSS. T his circuit configuration
shown in Figure 4 enables the output amplifier to develop out-
put voltages very close to AGND. Only the negative supply of the
REV. C
–8–
DAC8426
AP P LICATIO NS SETUP
UNIP O LAR O UTP UT O P ERATIO N
T he output voltage appearing at any output VOUT is equal to the
internal 10 V reference multiplied by the decimal value of the
latched digital input divided by 28 (= 256). In equation form:
One additional characteristic guaranteed is a DNL of ±1 LSB
on all grades. T he DAC8426 is therefore guaranteed to be mon-
otonic. In the situation where a continuously positive 1 LSB
digital increment is applied, the output voltage will always in-
crease in value, never decrease. T his is very important is servo
applications and other closed-loop feedback systems. Finally, in
the typical characteristic curves, long term output voltage drift
(stability) is provided.
VOUT(D) = D/256 × 10 V
where D = 010 to 25510
BIP O LAR O UTP UT O P ERATIO N
An external op amp plus two resistors can easily convert any
DAC output to bipolar output voltage swings. Figure 6 shows all
four DACs output operating in bipolar mode. This is the general
expression describing the bipolar output transfer equation:
VOUT(D) = [(1 +R2/R1) × D/256 × 10 V] –R2/R1 × 10 V,
where D = 010 to 25510
If R1 = R2, then VOUT becomes:
VOUT (D) = (D/128–1) × 10 V
T able III lists various output voltages with R1 = R2 versus digital
input code. T his coding is considered offset binary. Note that
the LSB step size is now 20 V/256 = 0.078 V, twice as large as
the unipolar output case previously discussed. In order to minimize
gain and offset errors, choose R1 and R2 to match and track
within 0.1% over the selected operating temperature range
of interest.
Figure 4. Am plifier Output Stage
Note that the maximum possible output is 1 LSB less than the
internal 10 V reference, that is, 255/256 × 10 V = 9.961 V.
T able II lists output voltages for a given digital input. T he total
unadjusted error (T UE) specification of the product grade used
determines the output tolerances of the values listed in T able II.
For example, a ±2 LSB grade DAC8426FP loaded with decimal
12810 (half-scale) would have a guaranteed output voltage oc-
curring in the range of 5 V ±2 LSB, which is 5 V ±(2 × 10 V/256)
= 5 V ±0.078 V. T herefore VOUT is guaranteed to occur in the
following range:
Table II. Unipolar O utput Voltage as a Function of
D igital Input Code
D igital Input
Code
Analog O utput
Voltage (= D /256 × 10 V)
255
254
129
128
127
1
9.961 V
9.922 V
5.039 V
5.000 V
4.961 V
0.039 V
0.000 V
Full-Scale (FS)
FS-1 LSB
4.922 V ≤ VOUT(128) ≤ 5.078 V
Half-Scale
1 LSB
Zero-Scale
0
O FFSETTING AGND
Since the DAC ladder and bandgap reference are terminated at
AGND, it is possible to offset AGND positive with respect to
DGND. T he 10 V output span remains if a positive offset is ap-
plied to AGND. T he offset voltage source connected to AGND
must be capable of sinking 14 mA. AGND cannot be taken
negative with respect to DGND; this would forward bias an in-
ternal diode. Allowance must be made at VDD to maintain 3.5 V
of headroom above VREFOUT . T his connection setup is useful
in single supply applications where virtual ground needs to be
slightly positive with respect to ground. In this application con-
nect VSS to DGND to take advantage of the extra buffer output
current sinking capability when the DAC output is programmed
to all zeros code, see Figure 7.
Figure 5. DAC Output Current Sink
For the top grade DAC8426EP ±1 LSB total unadjusted error
(TUE), the guaranteed range is 4.961 V ≤ VOUT (12810) ≤ 5.039 V.
T hese tolerances provide the worst case analysis including tem-
perature changes.
REV. C
–9–
DAC8426
Table III. Bipolar O utput Voltage as a Function of D igital
Input Code
D igital Input
Code
Analog O utput
Voltage (= D /256 × 10 V)
255
254
129
128
127
1
9.922 V
9.844 V
0.078 V
0.000 V
–0.078 V
–9.922 V
–10.000 V
Full-Scale (FS)
FS-1 LSB
Zero-Scale
0
Neg Full-Scale
Figure 7. AGND Biasing Schem e Providing Offset Output
Range
3. Power Supply Sequencing—No special requirements exist
with the DAC8426. However, users should be aware that of-
ten the 5 V logic supply may be powered up momentarily
prior to the +15 V analog supply. In this situation, the
DAC8426 ESD input protection diodes will forward bias if
the applied input logic is at logic “1”. No damage will result
to the input since the DAC8426 is designed to withstand mo-
mentary currents of up to 130 mA. T his situation will likely
exist for any DAC or ADC operating from a separate analog
supply.
Figure 6. Bipolar Operation
CO NNECTIO N AND LAYO UT GUID ELINES
Layout and design techniques used in the interface between dig-
ital and analog circuitry require special attention to detail. The
following considerations should be evaluated prior to PCB layout.
1. Return signal paths through the ground system should be
carefully considered. High-speed digital logic current pulses
traveling on return ground traces generate glitches that can be
radiated to the analog circuits if the ground path layout pro-
duces loop antennas. Ground planes can minimize this situa-
tion. Separate digital and analog grounding areas to minimize
crosstalk. Ideally a single common-point ground should be on
the same PCB board as the DAC8426. T he analog ground re-
turns should take advantage of the appropriate placement of
power supply bypass capacitors.
4. ESD input protection—Attention has been given in the de-
sign of the DAC8426 to ESD sensitivity. Using the human
body model test technique (MIL-ST D 3015.4) the DAC8426
generally will withstand 1500 V ESD transients on all pins.
Handling and testing prior to PCB insertion generally exposes
ICs to the toughest environment they will experience. Once
the IC is soldered in the PCB, it is still important to consider
any traces that connect to PCB edge connectors. T hese traces
should be protected with appropriate devices especially if the
boards will experience field replacement or adjustment. Han-
dling the exposed edge connectors by field maintenance
people in a low humidity environment can produce 20 kV
ESD transients which will be detrimental to almost any inte-
grated IC connected to the edge connector.
2. For optimum performance, bypass VDD and VSS (if using
negative supply voltage) with 0.1 µF ceramic disk capacitors
to shunt high-frequency spikes. Also use in parallel 6.8 µF to
10 µF capacitors to provide a charge reservoir for lower fre-
quency load change requirements. T he reference output
(VREFOUT ) should be bypassed with a 10 µF tantalum ca-
pacitor to optimize reference output stability during data in-
put changes. T his helps to minimize digital crosstalk.
REV. C
–10–
DAC8426
MICRO P RO CESSO R INTERFACING
T he DAC8426 easily interfaces to most 8- and 16-bit wide data-
bus systems. Serial and 4-bit busses can also be accommodated
with additional latches and control circuitry. Interfacing can be
accomplished with databus transfers running with 50 ns write
pulse widths.
Examples of various microprocessor interface circuits are pro-
vided in Figures 8 through 12. T hese figures have omitted cir-
cuitry not essential to the bus interface. T he design process
should include review of the DAC8426 timing diagram with the
µP system timing diagram.
Figure 10. DAC8426 to 6809 Interface (Sim plified circuit,
only lines of interest are shown.)
Figure 11. DAC8426 to 6502 Interface (Sim plified circuit,
only lines of interest are shown.)
Figure 8. DAC8426 to 8085A Interface (Sim plified circuit,
only lines of interest are shown.)
Figure 9. DAC8426 to Z-80 Interface (Sim plified circuit,
only lines of interest are shown.)
Figure 12. DAC8426 to 68000 Interface (Sim plified circuit,
only lines of interest are shown.)
REV. C
–11–
DAC8426
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
20-P in Cerdip
(Q-20)
0.005 (0.13) MIN
0.098 (2.49) MAX
11
20
0.310 (7.87)
0.220 (5.59)
1
10
0.320 (8.13)
0.290 (7.37)
PIN 1
1.060 (26.92) MAX
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
0.023 (0.58)
0.014 (0.36)
0.100
(2.54)
BSC
SEATING
PLANE
0.070 (1.78)
0.030 (0.76)
15°
0°
20-P in P lastic D IP
(N-20)
1.060 (26.90)
0.925 (23.50)
20
1
11
10
0.280 (7.11)
0.240 (6.10)
0.325 (8.25)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
PIN 1
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.100
(2.54)
BSC
0.070 (1.77)
0.045 (1.15)
0.022 (0.558)
0.014 (0.356)
20-Lead SO L
(R-20)
0.5118 (13.00)
0.4961 (12.60)
20
11
1
10
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
x 45°
0.0098 (0.25)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
0.0138 (0.35)
REV. C
–12–
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