DAC8420FP [ADI]
Quad 12-Bit Serial Voltage Output DAC; 四通道12位串行电压输出DAC
| 型号： | DAC8420FP |
| 厂家： | 
ADI |
| 描述： | Quad 12-Bit Serial Voltage Output DAC |
| 文件： | 总16页 (文件大小：590K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad 12-Bit Serial
Voltage Output DAC
a
DAC8420
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Guaranteed Monotonic Over Temperature
Excellent Matching Between DACs
Unipolar or Bipolar Operation
VDD
1
VREFHI
5
SDI 10
CS 12
Buffered Voltage Outputs
REG
DAC A
DAC B
DAC C
DAC D
7
6
VOUTA
VOUTB
VOUTC
VOUTD
A
High Speed Serial Digital Interface
Reset to Zero- or Center-Scale
Wide Supply Range, +5 V-Only to ؎15 V
Low Power Consumption (35 mW max)
Available in 16-Pin DIP and SOL Packages
12
CLK
11
REG
B
SHIFT
REGISTER
APPLICATIONS
Software Controlled Calibration
Servo Controls
Process Control and Automation
ATE
NC
13
REG
C
3
4
DECODE
14
LD
REG
D
2
2
9
16
15
4
8
VREFLO
VSS
GND
CLSEL CLR
GENERAL DESCRIPTION
The DAC8420 is available in 16-pin epoxy DIP, cerdip, and
wide-body SOL (small-outline surface mount) packages. Opera-
tion is specified with supplies ranging from +5 V-only to ±15 V,
with references of +2.5 V to ±10 V respectively. Power dissipa-
tion when operating from ±15 V supplies is less than 255 mW
(max), and only 35 mW (max) with a +5 V supply.
The DAC8420 is a quad, 12-bit voltage-output DAC with serial
digital interface, in a 16-pin package. Utilizing BiCMOS tech-
nology, this monolithic device features unusually high circuit
density and low power consumption. The simple, easy-to-use
serial digital input and fully buffered analog voltage outputs
require no external components to achieve specified performance.
For applications requiring product meeting MIL-STD-883,
contact your local sales office for the DAC8420/883 data sheet,
which specifies operation over the –55°C to +125°C tempera-
ture range.
The three-wire serial digital input is easily interfaced to micro-
processors running at 10 MHz rates, with minimal additional
circuitry. Each DAC is addressed individually by a 16-bit serial
word consisting of a 12-bit data word and an address header.
The user-programmable reset control CLR forces all four DAC
outputs to either zero or midscale, asynchronously overriding
the current DAC register values. The output voltage range, de-
termined by the inputs VREFHI and VREFLO, is set by the
user for positive or negative unipolar or bipolar signal swings
within the supplies allowing considerable design flexibility.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
DAC8420–SPECIFICATIONS
(at VDD = +5.0 V ؎ 5%, VSS = 0.0 V, VVREFHI = +2.5 V, VVREFLD = 0.0 V, and
VSS = –5.0 V ؎ 5%, VVREFLO = –2.5 V, –40؇C ≤ TA ≤ +85؇C unless otherwise noted. See Note 1 for supply variations.)
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Condition
Min
Typ
Max
Units
STATIC ACCURACY
Integral Linearity “E”
Integral Linearity “E”
Integral Linearity “F”
Integral Linearity “F”
Differential Linearity
Min-Scale Error
Full-Scale Error
Min-Scale Error
Full-Scale Error
Min-Scale Tempco
Full-Scale Tempco
INL
INL
INL
INL
DNL
ZSE
FSE
ZSE
FSE
±1/4
±1/2
±3/4
±1
±1
±3
±2
±4
±1
±4
±4
±8
±8
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Note 2, VSS = 0 V
Note 2, VSS = 0 V
Monotonic Over Temperature
±1/4
R
R
L = 2 kΩ, VSS = –5 V
L = 2 kΩ, VSS = –5 V
Note 2, RL = 2 kΩ, VSS = 0 V
Note 2, RL = 2 kΩ, VSS = 0 V
Note 3, RL = 2 kΩ, VSS = –5 V
Note 3, RL = 2 kΩ, VSS = –5 V
LSB
ppm/°C
ppm/°C
TCZSE
TCFSE
±10
±10
MATCHING PERFORMANCE
Linearity Matching
±1
LSB
REFERENCE
Positive Reference Input Range
Negative Reference Input Range
Negative Reference Input Range
Reference High Input Current
Reference Low Input Current
VVREFHI
VVREFLO
VVREFLO
IVREFHI
Note 4
Note 4
VVREFLO +2.5
VSS
0
–0.75
–1.0
VDD –2.5
V
V
V
mA
mA
VVREFHI –2.5
VVREFHI –2.5
+0.75
Note 4, VSS = 0 V
Codes 000H, 555H
Codes 000H, 555H, VSS = –5 V
±0.25
–0.6
IVREFLO
AMPLIFIER CHARACTERISTICS
Output Current
Settling Time
IOUT
tS
SR
VSS = –5 V
to 0.01%, Note 5
10% to 90%, Note 5
–1.25
2.4
+1.25
mA
µs
V/µs
8
1.5
Slew Rate
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
VINH
VINL
IIN
V
V
µA
pF
0.8
10
Input Capacitance
CIN
Note 3
13
LOGIC TIMING CHARACTERISTICS3, 6
Data Setup Time
Data Hold
Clock Pulse Width HIGH
Clock Pulse Width LOW
Select Time
Deselect Delay
Load Disable Time
Load Delay
Load Pulse Width
Clear Pulse Width
tDS
tDH
tCH
tCL
tCSS
tCSH
tLD1
tLD2
tLDW
tCLRW
25
55
90
120
90
5
130
35
80
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SUPPLY CHARACTERISTICS
Power Supply Sensitivity
Positive Supply Current
Negative Supply Current
Power Dissipation
PSRR
IDD
ISS
0.002
4
–3
0.01
7
%/%
mA
mA
–6
PDISS
VSS = 0 V
20
35
mW
NOTES
1All supplies can be varied ±5% and operation is guaranteed. Device is tested with VDD = +4.75 V.
2For single-supply operation (VVREFLO = 0 V, VSS = 0 V), due to internal offset errors INL and DNL are measured beginning at code 003H.
3Guaranteed but not tested.
4Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
5VOUT swing between +2.5 V and –2.5 V with VDD = 5.0 V.
6All input control signals are specified with tr = tf =5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
7Typical values indicate performance measured at +25°C.
Specifications subject to change without notice.
–2–
REV. 0
DAC8420
ELECTRICAL CHARACTERISTICS
(at VDD = +15.0 V ؎ 5%, VSS = –15.0 V ؎ 5%, VVREFHI = +10.0 V,
VVREFLO = –10.0 V, –40؇C ≤ TA ≤ +85؇C unless otherwise noted. See Note 1 for supply variations.)
Parameter
Symbol Condition
Min
Typ
Max
Units
STATIC ACCURACY
Integral Linearity “E”
Integral Linearity “F”
Differential Linearity
Min-Scale Error
INL
INL
DNL
ZSE
±1/4
±1/2
±1/4
±1/2
±1
±1
LSB
LSB
LSB
LSB
Monotonic Over Temperature
RL = 2 kΩ
±2
Full-Scale Error
FSE
RL = 2 kΩ
±2
LSB
Min-Scale Tempco
Full-Scale Tempco
TCZSE
TCFSE
Note 2, RL = 2 kΩ
Note 2, RL = 2 kΩ
±4
±4
ppm/°C
ppm/°C
MATCHING PERFORMANCE
Linearity Matching
±1
LSB
REFERENCE
Positive Reference Input Range
Negative Reference Input Range
Reference High Input Current
Reference Low Input Current
VVREFHI Note 3
VVREFLO Note 3
VVREFLO +2.5
–10
VDD –2.5
VVREFHI –2.5
+2.0
V
V
mA
mA
IVREFHI
IVREFLO
Codes 000H, 555H
Codes 000H, 555H
–2.0
–3.5
±1.0
–2.0
AMPLIFIER CHARACTERISTICS
Output Current
Settling Time
IOUT
tS
SR
–5
+5
mA
µs
V/µs
to 0.01%, Note 4
10% to 90%, Note 4
13
2
Slew Rate
DYNAMIC PERFORMANCE
Analog Crosstalk
Digital Feedthrough
Note 2
Note 2
>64
>72
90
dB
dB
kHz
Large Signal Bandwidth
3 dB, VVREFHI = 5 V + 10 V p-p,
VVREFLO = –10 V, Note 2
Code Transition = 7FFH to 800H, Note 2
Glitch Impulse
64
nV-s
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
VINH
VINL
IIN
2.4
V
V
µA
pF
0.8
10
Input Capacitance
CIN
Note 2
13
LOGIC TIMING CHARACTERISTICS2, 5
Data Setup Time
Data Hold
Clock Pulse Width HIGH
Clock Pulse Width LOW
Select Time
Deselect Delay
Load Disable Time
Load Delay
Load Pulse Width
Clear Pulse Width
tDS
tDH
tCH
tCL
tCSS
tCSH
tLD1
tLD2
tLDW
tCLRW
25
20
30
50
55
15
40
15
45
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SUPPLY CHARACTERISTICS
Power Supply Sensitivity
Positive Supply Current
Negative Supply Current
Power Dissipation
PSRR
IDD
ISS
0.002
6
–5
0.01
9
%/%
mA
mA
–8
PDISS
255
mW
NOTES
1All supplies can be varied ±5% and operation is guaranteed.
2Guaranteed but not tested.
3Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
4VOUT swing between +10 V and –10 V.
5All input control signals are specified with tr = tf =5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
6Typical values indicate performance measured at +25°C.
Specifications subject to change without notice.
REV. 0
–3–
DAC8420
(at VDD = +15.0 V, VSS = –15.0 V, VREFHI = +10.0 V, VREFLO = –10.0 V, TA = +25؇C
WAFER TEST LIMITS unless otherwise noted)
DAC8420G
Limit
Parameter
Symbol
Conditions
Units
Integral Linearity
Differential Linearity
Min-Scale Offset
INL
DNL
±1
±1
±1
±1
2.4
0.8
1
LSB max
LSB max
LSB max
LSB max
V min
Max-Scale Offset
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
Positive Supply Current
Negative Supply Current
VINH
VINL
IIN
IDD
ISS
V max
µA max
mA max
mA max
8
7
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
ABSOLUTE MAXIMUM RATINGS
3. Remove power before inserting or removing units from their
(TA = +25°C unless otherwise noted)
sockets.
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +18.0 V
4. Analog Outputs are protected from short circuits to ground
or either supply.
V
V
V
V
SS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –18.0 V
SS to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +36.0 V
SS to VVREFLO . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VSS – 2.0 V
VREFHI to VVREFLO . . . . . . . . . . . . . . . . . . . +2.0 V, VDD – VSS
DICE CHARACTERISTICS
VVREFHI to VDD . . . . . . . . . . . . . . . . . . . . . . . +2.0 V, +33.0 V
VREFHI, IVREFLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
I
(SUBSTRATE)
Digital Input Voltage to GND . . . . . . . . . –0.3 V, VDD + 0.3 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Operating Temperature Range
CLSEL
16
CLR
15
VOUTD
2
VDD
1
EP, FP, ES, FS, EQ, FQ . . . . . . . . . . . . . . –40°C to +85°C
Dice Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . +300°C
14 LD
13 NC
Thermal Resistance
Package Type
θJA
θJC
Units
VOUTC 3
VREFLO
16-Pin Plastic DIP (P)
16-Pin Hermetic DIP (Q)
16-Lead Small Outline
Surface Mount (S)
701
821
27
9
°C/W
°C/W
4
862
22
°C/W
VREFHI 5
VOUTB 6
NOTES
1θJA is specified for worst case mounting conditions, i.e., θJA is specified for
device in socket.
2θJA is specified for device on board.
CAUTION
1. Stresses above those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this
specification is not implied. Exposure to the above maximum
rating conditions for extended periods may affect device
reliability.
12 CS
11 CLK
7
8
9
10
SDI
VOUTA
VSS GND
2. Digital inputs and outputs are protected, however, permanent
damage may occur on unprotected units from high-energy
electrostatic fields. Keep units in conductive foam or packaging
at all times until ready to use. Use proper antistatic handling
procedures.
NC = NO CONNECT
Die Size 0.119 × 0.283 inch, 33,677 sq. mils
(3.023 × 7.188 mm, 21.73 sq. mm)
Transistor Count 2,207
For additional DICE ordering information, refer to databook.
–4–
REV. 0
DAC8420
DATA LOAD SEQUENCE
CS
tCSH
tCSS
SDI
A1
A0
X
X
D11
D10
D9
D8
D4
D3
D2
D1
D0
CLK
LD
tLD1
tLD2
tDS
tDH
DATA LOAD TIMING
SDI
CLEAR TIMING
CLSEL
tCLRW
CLK
CS
CLR
tCH
tCL
tS
±1LSB
tCSH
V
OUT
tLD2
tLDW
LD
tS
V
±1LSB
OUT
Timing Diagram
ORDERING GUIDE
5kΩ
10Ω
Temperature
Range
INL
Package
Package
+15V
1N4001
1
2
3
4
16
Model1
(؎LSB) Description Option2
+
10µF
0.1µF
NC
15
14
DAC8420EP
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0.5
0.5
0.5
1.0
1.0
1.0
1.0
Plastic DIP
Cerdip
P
NC
DAC8420EQ
DAC8420ES
DAC8420FP
DAC8420FQ
DAC8420FS
DAC8420QBC
Q
10Ω
NC
–10V
1N4001
13
12
11
SOIC
SOL
P
DUT
10µF
0.1µF
0.1µF
+
+
Plastic DIP
Cerdip
5
6
Q
5kΩ
NC
NC
SOIC
Dice3
SOL
10Ω
+10V
1N4001
7
8
10
9
10µF
NOTES
1A complete /883 data sheet is available. For availability and burn-in informa-
tion, contact your local sales office.
10kΩ
10Ω
2PMI division letter designator.
–15V
1N4001
3Dice tested at +25°C only.
10µF
0.1µF
NC = NO CONNECT
+
Burn-In Diagram
REV. 0
–5–
DAC8420
PIN CONFIGURATIONS
SOL
DIP
16
15
14
13
12
1
2
3
4
5
6
7
8
VDD
CLSEL
CLR
1
2
3
4
VDD
16 CLSEL
15
VOUTD
CLR
VOUTD
VOUTC
VOUTC
LD
NC
14 LD
DAC8420
VREFLO
TOP VIEW
VREFLO
DAC8420
TOP VIEW
(Not to Scale)
13 NC
12 CS
(Not to Scale)
CS
VREFHI
VOUTB
5
6
7
8
VREFHI
VOUTB
VOUTA
11
10
9
CLK
SDI
11 CLK
10 SDI
VOUTA
VSS
GND
9
GND
VSS
NC = NO CONNECT
NC = NO CONNECT
PIN FUNCTION DESCRIPTION
Power Supplies
VDD: Positive Supply, +5 V to +15 V.
VSS: Negative Supply, 0 V to –15 V.
GND: Digital Ground.
Clock
CLK: System Serial Data Clock Input, TTL/CMOS levels. Data presented to the input SDI is shifted into
the internal serial-parallel input register on the rising edge of clock. This input is logically ORed with CS.
Control Inputs
(All are CMOS/TTL compatible.)
CLR: Asynchronous Clear, active low. Sets internal data registers A-D to zero or midscale, depending on cur-
rent state of CLSEL. The data in the serial input shift register is unaffected by this control.
CLSEL: Determines action of CLR. If HIGH, a Clear command will set the internal DAC registers A-D to
midscale (800H). If LOW, the registers are set to zero (000H).
CS: Device Chip Select, active low. This input is logically ORed with the clock and disables the serial data
register input when HIGH. When LOW, data input clocking is enabled, see the Control Function Table.
LD: Asynchronous DAC Register Load Control, active low. The data currently contained in the serial input
shift register is shifted out to the DAC data registers on the falling edge of LD, independent of CS. Input data
must remain stable while LD is LOW.
Data Input
(All are CMOS/TTL compatible.)
SDI: Serial Data Input. Data presented to this pin is loaded into the internal serial-parallel shift register, which
shifts data in beginning with DAC address Bit A1. This input is ignored when CS is HIGH.
The format of the 16-bit serial word is:
(FIRST)
(LAST)
B10 B11 B12 B13 B14 B15
B0
A1
B1
A0
B2
B3
B4
B5
B6
B7
B8
B9
NC NC D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
—Address Word—
(MSB)
—DAC Data Word—
(LSB)
NC = Don’t Care.
Reference Inputs
Analog Outputs
VREFHI: Upper DAC ladder reference voltage input. Allowable range is (VDD – 2.5 V) to (VVREFLO +2.5 V).
VREFLO: Lower DAC ladder reference voltage input, equal to zero scale output. Allowable range is VSS to
(VVREFHI – 2.5 V).
VOUTA through VOUTD: Four buffered DAC voltage outputs.
–6–
REV. 0
DAC8420
Table I. Control Function Logic Table
CLK1
CS1
LD
CLR
CLSEL
Serial Input Shift Register
DAC Registers A-D
NC
NC
NC
↑
L
H
H
H
H
L
H
H
H
H
H
↓
L
L
↑
H
H
H
H
H
H
L
No Change
No Change
No Change
Shifts Register One Bit
Shifts Register One Bit
No Change
No Change
No Change
Loads Midscale Value (800H)
Loads Zero-Scale Value (000H)
Latches Value
H/L
NC
NC
NC
NC
NC
No Change
↑
No Change
NC ( )
NC
H
Loads the Serial Data Word2
↑
H
NC
L
H
Transparent3
No Change
NC = Don’t Care.
NOTES
1CS and CLK are interchangeable.
2Returning CS HIGH while CLK is HIGH avoids an additional “false clock” of serial input data. See Note 1.
3Do not clock in serial data while LD is LOW.
(000H) or midscale (800H), depending on the state of CLSEL as
shown in the Digital Function Table. The CLEAR function is
asynchronous and is totally independent of CS. When CLR
returns HIGH, the DAC outputs remain latched at the reset
value until LD is strobed, reloading the individual DAC data word
registers with either the data held in the serial input register prior
to the reset, or new data loaded through the serial interface.
OPERATION
Introduction
The DAC8420 is a quad, voltage-output 12-bit DAC with serial
digital input, capable of operating from a single +5 V supply.
The straightforward serial interface can be connected directly to
most popular microprocessors and microcontrollers, and can ac-
cept data at a 10 MHz clock rate when operating from ±15 V
supplies. A unique voltage reference structure assures maximum
utilization of DAC output resolution by allowing the user to set
the zero- and full-scale output levels within the supply rails. The
analog voltage outputs are fully buffered, and are capable of
driving a 2 kΩ load. Output glitch impulse during major code
transitions is a very low 64 nV-s (typ).
Table II. DAC Address Word Decode Table
A1
A0
DAC Addressed
0
0
1
1
0
1
0
1
DAC A
DAC B
DAC C
DAC D
Digital Interface Operation
The serial input of the DAC-8420, consisting of CS, SDI, and
LD, is easily interfaced to a wide variety of microprocessor serial
ports. As shown in Table I and the Timing Diagram, while CS
is LOW the data presented to the input SDI is shifted into the
internal serial/parallel shift register on the rising edge of the
clock, with the address MSB first, data LSB last. The data for-
mat, shown above, is two bits of DAC address and two “don’t
care” fill bits, followed by the 12-bit DAC data word. Once all
16 bits of the serial data word have been input, the load control
LD is strobed and the word is parallel-shifted out onto the inter-
nal data bus. The two address bits are decoded and used to
route the 12-bit data word to the appropriate DAC data regis-
ter, see the Applications Information.
Programming the Analog Outputs
The unique differential reference structure of the DAC8420
allows the user to tailor the output voltage range precisely to the
needs of the application. Instead of spending DAC resolution
on an unused region near the positive or negative rail, the
DAC8420 allows the user to determine both the upper and
lower limits of the analog output voltage range. Thus, as shown
in Table III and Figure 1, the outputs of DACs A through D
range between VREFHI and VREFLO, within the limits speci-
fied in the Electrical Characteristics tables. Note also that
VREFHI must be greater than VREFLO.
Correct Operation of CS and CLK
V
DD
As mentioned in Table I, the control pins CLK and CS require
some attention during a data load cycle. Since these two inputs
are fed to the same logical “OR” gate, their operation is in fact
identical. The user must take care to operate them accordingly
in order to avoid clocking in false data bits. As shown in the
Timing Diagram, CLK must be either halted HIGH, or CS
brought HIGH during the last HIGH portion of the CLK fol-
lowing the rising edge which latched in the last data bit. Other-
wise, an additional rising edge is generated by CS rising while
CLK is LOW, causing CS to act as the clock and allowing a
false data bit into the serial input register. The same issue must
be considered in the beginning of the data load sequence also.
2.5V MIN
V
VREFHI
FFF
H
1 LSB
2.5V MIN
000
H
–10V MIN
V
VREFLO
0V MIN
Using CLR and CLSEL
V
SS
The CLEAR (CLR) control allows the user to perform an asyn-
chronous reset function. Asserting CLR loads all four DAC data
word registers, forcing the DAC outputs to either zero-scale
Figure 1. Output Voltage Range Programming
REV. 0
–7–
DAC8420
Table III. Analog Output Code
DAC Data Word (HEX)
VOUT
Note
(VREFHI –VREFLO )
VREFLO +
× 4095
FFF
801
800
7FF
000
Full-Scale Output
Midscale + 1
Midscale
4096
(VREFHI –VREFLO )
VREFLO +
VREFLO +
VREFLO +
VREFLO +
× 2049
× 2048
× 2047
× 0
4096
(VREFHI –VREFLO )
4096
(VREFHI –VREFLO )
Midscale – 1
Zero Scale
4096
(VREFHI –VREFLO )
4096
Typical Performance Characteristics
0.3
0.10
0.3
0.2
T
= +25°C
T
V
= +25°C
A
A
0.05
0.2
= +5V, V = 0V
V
V
= +15V, V = –15V
DD
SS
DD
SS
V
= 0V
= –10V
VREFLO
VREFLO
0
0.1
0
0.1
0
–0.05
–0.10
–0.15
–0.1
–0.1
T
= +25°C
–0.20
–0.25
A
V
V
= +15V, V = –15V
–0.2
–0.3
DD
SS
–0.2
–0.3
= –10V
VREFLO
–0.30
1.5
2.0
2.5
3.0
– V
3.5
–6 –4 –2
0
2
4
6
8
10 12 14
–6 –4 –2
0
2
4
6
8
10 12 14
V
– V
V
VREFHI
V
– V
VREFHI
VREFHI
Figure 3. Differential Linearity vs.
VREFHI (+5 V)
Figure 2. Differential Linearity vs.
VREFHI (±15 V)
Figure 4. INL vs. VREFHI (±15 V)
0.7
0.4
1.2
T
= +25°C
x + 3σ
A
x + 3σ
0.3
0.5
1.0
V
V
= +5V, V = 0V
DD
SS
V
V
V
= +15V, V = –15V
SS
= 0V
DD
VREFLO
0.2
0.1
V
V
V
= +15V, V = –15V
SS
= +10V
DD
VREFHI
0.3
0.1
0.8
0.6
= +10V
= –10V
VREFHI
VREFLO
= –10V
VREFLO
x
0
x
–0.1
–0.1
0.4
–0.2
–0.3
–0.3
–0.5
0.2
0
x – 3σ
x – 3σ
–0.4
0
200
400
600
800
1000
1.5
2.0
2.5
3.0
– V
3.5
0
200
400
600
800
1000
T = HOURS OF OPERATION AT +125°C
CURVES NOT NORMALIZED
V
T = HOURS OF OPERATION AT +125
°C
VREFHI
CURVES NOT NORMALIZED
Figure 5. INL vs. VREFHI (+5 V)
Figure 6. Full-Scale Error vs.
Time Accelerated by Burn-In
Figure 7. Zero-Scale Error vs.
Time Accelerated by Burn-In
–8–
REV. 0
DAC8420
1.2
0.2
0.9
T
= +25°C
A
V
V
V
= +15V, V = –15V
SS
V
V
V
= +15V, V = –15V
DD
DD SS
V
V
= +15V, V = –15V
SS
0.7
0.5
1.0
0.8
DD
0.1
0
= +10V
= +10V
VREFHI
VREFHI
= +10V
DAC C
DAC D
= –10V
= –10V
VREFLO
VREFLO
DAC A
0.3
0.1
0.6
0.4
–0.1
–0.2
DAC B
DAC C
DAC D
–0.1
–0.3
–0.5
0.2
0
–0.3
–0.4
DAC A
DAC B
–0.2
–0.4
–0.5
–0.6
–0.7
–0.9
–75 –50 –25
0
25
50
75 100 125
0
500 1000 1500 2000 2500 3000 3500 4000 4500
DIGITAL INPUT CODE
–75 –50 –25
0
25
50
75 100 125
TEMPERATURE –
°
C
TEMPERATURE – °C
Figure 8. Full-Scale Error vs.
Temperature
Figure 9. Zero-Scale Error vs.
Temperature
Figure 10. Channel-to-Channel
Matching ±15/±10
+0.8
+0.7
13
+1.5
T
= +25°C
T
= +25, –55, 125°C
= +15V, V = –15V
T
= +25°C
A
A
A
12
11
10
9
V
V
= +15V, V = –15V
V
V
V
V
V
V
= +5V, V = 0V
DD
SS
DD
SS
DD
SS
+1.0
+0.5
+0.6
+0.5
= –10V
= +10V
= +2.5V
VREFLO
VREFHI
VREFHI
= –10V
= 0V
VREFLO
VREFLO
+0.4
+0.3
+0.2
0
–0.5
–1.0
–1.5
+0.1
0
8
7
–0.1
–0.2
6
–0.3
–0.4
5
4
0
500 1000 1500 2000 2500 3000 3500 4000 4500
DIGITAL INPUT CODE
–7 –5 –3 –1 0
1
3
5
7
9
11 13
0
500 1000 1500 2000 2500 3000 3500 4000 4500
DIGITAL INPUT CODE
V
– V
VREFHI
Figure 13. INL vs. Code ±15/±10
Figure 11. Channel-to-Channel
Matching +5/+2.5
Figure 12. IDD vs. VVREFHI, All
DACs HIGH
6.5mV
CLR
+1.5
+1.0
+0.5
0
–250µV
LD
T
= +25°C
A
V
V
V
= +5V, V = –5V
DD
SS
= +2.5V
VREFHI
1.22mV
= –2.5V
VREFLO
1 LSB
0mV
0mV
1 LSB
–1.22mV
T
= +25°C
A
T
= +25°C
A
V
V
V
= +5V, V = –5V
DD
SS
V
V
V
= +15V, V = –15V
DD
SS
–0.5
–1.0
= +2.5V
VREFHI
= +10V
VREFHI
= –2.5V
VREFLO
= –10V
VREFLO
–10.25mV
–3.5mV
–4.9µs
0
500 1000 1500 2000 2500 3000 3500 4000
DIGITAL INPUT CODE
+5µs/DIV
+45.1µs
–4.9µs
5µs/DIV
45.1µs
tSETT 8µs
tSETT 8µs
Figure 14. IVREFHI vs. Code
Figure 15. Settling Time (+)(±5 V)
Figure 16. Settling Time (–)(±5 V)
REV. 0
–9–
DAC8420
+43.75mV
CLR
+31.25mV
+5V
LD
T
= +25°C
A
T
= +25°C
A
V
V
V
= +15V, V = –15V
DD
SS
V
V
V
= +15V, V = –15V
DD
SS
= +10V
VREFHI
= +10V
VREFHI
= –10V
VREFLO
= –10V
+1V
/DIV
VREFLO
0
4.88mV
1 LSB
0mV
T
= +25°C
A
V
V
V
= +5V, V = –5V
0mV
1 LSB
DD
SS
= +2.5V
VREFHI
–4.88mV
= –2.5V
VREFLO
–5V
–47.6µs
–18.75mV
–9.8µs
–6.25mV
20µs/DIV
V
µs
152.4µs
V
µs
+10µs/DIV
+90.2µs
–9.8µs
+10µs/DIV
+90.2µs
tSETT 13µs
tSETT 13µs
SR
= 1.65
SR = 1.17
FALL
RISE
Figure 17. Settling Time (+)(±15 V)
Figure 18. Settling Time (–)(±15 V)
Figure 19. Slew Rate (±5 V)
+25V
100
90
LD
80
70
CLR
+10
0
–10
–20
+5V
/DIV
0
60
50
40
–30
T
= +25°C
A
T
= +25°C
A
V
V
V
= +15V, V = –15V
30
20
10
0
DD
SS
DATA = 000
H
= 0 ± 100mV
T
= +25°C
VREFHI
A
V
V
V
= +15V ±1V, V = –15V
SS
DD
= –10V
V
V
= +15V, V = –15V
VREFLO
DD
SS
= +10V
VREFHI
ALL BITS HIGH 200mV p-p
= +10V, V
= –10V
VREFHI
VREFLO
= –10V
VREFLO
–25V
–33.6µs
10
100
1k
10k
100k
1M
20µs/DIV
166.4µs
10
100
1k
10k
100k
1M
10M
V
µs
V
µs
FREQUENCY – Hz
FREQUENCY – Hz
SR
RISE
= 1.9
SR
= 2.02
FALL
Figure 22. PSRR vs. Frequency
Figure 21. Small-Signal Response
Figure 20. Slew Rate (±15 V)
10
8
6
I
DD
VOUTA THROUGH VOUTD
4
2
T = +25°C
A
V
V
V
V
= +15V
= –15V
DD
SS
= +10V
= –10V
VREFHI
V
V
V
V
= +15V
= –15V
6
DD
SS
T
= +25°C
VREFLO
A
0
DATA = 800
V
V
V
V
= +15V
= –15V
= +10V
= –10V
H
DD
SS
VREFHI
4
2
VREFLO
= +10V
ALL DACS HIGH (FULL SCALE)
VREFHI
–2
= –10V
VREFLO
DATA = FFF OR 000
H
H
–4
–6
I
SS
0
10
100
1k
10k
–75
0
75
150
TEMPERATURE – °C
5V/DIV
LOAD RESISTANCE – Ω
Figure 24. DAC Output Current vs.
VOUTX
Figure 23. Power Supply Current
vs. Temperature
Figure 25. Output Swing vs.
Load Resistance
–10–
REV. 0
DAC8420
VREFHI Input Requirements
The DAC8420 should have ample supply bypassing, located as
close to the package as possible. Figure 26 shows the recom-
mended capacitor values of 10 µF in parallel with 0.1 µF. The
0.1 µF cap should have low “Effective Series Resistance” (ESR)
and “Effective Series Inductance” (ESI), such as the common
ceramic types, which provide a low impedance path to ground
at high frequencies to handle transient currents due to internal
logic switching. In order to preserve the specified analog perfor-
mance of the device, the supply should be as noise free as pos-
sible. In the case of 5 V only systems it is desirable to use the
same 5 V supply for both the analog circuitry and the digital
portion of the circuit. Unfortunately, the typical 5 V supply is
extremely noisy due to the fast edge rates of the popular CMOS
logic families which induce large inductive voltage spikes, and
busy microcontroller or microprocessor busses which commonly
have large current spikes during bus activity. However, by prop-
erly filtering the supply as shown in Figure 27, the digital 5 V
supply can be used. The inductors and capacitors generate a fil-
ter that not only rejects noise due to the digital circuitry, but
also filters out the lower frequency noise of switch mode power
supplies. The analog supply should be connected as close as
possible to the origin of the digital supply to minimize noise
pickup from the digital section.
The DAC8420 utilizes a unique, patented DAC switch driver
circuit which compensates for different supply, reference volt-
age, and digital code inputs. This ensures that all DAC ladder
switches are always biased equally, ensuring excellent linearity
under all conditions. Thus, as indicated in the specifications,
the VREFHI input of the DAC8420 will require both sourcing
and sinking current capability from the reference voltage source.
Many positive voltage references are intended as current sources
only, and offer little sinking capability. The user should consider
references such as the AD584, AD586, AD587, AD588, AD780,
and REF43 in this application.
APPLICATIONS
Power Supply Bypassing and Grounding
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The DAC8420 has a single ground pin
that is internally connected to the digital section as the logic
reference level. The first thought may be to connect this pin to
the digital ground; however, in large systems the digital ground
is often noisy because of the switching currents of other digital
circuitry. Any noise that is introduced at the ground pin could
couple into the analog output. Thus, to avoid error causing
digital noise in the sensitive analog circuitry, the ground pin
should be connected to the system analog ground. The ground
path (circuit board trace) should be as wide as possible to re-
duce any effects of parasitic inductance and ohmic drops. A
ground plane is recommended if possible. The noise immunity
of the onboard digital circuitry, typically in the hundreds of mil-
livolts, is well able to reject the common-mode noise typically
seen between system analog and digital grounds. Finally, the
analog and digital ground should be connected together at a
single point in the system to provide a common reference.
This is preferably done at the power supply.
FERRITE BEADS:
2 TURNS, FAIR-RITE
#2677006301
+5V
TTL/CMOS
LOGIC
CIRCUITS
100µF
ELECT.
10–22µF
TANT.
0.1µF
CER.
+5V
RETURN
+5V
POWER SUPPLY
Good grounding practice is essential to maintaining analog
performance in the surrounding analog support circuitry as well.
With two reference inputs, and four analog outputs capable of
moderate bandwidth and output current, there is a significant
potential for ground loops. Again, a ground plane is recom-
mended as the most effective solution to minimizing errors due
to noise and ground offsets.
Figure 27. Single-Supply Analog Supply Filter
Analog Outputs
The DAC8420 features buffered analog voltage outputs capable
of sourcing and sinking up to 5 mA when operating from ±15 V
supplies, eliminating the need for external buffer amplifiers in
most applications while maintaining specified accuracy over the
rated operating conditions. The buffered outputs are simply an
op amp connected as a voltage follower, and thus have output
characteristics very similar to the typical operational amplifier.
These amplifiers are short-circuit protected. The designer
should verify that the output load meets the capabilities of the
device, in terms of both output current and load capacitance.
The DAC8420 is stable with capacitive loads up to 2 nF typical.
However, any capacitive load will increase the settling time, and
should be minimized if speed is a concern.
1
+V
S
VDD
10µF
0.1µF
The output stage includes a p-channel MOSFET to pull the
output voltage down to the negative supply. This is very impor-
tant in single supply systems, where VREFLO usually has the
same potential as the negative supply. With no load, the
zero-scale output voltage in these applications will be less than
500 µV typically, or less than 1 LSB when VVREFHI = 2.5 V.
However, when sinking current this voltage does increase
because of the finite impedance of the output stage. The effec-
tive value of the pull-down resistor in the output stage is
typically 320 Ω. With a 100 kΩ resistor connected to +5 V, the
resulting zero-scale output voltage is 16 mV. Thus, the best
8
9
–V
VSS
S
GND
10µF
0.1µF
10µF = TANTALUM
0.1µF = CERAMIC
Figure 26. Recommended Supply Bypassing Scheme
REV. 0
–11–
DAC8420
single supply operation is obtained with the output load
connected to ground, so the output stage does not have to sink
current.
DACs to synthesize symmetric bipolar wave forms, which
requires an accurate, low drift bipolar reference. The AD588
provides both voltages and needs no external components. Ad-
ditionally, the part is trimmed in production for 12-bit accuracy
over the full temperature range without user calibration. Per-
forming a Clear with the reset select CLSEL HIGH allows the
user to easily reset the DAC outputs to midscale, or zero volts in
these applications.
Like all amplifiers, the DAC8420 output buffers do generate
voltage noise, 52 nV/√Hz typically. This is easily reduced by
adding a simple RC low-pass filter on each output.
Reference Configuration
The two reference inputs of the DAC8420 allow a great deal of
flexibility in circuit design. The user must take care, however, to
observe the minimum voltage input levels on VREFHI and
VREFLO to maintain the accuracy shown in the data sheet.
These input voltages can be set anywhere across a wide range
within the supplies, but must be a minimum of 2.5 V apart in
any case. See Figure 1. A wide output voltage range can be
obtained with ±5 V references, which can be provided by the
AD588 as shown in Figure 28. Many applications utilize the
When driving the reference inputs VREFHI and VREFLO, it is
important to note that VREFHI both sinks and sources current,
and that the input currents of both are code dependent. Many
voltage reference products have limited current sinking capabil-
ity and must be buffered with an amplifier to drive VREFHI, in
order to maintain overall system accuracy. The input VREFLO,
however, has no such requirement.
+15V SUPPLY
1µF
+5V
VREFHI
0.1µF
6
7
4
3
1
5
DAC-8420
R
+5V
–5V
DAC A
VOUTA
VOUTB
B
7
6
3
2
A3
A4
1
A1
AD588
14
15
R4
R5
DAC B
DAC C
R1
R2
VOUTC
VOUTD
+15V
SUPPLY
2
+V
DIGITAL
CONTROL
S
R3
R6
0.1µF
0.1µF
A2
DAC D
4
SYSTEM
GROUND
–V 16
S
5
9
10
12
8
11
13
10 11 12 14 15 16
DIGITAL INPUTS
9
8
–15V
SUPPLY
VREFLO
–5V
GND
0.1µF
–15V SUPPLY
Figure 28. ±10 V Bipolar Reference Configuration Using the AD588
–12–
REV. 0
DAC8420
One opto-isolated line (LD) can be eliminated from this circuit
by adding an inexpensive 4-bit TTL Counter to generate the
Load pulse for the DAC8420 after 16 clock cycles. The counter
is used to count of the number of clock cycles loading serial data
to the DAC8420. After all 16 bits have been clocked into the
converter, the counter resets, and a load pulse is generated on
clock 17. In either circuit, the DAC8420’s serial interface pro-
vides a simple, low cost method of isolating the digital control.
For a single 5 V supply, VVREFHI is limited to at most 2.5 V, and
must always be at least 2.5 V less than the positive supply to
ensure linearity of the device. For these applications, the REF43
is an excellent low drift 2.5 V reference that consumes only
450 µA (max). It works well with the DAC8420 in a single 5 V
system as shown in Figure 29.
+5V SUPPLY
REF-43
2
VIN
+5V SUPPLY
HIGH VOLTAGE
ISOLATION
0.1µF
+5V
+5V
2.5V
REG
GND VOUT
4
6
POWER
0.1µF
VREFHI
5
1
+5V
+5V
REF-43
10kΩ
2
4
VIN
DAC A
VOUTA
VOUTB
VOUTC
VOUTD
7
DAC-8420
+5V
VOUT
GND
6
LD
2.5V
0.1µF
6
3
2
DAC B
DAC C
+5V
5
1
10kΩ
VREFHI
CLR
VDD
15
16
14
12
11
10
10kΩ
VOUTA
7
6
3
1µF
SCLK
DIGITAL
CONTROL
CLSEL
LD
VOUTB
VOUTC
VOUTD
DAC D
4
DAC-8420
+5V
CS
CLK
10 11 12 14 15 16
DIGITAL INPUTS
9
8
10kΩ
2
GND
VREFLO
SDI
SDI
GND
9
VREFLO VSS
4
8
Figure 29. +5 V Single Supply Operation Using REF43
Isolated Digital Interface
Because the DAC8420 is ideal for generating accurate voltages
in process control and industrial applications, due to noise,
safety requirements, or distance, it may be necessary to isolate it
from the central controller. This can be easily achieved by using
opto-isolators, which are commonly used to provide electrical
isolation in excess of 3 kV. Figure 30 shows a simple 3-wire
interface scheme to control the clock, data, and load pulse. For
normal operation, CS is tied permanently LOW so that the
DAC8420 is always selected. The resistor and capacitor on the
CLR pin provide a power-on reset with 10 ms time constant. The
three opto-isolators are used for the SDI, CLK, and LD lines.
Figure 30. Opto-lsolated 3-Wire Interface
Dual Window Comparator
Often a comparator is needed to signal an out-of-range warning.
Combining the DAC8420 with a quad comparator such as the
CMP04 provides a simple dual window comparator with adjust-
able trip points as shown in Figure 31. This circuit can be
operated with either a dual or a single supply. For the A input
channel, DAC B sets the low trip point and DAC A sets the up-
per trip point. The CMP04 has open-collector outputs that are
connected together in “Wired-OR” configuration to generate an
out-of-range signal. For example, when VINA goes below the
trip point set by DAC B, comparator C2 pulls the output down,
turning the red LED on. The output can also be used as a logic
signal for further processing.
REV. 0
–13–
DAC8420
+5V SUPPLY
VINA
+5V
REF-43
+5V SUPPLY
2
4
VIN
0.1µF
0.1µF
2.5V
6
+5V
V
GND
OUT
0.1µF
VREFHI
3
604Ω
5
1
CMP-04
VOUTA
VOUTB
RED LED
5
4
7
DAC A
DAC B
DAC-8420
2
OUT A
C1
C2
+5V
7
6
6
3
2
604Ω
1
VOUTC
VOUTD
RED LED
9
8
DAC C
OUT B
14
13
C3
DIGITAL
CONTROL
11
10
DAC D
4
C4
12
10 11 12 14 15 16
DIGITAL INPUTS
9
8
GND
VREFLO
VSS
VINB
Figure 31. Dual Programmable Window Comparator
MC68HC11 Microcontroller Interfacing
For correct operation, the 68HC11 should be configured such
that its CPOL bit and CPHA bit are both set to 1. In this con-
figuration, serial data on MOSI of the 68HC11 is valid on the
rising edge of the clock, which is the required timing for the
DAC8420 Data is transmitted in 8-bit bytes (MSB first), with
only eight rising clock edges occurring in the transmit cycle. To
load data to the DAC8420’s input register, PC0 is taken low
and held low during the entire loading cycle. The first 8 bits are
shifted in address first, immediately followed by another 8 bits
in the second least-significant byte to load the complete 16-bit
word. At the end of the second byte load, PC0 is then taken
high. To prevent an additional advancing of the internal shift
register, SCK must already be asserted before PC0 is taken
high. To transfer the contents of the input shift register to the
DAC register, PD5 is then taken low, asserting the LD input of
the DAC and completing the loading process. PD5 should re-
turn high before the next load cycle begins. The DAC8420’s
CLR input, controlled by the output PC1, provides an asyn-
chronous clear function.
Figure 32 shows a serial interface between the DAC8420 and
the MC68HC11 8-bit microcontroller. The SCK output of the
68HC11 drives the CLK input of the DAC, and the MOSI port
outputs the serial data to load into the SDI input of the DAC.
The port lines PD5, PC0, PC1, and PC2 provide the controls to
the DAC as shown.
PC2
PC1
PC0
CLSEL
CLR
CS
MC68HC11*
DAC-8420*
(PD5) SS
SCK
LD
CLK
SDI
MOSI
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 32. MC68HC11 Microcontroller Interface
–14–
REV. 0
DAC8420
DAC8420 to M68HC11 Interface Assembly Program
*
M68HC11 Register Definitions
* Initialize SPI Interface
LDAA #$5F
PORTC EQU $1003 Port C control register
*
“0,0,0,0;0,CLSEL,CLR,CS”
STAA SPCR SPI is Master,CPHA=1,CPOL=1,Clk rate=E/32
* Call update subroutine
DDRC EQU $1007 Port C data direction
PORTD EQU $1008 Port D data register
*
BSR UPDATE Xfer 2 8-bit words to DAC-8420
JMP $E000 Restart BUFFALO
“0,0,LD,SCLK;SDI,0,0,0”
DDRD EQU $1009 Port D data direction
SPCR EQU $1028 SPI control register
* Subroutine UPDATE
UPDATE PSHX
PSHY
Save registers X, Y, and A
*
“SPIE,SPE,DWOM,MSTR;CPOL,CPHA,SPR1,SPR0”
SPSR EQU $1029 SPI status register
“SPIF,WCOL,0,MODF;0,0,0,0”
PSHA
*
* Enter Contents of SDI1 Data Register (DAC# and 4 MSBs)
LDAA #$80 1,0,0,0;0,0,0,0
STAA SDI1 SDI1 is set to 80 (Hex)
* Enter Contents of SDI2 Data Register
LDAA #$00 0,0,0,0;0,0,0,0
STAA SDI2 SDI2 is set to 00 (Hex)
LDX #SDI1 Stack pointer at 1st byte to send via SDI
LDY #$1000 Stack pointer at on-chip registers
* Clear DAC output to zero
SPDR EQU $102A SPI data register; Read-Buffer; Write-Shifter
*
* SDI RAM variables: SDI1 is encoded from 0 (Hex) to CF (Hex)
* To select: DAC A – Set SDI1 to $0X
DAC B – Set SDI1 to $4X
DAC C – Set SDI1 to $8X
DAC D – Set SDI1 to $CX
SDI2 is encoded from 00 (Hex) to FF (Hex)
*
DAC requires two 8-bit loads – Address + 12 bits
BCLR PORTC,Y $02 Assert CLR
SDI1 EQU $00 SDI packed byte 1 “A1,A0,0,0;MSB,DB10,DB9,DB8”
SDI2 EQU $01 SDI packed byte 2
BSET PORTC,Y $02 Deassert CLR
* Get DAC ready for data input
BCLR PORTC,Y $01 Assert CS
“DB7,DB6,DB5,DB4;DB3,DB2,DB1,DB0”
* Main Program
TFRLP LDAA 0,X Get a byte to transfer via SPI
STAA SPDR Write SDI data reg to start xfer
WAIT LDAA SPSR Loop to wait for SPIF
BPL WAIT SPIF is the MSB of SPSR
ORG $C000 Start of user’s RAM in EVB
INIT LDS #$CFFF Top of C page RAM
* Initialize Port C Outputs
*
(when SPIF is set, SPSR is negated)
INX
Increment counter to next byte for xfer
LDAA #$07 0,0,0,0;0,1,1,1
CPX #SDI2+ 1 Are we done yet ?
BNE TFRLP If not, xfer the second byte
*
*
*
CLSEL-Hi, CLR-Hi, CS-Hi
To reset DAC to ZERO-SCALE, set CLSEL-Lo ($03)
To reset DAC to MID-SCALE, set CLSEL-Hi ($07)
STAA PORTC Initialize Port C Outputs
LDAA #$07 0,0,0,0;0,1,1,1
STAA DDRC CLSEL, CLR, and CS are now enabled as outputs
* Update DAC output with contents of DAC register
BCLR PORTD,Y 520 Assert LD
BSET PORTD,Y $20 Latch DAC register
BSET PORTC,Y $01 De-assert CS
PULA When done, restore registers X, Y & A
PULY
* Initialize Port D Outputs
LDAA #$30 0,0,1,1;0,0,0,0
PULX
*
LD-Hi,SCLK-Hi,SDI-Lo
RTS
** Return to Main Program **
STAA PORTD Initialize Port D Outputs
LDAA #$38 0,0,1,1;1,0,0,0
STAA DDRD LD,SCLK, and SDI are now enabled as outputs
REV. 0
–15–
DAC8420
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Pin Epoxy DIP
(P Suffix)
16
1
9
0.280 (7.11)
0.240 (6.10)
PIN 1
8
0.325 (8.25)
0.840 (21.33)
0.745 (18.93)
0.300 (7.62)
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.195 (4.95)
0.115 (2.93)
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
16-Pin Wide-Body SOL
(SOL)
16
9
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
PIN 1
8
1
0.1043 (2.65)
0.4133 (10.50)
0.3977 (10.00)
0.0926 (2.35)
0.0291 (0.74)
x 45°
0.0098 (0.25)
0.0500 (1.27)
0.0157 (0.40)
8
0
°
°
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
0.0125 (0.32)
0.0091 (0.23)
16-Pin Cerdip
(Q Suffix)
0.080 (2.03) MAX
0.005 (0.13) MIN
9
16
0.310 (7.87)
PIN 1
0.220 (5.59)
1
8
0.320 (8.13)
0.290 (7.37)
0.840 (21.34) MAX
0.060 (1.52)
0.015 (0.38)
0.200
(5.08)
MAX
0.150
(3.81)
MIN
0.015 (0.38)
0.008 (0.20)
0.200 (5.08)
0.125 (3.18)
15°
0°
0.070 (1.78)
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
0.100
(2.54)
BSC
0.030 (0.76)
–16–
REV. 0
相关型号：
DAC8420FSZ
QUAD, SERIAL INPUT LOADING, 8 us SETTLING TIME, 12-BIT DAC, PDSO16, ROHS COMPLIANT, MS-013AA, SOIC-16
ROCHESTER
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