ADuM1200WTRZ-RL7 [ADI]
Dual-Channel Digital Isolators; 双通道数字隔离器
| 型号： | ADuM1200WTRZ-RL7 |
| 厂家： | 
ADI |
| 描述： | Dual-Channel Digital Isolators |
| 文件： | 总28页 (文件大小：444K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual-Channel Digital Isolators
ADuM1200/ADuM1201
current transfer ratios, nonlinear transfer functions, and temper-
ature and lifetime effects are eliminated with the simple iCoupler
digital interfaces and stable performance characteristics. The need
for external drivers and other discrete components is eliminated
with these iCoupler products. Furthermore, iCoupler devices
consume one-tenth to one-sixth the power of optocouplers at
comparable signal data rates.
Data Sheet
FEATURES
Narrow body, RoHS-compliant, SOIC 8-lead package
Low power operation
5 V operation
1.1 mA per channel maximum @ 0 Mbps to 2 Mbps
3.7 mA per channel maximum @ 10 Mbps
8.2 mA per channel maximum @ 25 Mbps
3 V operation
The ADuM120x isolators provide two independent isolation
channels in a variety of channel configurations and data rates
(see the Ordering Guide). Both parts operate with the supply
voltage on either side ranging from 2.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling a
voltage translation functionality across the isolation barrier.
In addition, the ADuM120x provide low pulse width distortion
(<3 ns for CR grade) and tight channel-to-channel matching
(<3 ns for CR grade). Unlike other optocoupler alternatives,
the ADuM120x isolators have a patented refresh feature that
ensures dc correctness in the absence of input logic transitions
and during power-up/power-down conditions.
0.8 mA per channel maximum @ 0 Mbps to 2 Mbps
2.2 mA per channel maximum @ 10 Mbps
4.8 mA per channel maximum @ 25 Mbps
Bidirectional communication
3 V/5 V level translation
High temperature operation: 125°C
High data rate: dc to 25 Mbps (NRZ)
Precise timing characteristics
3 ns maximum pulse width distortion
3 ns maximum channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Qualified for automotive applications
Safety and regulatory approvals
UL recognition
The ADuM1200W and ADuM1201W are automotive grade
versions qualified for 125°C operation. See the Automotive
Products section for more information.
2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE Certificate of Conformity
FUNCTIONAL BLOCK DIAGRAMS
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
1
2
3
4
8
7
6
5
V
V
V
V
V
IORM = 560 V peak
DD1
DD2
OA
OB
ENCODE
ENCODE
DECODE
DECODE
V
V
IA
APPLICATIONS
Size-critical multichannel isolation
IB
SPI interface/data converter isolation
RS-232/RS-422/RS-485 transceiver isolation
Digital field bus isolation
GND
GND
2
1
Figure 1. ADuM1200 Functional Block Diagram
Hybrid electric vehicles, battery monitor, and motor drive
GENERAL DESCRIPTION
1
2
3
4
8
7
6
5
V
V
V
V
DD1
DD2
The ADuM120x1 are dual-channel digital isolators based on
the Analog Devices, Inc., iCoupler® technology. Combining
high speed CMOS and monolithic transformer technologies,
these isolation components provide outstanding performance
characteristics superior to alternatives, such as optocouplers.
DECODE
ENCODE
ENCODE
DECODE
V
OA
IA
V
IB
OB
GND
GND
1
2
Figure 2. ADuM1201 Functional Block Diagram
By avoiding the use of LEDs and photodiodes, iCoupler devices
remove the design difficulties commonly associated with opto-
couplers. The typical optocoupler concerns regarding uncertain
1
Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.
Rev. I
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved.
ADuM1200/ADuM1201
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
Insulation Characteristics ......................................................... 20
Recommended Operating Conditions .................................... 20
Absolute Maximum Ratings ......................................................... 21
ESD Caution................................................................................ 21
Pin Configurations and Function Descriptions......................... 22
Typical Performance Characteristics ........................................... 23
Applications Information.............................................................. 24
PCB Layout ................................................................................. 24
Propagation Delay-Related Parameters................................... 24
DC Correctness and Magnetic Field Immunity........................... 24
Power Consumption .................................................................. 25
Insulation Lifetime..................................................................... 26
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
Automotive Products................................................................. 28
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Electrical Characteristics—5 V, 105°C Operation ................... 4
Electrical Characteristics—3 V, 105°C Operation ................... 6
Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V,
105°C Operation........................................................................... 8
Electrical Characteristics—5 V, 125°C Operation ................. 11
Electrical Characteristics—3 V, 125°C Operation ................. 13
Electrical Characteristics—Mixed 5 V/3 V, 125°C Operation 15
Electrical Characteristics—Mixed 3 V/5 V, 125°C Operation 17
Package Characteristics ............................................................. 19
Regulatory Information............................................................. 19
Insulation and Safety-Related Specifications.......................... 19
Rev. I | Page 2 of 28
Data Sheet
ADuM1200/ADuM1201
REVISION HISTORY
8/07—Rev. C to Rev. D
3/12—Rev. H to Rev. I
Updated VDE Certification Throughout.......................................1
Changes to Features, Note 1, Figure 1, and Figure 2....................1
Changes to Table 3 ............................................................................7
Changes to Regulatory Information Section...............................10
Added Table 10................................................................................12
Added Insulation Lifetime Section...............................................16
Updated Outline Dimensions........................................................18
Changes to Ordering Guide...........................................................18
Created Hyperlink for Safety and Regulatory Approvals
Entry in Features Section .................................................................1
Change to General Description Section.........................................1
Change to PCB Layout Section .....................................................24
Moved Automotive Products Section...........................................28
1/09—Rev. G to Rev. H
Changes to Table 5, Switching Specifications Parameter...........13
Changes to Table 6, Switching Specifications Parameter...........15
Changes to Table 7, Switching Specifications Parameter...........17
2/06—Rev. B to Rev. C
Updated Format ................................................................. Universal
Added Note 1.....................................................................................1
Changes to Absolute Maximum Ratings......................................12
Changes to DC Correctness and Magnetic Field
9/08—Rev. F to Rev. G
Changes to Table 9 ..........................................................................19
Changes to Table 13 ........................................................................21
Changes to Ordering Guide...........................................................27
Immunity Section............................................................................15
9/04—Rev. A to Rev. B
Changes to Table 5 ..........................................................................10
3/08—Rev. E to Rev. F
Changes to Features Section ............................................................1
Changes to Applications Section.....................................................1
Added Table 4 ..................................................................................11
Added Table 5 ..................................................................................13
Added Table 6 ..................................................................................15
Added Table 7 ..................................................................................17
Changes to Table 12 ........................................................................20
Changes to Table 13 ........................................................................21
Added Automotive Products Section ...........................................26
Changes to Ordering Guide...........................................................27
6/04—Rev. 0 to Rev. A
Changes to Format............................................................. Universal
Changes to General Description.....................................................1
Changes to Electrical Characteristics—5 V Operation................3
Changes to Electrical Characteristics—3 V Operation................5
Changes to Electrical Characteristics—Mixed 5 V/3 V or
3 V/5 V Operation ............................................................................7
4/04—Revision 0: Initial Version
11/07—Rev. D to Rev. E
Changes to Note 1 .............................................................................1
Added ADuM120xAR Change vs. Temperature Parameter .......3
Added ADuM120xAR Change vs. Temperature Parameter .......5
Added ADuM120xAR Change vs. Temperature Parameter .......8
Rev. I | Page 3 of 28
ADuM1200/ADuM1201
Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V, 105°C OPERATION
All voltages are relative to their respective ground; 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply
over the entire recommended operating range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V; this
does not apply to the ADuM1200W and ADuM1201W automotive grade products.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
ADuM1200 Total Supply Current, Two Channels1
DC to 2 Mbps
IDDI (Q)
0.50
0.19
0.60
0.25
mA
mA
IDDO (Q)
VDD1 Supply Current
IDD1 (Q)
IDD2 (Q)
1.1
0.5
1.4
0.8
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
VDD2 Supply Current
10 Mbps (BR and CR Grades Only)
VDD1 Supply Current
IDD1 (10)
IDD2 (10)
4.3
1.3
5.5
2.0
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
VDD2 Supply Current
25 Mbps (CR Grade Only)
VDD1 Supply Current
IDD1 (25)
IDD2 (25)
10
13
mA
mA
12.5 MHz logic signal freq.
12.5 MHz logic signal freq.
VDD2 Supply Current
2.8
3.4
ADuM1201 Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
IDD2 (Q)
0.8
0.8
1.1
1.1
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
VDD2 Supply Current
10 Mbps (BR and CR Grades Only)
VDD1 Supply Current
IDD1 (10)
IDD2 (10)
2.8
2.8
3.5
3.5
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
VDD2 Supply Current
25 Mbps (CR Grade Only)
VDD1 Supply Current
IDD1 (25)
IDD2 (25)
6.3
6.3
8.0
8.0
mA
mA
12.5 MHz logic signal freq.
12.5 MHz logic signal freq.
VDD2 Supply Current
For All Models
Input Currents
IIA, IIB
VIH
−10
+0.01
+10
μA
V
0 V ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
0.7 (VDD1 or VDD2)
VIL
0.3 (VDD1 or VDD2
)
V
VOAH, VOBH
(VDD1 or VDD2) − 0.1
(VDD1 or VDD2) − 0.5
5.0
4.8
0.0
0.04
0.2
V
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 400 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
V
Logic Low Output Voltages
VOAL, VOBL
0.1
0.1
0.4
V
V
V
SWITCHING SPECIFICATIONS
ADuM120xAR
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
Maximum Data Rate3
PW
1000
ns
1
Mbps
ns
Propagation Delay4
tPHL, tPLH
PWD
50
150
40
4
ns
Pulse Width Distortion, |tPLH − tPHL
|
Change vs. Temperature
Propagation Delay Skew5
11
10
ps/°C
ns
tPSK
100
50
Channel-to-Channel Matching6
tPSKCD/tPSKOD
tR/tF
ns
Output Rise/Fall Time (10% to 90%)
ns
Rev. I | Page 4 of 28
Data Sheet
ADuM1200/ADuM1201
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
ADuM120xBR
Minimum Pulse Width2
PW
100
ns
Maximum Data Rate3
Propagation Delay4
10
20
Mbps
ns
t
PHL, tPLH
50
3
4
PWD
ns
Pulse Width Distortion, |tPLH − tPHL
|
Change vs. Temperature
5
ps/°C
ns
Propagation Delay Skew5
Channel-to-Channel Matching
Codirectional Channels6
Opposing Directional Channels6
Output Rise/Fall Time (10% to 90%)
ADuM120xCR
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
tPSK
15
3
tPSKCD
tPSKOD
tR/tF
ns
ns
ns
15
40
2.5
PW
20
50
ns
25
20
Mbps
ns
t
PHL, tPLH
45
3
4
PWD
ns
Pulse Width Distortion, |tPLH − tPHL
|
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching
Codirectional Channels6
Opposing Directional Channels6
Output Rise/Fall Time (10% to 90%)
For All Models
5
ps/°C
ns
tPSK
15
3
ns
tPSKCD
tPSKOD
tR/tF
15
ns
ns
2.5
35
Common-Mode Transient Immunity
Logic High Output7
|CMH|
25
25
kV/μs
VIx = VDD1 or VDD2, VCM
1000 V, transient
=
magnitude = 800 V
Logic Low Output7
|CML|
fr
35
kV/μs
Mbps
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate
Dynamic Supply Current per Channel8
1.2
Input
IDDI (D)
0.19
0.05
mA/
Mbps
Output
IDDO (D)
mA/
Mbps
1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11
for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for
information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on
calculating per-channel supply current for a given data rate.
Rev. I | Page 5 of 28
ADuM1200/ADuM1201
Data Sheet
ELECTRICAL CHARACTERISTICS—3 V, 105°C OPERATION
All voltages are relative to their respective ground; 2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply
over the entire recommended operating range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V; this
does not apply to ADuM1200W and ADuM1201W automotive grade products.
Table 2.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
ADuM1200 Total Supply Current, Two Channels1
DC to 2 Mbps
IDDI (Q)
0.26
0.11
0.35
0.20
mA
mA
IDDO (Q)
VDD1 Supply Current
IDD1 (Q)
IDD2 (Q)
0.6
0.2
1.0
0.6
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
VDD2 Supply Current
10 Mbps (BR and CR Grades Only)
VDD1 Supply Current
IDD1 (10)
IDD2 (10)
2.2
0.7
3.4
1.1
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
VDD2 Supply Current
25 Mbps (CR Grade Only)
VDD1 Supply Current
IDD1 (25)
IDD2 (25)
5.2
1.5
7.7
2.0
mA
mA
12.5 MHz logic signal freq.
12.5 MHz logic signal freq.
VDD2 Supply Current
ADuM1201 Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
IDD2 (Q)
0.4
0.4
0.8
0.8
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
VDD2 Supply Current
10 Mbps (BR and CR Grades Only)
VDD1 Supply Current
IDD1 (10)
IDD2 (10)
1.5
1.5
2.2
2.2
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
VDD2 Supply Current
25 Mbps (CR Grade Only)
VDD1 Supply Current
IDD1 (25)
IDD2 (25)
3.4
3.4
4.8
4.8
mA
mA
12.5 MHz logic signal freq.
12.5 MHz logic signal freq.
VDD2 Supply Current
For All Models
Input Currents
IIA, IIB
VIH
−10
+0.01
+10
μA
V
0 V ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
0.7 (VDD1 or VDD2)
VIL
0.3 (VDD1 or VDD2)
VOAH, VOBH
(VDD1 or VDD2) − 0.1 3.0
(VDD1 or VDD2) − 0.5 2.8
0.0
V
V
V
V
V
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 400 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
Logic Low Output Voltages
VOAL, VOBL
0.1
0.1
0.4
0.04
0.2
SWITCHING SPECIFICATIONS
ADuM120xAR
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
Maximum Data Rate3
PW
1000
ns
1
Mbps
ns
Propagation Delay4
tPHL, tPLH
PWD
50
150
40
4
ns
Pulse Width Distortion, |tPLH − tPHL
|
Change vs. Temperature
11
10
ps/°C
ns
Propagation Delay Skew5
tPSK
100
50
Channel-to-Channel Matching6
tPSKCD/tPSKOD
tR/tF
ns
Output Rise/Fall Time (10% to 90%)
ns
Rev. I | Page 6 of 28
Data Sheet
ADuM1200/ADuM1201
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
ADuM120xBR
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
PW
100
ns
Maximum Data Rate3
Propagation Delay4
10
20
Mbps
ns
t
PHL, tPLH
60
3
4
PWD
ns
Pulse Width Distortion, |tPLH − tPHL
|
Change vs. Temperature
5
ps/°C
ns
Propagation Delay Skew5
Channel-to-Channel Matching
Codirectional Channels6
Opposing Directional Channels6
Output Rise/Fall Time (10% to 90%)
ADuM120xCR
tPSK
22
tPSKCD
tPSKOD
tR/tF
3
ns
ns
ns
22
3.0
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
PW
20
50
40
ns
25
20
Mbps
ns
tPHL, tPLH
55
3
4
PWD
ns
Pulse Width Distortion, |tPLH − tPHL
|
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching
Codirectional Channels6
Opposing Directional Channels6
Output Rise/Fall Time (10% to 90%)
For All Models
5
ps/°C
ns
tPSK
16
tPSKCD
tPSKOD
tR/tF
3
ns
ns
ns
16
3.0
Common-Mode Transient Immunity
Logic High Output7
|CMH|
|CML|
fr
25
25
35
35
1.1
kV/μs
kV/μs
Mbps
VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
Logic Low Output7
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate
Dynamic Supply Current per Channel8
Input
IDDI (D)
0.10
0.03
mA/
Mbps
Output
IDDO (D)
mA/
Mbps
1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11
for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for
information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on
calculating per-channel supply current for a given data rate.
Rev. I | Page 7 of 28
ADuM1200/ADuM1201
Data Sheet
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V, 105°C OPERATION
All voltages are relative to their respective ground; 5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V. 3 V/5 V operation:
2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operating range,
unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5.0 V; or VDD1 = 5.0 V, VDD2 = 3.0 V; this does not
apply to ADuM1200W and ADuM1201W automotive grade products.
Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel,
Quiescent
IDDI (Q)
5 V/3 V Operation
3 V/5 V Operation
0.50
0.26
0.6
mA
mA
0.35
Output Supply Current per Channel,
Quiescent
IDDO (Q)
5 V/3 V Operation
3 V/5 V Operation
0.11
0.19
0.20
0.25
mA
mA
ADuM1200 Total Supply Current,
Two Channels1
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
10 Mbps (BR and CR Grades Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
25 Mbps (CR Grade Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD1 (Q)
1.1
0.6
1.4
1.0
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
IDD2 (Q)
0.2
0.5
0.6
0.8
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
IDD1 (10)
4.3
2.2
5.5
3.4
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
IDD2 (10)
0.7
1.3
1.1
2.0
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
IDD1 (25)
10
13
mA
mA
12.5 MHz logic signal freq.
12.5 MHz logic signal freq.
5.2
7.7
IDD2 (25)
1.5
2.8
2.0
3.4
mA
mA
12.5 MHz logic signal freq.
12.5 MHz logic signal freq.
ADuM1201 Total Supply Current,
Two Channels1
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
10 Mbps (BR and CR Grades Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD1 (Q)
0.8
0.4
1.1
0.8
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
IDD2 (Q)
0.4
0.8
0.8
1.1
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
IDD1 (10)
2.8
1.5
3.5
2.2
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
IDD2 (10)
1.5
2.8
2.2
3.5
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
Rev. I | Page 8 of 28
Data Sheet
ADuM1200/ADuM1201
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
25 Mbps (CR Grade Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD1 (25)
6.3
3.4
8.0
4.8
mA
mA
12.5 MHz logic signal freq.
12.5 MHz logic signal freq.
IDD2 (25)
3.4
6.3
4.8
8.0
mA
mA
12.5 MHz logic signal freq.
12.5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB
VIH
−10
+0.01
+10
μA
V
0 V ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
0.7 (VDD1 or VDD2)
VIL
0.3 (VDD1 or VDD2
)
V
VOAH, VOBH
(VDD1 or VDD2) − 0.1 VDD1 or VDD2
V
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 400 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
(VDD1 or VDD2) − 0.5 (VDD1 or VDD2) − 0.2
V
Logic Low Output Voltages
VOAL, VOBL
0.0
0.1
0.1
0.4
V
0.04
0.2
V
V
SWITCHING SPECIFICATIONS
ADuM120xAR
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
PW
1000
ns
1
Mbps
ns
tPHL, tPLH
PWD
50
150
40
4
ns
Pulse Width Distortion, |tPLH − tPHL
|
Change vs. Temperature
11
10
ps/°C
ns
Propagation Delay Skew5
tPSK
50
50
Channel-to-Channel Matching6
tPSKCD/tPSKOD
tR/tF
ns
Output Rise/Fall Time (10% to 90%)
ADuM120xBR
ns
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
PW
100
ns
10
15
Mbps
ns
tPHL, tPLH
55
3
4
PWD
ns
Pulse Width Distortion, |tPLH − tPHL
|
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching
Codirectional Channels6
Opposing Directional Channels6
Output Rise/Fall Time (10% to 90%)
5 V/3 V Operation
5
ps/°C
ns
tPSK
22
tPSKCD
tPSKOD
tR/tF
3
ns
ns
22
3.0
2.5
ns
ns
3 V/5 V Operation
ADuM120xCR
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
PW
20
40
ns
25
20
50
5
Mbps
ns
tPHL, tPLH
50
3
4
PWD
ns
Pulse Width Distortion, |tPLH − tPHL
|
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching
Codirectional Channels6
Opposing Directional Channels6
Output Rise/Fall Time (10% to 90%)
5 V/3 V Operation
ps/°C
ns
tPSK
15
tPSKCD
tPSKOD
tR/tF
3
ns
ns
15
3.0
2.5
ns
ns
3 V/5 V Operation
Rev. I | Page 9 of 28
ADuM1200/ADuM1201
Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
For All Models
Common-Mode Transient Immunity
Logic High Output7
|CMH|
|CML|
fr
25
25
35
35
kV/μs
kV/μs
VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
Logic Low Output7
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate
5 V/3 V Operation
3 V/5 V Operation
1.2
1.1
Mbps
Mbps
Input Dynamic Supply Current
per Channel8
IDDI (D)
5 V/3 V Operation
0.19
0.10
mA/
Mbps
3 V/5 V Operation
mA/
Mbps
Output Dynamic Supply Current per
Channel8
IDDO (D)
5 V/3 V Operation
0.03
0.05
mA/
Mbps
3 V/5 V Operation
mA/
Mbps
1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11
for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for
information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on
calculating per-channel supply current for a given data rate.
Rev. I | Page 10 of 28
Data Sheet
ADuM1200/ADuM1201
ELECTRICAL CHARACTERISTICS—5 V, 125°C OPERATION
All voltages are relative to their respective ground; 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply
over the entire recommended operating range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V; this
applies to ADuM1200W and ADuM1201W automotive grade products.
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel,
Quiescent
IDDI (Q)
0.50
0.19
0.60
0.25
mA
mA
Output Supply Current per Channel,
Quiescent
IDDO (Q)
ADVM1200W, Total Supply Current,
Two Channels1
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (TRZ and URZ Grades Only)
VDD1 Supply Current
VDD2 Supply Current
25 Mbps (URZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.1
0.5
1.4
0.8
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
IDD1 (10)
IDD2 (10)
4.3
1.3
5.5
2.0
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
IDD1 (25)
IDD2 (25)
10
13
mA
mA
12.5 MHz logic signal freq.
12.5 MHz logic signal freq.
2.8
3.4
ADVM1201W, Total Supply Current,
Two Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
IDD2 (Q)
0.8
0.8
1.1
1.1
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
VDD2 Supply Current
10 Mbps (TRZ and URZ Grades Only)
VDD1 Supply Current
IDD1 (10)
IDD2 (10)
2.8
2.8
3.5
3.5
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
VDD2 Supply Current
25 Mbps (URZ Grade Only)
VDD1 Supply Current
IDD1 (25)
IDD2 (25)
6.3
6.3
8.0
8.0
mA
mA
12.5 MHz logic signal freq.
12.5 MHz logic signal freq.
VDD2 Supply Current
For All Models
Input Currents
IIA, IIB
VIH
−10
+0.01
+10
μA
V
0 7 ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
0.7 (VDD1 or VDD2)
VIL
0.3 (VDD1 or VDD2
)
V
VOAH, VOBH
(VDD1 or VDD2) − 0.1 5.0
(VDD1 or VDD2) − 0.5 4.8
0.0
V
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 400 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
V
Logic Low Output Voltages
VOAL, VOBL
0.1
0.1
0.4
V
0.04
V
0.2
V
SWITCHING SPECIFICATIONS
ADuM120xWSRZ
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
Maximum Data Rate3
PW
1000
ns
1
Mbps
ns
Propagation Delay4
tPHL, tPLH
PWD
20
150
40
4
ns
Pulse Width Distortion, |tPLH − tPHL
|
Propagation Delay Skew5
tPSK
100
50
ns
Channel-to-Channel Matching6
tPSKCD/tPSKOD
tR/tF
ns
Output Rise/Fall Time (10% to 90%)
2.5
ns
Rev. I | Page 11 of 28
ADuM1200/ADuM1201
Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
CL = 15 pF, CMOS signal levels
ADuM120xWTRZ
Minimum Pulse Width2
Maximum Data Rate3
PW
100
ns
10
20
Mbps
ns
Propagation Delay4
t
PHL, tPLH
50
3
4
PWD
ns
Pulse Width Distortion, |tPLH − tPHL
|
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching
Codirectional Channels6
Opposing Directional Channels6
Output Rise/Fall Time (10% to 90%)
ADuM120xWURZ
5
ps/°C
ns
tPSK
15
tPSKCD
tPSKOD
tR/tF
3
ns
ns
ns
15
2.5
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
PW
20
50
40
ns
25
20
Mbps
ns
t
PHL, tPLH
45
3
4
PWD
ns
Pulse Width Distortion, |tPLH − tPHL
|
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching
Codirectional Channels6
Opposing Directional Channels6
Output Rise/Fall Time (10% to 90%)
For All Models
5
ps/°C
ns
tPSK
15
tPSKCD
tPSKOD
tR/tF
3
ns
ns
ns
15
2.5
Common-Mode Transient Immunity
Logic High Output7
|CMH|
|CML|
fr
25
25
35
35
1.2
kV/μs
kV/μs
Mbps
VIx = VDD1, VDD2, VCM = 1000 V,
transient magnitude = 800 V
Logic Low Output7
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate
Dynamic Supply Current per Channel8
Input
IDDI (D)
0.19
0.05
mA/
Mbps
Output
IDDO (D)
mA/
Mbps
1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11
for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1200W and ADuM1201W channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for
information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on
calculating per-channel supply current for a given data rate.
Rev. I | Page 12 of 28
Data Sheet
ADuM1200/ADuM1201
ELECTRICAL CHARACTERISTICS—3 V, 125°C OPERATION
All voltages are relative to their respective ground; 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V. All minimum/maximum specifications apply
over the entire recommended operating range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V;
this applies to ADuM1200W and ADuM1201W automotive grade products.
Table 5.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel,
Quiescent
IDDI (Q)
0.26
0.11
0.35
0.20
mA
mA
Output Supply Current per Channel, Quiescent IDDO (Q)
ADVM1200W, Total Supply Current,
Two Channels1
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
0.6
0.2
1.0
0.6
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (TRZ and URZ Grades Only)
VDD1 Supply Current
IDD1 (10)
IDD2 (10)
2.2
0.7
3.4
1.1
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
VDD2 Supply Current
25 Mbps (URZ Grade Only)
VDD1 Supply Current
IDD1 (25)
IDD2 (25)
5.2
1.5
7.7
2.0
mA
mA
12.5 MHz logic signal freq.
12.5 MHz logic signal freq.
VDD2 Supply Current
ADVM1201W, Total Supply Current,
Two Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
IDD2 (Q)
0.4
0.4
0.8
0.8
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
VDD2 Supply Current
10 Mbps (TRZ and URZ Grades Only)
VDD1 Supply Current
IDD1 (10)
IDD2 (10)
1.5
1.5
2.2
2.2
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
VDD2 Supply Current
25 Mbps (URZ Grade Only)
VDD1 Supply Current
IDD1 (25)
IDD2 (25)
3.4
3.4
4.8
4.8
mA
mA
12.5 MHz logic signal freq.
12.5 MHz logic signal freq.
VDD2 Supply Current
For All Models
Input Currents
IIA, IIB
VIH
−10
+0.01
+10
μA
V
0 7 ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
0.7 (VDD1 or VDD2)
VIL
0.3 (VDD1 or VDD2)
VOAH, VOBH
(VDD1 or VDD2) − 0.1
(VDD1 or VDD2) − 0.5
3.0
2.8
0.0
0.04
0.2
V
V
V
V
V
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 400 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
Logic Low Output Voltages
VOAL, VOBL
0.1
0.1
0.4
SWITCHING SPECIFICATIONS
ADuM120xWSRZ
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
Maximum Data Rate3
PW
1000
ns
1
Mbps
ns
Propagation Delay4
tPHL, tPLH
PWD
20
150
40
4
ns
Pulse Width Distortion, |tPLH − tPHL
|
Propagation Delay Skew5
tPSK
100
50
ns
Channel-to-Channel Matching6
tPSKCD/tPSKOD
tR/tF
ns
Output Rise/Fall Time (10% to 90%)
3
ns
Rev. I | Page 13 of 28
ADuM1200/ADuM1201
Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
ADuM120xWTRZ
Minimum Pulse Width2
Maximum Data Rate3
CL = 15 pF, CMOS signal levels
PW
100
ns
10
20
Mbps
ns
Propagation Delay4
tPHL, tPLH
60
3
4
PWD
ns
Pulse Width Distortion, |tPLH − tPHL
|
Change vs. Temperature
5
ps/°C
ns
Propagation Delay Skew5
Channel-to-Channel Matching
Codirectional Channels6
Opposing Directional Channels6
Output Rise/Fall Time (10% to 90%)
ADuM120xWCR
tPSK
22
tPSKCD
tPSKOD
tR/tF
3
ns
ns
ns
22
3.0
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
PW
20
50
40
ns
25
20
Mbps
ns
tPHL, tPLH
55
3
4
PWD
ns
Pulse Width Distortion, |tPLH − tPHL
|
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching
Codirectional Channels6
Opposing Directional Channels6
Output Rise/Fall Time (10% to 90%)
For All Models
5
ps/°C
ns
tPSK
16
tPSKCD
tPSKOD
tR/tF
3
ns
ns
ns
16
3.0
Common-Mode Transient Immunity
Logic High Output7
|CMH|
|CML|
fr
25
25
35
35
1.1
kV/μs
kV/μs
Mbps
VIx = VDD1, VDD2, VCM = 1000 V,
transient magnitude = 800 V
Logic Low Output7
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate
Dynamic Supply Current per Channel8
Input
IDDI (D)
0.10
0.03
mA/
Mbps
Output
IDDO (D)
mA/
Mbps
1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11
for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1200W and ADuM1201W channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for
information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on
calculating per-channel supply current for a given data rate.
Rev. I | Page 14 of 28
Data Sheet
ADuM1200/ADuM1201
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V, 125°C OPERATION
All voltages are relative to their respective ground; 5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V. 3 V/5 V operation; all
minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted; all typical specifications
are at TA = 25°C; VDD1 = 5.0 V, VDD2 = 3.0 V; this applies to ADuM1200W and ADuM1201W automotive grade products.
Table 6.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel,
Quiescent
IDDI (Q)
0.50
0.11
0.6
mA
mA
Output Supply Current per Channel,
Quiescent
IDDO (Q)
0.20
ADuM1200W, Total Supply Current,
Two Channels1
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (TRZ and URZ Grades Only)
VDD1 Supply Current
VDD2 Supply Current
25 Mbps (URZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.1
0.2
1.4
0.6
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
IDD1 (10)
IDD2 (10)
4.3
0.7
5.5
1.1
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
IDD1 (25)
IDD2 (25)
10
13
mA
mA
12.5 MHz logic signal freq.
12.5 MHz logic signal freq.
1.5
2.0
ADuM1201W, Total Supply Current,
Two Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
IDD2 (Q)
0.8
0.4
1.1
0.8
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
VDD2 Supply Current
10 Mbps (TRZ and URZ Grades Only)
VDD1 Supply Current
IDD1 (10)
IDD2 (10)
2.8
1.5
3.5
2.2
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
VDD2 Supply Current
25 Mbps (URZ Grade Only)
VDD1 Supply Current
IDD1 (25)
IDD2 (25)
6.3
3.4
8.0
4.8
mA
mA
12.5 MHz logic signal freq.
12.5 MHz logic signal freq.
VDD2 Supply Current
For All Models
Input Currents
IIA, IIB
VIH
−10
+0.01
+10
μA
V
0 V ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
0.7 (VDD1 or VDD2)
VIL
0.3 (VDD1 or VDD2
)
V
VOAH, VOBH
(VDD1 or VDD2) − 0.1 VDD1 or VDD2
V
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 400 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
(VDD1 or VDD2) − 0.5 (VDD1 or VDD2) − 0.2
V
Logic Low Output Voltages
VOAL, VOBL
0.0
0.1
0.1
0.4
V
0.04
0.2
V
V
SWITCHING SPECIFICATIONS
ADuM120xWSRZ
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
Maximum Data Rate3
PW
1000
ns
1
Mbps
ns
Propagation Delay4
tPHL, tPLH
PWD
15
150
40
4
ns
Pulse Width Distortion, |tPLH − tPHL
|
Propagation Delay Skew5
tPSK
50
ns
Channel-to-Channel Matching6
tPSKCD/ tPSKOD
tR/tF
50
ns
Output Rise/Fall Time (10% to 90%)
3
ns
Rev. I | Page 15 of 28
ADuM1200/ADuM1201
Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
ADuM120xWTRZ
Minimum Pulse Width2
Maximum Data Rate3
CL = 15 pF, CMOS signal levels
PW
100
ns
10
15
Mbps
Propagation Delay4
tPHL, tPLH
55
3
ns
4
PWD
ns
Pulse Width Distortion, |tPLH − tPHL
|
Change vs. Temperature
5
ps/°C
ns
Propagation Delay Skew5
Channel-to-Channel Matching
Codirectional Channels6
Opposing Directional Channels6
Output Rise/Fall Time (10% to 90%)
ADuM120xWURZ
tPSK
22
tPSKCD
tPSKOD
tR/tF
3
ns
ns
ns
22
3.0
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
PW
20
50
40
ns
25
20
Mbps
ns
tPHL, tPLH
50
3
4
PWD
ns
Pulse Width Distortion, |tPLH − tPHL
|
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching
Codirectional Channels6
Opposing Directional Channels6
Output Rise/Fall Time (10% to 90%)
For All Models
5
ps/°C
ns
tPSK
15
tPSKCD
tPSKOD
tR/tF
3
ns
ns
ns
15
3.0
Common-Mode Transient Immunity
Logic High Output7
|CMH|
|CML|
fr
25
25
35
35
1.2
kV/μs
kV/μs
Mbps
VIx = VDD1, VDD2, VCM = 1000 V,
transient magnitude = 800 V
Logic Low Output7
VIx = VDD1, VDD2, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate
Dynamic Supply Current per Channel8
Input
IDDI (D)
0.19
0.03
mA/
Mbps
Output
IDDO (D)
mA/
Mbps
1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11
for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1200W and ADuM1201W channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for
information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on
calculating per-channel supply current for a given data rate.
Rev. I | Page 16 of 28
Data Sheet
ADuM1200/ADuM1201
ELECTRICAL CHARACTERISTICS—MIXED 3 V/5 V, 125°C OPERATION
All voltages are relative to their respective ground; 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply
over the entire recommended operating range, unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5.0 V;
this applies to ADuM1200W and ADuM1201W automotive grade products.
Table 7.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel,
Quiescent
IDDI (Q)
0.26
0.19
0.35
0.25
mA
mA
Output Supply Current per Channel,
Quiescent
IDDO (Q)
ADuM1200W, Total Supply Current,
Two Channels1
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (TRZ and URZ Grades Only)
VDD1 Supply Current
VDD2 Supply Current
25 Mbps (URZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
0.6
0.5
1.0
0.8
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
IDD1 (10)
IDD2 (10)
2.2
1.3
3.4
2.0
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
IDD1 (25)
IDD2 (25)
5.2
2.8
7.7
3.4
mA
mA
12.5 MHz logic signal freq.
12.5 MHz logic signal freq.
ADuM1201W, Total Supply Current,
Two Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
IDD2 (Q)
0.4
0.8
0.8
1.1
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
VDD2 Supply Current
10 Mbps (TRZ and URZ Grades Only)
VDD1 Supply Current
IDD1 (10)
IDD2 (10)
1.5
2.8
2.2
3.5
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
VDD2 Supply Current
25 Mbps (URZ Grade Only)
VDD1 Supply Current
IDD1 (25)
IDD2 (25)
3.4
6.3
4.8
8.0
mA
mA
12.5 MHz logic signal freq.
12.5 MHz logic signal freq.
VDD2 Supply Current
For All Models
Input Currents
IIA, IIB
VIH
−10
+0.01
+10
μA
V
0 V ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
0.7 (VDD1 or VDD2)
VIL
0.3 (VDD1 or VDD2
)
V
VOAH, VOBH
(VDD1 or VDD2) − 0.1 VDD1 or VDD2
V
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 400 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
(VDD1 or VDD2) − 0.5 (VDD1 or VDD2) − 0.2
V
Logic Low Output Voltages
VOAL, VOBL
0.0
0.1
0.1
0.4
V
0.04
0.2
V
V
SWITCHING SPECIFICATIONS
ADuM120xWSRZ
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
Maximum Data Rate3
PW
1000
ns
1
Mbps
ns
Propagation Delay4
tPHL, tPLH
PWD
tPSK
15
150
40
4
ns
Pulse Width Distortion, |tPLH − tPHL
|
Propagation Delay Skew5
50
ns
Channel-to-Channel Matching6
tPSKCD/
tPSKOD
50
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
3
ns
Rev. I | Page 17 of 28
ADuM1200/ADuM1201
Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
ADuM120xWTRZ
Minimum Pulse Width2
Maximum Data Rate3
CL = 15 pF, CMOS signal levels
PW
100
ns
10
15
Mbps
ns
Propagation Delay4
t
PHL, tPLH
55
3
4
PWD
ns
Pulse Width Distortion, |tPLH − tPHL
|
Change vs. Temperature
5
ps/°C
ns
Propagation Delay Skew5
Channel-to-Channel Matching
Codirectional Channels6
Opposing Directional Channels6
Output Rise/Fall Time (10% to 90%)
ADuM120xWURZ
tPSK
22
tPSKCD
tPSKOD
tR/tF
3
ns
ns
ns
22
2.5
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
PW
20
50
40
ns
25
20
Mbps
ns
t
PHL, tPLH
50
3
4
PWD
ns
Pulse Width Distortion, |tPLH − tPHL
|
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching
Codirectional Channels6
Opposing Directional Channels6
Output Rise/Fall Time (10% to 90%)
For All Models
5
ps/°C
ns
tPSK
15
tPSKCD
tPSKOD
tR/tF
3
ns
ns
ns
15
2.5
Common-Mode Transient Immunity
Logic High Output7
|CMH|
|CML|
25
25
35
35
kV/μs
kV/μs
Mbps
VIx = VDD1, VDD2, VCM = 1000 V,
transient magnitude = 800 V
Logic Low Output7
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate
fr
1.1
Input Dynamic Supply Current
per Channel8
IDDI (D)
0.10
mA/
Mbps
Output Dynamic Supply Current
per Channel8
IDDO (D)
0.05
mA/
Mbps
1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11
for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1200W and ADuM1201W channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for
information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on
calculating per-channel supply current for a given data rate.
Rev. I | Page 18 of 28
Data Sheet
ADuM1200/ADuM1201
PACKAGE CHARACTERISTICS
Table 8.
Parameter
Symbol
RI-O
CI-O
CI
θJCI
Min
Typ
1012
1.0
4.0
46
Max
Unit
Ω
pF
pF
°C/W
Test Conditions
Resistance (Input-to-Output)1
Capacitance (Input-to-Output)1
Input Capacitance
f = 1 MHz
IC Junction-to-Case Thermal Resistance, Side 1
Thermocouple located at
center of package underside
IC Junction-to-Case Thermal Resistance, Side 2
θJCO
41
°C/W
1 The device is considered a 2-terminal device; Pin 1, Pin, 2, Pin 3, and Pin 4 are shorted together, and Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together.
REGULATORY INFORMATION
The ADuM1200/ADuM1201 and ADuM1200W/ADuM1201W are approved by the organizations listed in Table 9; refer to Table 14 and
the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-isolation waveforms and
insulation levels.
Table 9.
UL
CSA
VDE
Recognized Under 1577 Component
Recognition Program1
Approved under CSA Component Acceptance
Notice #5A; approval pending for ADuM1200W/
ADuM1201W automotive 125°C temperature grade
Certified according to DIN V VDE V
0884-10 (VDE V 0884-10): 2006-122
Single/Basic 2500 V rms Isolation Voltage
Basic insulation per CSA 60950-1-03 and
IEC 60950-1, 400 V rms (566 peak) maximum
working voltage
Reinforced insulation, 560 V peak
Functional insulation per CSA 60950-1-03 and
IEC 60950-1, 800 V rms (1131 V peak) maximum
working voltage
File E214100
File 205078
File 2471900-4880-0001
1 In accordance with UL 1577, each ADuM120x is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 μA).
2 In accordance with DIN V VDE V 0884-10, each ADuM120x is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 sec (partial discharge detection
limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 10.
Parameter
Symbol Value
Unit
Conditions
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
2500
4.90 min
V rms 1 minute duration
L(I01)
L(I02)
mm
mm
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Minimum External Tracking (Creepage)
4.01 min
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
0.017 min mm
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
CTI
>175
IIIa
V
Rev. I | Page 19 of 28
ADuM1200/ADuM1201
Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 INSULATION CHARACTERISTICS
This isolator is suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by protective
circuits. Note that the asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for a 560 V peak working voltage.
Table 11.
Description
Conditions
Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method B1
I to IV
I to III
I to II
40/105/21
2
VIORM
VPR
560
1050
V peak
V peak
VIORM × 1.875 = VPR, 100% production test,
tm = 1 second, partial discharge < 5 pC
Input-to-Output Test Voltage, Method A
VIORM × 1.6 = VPR, tm = 60 seconds,
partial discharge < 5 pC
VPR
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
896
672
V peak
V peak
VIORM × 1.2 = VPR, tm = 60 seconds,
partial discharge < 5 pC
Highest Allowable Overvoltage
Safety-Limiting Values
Transient overvoltage, tTR = 10 seconds
Maximum value allowed in the event of a failure
(see Figure 3)
VTR
4000
V peak
Case Temperature
Side 1 Current
Side 2 Current
TS
IS1
IS2
RS
150
160
170
>109
°C
mA
mA
Ω
Insulation Resistance at TS
VIO = 500 V
RECOMMENDED OPERATING CONDITIONS
200
180
160
140
Table 12.
Parameter
Rating
Operating Temperature (TA)1
Operating Temperature (TA)2
−40°C to +105°C
−40°C to +125°C
2.7 V to 5.5 V
3.0 V to 5.5 V
1.0 ms
SIDE #2
SIDE #1
120
100
80
60
40
20
0
1, 3
Supply Voltages (VDD1, VDD2
Supply Voltages (VDD1, VDD2
)
)
2, 3
Input Signal Rise and Fall Times
1 Does not apply to ADuM1200W and ADuM1201W automotive grade
products.
2 Applies to ADuM1200W and ADuM1201W automotive grade products.
3 All voltages are relative to their respective ground. See the DC Correctness
and Magnetic Field Immunity section for information on immunity to external
magnetic fields.
0
50
100
150
200
CASE TEMPERATURE (°C)
Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting Values
on Case Temperature per DIN V VDE V 0884-10
Rev. I | Page 20 of 28
Data Sheet
ADuM1200/ADuM1201
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 13.
Parameter
Rating
Storage Temperature (TST)
Ambient Operating Temperature (TA)1
−55°C to +150°C
−40°C to +105°C
−40°C to +125°C
−0.5 V to +7.0 V
−0.5 V to VDDI + 0.5 V
−0.5 V to VDDO + 0.5 V
−11 mA to +11 mA
Ambient Operating Temperature (TA)2
3
Supply Voltages (VDD1, VDD2
)
ESD CAUTION
Input Voltages (VIA, VIB)3, 4
Output Voltages (VOA, VOB)3, 4
Average Output Current per Pin (IO)5
Common-Mode Transients (CML, CMH)6 −100 kV/μs to +100 kV/μs
1 Does not apply to ADuM1200W and ADuM1200W automotive grade
products.
2 Applies to ADuM1200W and ADuM1201W automotive grade products.
3 All voltages are relative to their respective ground.
4 VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively.
5 See Figure 3 for maximum rated current values for various temperatures.
6 Refers to common-mode transients across the insulation barrier.
Common-mode transients exceeding the absolute maximum ratings
can cause latch-up or permanent damage.
Table 14. Maximum Continuous Working Voltage1
Parameter
Max
Unit
Constraint
AC Voltage, Bipolar Waveform
AC Voltage, Unipolar Waveform
Functional Insulation
Basic Insulation
565
V peak
50-year minimum lifetime
1131
560
V peak
V peak
Maximum approved working voltage per IEC 60950-1
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
DC Voltage
Functional Insulation
Basic Insulation
1131
560
V peak
V peak
Maximum approved working voltage per IEC 60950-1
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Rev. I | Page 21 of 28
ADuM1200/ADuM1201
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
V
V
V
V
V
V
V
DD1
DD2
IA
DD1
DD2
OA
OB
ADuM1201
TOP VIEW
(Not to Scale)
ADuM1200
V
V
V
OA
IA
IB
TOP VIEW
V
IB
OB
(Not to Scale)
GND
GND
2
GND
GND
1
1
2
Figure 4. ADuM1200 Pin Configuration
Figure 5. ADuM1201 Pin Configuration
Table 15. ADuM1200 Pin Function Descriptions
Table 16. ADuM1201 Pin Function Descriptions
Pin
No.
Pin
No.
Mnemonic Description
Mnemonic
VDD1
VOA
Description
1
2
VDD1
VIA
Supply Voltage for Isolator Side 1.
Logic Input A.
1
2
Supply Voltage for Isolator Side 1.
Logic Output A.
3
VIB
Logic Input B.
3
VIB
Logic Input B.
4
5
6
GND1
GND2
VOB
Ground 1. Ground Reference for Isolator Side 1.
Ground 2. Ground Reference for Isolator Side 2.
Logic Output B.
4
5
6
GND1
GND2
VOB
Ground 1. Ground Reference for Isolator Side 1.
Ground 2. Ground Reference for Isolator Side 2.
Logic Output B.
7
VOA
Logic Output A.
7
VIA
Logic Input A.
8
VDD2
Supply Voltage for Isolator Side 2.
8
VDD2
Supply Voltage for Isolator Side 2.
Table 17. ADuM1200 Truth Table (Positive Logic)
VIA Input
VIB Input
VDD1 State
Powered
Powered
Powered
Powered
Unpowered
VDD2 State
Powered
Powered
Powered
Powered
Powered
VOA Output
VOB Output
Notes
H
L
H
L
H
L
L
H
X
H
L
H
L
H
L
L
H
H
X
H
Outputs return to the input state within
1 μs of VDDI power restoration.
X
X
Powered
Unpowered
Indeterminate
Indeterminate
Outputs return to the input state within
1 μs of VDDO power restoration.
Table 18. ADuM1201 Truth Table (Positive Logic)
VIA Input
VIB Input
VDD1 State
Powered
Powered
Powered
Powered
Unpowered
VDD2 State
Powered
Powered
Powered
Powered
Powered
VOA Output
VOB Output
Notes
H
L
H
L
H
L
L
H
X
H
L
H
L
H
L
L
H
H
X
Indeterminate
Outputs return to the input state within
1 μs of VDDI power restoration.
X
X
Powered
Unpowered
H
Indeterminate
Outputs return to the input state within
1 μs of VDDO power restoration.
Rev. I | Page 22 of 28
Data Sheet
ADuM1200/ADuM1201
TYPICAL PERFORMANCE CHARACTERISTICS
10
20
15
10
5
8
6
4
5V
3V
5V
3V
2
0
0
0
10
20
30
0
10
20
30
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 6. Typical Input Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation
Figure 9. Typical ADuM1200 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
4
4
3
2
3
2
5V
5V
3V
1
1
0
3V
0
0
10
20
30
0
10
20
30
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 7. Typical Output Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation (No Output Load)
Figure 10. Typical ADuM1200 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
4
10
8
3
6
5V
5V
2
4
3V
3V
1
2
0
0
0
10
20
30
0
10
20
30
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 8. Typical Output Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation (15 pF Output Load)
Figure 11. Typical ADuM1201 VDD1 or VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
Rev. I | Page 23 of 28
ADuM1200/ADuM1201
Data Sheet
APPLICATIONS INFORMATION
The ADuM120x are extremely immune to external magnetic
fields. The limitation on the magnetic field immunity of the
ADuM120x is set by the condition in which induced voltage in
the receiving coil of the transformer is sufficiently large enough
to either falsely set or reset the decoder. The following analysis
defines the conditions under which this can occur. The 3 V
operating condition of the ADuM120x is examined because
it represents the most susceptible mode of operation.
PCB LAYOUT
The ADuM120x digital isolators require no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins.
The capacitor value should be between 0.01 μF and 0.1 μF.
The total lead length between both ends of the capacitor and
the input power supply pin should not exceed 20 mm.
See the AN-1109 Application Note for board layout guidelines.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V,
therefore establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output can differ from the propagation delay
to a logic high output.
2
V = (−dβ/dt)Σ∏rn ; n = 1, 2, … , N
where:
INPUT (V
)
50%
Ix
β is the magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
tPLH
tPHL
OUTPUT (V
)
50%
Ox
Figure 12. Propagation Delay Parameters
Given the geometry of the receiving coil in the ADuM120x and
an imposed requirement that the induced voltage be 50% at
most of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated, as shown in Figure 13.
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of
how accurately the timing of the input signal is preserved.
100
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM120x component.
10
1
Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple ADuM120x
components operating under the same conditions.
0.1
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
0.01
0.001
Positive and negative logic transitions at the isolator input send
narrow (~1 ns) pulses to the decoder via the transformer. The
decoder is bistable and is therefore either set or reset by the pulses,
indicating input logic transitions. In the absence of logic transi-
tions of more than ~1 μs at the input, a periodic set of refresh
pulses indicative of the correct input state is sent to ensure dc
correctness at the output. If the decoder receives no internal
pulses for more than about 5 μs, the input side is assumed to be
unpowered or nonfunctional, in which case the isolator output
is forced to a default state (see Table 17 and Table 18) by the
watchdog timer circuit.
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 13. Maximum Allowable External Magnetic Flux Density
Rev. I | Page 24 of 28
Data Sheet
ADuM1200/ADuM1201
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurs during a transmitted pulse
(and has the worst-case polarity), it reduces the received pulse
from >1.0 V to 0.75 V—still well above the 0.5 V sensing
threshold of the decoder.
POWER CONSUMPTION
The supply current at a given channel of the ADuM120x
isolator is a function of the supply voltage, the data rate of the
channel, and the output load of the channel.
For each input channel, the supply current is given by
I
I
DDI = IDDI (Q)
f ≤ 0.5fr
f > 0.5fr
DDI = IDDI (D) × (2f − fr) + IDDI (Q)
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances away from the
ADuM120x transformers. Figure 14 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As seen, the ADuM120x are extremely immune and
can be affected only by extremely large currents operating very
close to the component at a high frequency. For the 1 MHz
example, a 0.5 kA current would have to be placed 5 mm away
from the ADuM120x to affect the operation of the component.
For each output channel, the supply current is given by
I
I
DDO = IDDO (Q)
f ≤ 0.5fr
DDO = (IDDO (D) + (0.5 × 10−3) × CLVDDO) × (2f − fr) + IDDO (Q)
f > 0.5fr
where:
DDI (D), IDDO (D) are the input and output dynamic supply currents
I
per channel (mA/Mbps).
CL is the output load capacitance (pF).
1000
V
DDO is the output supply voltage (V).
DISTANCE = 1m
f is the input logic signal frequency (MHz, half of the input data
rate, NRZ signaling).
100
fr is the input stage refresh rate (Mbps).
10
IDDI (Q), IDDO (Q) are the specified input and output quiescent
supply currents (mA).
DISTANCE = 100mm
1
To calculate the total IDD1 and IDD2 supply currents, the supply
currents for each input and output channel corresponding to
DISTANCE = 5mm
0.1
I
DD1 and IDD2 are calculated and totaled. Figure 6 and Figure 7
provide per-channel supply currents as a function of data rate
for an unloaded output condition. Figure 8 provides per-
channel supply current as a function of data rate for a 15 pF
output condition. Figure 9 through Figure 11 provide total
0.01
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 14. Maximum Allowable Current for Various
Current-to-ADuM120x Spacings
VDD1 and VDD2 supply current as a function of data rate for
ADuM1200 and ADuM1201 channel configurations.
Note that, at combinations of strong magnetic fields and high
frequencies, any loops formed by PCB traces can induce suffi-
ciently large error voltages to trigger the threshold of succeeding
circuitry. Care should be taken in the layout of such traces to
avoid this possibility.
Rev. I | Page 25 of 28
ADuM1200/ADuM1201
Data Sheet
In the case of unipolar ac or dc voltage, the stress on the insu-
lation is significantly lower, which allows operation at higher
working voltages yet still achieves a 50-year service life. The
working voltages listed in Table 14 can be applied while main-
taining the 50-year minimum lifetime provided the voltage
conforms to either the unipolar ac or dc voltage cases. Any cross-
insulation voltage waveform that does not conform to Figure 16
or Figure 17 is to be treated as a bipolar ac waveform, and its
peak voltage is to be limited to the 50-year lifetime voltage value
listed in Table 14.
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of insu-
lation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition
to the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADuM120x.
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage. Accel-
eration factors for several operating conditions are determined.
These factors allow calculation of the time to failure at the actual
working voltage. The values shown in Table 14 summarize the
peak voltage for 50 years of service life for a bipolar ac operating
condition and the maximum CSA/VDE approved working volt-
ages. In many cases, the approved working voltage is higher than
the 50-year service life voltage. Operation at these high working
voltages can lead to shortened insulation life in some cases.
Note that the voltage presented in Figure 16 is shown as sinu-
soidal for illustration purposes only. It is meant to represent any
voltage waveform varying between 0 V and some limiting value.
The limiting value can be positive or negative, but the voltage
cannot cross 0 V.
RATED PEAK VOLTAGE
0V
Figure 15. Bipolar AC Waveform
The insulation lifetime of the ADuM120x depends on the
voltage waveform type imposed across the isolation barrier.
The iCoupler insulation structure degrades at different rates
depending on whether the waveform is bipolar ac, unipolar
ac, or dc. Figure 15, Figure 16, and Figure 17 illustrate these
different isolation voltage waveforms, respectively.
RATED PEAK VOLTAGE
0V
Figure 16. Unipolar AC Waveform
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the ac bipolar condition
determines the Analog Devices recommended maximum
working voltage.
RATED PEAK VOLTAGE
0V
Figure 17. DC Waveform
Rev. I | Page 26 of 28
Data Sheet
ADuM1200/ADuM1201
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 18. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Number
of Inputs,
VDD1 Side
Number
of Inputs, Data Rate
Maximum
Maximum
Propagation
Delay, 5 V (ns) Distortion (ns)
Maximum
Pulse Width
Temperature
Range
Package
Option3
Model1, 2
VDD2 Side
(Mbps)
ADuM1200AR
ADuM1200ARZ
ADuM1200ARZ-RL7
ADuM1200BR
ADuM1200BR-RL7
ADuM1200BRZ
ADuM1200BRZ-RL7
ADuM1200CR
ADuM1200CR-RL7
ADuM1200CRZ
ADuM1200CRZ-RL7
ADuM1200WSRZ
ADuM1200WSRZ-RL7
ADuM1200WTRZ
ADuM1200WTRZ-RL7
ADuM1200WURZ
ADuM1200WURZ-RL7
ADuM1201AR
ADuM1201AR-RL7
ADuM1201ARZ
ADuM1201ARZ-RL7
ADuM1201BR
ADuM1201BR-RL7
ADuM1201BRZ
ADuM1201BRZ-RL7
ADuM1201CR
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
150
150
150
50
50
50
50
45
45
45
40
40
40
3
3
3
3
3
3
3
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
10
10
10
10
25
25
25
25
1
45
3
150
150
50
50
45
40
40
3
3
3
1
10
10
25
25
1
1
1
1
10
10
10
10
25
25
25
45
3
150
150
150
150
50
50
50
50
45
40
40
40
40
3
3
3
3
3
ADuM1201CRZ
ADuM1201CRZ-RL7
45
45
3
3
Rev. I | Page 27 of 28
ADuM1200/ADuM1201
Data Sheet
Number
of Inputs,
Number
of Inputs, Data Rate
VDD2 Side
Maximum
Maximum
Propagation
Delay, 5 V (ns) Distortion (ns)
Maximum
Pulse Width
Temperature
Range
Package
Option3
Model1, 2
V
1
1
1
1
1
1
DD1 Side
(Mbps)
ADuM1201WSRZ
ADuM1201WSRZ-RL7
ADuM1201WTRZ
ADuM1201WTRZ-RL7
ADuM1201WURZ
ADuM1201WURZ-RL7
1
1
1
1
1
1
1
1
10
10
25
25
150
150
50
50
45
40
40
3
3
3
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
R-8
R-8
R-8
R-8
R-8
R-8
45
3
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
3 R-8 = 8-lead narrow-body SOIC_N.
AUTOMOTIVE PRODUCTS
The ADuM1200W/ADuM1201W models are available with controlled manufacturing to support the quality and reliability requirements
of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore,
designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for
use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and
to obtain the specific Automotive Reliability reports for these models.
©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04642-0-3/12(I)
Rev. I | Page 28 of 28
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