ADUM3402BRWZ [ADI]
Quad-Channel, Digital Isolators, Enhanced System-Level ESD Reliability; 四通道数字隔离器，增强的系统级ESD可靠性
| 型号： | ADUM3402BRWZ |
| 厂家： | 
ADI |
| 描述： | Quad-Channel, Digital Isolators, Enhanced System-Level ESD Reliability |
| 文件： | 总24页 (文件大小：513K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad-Channel, Digital Isolators,
Enhanced System-Level ESD Reliability
ADuM3400/ADuM3401/ADuM3402
FEATURES
GENERAL DESCRIPTION
Enhanced system-level ESD performance per IEC 61000-4-x
Low power operation
5 V operation
The ADuM340x1 are 4-channel digital isolators based on
Analog Devices’ iCoupler® technology. Combining high speed
CMOS and monolithic air core transformer technology, these
isolation components provide outstanding performance
1.4 mA per channel maximum @ 0 Mbps to 2 Mbps
4.3 mA per channel maximum @ 10 Mbps
34 mA per channel maximum @ 90 Mbps
3 V operation
0.9 mA per channel maximum @ 0 Mbps to 2 Mbps
2.4 mA per channel maximum @ 10 Mbps
20 mA per channel maximum @ 90 Mbps
Bidirectional communication
characteristics superior to alternatives such as optocoupler devices.
iCoupler devices remove the design difficulties commonly
associated with optocouplers. Typical optocoupler concerns
regarding uncertain current transfer ratios, nonlinear transfer
functions, and temperature and lifetime effects are eliminated
with the simple iCoupler digital interfaces and stable performance
characteristics. The need for external drivers and other discrete
components is eliminated with these iCoupler products.
3 V/5 V level translation
High temperature operation: 105°C
High data rate: dc to 90 Mbps (NRZ)
Precise timing characteristics
Furthermore, iCoupler devices consume one-tenth to one-sixth the
power of optocouplers at comparable signal data rates.
2 ns maximum pulse-width distortion
2 ns maximum channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Output enable function
16-lead SOIC wide body, Pb-free package
Safety and regulatory approvals
UL recognition: 2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE Certificate of Conformity
DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01
DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000
VIORM = 560 V peak
The ADuM340x isolators provide three independent isolation
channels in a variety of channel configurations and data rates
(see the Ordering Guide). All models operate with the supply
voltage on either side ranging from 2.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling a
voltage translation functionality across the isolation barrier. The
ADuM340x isolators have a patented refresh feature that ensures dc
correctness in the absence of input logic transitions and during
power-up/power-down conditions.
In comparison to the ADuM140x isolators, the ADuM340x
isolators contain various circuit and layout changes to provide
increased capability relative to system-level IEC 61000-4-x testing
(ESD/burst/surge). The precise capability in these tests for either
the ADuM140x or ADuM340x products is strongly determined by
the design and layout of the user’s board or module. For more
information, see Application Note AN-793, ESD/Latch-Up
Considerations with iCoupler Isolation Products.
APPLICATIONS
General-purpose multichannel isolation
SPI® interface/data converter isolation
RS-232/RS-422/RS-485 transceivers
Industrial field bus isolation
1 Protected by U.S. Patents 5,952,849 and 6,873,065. Other patents pending.
FUNCTIONAL BLOCK DIAGRAMS
1
2
3
16
15
14
1
2
3
16
15
14
1
2
3
16
15
14
V
V
V
V
DD2
V
V
DD2
DD1
DD2
DD1
DD1
GND
V
GND
GND
V
GND
2
GND
V
GND
1
2
1
1
2
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
ENCODE
V
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
ENCODE
ENCODE
V
ENCODE
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
V
IA
IB
OA
IA
IB
OA
IA
IB
OA
V
V
V
4
5
13
12
4
5
13
12
4
5
13
12
V
V
V
OB
OB
OB
V
V
V
V
V
V
V
V
IC
OC
OC
IC
IC
OC
6
7
8
11
10
9
6
7
8
11
10
9
6
7
8
11
10
9
V
V
V
V
OD
ID
OD
ID
ID
OD
V
V
V
V
NC
GND
V
E1
E2
E1
E2
E2
GND
GND
GND
GND
2
GND
1
2
1
1
2
Figure 1. ADuM3400 Functional Block Diagram
Figure 2. ADuM3401 Functional Block Diagram
Figure 3. ADuM3402 Functional Block Diagram
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADuM3400/ADuM3401/ADuM3402
TABLE OF CONTENTS
Features .............................................................................................. 1
Recommended Operating Conditions .................................... 13
Absolute Maximum Ratings ......................................................... 14
ESD Caution................................................................................ 14
Pin Configurations and Function Descriptions......................... 15
Typical Performance Characteristics ........................................... 18
Application Information................................................................ 20
PC Board Layout ........................................................................ 20
System-Level ESD Considerations and Enhancements ........ 20
Propagation Delay-Related Parameters................................... 20
DC Correctness and Magnetic Field Immunity........................... 20
Power Consumption .................................................................. 22
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 23
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—5 V Operation................................ 3
Electrical Characteristics—3 V Operation................................ 6
Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V
Operation....................................................................................... 8
Package Characteristics ............................................................. 12
Regulatory Information............................................................. 12
Insulation and Safety-Related Specifications.......................... 12
DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation
Characteristics ............................................................................ 13
REVISION HISTORY
3/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADuM3400/ADuM3401/ADuM3402
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION1
4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V.
Table 1.
Parameter
Symbol
Min
Typ Max Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
ADuM3400, Total Supply Current, Four Channels2
DC to 2 Mbps
IDDI (Q)
IDDO (Q)
0.57 0.83 mA
0.29 0.35 mA
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
2.9
1.2
3.5
1.9
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
9.0
3.0
11.6 mA
5.5 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (90)
IDD2 (90)
72
19
100 mA
45 MHz logic signal freq.
45 MHz logic signal freq.
36
mA
ADuM3401, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
2.5
1.6
3.2
2.4
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
7.4
4.4
10.6 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
6.5
mA
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (90)
IDD2 (90)
59
32
82
46
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
ADuM3402, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 or VDD2 Supply Current
10 Mbps (BRW and CRW Grades Only)
VDD1 or VDD2 Supply Current
90 Mbps (CRW Grade Only)
VDD1 or VDD2 Supply Current
For All Models
IDD1 (Q), IDD2 (Q)
IDD1 (10), IDD2 (10)
IDD1 (90), IDD2 (90)
2.0
6.0
51
2.8
7.5
62
mA
mA
mA
DC to 1 MHz logic signal freq.
5 MHz logic signal freq.
45 MHz logic signal freq.
Input Currents
IIA, IIB, IIC,
IID, IE1, IE2
VIH, VEH
VIL, VEL
VOAH, VOBH
VOCH, VODH
−10
2.0
+0.01 +10 μA
V
0 ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2
0 ≤ VE1, VE2 ≤ VDD1 or VDD2
,
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
0.8
V
V
V
V
V
V
,
VDD1, VDD2 − 0.1 5.0
VDD1, VDD2 − 0.4 4.8
0.0
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 400 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
Logic Low Output Voltages
VOAL, VOBL
VOCL, VODL
,
0.1
0.04 0.1
0.2 0.4
Rev. 0 | Page 3 of 24
ADuM3400/ADuM3401/ADuM3402
Parameter
Symbol
Min
Typ Max Unit
Test Conditions
SWITCHING SPECIFICATIONS
ADuM340xARW
Minimum Pulse Width3
Maximum Data Rate4
PW
1000 ns
Mbps
100 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
50
Propagation Delay5
tPHL, tPLH
PWD
tPSK
65
5
Pulse-Width Distortion, |tPLH − tPHL
Propagation Delay Skew6
Channel-to-Channel Matching7
ADuM340xBRW
|
40
50
50
ns
ns
ns
tPSKCD/OD
Minimum Pulse Width3
PW
100 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Maximum Data Rate4
10
20
Propagation Delay5
tPHL, tPLH
PWD
32
5
50
3
5
Pulse-Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
|
ns
ps/°C
ns
ns
tPSK
tPSKCD
15
3
Channel-to-Channel Matching,
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels7
ADuM340xCRW
Minimum Pulse Width3
Maximum Data Rate4
PW
8.3
120
27
0.5
3
11.1 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
90
18
Propagation Delay5
tPHL, tPLH
PWD
32
2
5
Pulse-Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
|
ns
ps/°C
ns
ns
tPSK
tPSKCD
10
2
Channel-to-Channel Matching,
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels7
For All Models
Output Disable Propagation Delay
(High/Low-to-High Impedance)
Output Enable Propagation Delay
(High Impedance-to-High/Low)
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
at Logic High Output8
t
PHZ, tPLH
6
6
8
8
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
tPZH, tPZL
tR/tF
|CMH|
2.5
35
ns
kV/μs
25
25
Common-Mode Transient Immunity
at Logic Low Output8
|CML|
35
kV/μs
transient magnitude = 800 V
Refresh Rate
fr
1.2
0.20
0.05
Mbps
mA/Mbps
mA/Mbps
Input Dynamic Supply Current per Channel9
IDDI (D)
Output Dynamic Supply Current per Channel9 IDDO (D)
Rev. 0 | Page 4 of 24
ADuM3400/ADuM3401/ADuM3402
1 All voltages are relative to their respective ground.
2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3400/ADuM3401/ADuM3402 channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. 0 | Page 5 of 24
ADuM3400/ADuM3401/ADuM3402
ELECTRICAL CHARACTERISTICS—3 V OPERATION1
2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V.
Table 2.
Parameter
Symbol
Min
Typ Max Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
ADuM3400, Total Supply Current, Four Channels2
DC to 2 Mbps
IDDI (Q)
IDDO (Q)
0.31 0.49 mA
0.19 0.27 mA
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.6
0.7
2.1
1.2
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
4.8
1.8
7.1
2.3
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (90)
IDD2 (90)
37
11
54
15
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
ADuM3401, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.4
0.9
1.9
1.5
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
4.1
2.5
5.6
3.3
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (90)
IDD2 (90)
31
17
44
24
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
ADuM3402, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 or VDD2 Supply Current
10 Mbps (BRW and CRW Grades Only)
VDD1 or VDD2 Supply Current
90 Mbps (CRW Grade Only)
VDD1 or VDD2 Supply Current
For All Models
IDD1 (Q), IDD2 (Q)
IDD1 (10), IDD2 (10)
IDD1 (90), IDD2 (90)
1.2
3.3
24
1.7
4.4
39
mA
mA
mA
DC to 1 MHz logic signal freq.
5 MHz logic signal freq.
45 MHz logic signal freq.
Input Currents
IIA, IIB, IIC,
IID, IE1, IE2
VIH, VEH
VIL, VEL
VOAH, VOBH
VOCH, VODH
−10
1.6
+0.01 +10 μA
V
0 ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2
0 ≤ VE1,VE2 ≤ VDD1 or VDD2
,
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
0.4
V
V
V
V
V
V
,
VDD1, VDD2 − 0.1 3.0
VDD1, VDD2 − 0.4 2.8
0.0
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 400 μA, VIx = VIxL
Logic Low Output Voltages
VOAL, VOBL
VOCL, VODL
,
0.1
0.04 0.1
0.2
0.4
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM340xARW
Minimum Pulse Width3
Maximum Data Rate4
PW
1000 ns
Mbps
100 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
50
Propagation Delay5
tPHL, tPLH
PWD
tPSK
75
5
Pulse-Width Distortion, |tPLH − tPHL
|
40
50
50
ns
ns
ns
Propagation Delay Skew6
Channel-to-Channel Matching7
tPSKCD/OD
Rev. 0 | Page 6 of 24
ADuM3400/ADuM3401/ADuM3402
Parameter
Symbol
Min
Typ Max Unit
Test Conditions
ADuM340xBRW
Minimum Pulse Width3
PW
100 ns
Mbps
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Maximum Data Rate4
10
20
Propagation Delay5
tPHL, tPLH
PWD
38
5
50
3
ns
ns
5
Pulse-Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
|
ps/°C
ns
ns
tPSK
tPSKCD
22
3
Channel-to-Channel Matching,
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels7
ADuM340xCRW
Minimum Pulse Width3
Maximum Data Rate4
PW
8.3
120
34
0.5
3
11.1 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
90
20
Propagation Delay5
tPHL, tPLH
PWD
45
2
5
Pulse-Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
|
ns
ps/°C
ns
ns
tPSK
tPSKCD
16
2
Channel-to-Channel Matching,
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels7
For All Models
Output Disable Propagation Delay
(High/Low-to-High Impedance)
Output Enable Propagation Delay
(High Impedance-to-High/Low)
tPHZ, tPLH
tPZH, tPZL
6
6
8
8
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
3
ns
Common-Mode Transient Immunity
at Logic High Output8
Common-Mode Transient Immunity
at Logic Low Output8
|CMH|
25
25
35
kV/μs
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
|CML|
35
kV/μs
transient magnitude = 800 V
Refresh Rate
fr
1.1
0.10
0.03
Mbps
mA/Mbps
mA/Mbps
Input Dynamic Supply Current per Channel9 IDDI (D)
Output Dynamic Supply Current per Channel9
IDDO (D)
1 All voltages are relative to their respective ground.
2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3400/ADuM3401/ADuM3402 channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. 0 | Page 7 of 24
ADuM3400/ADuM3401/ADuM3402
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION1
5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all
minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications
are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V or VDD1 = 5 V, VDD2 = 3.0 V.
Table 3.
Parameter
Symbol Min
Typ
Max Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q)
5 V/3 V Operation
3 V/5 V Operation
0.57
0.31
0.83 mA
0.49 mA
Output Supply Current per Channel, Quiescent
5 V/3 V Operation
3 V/5 V Operation
ADuM3400, Total Supply Current, Four Channels2
IDDO (Q)
0.29
0.19
0.27 mA
0.35 mA
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD1 (Q)
2.9
1.6
3.5
2.1
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (Q)
0.7
1.2
1.2
1.9
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
5 V/3 V Operation
IDD1 (10)
9.0
4.8
11.6 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
3 V/5 V Operation
7.1
mA
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (10)
1.8
3.0
2.3
5.5
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
5 V/3 V Operation
IDD1 (90)
72
37
100 mA
45 MHz logic signal freq.
45 MHz logic signal freq.
3 V/5 V Operation
54
mA
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (90)
11
19
15
36
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
ADuM3401, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD1 (Q)
2.5
1.4
3.2
1.9
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (Q)
0.9
1.6
1.5
2.4
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
5 V/3 V Operation
IDD1 (10)
7.4
4.1
10.6 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
3 V/5 V Operation
5.6
mA
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (10)
2.5
4.4
3.3
6.5
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
Rev. 0 | Page 8 of 24
ADuM3400/ADuM3401/ADuM3402
Parameter
90 Mbps (CRW Grade Only)
Symbol Min
Typ
Max Unit
Test Conditions
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD1 (90)
59
31
82
44
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (90)
17
32
24
46
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
ADuM3402, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD1 (Q)
2.0
1.2
2.8
1.7
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (Q)
1.2
2.0
1.7
2.8
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
5 V/3 V Operation
IDD1 (10)
6.0
3.3
7.5
4.4
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (10)
3.3
6.0
4.4
7.5
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
5 V/3 V Operation
IDD1 (90)
46
24
62
39
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (90)
24
46
39
62
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC,
IID, IE1, IE2
−10
+0.01
+10 μA
0 ≤ VIA,VIB, VIC,VID ≤ VDD1 or VDD2
0 ≤ VE1,VE2 ≤ VDD1 or VDD2
,
Logic High Input Threshold
5 V/3 V Operation
3 V/5 V Operation
VIH, VEH
2.0
1.6
V
V
Logic Low Input Threshold
5 V/3 V Operation
3 V/5 V Operation
VIL, VEL
0.8
0.4
V
V
V
V
V
V
V
Logic High Output Voltages
VOAH, VOBH, VDD1, VDD2 − 0.1 VDD1, VDD2
VOCH, VODH
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 400 μA, VIx = VIxL
V
DD1, VDD2 − 0.4 VDD1, VDD2 − 0.2
Logic Low Output Voltages
VOAL, VOBL,
VOCL, VODL
0.0
0.04
0.2
0.1
0.1
0.4
I
Ox = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM340xARW
Minimum Pulse Width3
Maximum Data Rate4
PW
1000 ns
Mbps
100 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
50
Propagation Delay5
tPHL, tPLH
PWD
tPSK
70
5
Pulse-Width Distortion, |tPLH − tPHL
|
40
50
50
ns
ns
ns
Propagation Delay Skew6
Channel-to-Channel Matching7
tPSKCD/OD
Rev. 0 | Page 9 of 24
ADuM3400/ADuM3401/ADuM3402
Parameter
Symbol Min
Typ
Max Unit
Test Conditions
ADuM340xBRW
Minimum Pulse Width3
PW
100 ns
Mbps
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Maximum Data Rate4
10
15
Propagation Delay5
tPHL, tPLH
PWD
35
5
50
3
ns
ns
5
Pulse-Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
|
ps/°C
ns
ns
tPSK
tPSKCD
22
3
Channel-to-Channel Matching,
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels7
ADuM340xCRW
Minimum Pulse Width3
Maximum Data Rate4
PW
8.3
120
30
0.5
3
11.1 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
90
20
Propagation Delay5
tPHL, tPLH
PWD
40
2
5
Pulse-Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
|
ns
ps/°C
ns
ns
tPSK
tPSKCD
14
2
Channel-to-Channel Matching,
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels7
For All Models
Output Disable Propagation Delay
(High/Low-to-High Impedance)
Output Enable Propagation Delay
(High Impedance-to-High/Low)
Output Rise/Fall Time (10% to 90%)
5 V/3 V Operation
3 V/5 V Operation
Common-Mode Transient Immunity
at Logic High Output8
Common-Mode Transient Immunity
at Logic Low Output8
tPHZ, tPLH
tPZH, tPZL
tR/tf
6
6
8
8
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
3.0
2.5
35
ns
ns
kV/μs
|CMH|
|CML|
fr
25
25
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
35
kV/μs
transient magnitude = 800 V
Refresh Rate
5 V/3 V Operation
3 V/5 V Operation
Input Dynamic Supply Current per Channel9
1.2
1.1
Mbps
Mbps
IDDI (D)
5 V/3 V Operation
3 V/5 V Operation
0.20
0.10
mA/Mbps
mA/Mbps
Output Dynamic Supply Current per Channel9 IDDO (D)
5 V/3 V Operation
3 V/5 V Operation
0.03
0.05
mA/Mbps
mA/Mbps
Rev. 0 | Page 10 of 24
ADuM3400/ADuM3401/ADuM3402
1 All voltages are relative to their respective ground.
2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3400/ADuM3401/ADuM3402 channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. 0 | Page 11 of 24
ADuM3400/ADuM3401/ADuM3402
PACKAGE CHARACTERISTICS
Table 4.
Parameter
Symbol
RI-O
CI-O
CI
θJCI
Min
Typ
1012
2.2
4.0
33
Max
Unit
Ω
pF
pF
°C/W
°C/W
Test Conditions
Resistance (Input to Output)1
Capacitance (Input to Output)1
Input Capacitance2
f = 1 MHz
IC Junction-to-Case Thermal Resistance, Side 1
IC Junction-to-Case Thermal Resistance, Side 2
Thermocouple located at
center of package underside
θJCO
28
1 Device considered a 2-terminal device; Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, and Pin 8 shorted together and Pin 9, Pin 10, Pin 11, Pin 12, Pin 13, Pin 14, Pin 15, and
Pin 16 shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM340x is approved by the organizations listed in Table 5.
Table 5.
UL1
CSA
VDE2
Recognized under
Approved under
CSA Component Acceptance Notice #5A
Certified according to
1577 component recognition program1
DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-012
Double/reinforced insulation,
2500 V rms isolation voltage
Reinforced insulation per
CSA 60950-1-03 and IEC 60950-1,
400 V rms maximum working voltage
Basic insulation, 560 V peak
Complies with
DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01,
DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000
Reinforced insulation, 560 V peak
File 2471900-4880-0001
File E214100
File 205078
1 In accordance with UL1577, each ADuM340x is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 μA).
2 In accordance with DIN EN 60747-5-2, each ADuM340x is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection limit =
5 pC). The * marking branded on the component designates DIN EN 60747-5-2 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter
Symbol Value
Unit Conditions
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
2500
7.7 min
V rms 1-minute duration
L(I01)
L(I02)
mm
Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage)
8.1 min
mm
Measured from input terminals to output terminals,
shortest distance path along body
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
0.017 min mm
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
CTI
>175
IIIa
V
Rev. 0 | Page 12 of 24
ADuM3400/ADuM3401/ADuM3402
DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS
Table 7.
Description
Symbol
Characteristic
Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤150 V rms
For Rated Mains Voltage ≤300 V rms
For Rated Mains Voltage ≤400 V rms
Climatic Classification
I-IV
I-III
I-II
40/105/21
Pollution Degree (DIN VDE 0110, Table 1)
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method b1
VIORM × 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC
Input-to-Output Test Voltage, Method a
After Environmental Tests Subgroup 1
VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC
After Input and/or Safety Test Subgroup 2/3
VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec)
Safety-Limiting Values (Maximum Value Allowed in the Event of a Failure; also see Figure 4)
Case Temperature
2
560
1050
VIORM
VPR
V peak
V peak
VPR
896
V peak
V peak
V peak
672
VTR
4000
TS
IS1
IS2
RS
150
265
335
>109
°C
Side 1 Current
Side 2 Current
Insulation Resistance at TS, VIO = 500 V
mA
mA
Ω
These isolators are suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The * marking on packages denotes DIN EN 60747-5-2 approval.
350
RECOMMENDED OPERATING CONDITIONS
300
Table 8.
250
Parameter
Symbol Min Max Unit
TA −40 +105 °C
SIDE #2
200
150
100
50
Operating Temperature
Supply Voltages1
Input Signal Rise and Fall Times
VDD1, VDD 2 2.7 5.5
1.0
V
ms
SIDE #1
1 All voltages are relative to their respective ground. See the DC Correctness
and Magnetic Field Immunity section for information on immunity to
external magnetic fields.
0
0
50
100
CASE TEMPERATURE (°C)
150
200
Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per DIN EN 60747-5-2
Rev. 0 | Page 13 of 24
ADuM3400/ADuM3401/ADuM3402
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 9.
Parameter
Symbol
Min
−65
−40
−0.5
−0.5
−0.5
Max
Unit
°C
°C
V
V
V
Storage Temperature
Ambient Operating Temperature
Supply Voltages1
Input Voltage1, 2
Output Voltage1, 2
Average Output Current per Pin3
Side 1
TST
TA
+150
+105
+7.0
VDDI + 0.5
VDDO + 0.5
VDD1, VDD2
VIA, VIB, VIC, VID, VE1,VE2
VOA, VOB, VOC, VOD
IO1
−18
+18
mA
Side 2
IO2
CMH, CML
−22
−100
+22
+100
mA
kV/μs
Common-Mode Transients4
1 All voltages are relative to their respective ground.
2 VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the PC Board Layout section.
3 See Figure 4 for maximum rated current values for various temperatures.
4 Refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Ratings can cause latch-up or
permanent damage.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Table 10. Truth Table (Positive Logic)
VIX Input1 VEX Input2 VDDI State1 VDDO State1 VOX Output1
Notes
H
L
X
X
X
X
H or NC
H or NC
L
H or NC
L
X
Powered
Powered
Powered
Unpowered Powered
Unpowered Powered
Powered
Powered
Powered
H
L
Z
H
Z
Outputs return to the input state within 1 μs of VDDI power restoration.
Powered
Unpowered Indeterminate Outputs return to the input state within 1 μs of VDDO power restoration
if VEX state is H or NC. Outputs return to high impedance state within
8 ns of VDDO power restoration if VEX state is L.
1 VIX and VOX refer to the input and output signals of a given channel (A, B, C, or D). VEX refers to the output enable signal on the same side as the VOX outputs. VDDI and
DDO refer to the supply voltages on the input and output sides of the given channel, respectively.
2 In noisy environments, connecting VEX to an external logic high or low is recommended.
V
Rev. 0 | Page 14 of 24
ADuM3400/ADuM3401/ADuM3402
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
1
2
3
4
5
6
7
8
16
V
DD2
DD1
*GND
15 GND *
1
IA
IB
IC
ID
2
V
V
V
V
14
13
12
11
10
9
V
V
V
V
V
OA
OB
OC
OD
E2
ADuM3400
TOP VIEW
(Not to Scale)
NC
*GND
GND *
1
2
NC = NO CONNECT
Figure 5. ADuM3400 Pin Configuration
*Pin 2 and Pin 8 are internally connected and connecting both to GND1 is recommended. Pin 9 and Pin 15 are internally connected and
connecting both to GND2 is recommended. In noisy environments, connecting output enables (Pin 7 for ADuM3401/ADuM3402 and
Pin 10 for all models) to an external logic high or low is recommended.
Table 11. ADuM3400 Pin Function Descriptions
Pin No. Mnemonic Description
1
2, 8
3
VDD1
GND1
VIA
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
Ground 1. Ground Reference for Isolator Side 1.
Logic Input A.
4
VIB
Logic Input B.
5
VIC
Logic Input C.
6
VID
Logic Input D.
7
NC
No Connect.
9, 15
10
GND2
VE2
Ground 2. Ground reference for Isolator Side 2.
Output Enable 2. Active high logic input. VOA, VOB, VOC, and VOD outputs are enabled when VE2 is high or disconnected.
VOA, VOB, VOC, and VOD outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic
high or low is recommended.
11
12
13
14
16
VOD
VOC
VOB
VOA
VDD2
Logic Output D.
Logic Output C.
Logic Output B.
Logic Output A.
Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.
Rev. 0 | Page 15 of 24
ADuM3400/ADuM3401/ADuM3402
V
1
2
3
4
5
6
7
8
16
V
DD2
DD1
*GND
15 GND *
1
IA
IB
IC
2
V
V
V
14
13
12
11
10
9
V
V
V
V
V
OA
OB
OC
ID
ADuM3401
TOP VIEW
(Not to Scale)
V
OD
V
E1
E2
*GND
GND *
1
2
NC = NO CONNECT
Figure 6. ADuM3401 Pin Configuration
*Pin 2 and Pin 8 are internally connected and connecting both to GND1 is recommended. Pin 9 and Pin 15 are internally connected and
connecting both to GND2 is recommended. In noisy environments, connecting output enables (Pin 7 for ADuM3401/ADuM3402 and
Pin 10 for all models) to an external logic high or low is recommended.
Table 12. ADuM3401 Pin Function Descriptions
Pin No. Mnemonic Description
1
2, 8
3
VDD1
GND1
VIA
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
Ground 1. Ground reference for Isolator Side 1.
Logic Input A.
4
VIB
Logic Input B.
5
VIC
Logic Input C.
6
7
VOD
VE1
Logic Output D.
Output Enable 1. Active high logic input. VOD output is enabled when VE1 is high or disconnected. VOD is disabled when
VE1 is low. In noisy environments, connecting VE1 to an external logic high or low is recommended.
9, 15
10
GND2
VE2
Ground 2. Ground reference for isolator Side 2.
Output Enable 2. Active high logic input. VOA, VOB, and VOC outputs are enabled when VE2 is high or disconnected.
VOA, VOB, and VOC outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high
or low is recommended.
11
12
13
14
16
VID
Logic Input D.
Logic Output C.
Logic Output B.
Logic Output A.
VOC
VOB
VOA
VDD2
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
Rev. 0 | Page 16 of 24
ADuM3400/ADuM3401/ADuM3402
V
1
2
3
4
5
6
7
8
16
V
DD2
DD1
*GND
15 GND *
1
2
V
14
13
12
11
10
9
V
V
V
V
V
IA
OA
OB
IC
ADuM3402
V
IB
TOP VIEW
(Not to Scale)
V
V
OC
OD
ID
V
E1
E2
*GND
GND *
1
2
NC = NO CONNECT
Figure 7. ADuM3402 Pin Configuration
*Pin 2 and Pin 8 are internally connected and connecting both to GND1 is recommended. Pin 9 and Pin 15 are internally connected and
connecting both to GND2 is recommended. In noisy environments, connecting output enables (Pin 7 for ADuM3401/ADuM3402 and
Pin 10 for all models) to an external logic high or low is recommended.
Table 13. ADuM3402 Pin Function Descriptions
Pin No. Mnemonic Description
1
2, 8
3
VDD1
GND1
VIA
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
Ground 1. Ground reference for Isolator Side 1.
Logic Input A.
4
VIB
Logic Input B.
5
6
7
VOC
VOD
VE1
Logic Output C.
Logic Output D.
Output Enable 1. Active high logic input. VOC and VOD outputs are enabled when VE1 is high or disconnected.
VOC and VOD outputs are disabled when VE1 is low. In noisy environments, connecting VE1 to an external logic high or
low is recommended.
9, 15
10
GND2
VE2
Ground 2. Ground reference for isolator Side 2.
Output Enable 2. Active high logic input. VOA and VOB outputs are enabled when VE2 is high or disconnected.
VOA and VOB outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or
low is recommended.
11
12
13
14
16
VID
VIC
VOB
VOA
VDD2
Logic Input D.
Logic Input C.
Logic Output B.
Logic Output A.
Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.
Rev. 0 | Page 17 of 24
ADuM3400/ADuM3401/ADuM3402
TYPICAL PERFORMANCE CHARACTERISTICS
20
80
60
40
15
5V
10
5V
3V
3V
5
20
0
0
0
20
40
60
80
100
0
20
40
60
80
100
100
100
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 8. Typical Input Supply Current per Channel vs. Data Rate (No Load)
Figure 11. Typical ADuM3400 VDD1 Supply Current vs.
Data Rate for 5 V and 3 V Operation
20
80
60
40
15
10
5
20
0
5V
5V
3V
3V
0
0
20
40
60
80
100
0
20
40
60
80
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 9. Typical Output Supply Current per Channel vs. Data Rate (No Load)
Figure 12. Typical ADuM3400 VDD2 Supply Current vs.
Data Rate for 5 V and 3 V Operation
20
80
60
40
15
10
5V
5V
5
20
0
3V
3V
0
0
20
40
60
80
100
0
20
40
60
80
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 10. Typical Output Supply Current per Channel vs.
Data Rate (15 pF Output Load)
Figure 13. Typical ADuM3401 VDD1 Supply Current vs.
Data Rate for 5 V and 3 V Operation
Rev. 0 | Page 18 of 24
ADuM3400/ADuM3401/ADuM3402
40
35
30
25
80
60
40
3V
5V
20
0
5V
3V
–50
–25
0
25
50
75
100
0
20
40
60
80
100
TEMPERATURE (°C)
DATA RATE (Mbps)
Figure 14. Typical ADuM3401 VDD2 Supply Current vs.
Data Rate for 5 V and 3 V Operation
Figure 16. Propagation Delay vs. Temperature, C Grade
80
60
40
5V
20
0
3V
0
20
40
60
80
100
DATA RATE (Mbps)
Figure 15. Typical ADuM3402 VDD1 or VDD2 Supply Current vs.
Data Rate for 5 V and 3 V Operation
Rev. 0 | Page 19 of 24
ADuM3400/ADuM3401/ADuM3402
APPLICATION INFORMATION
While the ADuM340x improve system-level ESD reliability,
they are no substitute for a robust system-level design. See
Application Note AN-793 ESD/Latch-Up Considerations with
iCoupler Isolation Products for detailed recommendations on
board layout and system-level design.
PC BOARD LAYOUT
The ADuM340x digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins (see
Figure 17). Bypass capacitors are most conveniently connected
between Pin 1 and Pin 2 for VDD1 and between Pin 15 and
Pin 16 for VDD2. The capacitor value should be between 0.01 μF
and 0.1 μF. The total lead length between both ends of the
capacitor and the input power supply pin should not exceed
20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9
and Pin 16 should also be considered unless the ground pair on
each package side is connected close to the package.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output can differ from the propagation
delay to a logic high.
INPUT (V
)
50%
IX
V
GND
V
DD1
DD2
GND
tPLH
tPHL
1
IA
IB
2
V
V
V
V
V
V
V
OA
OB
OUTPUT (V
)
50%
OX
V
V
IC/OC
ID/OD
OC/IC
OD/ID
E2
Figure 18. Propagation Delay Parameters
V
E1
GND
GND
1
2
Pulse-width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the input signal’s timing is preserved.
Figure 17. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, care
should be taken to ensure that board coupling across the isolation
barrier is minimized. Furthermore, the board layout should be
designed such that any coupling that does occur equally affects
all pins on a given component side. Failure to ensure this could
cause voltage differentials between pins exceeding the device’s
Absolute Maximum Ratings, thereby leading to latch-up or
permanent damage.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM340x component.
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM340x
components operating under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
SYSTEM-LEVEL ESD CONSIDERATIONS AND
ENHANCEMENTS
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is, therefore, either set or reset by
the pulses, indicating input logic transitions. In the absence of
logic transitions at the input for more than 2 μs, a periodic set
of refresh pulses indicative of the correct input state are sent to
ensure dc correctness at the output. If the decoder receives no
internal pulses of more than about 5 μs, the input side is
assumed to be unpowered or nonfunctional, in which case the
isolator output is forced to a default state (see Table 10) by the
watchdog timer circuit.
System-level ESD reliability (for example, per IEC 61000-4-x) is
highly dependent on system design which varies widely by
application. The ADuM340x incorporate many enhancements
to make ESD reliability less dependent on system design. The
enhancements include:
• ESD protection cells added to all input/output interfaces.
• Key metal trace resistances reduced using wider geometry
and paralleling of lines with vias.
• The SCR effect inherent in CMOS devices minimized by use
of guarding and isolation technique between PMOS and
NMOS devices.
The limitation on the ADuM340x’s magnetic field immunity is
set by the condition in which induced voltage in the transformer’s
receiving coil is sufficiently large to either falsely set or reset the
decoder. The following analysis defines the conditions under
which this can occur. The 3 V operating condition of the
ADuM340x is examined because it represents the most
susceptible mode of operation.
• Areas of high electric field concentration eliminated using
45° corners on metal traces.
• Supply pin overvoltage prevented with larger ESD clamps
between each supply pin and its respective ground.
Rev. 0 | Page 20 of 24
ADuM3400/ADuM3401/ADuM3402
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances from the
ADuM340x transformers. Figure 20 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As shown, the ADuM340x is extremely immune and
can be affected only by extremely large currents operated at
high frequency very close to the component. For the 1 MHz
example noted, one would have to place a 0.5 kA current 5 mm
away from the ADuM340x to affect the component’s operation.
2
V = (−dβ/dt)∑∏rn ; n = 1, 2, … , N
where:
β is magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
1000
DISTANCE = 1m
Given the geometry of the receiving coil in the ADuM340x and
an imposed requirement that the induced voltage be at most
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated as shown in Figure 19.
100
10
DISTANCE = 100mm
100
1
DISTANCE = 5mm
10
0.1
1
0.01
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
0.1
Figure 20. Maximum Allowable Current
for Various Current-to-ADuM340x Spacings
0.01
Note that at combinations of strong magnetic field and high
frequency, any loops formed by printed circuit board traces
could induce error voltages sufficiently large enough to trigger
the thresholds of succeeding circuitry. Care should be taken in
the layout of such traces to avoid this possibility.
0.001
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 19. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event were to occur during a transmitted
pulse (and was of the worst-case polarity), it would reduce the
received pulse from >1.0 V to 0.75 V—still well above the 0.5 V
sensing threshold of the decoder.
Rev. 0 | Page 21 of 24
ADuM3400/ADuM3401/ADuM3402
POWER CONSUMPTION
The supply current at a given channel of the ADuM340x
isolator is a function of the supply voltage, the channel’s data
rate, and the channel’s output load.
For each input channel, the supply current is given by
IDDI = IDDI (Q)
DDI = IDDI (D) × (2f − fr) + IDDI (Q)
f ≤ 0.5 fr
f > 0.5 fr
I
For each output channel, the supply current is given by
IDDO = IDDO (Q) f ≤ 0.5 fr
I
DDO = (IDDO (D) + (0.5 × 10−3) × CL × VDDO) × (2f − fr) + IDDO (Q)
f > 0.5 fr
where:
DDI (D), IDDO (D) are the input and output dynamic supply currents
I
per channel (mA/Mbps).
CL is the output load capacitance (pF).
V
DDO is the output supply voltage (V).
f is the input logic signal frequency (MHz); it is half of the input
data rate expressed in units of Mbps.
fr is the input stage refresh rate (Mbps).
I
DDI (Q), IDDO (Q) are the specified input and output quiescent
supply currents (mA).
To calculate the total IDD1 and IDD2 supply current, the supply
currents for each input and output channel corresponding to
VDD1 and VDD2 are calculated and totaled. Figure 8 provides per-
channel input supply current as a function of data rate. Figure 9
and Figure 10 provide per-channel supply output current as a
function of data rate for an unloaded output condition and for a
15 pF output condition, respectively. Figure 11 through Figure 15
provide total VDD1 and VDD2 supply current as a function of data
rate for ADuM3400/ADuM3401/ADuM3402 channel
configurations.
Rev. 0 | Page 22 of 24
ADuM3400/ADuM3401/ADuM3402
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
16
1
9
8
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
1.27 (0.0500)
BSC
0.75 (0.0295)
× 45°
2.65 (0.1043)
2.35 (0.0925)
0.25 (0.0098)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 21. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Number of Number of Maximum Maximum
Maximum
Inputs,
DD1 Side
Inputs,
DD2 Side
Data Rate Propagation
(Mbps)
Pulse-Width
Package
Model
Temperature Range (°C)
V
V
Delay, 5 V (ns) Distortion (ns) Option1
ADuM3400ARWZ 2, 3 −40 to +105
ADuM3400BRWZ2, 3 −40 to +105
ADuM3400CRWZ2, 3 −40 to +105
ADuM3401ARWZ2, 3 −40 to +105
ADuM3401BRWZ2, 3 −40 to +105
ADuM3401CRWZ2, 3 −40 to +105
ADuM3402ARWZ2, 3 −40 to +105
ADuM3402BRWZ2, 3 −40 to +105
ADuM3402CRWZ2, 3 −40 to +105
4
0
1
100
50
32
40
3
2
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
4
4
3
3
3
2
2
2
0
0
1
1
1
2
2
2
10
90
1
10
90
1
100
50
32
40
3
2
100
50
32
40
3
2
10
90
1 RW-16 = 16-lead wide body SOIC.
2 Tape and reel are available. The addition of an “-RL” suffix designates a 13” (1,000 units) tape and reel option.
3 Z = Pb-free part.
Rev. 0 | Page 23 of 24
ADuM3400/ADuM3401/ADuM3402
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05985-0-3/06(0)
Rev. 0 | Page 24 of 24
相关型号：
©2020 ICPDF网 联系我们和版权申明