ADUM3224WCRZ-RL7 [ADI]
Isolated Precision Half-Bridge Driver, 4 A Output;
| 型号： | ADUM3224WCRZ-RL7 |
| 厂家： | 
ADI |
| 描述： | Isolated Precision Half-Bridge Driver, 4 A Output |
| 文件： | 总19页 (文件大小：561K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Isolated Precision Half-Bridge Driver,
4 A Output
Data Sheet
ADuM3224/ADuM4224
FEATURES
FUNCTIONAL BLOCK DIAGRAM
4 A peak output current
ADuM3224/
Working voltage
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
V
V
V
IA
DDA
OA
ADuM4224
High-side or low-side relative to input: 537 V peak
High frequency operation: 1 MHz maximum
3.3 V to 5 V CMOS input logic
4.5 V to 18 V output drive
Secondary UVLO
ADuM3224A/ADuM4224A UVLO at 4.1 V VDDA/VDDB
ADuM3224B/ADuM4224B UVLO at 6.9 V VDDA/VDDB
ADuM3224C/ADuM4224C UVLO at 10.5 V VDDA/VDDB
Precise timing characteristics
59 ns maximum isolator and driver propagation delay
5 ns maximum channel-to-channel matching
CMOS input logic levels
ENCODE
DECODE
IB
V
GND
NC
NC
V
DD1
A
GND
1
DISABLE
NC
DDB
ENCODE
DECODE
NC
V
OB
V
GND
B
DD1
NC = NO CONNECT
High common-mode transient immunity: >25 kV/μs
Enhanced system-level ESD performance per IEC 61000-4-x
High junction temperature operation: 125°C
Default low output
Safety and regulatory approvals
ADuM3224 narrow-body, 16-lead SOIC
UL recognition per UL 1577
Figure 1.
GENERAL DESCRIPTION
TheADuM3224/ADuM42241 are 4 A isolated, half-bridge gate
drivers that employ the Analog Devices, Inc., iCoupler® technology
to provide independent and isolated high-side and low-side
outputs. The ADuM3224 provides 3000 V rms isolation in the
narrow-body, 16-lead SOIC package, and the ADuM4224 provides
5000 V rms isolation in the wide-body, 16-lead SOIC package.
Combining high speed CMOS and monolithic transformer
technology, these isolation components provide outstanding
performance characteristics superior to the alternatives, such as
the combination of pulse transformers and gate drivers.
3000 V rms for 1 minute SOIC long package
CSA Component Acceptance Notice 5A
VDE certificate of conformity (pending)
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
V
IORM = 560 V peak
ADuM4224 wide-body, 16-lead SOIC
UL recognition per UL 1577
The ADuM3224/ADuM4224 isolators each provide two
independent isolated channels. They operate with an input
supply ranging from 3.0 V to 5.5 V, providing compatibility
with lower voltage systems. In comparison to gate drivers
employing high voltage level translation methodologies, the
ADuM3224/ADuM4224 offer the benefit of true, galvanic
isolation between the input and each output. Each output can
be continuously operated up to 537 V peak relative to the input,
thereby supporting low-side switching to negative voltages. The
differential voltage between the high-side and low-side can be as
high as 800 V peak.
5000 V rms for 1 minute SOIC long package
CSA Component Acceptance Notice 5A
VDE certificate of conformity (pending)
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 849 V peak
Qualified for automotive applications
APPLICATIONS
Switching power supplies
Isolated IGBT/MOSFET gate drives
Industrial inverters
As a result, the ADuM3224/ADuM4224 provide reliable control
over the switching characteristics of IGBT/MOSFET configurations
over a wide range of positive or negative switching voltages.
1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,239. Other patents pending.
Rev. B
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Tel: 781.329.4700 ©2013–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADuM3224/ADuM4224
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 11
Applications Information.............................................................. 14
Printed Circuit Board Layout ................................................... 14
Undervoltage Lockout ............................................................... 14
Propagation Delay-Related Parameters................................... 14
Thermal Limitations and Switch Load Characteristics......... 14
Output Load Characteristics..................................................... 14
Bootstrapped Half-Bridge Operation...................................... 15
DC Correctness and Magnetic Field Immunity .......................... 15
Power Consumption .................................................................. 17
Insulation Lifetime..................................................................... 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 19
Automotive Products................................................................. 19
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—5 V Operation................................ 3
Electrical Characteristics—3.3 V Operation ............................. 4
Package Characteristics ............................................................... 5
Insulation and Safety Related Specifications ............................ 5
Regulatory Information............................................................... 6
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics .............................................................................. 7
Recommended Operating Conditions ...................................... 8
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
REVISION HISTORY
11/15—Rev. A to Rev. B
Changes to Power Consumption Section.................................... 17
11/14—Rev. 0 to Rev. A
Changes to Features Section and General Description
Section................................................................................................ 1
Changes to Table 5............................................................................ 5
Changes to Regulatory Information Section, Table 6, and
Table 7 ................................................................................................ 6
Changes to Table 8 and Table 9....................................................... 7
12/13—Revision 0: Initial Version
Rev. B | Page 2 of 19
Data Sheet
ADuM3224/ADuM4224
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDDA ≤ 18 V, 4.5 V ≤ VDDB ≤ 1 8 V, unless stated otherwise.
All minimum/maximum specifications apply over TJ = −40°C to +125°C. All typical specifications are at TJ = 25°C, VDD1 = 5 V, V DDA
DDB = 12 V. Switching specifications are tested with CMOS signal levels.
=
V
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
DC SPECIFICATIONS
Input Supply Current, Quiescent
Output Supply Current, Per Channel, Quiescent
Supply Current at 1 MHz
VDD1 Supply Current
IDDI(Q)
1.4
2.3
2.4
3.2
mA
mA
IDDO(Q)
IDD1(Q)
1.6
5.6
2.5
8.0
mA
mA
µA
V
Up to 1 MHz, no load
Up to 1 MHz, no load
0 V ≤ VIA, VIB ≤ VDD1
VDDA/VDDB Supply Current
Input Currents
IDDA(Q)/IDDB(Q)
IIA, IIB
−1
+0.01 +1
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
VIH
0.7 × VDD1
VIL
0.3 × VDD1
0.15
V
VOAH, VOBH
VDDA
V
/
VDDA
DDB − 0.1 VDDB
/
V
IOx = −20 mA, VIx = VIxH
IOx = +20 mA, VIx = VIxL
Logic Low Output Voltages
Undervoltage Lockout, VDDA/VDDB Supply
A Grade
VOAL, VOBL
0.0
V
Positive Going Threshold
Negative Going Threshold
Hysteresis
VDDAUV+, VDDBUV+
VDDAUV−, VDDBUV−
VDDAUVH, VDDBUVH
4.1
4.4
V
V
V
3.2
5.7
8.9
3.6
0.5
B Grade
Positive Going Threshold
Negative Going Threshold
Hysteresis
VDDAUV+, VDDBUV+
VDDAUV−, VDDBUV−
VDDAUVH, VDDBUVH
6.9
6.2
0.7
7.4
V
V
V
C Grade
Positive Going Threshold
Negative Going Threshold
Hysteresis
VDDAUV+, VDDBUV+
VDDAUV−, VDDBUV−
VDDAUVH, VDDBUVH
IOA(SC), IOB(SC)
ROA, ROB
10.5
9.6
0.9
4.0
1.1
0.6
11.1
V
V
V
Output Short-Circuit Pulsed Current1
Output Pulsed Source Resistance
Output Pulsed Sink Resistance
SWITCHING SPECIFICATIONS
Pulse Width2
Maximum Data Rate3
Propagation Delay4
2.0
0.3
0.3
A
Ω
Ω
VDDA/VDDB = 12 V
VDDA/VDDB = 12 V
VDDA/VDDB = 12 V
3.0
3.0
ROA, ROB
PW
50
1
ns
CL = 2 nF, VDDA/VDDB = 12 V
CL = 2 nF, VDDA/VDDB = 12 V
MHz
ns
tDHL, tDLH
tDHL, tDLH
tPSK
31
35
43
47
54
59
12
5
CL = 2 nF, VDDA/VDDB = 12 V; see Figure 20
CL = 2 nF, VDDA/VDDB = 4.5 V; see Figure 20
CL = 2 nF, VDDA/VDDB = 12 V; see Figure 20
CL = 2 nF, VDDA/VDDB = 12 V; see Figure 20
CL = 2 nF, VDDA/VDDB = 4.5 V; see Figure 20
CL = 2 nF, VDDA/VDDB = 12 V; see Figure 20
ADuM3224A/ADuM4224A
Propagation Delay Skew5
Channel-to-Channel Matching6
ns
ns
tPSKCD
tPSKCD
tR/tF
1
ns
1
7
ns
Output Rise/Fall Time (10% to 90%)
Dynamic Input Supply Current Per Channel
Dynamic Output Supply Current Per Channel
Refresh Rate
6
12
18
ns
IDDI(D)
IDDO(D)
fr
0.05
1.65
1.2
mA/Mbps VDDA/VDDB = 12 V
mA/Mbps VDDA/VDDB = 12 V
Mbps
1 Short-circuit duration less than 1 µs. Average power must conform to the limit shown in the Absolute Maximum Ratings section.
2 The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed.
4 The tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% level of the VOx signal. The tDHL propagation
delay is measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOx signal. See Figure 20 for waveforms of propagation
delay parameters.
5 tPSK is the magnitude of the worst-case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions. See Figure 20 for waveforms of propagation delay parameters.
6 Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels.
Rev. B | Page 3 of 19
ADuM3224/ADuM4224
Data Sheet
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All voltages are relative to their respective ground. 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDDA ≤ 18 V, 4.5 V ≤ VDDB ≤ 1 8 V, unless stated otherwise.
All minimum/maximum specifications apply over TJ = −40°C to +125°C. All typical specifications are at TJ = 25°C, VDD1 = 3.3 V, VDDA
DDB = 12 V. Switching specifications are tested with CMOS signal levels.
=
V
Table 2.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
DC SPECIFICATIONS
Input Supply Current, Quiescent
Output Supply Current, Per Channel, Quiescent
Supply Current at 1 MHz
VDD1 Supply Current
IDDI(Q)
0.87
2.3
1.4
3.2
mA
mA
IDDO(Q)
IDD1(Q)
1.1
5.6
1.5
8.0
mA
mA
µA
V
Up to 1 MHz, no load
Up to 1 MHz, no load
0 V ≤ VIA, VIB ≤ VDD1
VDDA/VDDB Supply Current
Input Currents
IDDA(Q)/IDDB(Q)
IIA, IIB
−10
+0.01 +10
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
VIH
0.7 × VDD1
VIL
0.3 × VDD1
0.15
V
VOAH, VOBH
VDDA
/
VDDA
/
V
IOx = −20 mA, VIx = VIxH
VDDB − 0.1 VDDB
Logic Low Output Voltages
Undervoltage Lockout, VDDA/VDDB Supply
A Grade
VOAL, VOBL
0.0
V
IOx = +20 mA, VIx = VIxL
Positive Going Threshold
Negative Going Threshold
Hysteresis
VDDAUV+, VDDBUV+
4.1
4.4
V
V
V
VDDAUV−, VDDBUV− 3.2
VDDAUVH, VDDBUVH
3.6
0.5
B Grade
Positive Going Threshold
Negative Going Threshold
Hysteresis
VDDAUV+, VDDBUV+
6.9
6.2
0.7
7.4
V
V
V
VDDAUV−, VDDBUV− 5.7
VDDAUVH, VDDBUVH
C Grade
Positive Going Threshold
Negative Going Threshold
Hysteresis
VDDAUV+, VDDBUV+
10.5
9.6
0.9
4.0
1.1
0.6
11.1
V
VDDAUV−, VDDBUV− 8.9
VDDAUVH, VDDBUVH
IOA(SC), IOB(SC)
ROA, ROB
V
V
Output Short-Circuit Pulsed Current1
Output Pulsed Source Resistance
Output Pulsed Sink Resistance
SWITCHING SPECIFICATIONS
Pulse Width2
Maximum Data Rate3
Propagation Delay4
2.0
0.3
0.3
A
Ω
Ω
VDDA/VDDB = 12 V
VDDA/VDDB = 12 V
VDDA/VDDB = 12 V
3.0
3.0
ROA, ROB
PW
50
1
ns
CL = 2 nF, VDDA/VDDB = 12 V
CL = 2 nF, VDDA/VDDB = 12 V
MHz
ns
tDHL, tDLH
tDHL, tDLH
tPSK
35
37
47
51
59
65
12
5
CL = 2 nF, VDDA/VDDB = 12 V, see Figure 20
CL = 2 nF, VDDA/VDDB = 4.5 V,see Figure 20
CL = 2 nF, VDDA/VDDB = 12 V, see Figure 20
CL = 2 nF, VDDA/VDDB = 12 V, see Figure 20
CL = 2 nF, VDDA/VDDB = 4.5 V, see Figure 20
CL = 2 nF, VDDA/VDDB = 12 V, see Figure 20
ADuM3224A/ADuM4224A
Propagation Delay Skew5
Channel-to-Channel Matching6
ns
ns
tPSKCD
tPSKCD
tR/tF
1
ns
1
7
ns
Output Rise/Fall Time (10% to 90%)
6
12
22
ns
Dynamic Input Supply Current Per Channel
IDDI(D)
0.05
1.65
1.1
mA/Mbps VDDA/VDDB = 12 V
mA/Mbps VDDA/VDDB = 12 V
Mbps
Dynamic Output Supply Current Per Channel IDDO(D)
Refresh Rate fr
1 Short-circuit duration less than 1 µs. Average power must conform to the limit shown in the Absolute Maximum Ratings section.
2 The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed.
4 The tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% level of the VOx signal. The tDHL propagation
delay is measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOx signal. See Figure 20 for waveforms of propagation
delay parameters.
5 tPSK is the magnitude of the worst-case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions. See Figure 20 for waveforms of propagation delay parameters.
6 Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels.
Rev. B | Page 4 of 19
Data Sheet
ADuM3224/ADuM4224
PACKAGE CHARACTERISTICS
Table 3.
Parameter
Symbol
RI-O
CI-O
Min
Typ
1012
2.0
Max
Unit
Ω
pF
Test Conditions/Comments
Resistance (Input-to-Output)
Capacitance (Input-to-Output)
Input Capacitance
f = 1 MHz
CI
4.0
pF
IC Junction-to-Ambient Thermal Resistance
ADuM3224
ADuM4224
θJA
θJA
76
45
°C/W
°C/W
IC Junction-to-Case Thermal Resistance
ADuM3224
ADuM4224
θJC
θJC
42
29
°C/W
°C/W
INSULATION AND SAFETY RELATED SPECIFICATIONS
ADuM3224 Specifications
Table 4.
Parameter
Symbol Value
Unit
Test Conditions/Comments
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
3000
4.0 min
V rms 1 minute duration
L(I01)
L(I02)
mm
Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage)
4.0 min
mm
Measured from input terminals to output terminals,
shortest distance path along body
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
0.017 min mm
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
CTI
>400
II
V
ADuM4224 Specifications
Table 5.
Parameter
Symbol Value
Unit
Test Conditions/Comments
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
5000
7.6 min
V rms 1 minute duration
L(I01)
L(I02)
mm
Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage)
7.6 min
mm
Measured from input terminals to output terminals,
shortest distance path along body
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
0.017 min mm
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
CTI
>400
II
V
Rev. B | Page 5 of 19
ADuM3224/ADuM4224
Data Sheet
REGULATORY INFORMATION
The ADuM3224 is approved or pending approval by the organizations listed in Table 6.
Table 6.
UL
CSA
VDE (Pending)
Recognized under UL 1577
Component Recognition
Program1
Approved under CSA Component Acceptance Notice 5A
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10): 2006-122
Single/Protection 3000 V rms
Isolation Voltage
File E214100
Basic insulation per CSA 60950-1-07 and IEC 60950-1,
380 V rms (537 V peak) maximum working voltage
File 205078
Reinforced insulation, 560 V peak
File 2471900-4880-0001
1 In accordance with UL 1577, each ADuM3224 is proof tested by applying an insulation test voltage ≥ 3600 V rms for 1 second (current leakage detection limit = 6 µA).
2 In accordance with DIN V VDE V 0884-10, each ADuM3224 is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial discharge detection
limit = 5 pC). An asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.
The ADuM4224 is approved or pending approval by the organizations listed in Table 7.
Table 7.
UL
CSA
VDE (Pending)
Recognized under UL 1577
Component Recognition
Program1
Approved under CSA Component Acceptance Notice 5A
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10): 2006-122
Single/Protection 5000 V rms
Isolation Voltage
Reinforced insulation per CSA 60950-1-07 and IEC 60950-1,
380 V rms (537 V peak) maximum working voltage
Basic insulation per CSA 60950-1-07 and IEC 60950-1,
760 V rms (1074 V peak) maximum working voltage
Reinforced insulation, 849 V peak
File E214100
File 205078
File 2471900-4880-0001
1 In accordance with UL 1577, each ADuM4224 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 10 µA).
2 In accordance with DIN V VDE V 0884-10, each ADuM4224 is proof tested by applying an insulation test voltage ≥ 1590 V peak for 1 second (partial discharge detection
limit = 5 pC). An asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.
Rev. B | Page 6 of 19
Data Sheet
ADuM3224/ADuM4224
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for a 560 Vpeak working voltage.
Table 8. ADuM3224 VDE Characteristics (Pending)
Description
Test Conditions/Comments
Symbol Characteristic
Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method B1
I to IV
I to III
I to II
40/105/21
2
VIORM
Vpd(m)
560
1050
V peak
V peak
VIORM × 1.875 = Vpd(m), 100% production test,
tini = tm = 1 sec, partial discharge < 5 pC
Input-to-Output Test Voltage, Method A
VIORM × 1.5 = Vpd(m), tini = 60 sec,
Vpd(m)
tm = 10 sec, partial discharge < 5 pC
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2 VIORM × 1.2 = Vpd(m), tini = 60 sec,
896
672
V peak
V peak
Vpd(m)
and Subgroup 3
tm = 10 sec, partial discharge < 5 pC
Highest Allowable Overvoltage
Surge Isolation Voltage
Safety-Limiting Values
VIOTM
VIOSM
4242
6000
V peak
V peak
VPEAK = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time
Maximum value allowed in the event of a failure
(see Figure 2)
Maximum Junction Temperature
Safety Total Dissipated Power
Insulation Resistance at TS
TS
PS
RS
150
1.64
>109
°C
W
Ω
VIO = 500 V
Table 9. ADuM4224 VDE Characteristics (Pending)
Description
Test Conditions/Comments
Symbol Characteristic
Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method B1
I to IV
I to III
I to II
40/105/21
2
VIORM
Vpd(m)
849
1592
V peak
V peak
VIORM × 1.875 = Vpd(m), 100% production test,
tini = tm = 1 sec, partial discharge < 5 pC
Input-to-Output Test Voltage, Method A
After Environmental Tests Subgroup 1
VIORM × 1.5 = Vpd(m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
Vpd(m)
1273
1018
V peak
V peak
After Input and/or Safety Test Subgroup 2 VIORM × 1.2 = Vpd(m), tini = 60 sec, tm = 10 sec,
Vpd(m)
and Subgroup 3
partial discharge < 5 pC
Highest Allowable Overvoltage
Surge Isolation Voltage
Safety Limiting Values
VIOTM
VIOSM
7071
6000
V peak
V peak
VPEAK = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time
Maximum value allowed in the event of a failure
(see Figure 3)
Maximum Junction Temperature
Safety Total Dissipated Power
Insulation Resistance at TS
TS
PS
RS
150
2.77
>109
°C
W
Ω
VIO = 500 V
Rev. B | Page 7 of 19
ADuM3224/ADuM4224
Data Sheet
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
RECOMMENDED OPERATING CONDITIONS
Table 10.
Parameter
Symbol
Rating
Operating Junction
Temperature
Supply Voltages1
TJ
−40°C to +125°C
VDD1
VDDA, VDDB
tVDD1
3.0 V to 5.5 V
4.5 V to 18 V
1 V/µs
VDD1 Rise Time
VDDA, VDDB Rise Time
tVDDA, tVDDB
10 V/µs
Maximum Input Signal
Rise and Fall Times
t
VIA, tVIB
1 ms
Common-Mode Transient,
Static2
Common-Mode Transient
Immunity, Dynamic3
−50 kV/µs to +50 kV/µs
−25 kV/µs to +25 kV/µs
0
50
100
150
200
AMBIENT TEMPERATURE (°C)
Figure 2. ADuM3224 Thermal Derating Curve, Dependence of
Safety-Limiting Values on Case Temperature, per DIN V VDE V 0884-10
1 All voltages are relative to their respective ground. See the Applications
Information section for information on immunity to external magnetic fields.
2 Static common-mode transient immunity is defined as the largest dv/dt
between GND1 and GNDA/GNDB with inputs held either high or low such that
the output voltage remains either above 0.8 × VDDA/VDDB for VIA/VIB = high, or
0.8 V for VIA/VIB = low. Operation with transients above the recommended
levels can cause momentary data upsets.
3.0
2.5
2.0
1.5
1.0
0.5
0
3 Dynamic common-mode transient immunity is defined as the largest dv/dt
between GND1 and GNDA/GNDB with the switching edge coincident with the
transient test pulse. Operation with transients above the recommended
levels can cause momentary data upsets.
0
50
100
150
200
AMBIENT TEMPERATURE (°C)
Figure 3. ADuM4224 Thermal Derating Curve, Dependence of
Safety-Limiting Values on Case Temperature, per DIN V VDE V 0884-10
Rev. B | Page 8 of 19
Data Sheet
ADuM3224/ADuM4224
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 11.
Parameter
Rating
Storage Temperature (TST)
−55°C to +150°C
Operating Junction Temperature (TJ) −40°C to +150°C
Supply Voltages1
VDD1
VDDA, VDDB
Input Voltage (VIA, VIB, DISABLE)1
Output Voltage1
−0.5 V to +7.0 V
−0.5 V to +20 V
−0.5 V to VDD1 + 0.5 V
ESD CAUTION
VOA
VOB
−0.5 V to VDDA + 0.5 V
−0.5 V to VDDB + 0.5 V
Average Output Current, per Pin (IO)2 −35 mA to +35 mA
Common-Mode Transients
(CMH, CML)3
−100 kV/µs to +100 kV/µs
1 All voltages are relative to their respective ground.
2 See Figure 2 and Figure 3 for information on maximum allowable current for
various temperatures.
3 Refers to common-mode transients across the insulation barrier. Common-
mode transients exceeding the absolute maximum rating can cause
latch-up or permanent damage.
Table 12. Maximum Continuous Working Voltage1
Parameter
Max
Unit
Constraint
AC Voltage, Bipolar Waveform
AC Voltage, Unipolar Waveform
DC Voltage
565
1131
1131
V peak
V peak
V peak
50-year minimum lifetime
50-year minimum lifetime
50-year minimum lifetime
1 Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information.
Table 13. ADuM3224/ADuM4224 (Positive Logic) Truth Table1
VIA
VIB
Input
DISABLE Input
VDD1 State
VDDA/VDDB State
VOA Output
VOB Output
Notes
L
L
L
L
H
L
X
L
L
Powered
Powered
L
L
Outputs return to the input state within
1 µs of DISABLE = L assertion.
Outputs return to the input state within
1 µs of DISABLE = L assertion.
Outputs return to the input state within
1 µs of DISABLE = L assertion.
Outputs return to the input state within
1 µs of DISABLE = L assertion.
Outputs take on default low state
within 3 µs of DISABLE = H assertion.
Outputs return to the input state within
1 µs of VDD1 power restoration.
Outputs return to the input state within
50 µs of VDDA/VDDB power restoration.
L
H
L
Powered
Powered
Powered
Powered
Powered
Powered
Powered
Powered
L
H
L
H
H
X
L
H
H
L
H
X
L
H
L
Unpowered Powered
Powered Unpowered
L
L
X
X
L
L
1 X = don’t care, L = low, and H = high.
Rev. B | Page 9 of 19
ADuM3224/ADuM4224
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
V
1
2
3
4
5
6
7
8
16
15
V
IA
IB
DDA
OA
V
ADuM3224/
ADuM4224
TOP VIEW
(Not to Scale)
V
14 GND
13 NC
12 NC
DD1
A
GND
1
DISABLE
NC
11
10
9
V
V
DDB
NC
OB
V
GND
B
DD1
NOTES
1. NC = NO CONNECT. NOT INTERNALLY CONNECTED.
Figure 4. Pin Configuration
Table 14. ADuM3224/ADuM4224 Pin Function Descriptions
Pin No.1
Mnemonic
Description
Logic Input A.
Logic Input B.
1
2
VIA
VIB
3, 8
4
5
VDD1
GND1
DISABLE
Input Supply Voltage.
Ground Reference for Input Logic Signals.
Input Disable. Disables the isolator inputs and refresh circuits. Outputs take on the default low state within
3 μs of a DISABLE = high assertion. Outputs return to the input state within 1 μs of a DISABLE = low assertion.
6, 7, 12, 13
9
NC
GNDB
VOB
VDDB
GNDA
VOA
No Connect. These pins are not internally connected.
Ground Reference for Output B.
Output B.
Output B Supply Voltage.
Ground Reference for Output A.
Output A.
10
11
14
15
16
VDDA
Output A Supply Voltage.
1 Pin 3 and Pin 8 are internally connected; connecting both pins to the VDD1 supply is recommended.
Rev. B | Page 10 of 19
Data Sheet
ADuM3224/ADuM4224
TYPICAL PERFORMANCE CHARACTERISTICS
1000
800
600
400
200
0
CH2 = V (5V/DIV)
Ox
V
/V
= 5V
DDA DDB
2
V
/V
= 8V
DDA DDB
CH1 = V (5V/DIV)
Ix
V
/V
= 10V
DDA DDB
1
V
/V
= 15V
DDA DDB
CH1 5.00V CH1 5.00V
Ω
M40.0ns
A
CH1
2.70V
0
200
400
600
800
1000
2.50GSPS
100k POINTS
SWITCHING FREQUENCY (kHz)
Figure 8. Typical ADuM4224 Maximum Load vs. Switching Frequency
(RG = 1 Ω)
Figure 5. Output Waveform for 2 nF Load with
12 V Output Supply
3.0
2.5
2.0
a
b
a
b
–820ps
1.40V
10.5ns
∆11.3ns
11.4V
∆10.0V
CH2 = V
(5V/DIV)
OB
V
= 5V
DD1
1.5
1.0
0.5
0
2
V
= 3.3V
DD1
CH1 = V
(5V/DIV)
OA
1
0
0.25
0.50
FREQUENCY (MHz)
0.75
1.00
CH1 5.00V CH2 5.00V
Ω
M20.0ns
2.50GSPS
100k POINTS
A
CH1
2.70V
Figure 9. Typical IDD1 Supply Current vs. Frequency
Figure 6. Output Matching and Rise Time Waveforms for 2 nF Load
with 12 V Output Supply
50
40
30
20
10
0
500
V
V
V
/V
= 15V
= 10V
= 5V
DDA DDB
/V
DDA DDB
400
/V
DDA DDB
V
/V
= 5V
DDA DDB
300
200
100
0
V
/V
= 8V
DDA DDB
V
/V
= 10V
DDA DDB
V
/V
= 15V
DDA DDB
0
200
400
600
800
1000
0
0.25
0.50
FREQUENCY (MHz)
0.75
1.00
SWITCHING FREQUENCY (kHz)
Figure 7. Typical ADuM3224 Maximum Load vs. Switching Frequency
(RG = 1 Ω)
Figure 10. Typical IDDA, IDDB Supply Current vs. Frequency with 2 nF Load
Rev. B | Page 11 of 19
ADuM3224/ADuM4224
Data Sheet
60
50
40
30
20
10
0
30
25
20
15
10
5
tDHL
tDLH
FALL TIME
RISE TIME
0
–40
–20
0
20
40
60
80
100
120
140
5
7
9
11
13
15
17
JUNCTION TEMPERATURE (°C)
OUTPUT SUPPLY VOLTAGE (V)
Figure 11. Typical Propagation Delay vs. Junction Temperature
Figure 14. Typical Rise/Fall Time Variation vs. Output Supply Voltage
60
5
50
4
3
tDHL
tDLH
40
30
2
20
10
0
PD MATCH tDHL
PD MATCH tDLH
1
0
3.0
3.5
4.0
4.5
5.0
5.5
5
7
9
11
13
15
17
INPUT SUPPLY VOLTAGE (V)
OUTPUT SUPPLY VOLTAGE (V)
Figure 12. Typical Propagation Delay vs. Input Supply Voltage;
Figure 15. Typical Propagation Delay (PD) Channel-to-Channel Matching vs.
Output Supply Voltage
V
DDA, VDDB = 12 V
60
50
40
30
20
10
0
5
4
3
2
tDHL
tDLH
PD MATCH tDLH
1
PD MATCH tDHL
0
5
7
9
11
13
15
17
–40
–20
0
20
40
60
80
100
120
140
OUTPUT SUPPLY VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
Figure 13. Typical Propagation Delay vs. Output Supply Voltage,
DD1 = 5 V
Figure 16. Typical Propagation Delay (PD) Channel-to-Channel Matching vs.
Temperature; VDDA, VDDB = 12 V
V
Rev. B | Page 12 of 19
Data Sheet
ADuM3224/ADuM4224
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
8
7
6
5
4
3
2
1
0
SINK I
OUT
V
SOURCE RESISTANCE
OUT
SOURCE I
OUT
V
SINK RESISTANCE
OUT
4
6
8
10
12
14
16
18
4
6
8
10
12
14
16
18
OUTPUT SUPPLY VOLTAGE (V)
OUTPUT SUPPLY VOLTAGE (V)
Figure 17. Typical Output Resistance (ROUT) vs. Output Supply Voltage
Figure 18. Typical Source/Sink Output Current vs. Output Supply Voltage
Rev. B | Page 13 of 19
ADuM3224/ADuM4224
Data Sheet
APPLICATIONS INFORMATION
PRINTED CIRCUIT BOARD LAYOUT
90%
10%
The ADuM3224/ADuM4224 digital isolators require no external
interface circuitry for the logic interfaces. Power supply bypassing
is required at the input and output supply pins, as shown in
Figure 19. Use a small ceramic capacitor with a value between
0.01 μF and 0.1 μF to provide a good high frequency bypass. On
the output power supply pin, VDDA or VDDB, it is recommended
to also add a 10 μF capacitor to provide the charge required to
drive the gate capacitance at the ADuM3224/ADuM4224 outputs.
On the output supply pin, avoid the use of vias on the bypass
capacitor, or use multiple vias to reduce the inductance in the
bypassing. The total lead length between both ends of the smaller
capacitor and the input or output power supply pin must not
exceed 5 mm. For specific layout guidelines, refer to the AN-1109
Application Note, Recommendations for Control of Radiated
Emissions with iCoupler Devices.
OUTPUT
V
IH
INPUT
V
IL
tDHL
tDLH
tR
tF
Figure 20. Propagation Delay Parameters
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM3224/ADuM4224 component.
Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple ADuM3224/
ADuM4224 components operating under the same conditions.
V
V
V
DDA
IA
IB
V
OA
V
GND
A
THERMAL LIMITATIONS AND SWITCH LOAD
CHARACTERISTICS
DD1
GND
NC
NC
1
DISABLE
For isolated gate drivers, the necessary separation between the
input and output circuits prevents the use of a single thermal
pad beneath the device, and heat is, therefore, dissipated mainly
through the package pins.
NC
NC
V
DDB
V
OB
V
GND
B
DD1
Figure 19. Recommended PCB Layout
Package thermal dissipation limits the performance of output load
vs. switching frequency, as illustrated in Figure 7 and Figure 8 for
the maximum load capacitance that can be driven with a 1 Ω
series gate resistance for different values of output voltage. For
example, Figure 7 shows that a typical ADuM3224 can drive a
large MOSFET with 140 nC gate charge at 8 V output (which is
equivalent to a 17 nF load) up to a frequency of about 300 kHz.
UNDERVOLTAGE LOCKOUT
For the output of a channel of the ADuM3224/ADuM4224 to
be valid, both the VDD1 and the VDDA or VDDB power supplies
must be above the positive going undervoltage lockout (UVLO)
threshold. If, during operation, the supply voltage drops below
the negative going UVLO threshold, the output is brought low
to protect the switch from being underdriven. The VDD1 threshold is
typically around 2.5 V. There are three options for the secondary
supply thresholds, which can be selected by the different grades
(see the Ordering Guide). The UVLO of each output channel
acts independently of the other, but in the case of a VDD1 UVLO,
both channels are brought low.
Do not allow the internal junction temperature of the
ADuM3224/ADuM4224 to exceed the maximum junction
temperature of 150°C. Operation above this value causes damage to
the device. There is no internal thermal shutdown to protect the
ADuM3224/ADuM4224. If a thermal shutdown is desired, see
the ADuM3223/ADuM4223 data sheet.
OUTPUT LOAD CHARACTERISTICS
PROPAGATION DELAY-RELATED PARAMETERS
The ADuM3224/ADuM4224 output signals depend on the
characteristics of the output load, which is typically an N-channel
MOSFET. The driver output response to an N-channel MOSFET
load can be modeled with a switch output resistance (RSW), an
inductance due to the printed circuit board trace (LTRACE), a series
gate resistor (RGATE), and a gate-to-source capacitance (CGS), as
shown in Figure 21.
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output can differ from the propagation delay to
a logic high output. The ADuM3224/ADuM4224 specify tDLH
(see Figure 20) as the time between the rising input high logic
threshold, VIH, to the output rising 10% threshold. Likewise, the
falling propagation delay, tDHL, is defined as the time between
the input falling logic low threshold, VIL, and the output falling
90% threshold. The rise and fall times are dependent on the
loading conditions and are not included in the propagation
delay, which is the industry standard for gate drivers.
Rev. B | Page 14 of 19
Data Sheet
ADuM3224/ADuM4224
the VDDA voltage must be controlled to reduce the possibility of
glitches on the output. Keeping the dv/dt below 10 V/μs is
recommended for the ADuM3224/ADuM4224. This can be
controlled by introducing a series resistance, RBOOT, into the
charging path of CA. As an example, if VAUX is 12 V, CA has a
total capacitance of 10 μF, and the forward voltage drop of the
bootstrap diode is 1 V.
R
R
GATE
SW
V
V
OA
IA
V
ADuM3224/
ADuM4224
O
L
TRACE
C
GS
Figure 21. RLC Model of the Gate of an N-Channel MOSFET
RSW is the switch resistance of the internal ADuM3224/
ADuM4224 driver output, which is about 1.1 Ω. RGATE is the
intrinsic gate resistance of the MOSFET and any external series
resistance. A MOSFET that requires a 4 A gate driver has a
typical intrinsic gate resistance of about 1 Ω and a gate-to-source
capacitance, CGS, of between 2 nF and 10 nF. LTRACE is the
inductance of the printed circuit board trace, typically a value of
5 nH or less for a well designed layout with a very short and wide
connection from the ADuM3224/ADuM4224 output to the gate
of the MOSFET.
VAUX VDBOOT
12 V 1V
10μF10V/μs
VBOOT
0.11Ω
dv
CA
dtMAX
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is, therefore, either set or reset by
the pulses, indicating input logic transitions. In the absence of
logic transitions of more than 1 μs at the input, a periodic set of
refresh pulses indicative of the correct input state are sent to
ensure dc correctness at the output.
The following equation defines the Q factor of the
resistor/inductor/capacitor (RLC) circuit, which indicates how
the ADuM3224/ADuM4224 output responds to a step change.
For a well damped output, Q is less than 1. Adding a series gate
resistance dampens the output response.
If the decoder receives no internal pulses for more than about
3 μs, the input side is assumed to be unpowered or nonfunctional,
in which case, the isolator output is forced to a default low state
by the watchdog timer circuit. In addition, the outputs are in a
low default state while the power is coming up before the
UVLO threshold is crossed.
LTRACE
CGS
1
Q
(RSW RGATE
)
In Figure 5, the ADuM3224/ADuM4224 output waveforms for
a 12 V output are shown for a CGS of 2 nF. Note the small amount of
ringing of the output in Figure 5 with a CGS of 2 nF, RSW of 1.1 Ω,
RGATE of 0 Ω, and a calculated Q factor of 0.75, where less than 1
is desired for good damping.
The ADuM3224/ADuM4224 are immune to external magnetic
fields. The limitation on the ADuM3224/ADuM4224 magnetic
field immunity is set by the condition in which induced voltage
in the transformer receiving coil is sufficiently large to either
falsely set or reset the decoder. The following analysis defines
the conditions under which this can occur. The 3 V operating
condition of the ADuM3224/ADuM4224 is examined because
it represents the most susceptible mode of operation. The pulses
at the transformer output have an amplitude greater than 1.0 V.
The decoder has a sensing threshold at about 0.5 V, therefore
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
Output ringing can be reduced by adding a series gate resistance
to dampen the response. For applications of less than 1 nF load,
it is recommended to add a series gate resistor of about 2 Ω to 5 Ω.
BOOTSTRAPPED HALF-BRIDGE OPERATION
The ADuM3224/ADuM4224 are well suited to the operation of
two output gate signals that are referenced to separate grounds,
as in the case of a half-bridge configuration. Because isolated
auxiliary supplies are often expensive, it is beneficial to reduce
the amount of supplies. One method to perform this is to use a
bootstrap configuration for the high-side supply of the
ADuM3224/ADuM4224. In this topology, the decoupling
capacitor, CA, acts as the energy storage for the high-side supply,
and is filled whenever the low-side switch is closed, bringing
GNDA to GNDB. During the charging time of CA, the dv/dt of
2
V = (−dβ/dt) ∑π rn , n = 1, 2, …, N
where:
β is the magnetic flux density (gauss).
rn is the radius of the nth turn in the receiving coil (cm).
N is the number of turns in the receiving coil.
Rev. B | Page 15 of 19
ADuM3224/ADuM4224
Data Sheet
V
DBOOT
V
BUS
R
R
V
V
BOOT
V
V
ADuM3224/
ADuM4224
IA
DDA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D
BOOT
IB
EXT_A
OA
ENCODE
DECODE
C
A
V
PRIM
C
V
DD1
GND
NC
A
DD1
V
PRIM
GND
1
1
DISABLE
NC
NC
V
V
DDB
V
EXT_B
AUX
R
NC
OB
V
PRIM
ENCODE
DECODE
C
B
V
DD1
GND
B
2
NC = NO CONNECT
GND IS CONNECTED TO THE PRIMARY SIDE GROUND, ISOLATED FROM THE SECONDARY GROUND.
1
2
1
GND IS CONNECTED TO THE SECONDARY SIDE GROUND, ISOLATED FROM THE PRIMARY GROUND.
B
Figure 22. Circuit of Bootstrapped Half-Bridge Operation
Given the geometry of the receiving coil in the ADuM3224/
ADuM4224 and an imposed requirement that the induced
voltage be, at most, 50% of the 0.5 V margin at the decoder, a
maximum allowable magnetic field is calculated, as shown in
Figure 23.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances away from the
ADuM3224/ADuM4224 transformers. Figure 24 expresses
these allowable current magnitudes as a function of frequency
for selected distances. As shown in Figure 24, the ADuM3224/
ADuM4224 are immune and only can be affected by extremely
large currents operated at a high frequency and very close to the
component. For the 1 MHz example, a 0.2 kA current must be
placed 5 mm from the ADuM3224/ADuM4224 to affect the
operation of the component.
100
10
1
1k
DISTANCE = 1m
0.1
100
0.01
10
DISTANCE = 100mm
1
0.001
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
DISTANCE = 5mm
0.1
Figure 23. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.08 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event were to occur during a transmitted
pulse (and had the worst-case polarity), the received pulse is
reduced from >1.0 V to 0.75 V, still well above the 0.5 V sensing
threshold of the decoder.
0.01
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 24. Maximum Allowable Current for Various
Current-to-ADuM3224/ADuM4224 Spacings
Rev. B | Page 16 of 19
Data Sheet
ADuM3224/ADuM4224
POWER CONSUMPTION
INSULATION LIFETIME
All insulation structures eventually break down when subjected to
voltage stress over a sufficiently long period. The rate of insulation
degradation is dependent on the characteristics of the voltage
waveform applied across the insulation. In addition to the testing
performed by the regulatory agencies, Analog Devices carries out
an extensive set of evaluations to determine the lifetime of the
insulation structure within the ADuM3224/ADuM4224.
The supply current at a given channel of the ADuM3224/
ADuM4224 isolator is a function of the supply voltage,
channel data rate, and channel output load.
During the driving of a MOSFET gate, the driver must dissipate
power. This power is not insignificant and can lead to thermal
shutdown (TSD) if considerations are not made. The gate of a
MOSFET can be simulated approximately as a capacitive load.
Due to Miller capacitance and other nonlinearities, it is common
practice to take the stated input capacitance, CISS, of a given
MOSFET and multiply it by a factor of 5 to arrive at a conservative
estimate to approximate the load being driven. With this value,
the estimated total power dissipation per channel due to
switching action is given by
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage. Accel-
eration factors for several operating conditions are determined.
These factors allow calculation of the time to failure at the actual
working voltage.
The values shown in Table 12 summarize the peak voltage for
50 years of service life for a bipolar ac operating condition and
the maximum CSA/VDE approved working voltages. In many
cases, the approved working voltage is higher than the 50-year
service life voltage. Operation at these high working voltages
can lead to shortened insulation life in some cases.
P
DISS = CEST × (VDDx)2 × fS
where:
EST = CISS × 5.
C
fS is the switching frequency.
Alternately, use the gate charge to obtain a more precise value
The insulation lifetime of the ADuM3224/ADuM4224 depends
on the voltage waveform type imposed across the isolation barrier.
The iCoupler insulation structure degrades at different rates
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 25, Figure 26, and Figure 27 illustrate these different
isolation voltage waveforms.
for PDISS
DISS = QGATE × VDDx × fS
where:
.
P
QGATE is the gate charge for the MOSFET.
fS is the switching frequency.
This power dissipation is shared between the internal on
resistances of the internal gate driver switches and the external
gate resistances, RGON and RGOFF. The ratio of the internal gate
resistances to the total series resistance allows the calculation of
losses seen within the ADuM3224/ADuM4224 chips per channel.
A bipolar ac voltage environment is the worst case for the
iCoupler products and is the 50-year operating lifetime that
Analog Devices recommends for maximum working voltage. In
the case of unipolar ac or dc voltage, the stress on the insulation
is significantly lower. This allows operation at higher working
voltages while still achieving a 50-year service life. Treat any
cross insulation voltage waveform that does not conform to
Figure 26 or Figure 27 as a bipolar ac waveform, and limit its
peak voltage to the 50-year lifetime voltage value listed in Table 12.
P
R
DISS_IC = PDISS × ½ × (RDSON_P/(REXT_X + RDSON_P) +
DSON_N/(REXT_X + RDSON_N))
Taking the power dissipation found inside the chip and
multiplying it by θJA gives the rise above ambient temperature
that the ADuM3224/ADuM4224 experiences, multiplied by two
to reflect that there are two channels.
Note that the voltage presented in Figure 26 is shown as sinusoidal
for illustration purposes only. It is meant to represent any voltage
waveform varying between 0 V and some limiting value. The limiting
value can be positive or negative, but the voltage cannot cross 0 V.
RATED PEAK VOLTAGE
TJ = θJA × 2 × PDISS_IC + TAMB
For the device to remain within specification, TJ must not
exceed 125°C. If TJ exceeds 150°C (typical), the device enters TSD.
Quiescent power dissipation may also be added to give a more
accurate number for temperature rise, but the switching power
losses are often the largest source of power dissipation, and
quiescent losses can often be ignored. To calculate the total
supply current, the quiescent supply currents for each input and
output channel corresponding to IDD1(Q), IDDA(Q), and IDDB(Q) are
added. The full equation for the TJ becomes
0V
Figure 25. Bipolar AC Waveform
RATED PEAK VOLTAGE
0V
Figure 26. Unipolar AC Waveform
TJ = θJA × (2 × PDISS_IC + VDD1 × IDD1(Q) + VDDA × IDDA(Q)
DDB × IDDB(Q)) + TAMB
+
RATED PEAK VOLTAGE
V
Figure 9 provides total input IDD1 supply current as a function of
data rate for both input channels. Figure 10 provides total IDDA
or IDDB supply current as a function of data rate for both outputs
loaded with 2 nF capacitance.
0V
Figure 27. DC Waveform
Rev. B | Page 17 of 19
ADuM3224/ADuM4224
OUTLINE DIMENSIONS
Data Sheet
10.00 (0.3937)
9.80 (0.3858)
9
8
16
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
BSC
0.50 (0.0197)
0.25 (0.0098)
45°
1.75 (0.0689)
1.35 (0.0531)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 28. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
10.50 (0.4134)
10.10 (0.3976)
16
1
9
8
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.25 (0.0098)
1.27 (0.0500)
BSC
45°
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATIN
PLANE
G
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 29. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
Rev. B | Page 18 of 19
Data Sheet
ADuM3224/ADuM4224
ORDERING GUIDE
Minimum
Output
Voltage (V)
No. of
Channels
Output Peak
Current (A)
Temperature
Range
Package
Option
Ordering
Quantity
Model1, 2
Package Description
ADuM3224WARZ
2
2
2
2
2
2
2
2
2
2
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4.5
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
16-Lead SOIC_N
R-16
ADuM3224WARZ-RL7
ADuM3224WBRZ
4.5
16-Lead SOIC_N, 7” Tape and Reel
16-Lead SOIC_N
R-16
1,000
1,000
1,000
1,000
1,000
1,000
7.5
R-16
ADuM3224WBRZ-RL7
ADuM3224WCRZ
7.5
16-Lead SOIC_N, 7” Tape and Reel
16-Lead SOIC_N
R-16
11.5
11.5
4.5
R-16
ADuM3224WCRZ-RL7
ADuM4224WARWZ
ADuM4224WARWZ-RL
ADuM4224WBRWZ
ADuM4224WBRWZ-RL
ADuM4224WCRWZ
ADuM4224WCRWZ-RL
16-Lead SOIC_N, 7” Tape and Reel
16-Lead SOIC_W
R-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
4.5
16-Lead SOIC_W, 13” Tape and Reel
16-Lead SOIC_W
7.5
7.5
16-Lead SOIC_W, 13” Tape and Reel
16-Lead SOIC_W
11.5
11.5
16-Lead SOIC_W, 13” Tape and Reel
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The ADuM3224W and ADuM4224W models are available with controlled manufacturing to support the quality and reliability
requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial
models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products
shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product
ordering information and to obtain the specific Automotive Reliability reports for these models.
©2013–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11791-0-11/15(B)
Rev. B | Page 19 of 19
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