ADUC7022BCP_技术文档

Precision Analog Microcontroller

Small Package, 12-bit Analog I/O, ARM7TDMI® MCU

Preliminary Technical Data

ADuC7020/ADuC7021/ADuC7022

FEATURES

Analog I/O

On-Chip Peripherals

UART, dual I²C and SPI Serial I/O

14-Pin GPIO Port

2 X General Purpose Timers

Wake-up and Watchdog Timers

Power Supply Monitor

PLA – Programmable Logic (Array)

Power

Multi-Channel, 12-bit, 1MSPS ADC

- 5 Channels on the ADuC7020

- 8 Channels on the ADuC7021

- 10 Channels on the ADuC7022

Differential and single-ended modes

0 to Vref Analog Input Range

Multi-Channel 12-bit Voltage Output DACs

- 4 Outputs on the ADuC7020

- 2 Outputs on the ADuC7021

Specified for 3V operation

Active Mode: 6mW (@1MHz)

300mW (@45MHz)

On-Chip 20ppm/°C Voltage Reference

On-Chip Temperature Sensor ( 3°C)

Uncommitted Voltage Comparator

Microcontroller

Packages and Temperature Range

40 Pin LFCSP 6x6mm body package

Fully specified for –40°C to 85°C operation

Tools

ARM7TDMI Core, 16/32-bit RISC architecture

JTAG Port supports code download and debug

Low-Cost QuickStart Development System

Full Third-Party Support

Clocking options: - Trimmed On-Chip Oscillator ( 2%)

- External Watch crystal

APPLICATIONS

- External clock source

45MHz PLL with Programmable Divider

Memory

62k Bytes Flash/EE Memory, 8k Bytes SRAM

In-Circuit Download, JTAG based Debug

Software triggered in-circuit re-programmability

Optical Networking – Laser Power Control

Base Station Systems

Precision Instrumentation, Smart Sensors

Optical Transceivers – Digital Diagnostic Monitoring

(See general description on page 10)

FUNCTIONAL BLOCK DIAGRAM

ADC0

12-BIT DAC

DAC0***

ADuC7020

ADuC7021

ADuC7022

ADC5*

1MSPS

12-BIT ADC

MUX

DAC1***

DAC2****

DAC3****

ADC7*

ADC8**

ADC9**

TEMP

SENSOR

CMP0

CMP1

+

-

BANDGAP

REF

CMP

OUT

ARM7TDMI-BASED MCU WITH

ADDITIONAL PERIPHERALS

V

REF

2kX32 SRAM

31kX16 FLASH/EEPROM

PLA

GPIO

*

not on the ADuC7020

SERIAL I/O

4 GEN. PUR-

POSE TIMERS

** ADuC7022 only

*** not on the ADuC7022

**** ADuC7020 only

OSC

& PLL

JTAG

RST

POR

PSM

2

UART, SPI, 2xI

C

Figure 1

Rev. PrC

Information furnis hed by Analog Devices is believed to be accurate and reliable.

However, no res pons ibility is as s umed by Analog Devices for its us e, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.326.8703

ADuC7020/ADuC7021/ADuC7022

Preliminary Technical Data

TABLE OF CONTENTS

ADuC7020/21/22—Specifications ................................................. 3

General Description....................................................................... 10

Overview of the ARM7TDMI core.......................................... 10

Memory organisation ................................................................ 11

Outline Dimensions....................................................................... 16

Absolute Maximum Ratings............................................................ 7

Ordering Guide............................................................................. 7

Pin function descriptions ................................................................ 8

Rev. PrC | Page 2 of 16

Preliminary Technical Data

ADuC7020/ADuC7021/ADuC7022

ADUC7020/21/22—SPECIFICATIONS¹

Table 1. (AV_DD= IOV_DD= 2.7 to 3.6V, V_REF= 2.5 V Internal Reference, f_CORE= 45MHz, All specifications T_A= T_MAXto T_MIN, unless otherwise noted.)

Parameter

ADuC7020/21/22

Unit

Test Conditions/Comments

ADC CHANNEL SPECIFICATIONS

DC Accuracy ^{2, 3}

f_SAMPLE= 1MSPS

Resolution

12

Bits

Integral Nonlinearity

1.5

0.5

2.0

+1/-0.9

0.5

LSB max

LSB typ

LSB max

LSB typ

LSB max

LSB typ

2.5V internal reference

1.0V external reference

2.5V internal reference

1.0V external reference

ADC input is a dc voltage

Integral Nonlinearity ⁴

Differential Nonlinearity

4

Differential Nonlinearity

+1/-0.9

1

DC Code Distribution

CALIBRATED ENDPOINT ERRORS ⁵

Offset Error

Offset Error Match

Gain Error

5

1

5

1

LSB max

LSB typ

LSB max

LSB typ

Gain Error Match

DYNAMIC PERFORMANCE

Signal-to-Noise Ratio (SNR) ⁶

Total Harmonic Distortion (THD)

Peak Harmonic or Spurious Noise

Channel-to-Channel Crosstalk ⁷

ANALOG INPUT

Fin = 10kHz Sine Wave, f_SAMPLE= 1MSPS

71

dB typ

-78

-80

Input Voltage Ranges

Differential mode

8

V_CMV_REF/2

Volts

Single-ended mode

0 to V_REF

Volts

Leakage Current

Input Capacitance

5

20

µA max

pF typ

During ADC Acquisition

ON-CHIP VOLTAGE REFERENCE

Output Voltage

Accuracy

Reference Temperature Coefficient

Power Supply Rejection Ratio

Output Impedance

0.47µF from V_REF(pin 55) to AGND

2.5

10

80

10

1

V

mV max

ppm/°C typ

dB typ

Ω typ

Measured at T_A= 25°C

Internal V_REFPower-On Time

ms typ

EXTERNAL REFERENCE INPUT⁹

Input Voltage Range

0.625

AV_DD

TBD

V min

V max

KΩ typ

Input Impedance

DAC CHANNEL SPECIFICATIONS

DC ACCURACY

R_L= 5kΩ, C_L= 100pF

Resolution

12

2

1

2

5

Bits

Relative Accuracy

Differential Nonlinearity

Offset Error

LSB typ

LSB max

mV max

% max

% typ

Guaranteed Monotonic

DAC output unbuffered

DAC output buffered

Gain Error

Gain Error Mismatch

0.5

TBD

% of fullscale on DAC0

Rev. PrC | Page 3 of 16

ADuC7020/ADuC7021/ADuC7022

Preliminary Technical Data

Parameter

ADuC7020/21/22

Unit

Test Conditions/Comments

ANALOG OUTPUTS

Output Voltage Range_0

Ouput Voltage Range_1

Output Voltage Range_2

Output Impedance

0 to DACREF

0 to 2.5V

0 to DACV_DD

V typ

DACREF range: DACGND to DACV_DD

10

Ω typ

DAC AC CHARACTERISTICS

Voltage Output Settling Time

Digital to Analog Glitch Energy

COMPARATOR

10

15

TBD

µs typ

nV-sec typ

DAC Output buffered

DAC Output unbuffered

I LSB change at major carry

Input Offset Voltage

Input Bias Current

Input Voltage Range

Input Capacitance

10

mV

5

nA typ

V max

pF typ

mV min

mv max

µs min

µs max

AV_DD-1.2

7

5

Hysteresis

Hysteresis can be turned on or off via the CMPHYST

bit in the CMPCON register

Response time may be modified via the CMPRES bits

in the CMPCON register

10

1

10

Response Time

TEMPERATURE SENSOR

Voltage Output at 25°C

Voltage TC

TBD

-2.0

3

mV typ

mV/°C typ

°C typ

Accuracy

POWER SUPPLY MONITOR (PSM)

IOVDD Trip Point Selection

2.79

3.07

2.5

V

Two selectable Trip Points

Power Supply Trip Point Accuracy

Watchdog Timer (WDT)⁴

Timeout Period

% max

Of the selected nominal Trip Point Voltage

0

TBD

ms min

ms max

Flash/EE MEMORY

Endurance¹⁰

Data Retention¹¹

10,000

30

Cycles min

Years min

T_J= 55°C

Digital Inputs

All digital inputs including XTAL1 and XTAL2

Input Leakage Current

10

1

10

µA max

µA typ

pF typ

Input Capacitance

Logic Inputs⁴

All Logic inputs including XTAL1 and XTAL2

VINL, Input Low Voltage

VINH, Input High Voltage

Logic Outputs

0.4

2.0

V max

V min

VOH, Output High Voltage

VOL, Output Low Voltage

MCU CLOCK RATE

2.4

0.4

V min

V max

I_SOURCE= 20µA

I_SINK= 1.6mA

355.5

45.5

kHz min

MHz max

8 programmable core clock selections within this

range

STARTUP TIME

Core Clock = TBD MHz

At Power-On

From Idle Mode

From Power-Down Mode

Programmable Logic Array (PLA)

Propagation Delay

TBD

ns typ

From input pin to output pin

Rev. PrC | Page 4 of 16

Preliminary Technical Data

ADuC7020/ADuC7021/ADuC7022

Parameter

POWER REQUIREMENTS ¹²

ADuC7020/21/22

Unit

Test Conditions/Comments

13

,

Power Supply Voltage Range

AV_DD– AGND and IOV_DD- IOGND

2.7

3.6

V min

V max

Power Supply Current Normal Mode

3mA

5

50

mA typ

mA max

mA typ

mA max

1MHz clock

45MHz clock

60

Power Supply Current Idle Mode

1

mA max

Power Supply Current Power Down

Mode

30

100

µA typ

µA max

External Crystal or Internal Osc ON

¹Temperature Range -40° to +85°C

²All ADC Channel Specifications are guaranteed during normal MicroConverter core operation.

³These specification apply to all ADC input channels.

⁴These numbers are not production tested but are supported by design and/or characterization data on production release.

5

Based on external ADC system components, the user may need to execute a system calibration to remove external endpoint and a chieve these specifications..

SNR calculation includes distortion and noise components.

Channel-to-channel crosstalk is measured on adjacent channels.

6

7

8

The input signal can be centered on any dc common-mode voltage (V ) as long as this value is within the ADC voltage input range specified.

CM

9

When using an external reference input pin, the internal reference must be disabled by setting the lsb in the REFCON MemeoryMapped Register to 0.

¹⁰Endurance is qualified to 50,000 cycles as per JEDEC Std. 22 method A117 and measured at -40°C, +25°C and +85°C. Typical endurance at 25°C is 70,000 cycles.

¹¹Retention lifetime equivalent at junction temperature (Tj) = 55°C as per JEDEC Std. 22 method A117. Retention lifetime will derate with junction temperature.

¹²Power supply current consumption is measured in normal, idle and power-down modes under the following conditions:

Normal Mode:

Idle Mode:

Power-Down:

TBD

¹³DV_DDpower supply current increases typically by TBD mA during a Flash/EE memory program or erase cycle.

Rev. PrC | Page 5 of 16

ADuC7020/ADuC7021/ADuC7022

Terminology

Preliminary Technical Data

output of the ADC. The signal is the rms amplitude of the

fundamental. Noise is the rms sum of all nonfundamental

signals up to half the sampling frequency (fS/2), excluding dc.

The ratio is dependent upon the number of quantization levels

in the digitisation process; the more levels, the smaller the

quantization noise. The theoretical signal to (noise + distortion)

ratio for an ideal N-bit converter with a sine wave input is given

by:

ADC Specifications

Integral Nonlinearity

This is the maximum deviation of any code from a straight line

passing through the endpoints of the ADC transfer function.

The endpoints of the transfer function are zero scale, a point 1/2

LSB below the first code transition and full scale, a point 1/2

LSB above the last code transition.

Signal to (Noise + Distortion) = (6.02N + 1.76) dB

Thus for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

Total Harmonic Distortion is the ratio of the rms sum of the

harmonics to the fundamental.

Offset Error

DAC SPECIFICATIONS

This is the deviation of the first code transition (0000 . . . 000) to

(0000 . . . 001) from the ideal, i.e., +1/2 LSB.

Relative Accuracy

Relative accuracy or endpoint linearity is a measure of the

maximum deviation from a straight line passing through the

endpoints of the DAC transfer function. It is measured after

adjusting for zero error and full-scale error.

Gain Error

This is the deviation of the last code transition from the ideal

AIN voltage (Full Scale – 1.5 LSB) after the offset error has been

adjusted out.

VoltageOutputSettlingTime

Signal to (Noise + Distortion) Ratio

This is the amount of time it takes for the output to settle to

within a 1 LSB level for a full-scale input change..

This is the measured ratio of signal to (noise + distortion) at the

Rev. PrC | Page 6 of 16

Preliminary Technical Data

ADuC7020/ADuC7021/ADuC7022

ABSOLUTE MAXIMUM RATINGS

Table 2. Absolute Maximum Ratings (T_A= 25°C unless otherwise noted)

Parameter

Rating

TBD

PIN CONFIGURATION

40-Lead CSP

AV_DDto DV_DD

AGND to DGND

DV_DDto DGND, AV_DDto AGND

Digital Input Voltage to DGND

Digital Output Voltage to DGND

VREF to AGND

TBD

40

31

PIN 1

IDENTIFIER

30

1

Analog Inputs to AGND

TBD

Operating Temperature Range

Industrial ADuC7020/21/22

Storage Temperature Range

Junction Temperature

–40°C to +85°C

TOP VIEW

(Not to Scale)

TBD

θ_JAThermal Impedance

(ADuC7020/21/22BCP)

21

10

Lead Temperature, Soldering

Vapor Phase (60 sec)

Infrared (15 sec)

11

20

TBD

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those listed in the operational sections

of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ORDERING GUIDE

Model

Temperature Range

–40°C to + 85°C

Package Description

Package Option

CP-40

ADuC7020BCP

ADuC7021BCP

ADuC7022BCP

EVAL_ADuC7020QS

40-Lead Chip Scale Package

Development System

CP-40

Contact the factory for chip availability.

ESD Caution

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. PrC | Page 7 of 16

ADuC7020/ADuC7021/ADuC7022

Preliminary Technical Data

PIN FUNCTION DESCRIPTIONS

Table 3. Pin Function Descriptions

Pin# ADuC702X

Mnemonic

Type* Function

7020

7021

37

38

39

40

1

7022

36

37

38

39

40

1

38

39

40

1

2

-

ADC0

I

Single-ended or differential Analog input 0

Single-ended or differential Analog input 1

ADC1

ADC2/CMP0

ADC3/CMP1

ADC4

Single-ended or differential Analog input 2 / Comparator Positive Input

Single-ended or differential Analog input 3 / Comparator Negative Input

Single-ended or differential Analog input 4

2

ADC5

Single-ended or differential Analog input 5

-

3

2

ADC6

Single-ended or differential Analog input 6

-

4

3

ADC7

Single-ended or differential Analog input 7

-

4

ADC8

Single-ended or differential Analog input 8

-

5

ADC9

Single-ended or differential Analog input 9

Ground voltage reference for the ADC. For optimal performance the

analog power supply should be separated from IOGND and DGND

3

5

6

GND_REF

S

4

5

6

7

8

9

6

7

-

DAC0/ADC12

DAC1/ADC13

DAC2/ADC14

DAC3/ADC15

TMS

I/O

I

DAC0 Voltage Output / Single-ended or differential Analog input 12

DAC1 Voltage Output / Single-ended or differential Analog input 13

DAC2 Voltage Output / Single-ended or differential Analog input 14

DAC3 Voltage Output / Single-ended or differential Analog input 15

JTAG Test Port Input - Test Mode Select. Debug and download access

JTAG Test Port Input – Test Data In. Debug and download access

Multifunction I/O pin:

-

8

9

7

8

TDI

I

Boot Mode. The ADuC702X will enter UART serial download mode if BM

is low at reset and will execute code if BM is pulled high at reset through

a 1kOhm resistor/ General Purpose Input-Output Port 0.0 / Voltage

Comparator Output/ Programmable Logic Array Input Element 7

BM/P0.0/CMP_OUT/P

LAI[7]

10

9

I/O

Multifunction pin: driven low after reset

General Purpose Output Port 0.6 / Timer 1 Input / Power on reset output

/ Programmable Logic Array Output Element 3

P0.6/T1/MRST/PLA

O[3]

11

12

11

12

10

11

O

I

JTAG Test Port Input - Test Clock. Debug and download access / Input to

the internal clock generator circuits

TCK/XCLK

13

14

15

13

14

15

12

13

14

TDO

O

S

JTAG Test Port Output - Test Data Out. Debug and download access

Ground for GPIO. Typically connected to DGND

IOGND

IOV_DD

S

3.3V Supply for GPIO and input of the on-chip voltage regulator.

2.5V. Output of the on-chip voltage regulator. Must be connected to a

0.47µF capacitor to DGND

16

15

LV_DD

S

17

18

19

17

18

19

16

17

18

DGND

TRST

RST

S

I

Ground for core logic.

JTAG Test Port Output - Test Reset. Debug and download access

Reset Input. (active low)

I

Multifunction I/O pin:

IRQ0/P0.4/CONV_ST

_ART/PLAO[1]

External Interrupt Request 0, active high / General Purpose Input-Output

Port 0.4 / Start conversion input signal for ADC / Programmable Logic

Array Output Element 1

20

21

20

21

19

20

I/O

Multifunction I/O pin:

External Interrupt Request 1, active high / General Purpose Input-Output

Port 0.5 / ADC_BUSYsignal / Programmable Logic Array Output Element 2

IRQ1/P0.5/ADC_BUSY

/PLAO[2]

Serial Port Multiplexed:

General Purpose Input-Output Port 2.0 / UART / Programmable Logic

Array Output Element 5/ Start conversion input signal for ADC

P2.0/SPM9/PLAO[

5]/CONV_START

22

23

22

23

21

22

I/O

Serial Port Multiplexed:

General Purpose Input-Output Port 0.7 / Output for External Clock signal

P0.7/ECLK/SPM8/P

LAO[4]

Rev. PrC | Page 8 of 16

Preliminary Technical Data

ADuC7020/ADuC7021/ADuC7022

Pin# ADuC702X

Mnemonic

Type* Function

7020

7021

7022

/ UART / Programmable Logic Array Output Element 4

Output to the crystal oscillator inverter

24

25

24

23

24

XCLKO

XCLKI

O

I

Input to the crystal oscillator inverter and input to the internal clock

generator circuits

Serial Port Multiplexed:

General Purpose Input-Output Port 1.7 / UART / SPI / Programmable

Logic Array Output Element 0

P1.7/SPM7/PLAO[

0]

26

27

28

29

30

31

32

33

26

27

28

29

30

31

32

33

25

26

27

28

29

30

31

32

I/O

Serial Port Multiplexed:

General Purpose Input-Output Port 1.6 / UART / SPI / Programmable

Logic Array Input Element 6

P1.6/SPM6/PLAI[6]

P1.5/SPM5/PLAI[5]

P1.4/SPM4/PLAI[4]

P1.3/SPM3/PLAI[3]

P1.2/SPM2/PLAI[2]

P1.1/SPM1/PLAI[1]

Serial Port Multiplexed:

General Purpose Input-Output Port 1.5 / UART / SPI / Programmable

Logic Array Input Element 5

Serial Port Multiplexed:

General Purpose Input-Output Port 1.4 / UART / SPI / Programmable

Logic Array Input Element 4

Serial Port Multiplexed:

General Purpose Input-Output Port 1.3/ UART / I²C1 /Programmable

Logic Array Input Element 3

Serial Port Multiplexed:

General Purpose Input-Output Port 1.2 / UART / I²C1 /Programmable

Logic Array Input Element 2

Serial Port Multiplexed:

General Purpose Input-Output Port 1.1 / UART / I²C0 / Programmable

Logic Array Input Element 1

Serial Port Multiplexed:

General Purpose Input-Output Port 1.0/ Timer 1 Input / UART / I²C0 /

Programmable Logic Array Input Element 0

P1.0/T1/SPM0/PLA

I[0]

General Purpose Input-Output Port 4.2 / Programmable Logic Array

Output Element 10

34

35

-

P4.2/PLAO[10]

V_REF

I/O

2.5V internal Voltage Reference. Must be connected to a 0.47uF capacitor

when using the internal reference.

34

33

36

37

35

36

34

35

AGND

AV_DD

S

Analog Ground. Ground reference point for the analog circuitry

3.3V Analog Power

^*I = Input, O = Output, S = Supply.

- No pin assigned.

Rev. PrC | Page 9 of 16

ADuC7020/ADuC7021/ADuC7022

GENERAL DESCRIPTION

Preliminary Technical Data

compressed into 16-bits, the Thumb instruction set. Faster

execution from 16-bit memory and greater code density can

usually be achieved by using the Thumb instruction set instead

of the ARM instruction set, which makes the ARM7TDMI core

particularly suitable for embedded applications.

The ADuC7020/21/22 are fully integrated, 1MSPS, 12-bit data

acquisition systems incorporating a high performance multi-

channel ADC, a 16/32-bit MCU and Flash/EE Memory on a

single chip.

The ADC consists of 5/8/10 single-ended inputs. An additional

2/4 inputs are available on the ADuC7021/20 but are

multiplexed with the 2/4 DAC output pins. The ADC can

operate in single-ended or differential input modes with a fully

flexible front end. The ADC input voltage is 0 to V_REF. Low drift

bandgap reference, temperature sensor and voltage comparator

complete the ADC peripheral set.

However the Thumb mode has two limitations:

- Thumb code usually uses more instructions for the same job,

so ARM code is usually best for maximising the performance

of the time-critical code.

- The Thumb instruction set does not include some

instructions that are needed for exception handling, so ARM

code needs to be used for exception handling.

The part also integrates 2/4 buffered voltage output DACs on-

chip. The DAC output range is 0 to AV_DDmax.

See ARM7TDMI User Guide for details on the core

architecture, the programming model and both the ARM and

ARM Thumb instruction sets.

The device operates from the on-chip oscillator and PLL

generating an internal high-frequency clock of 45 MHz. This

clock is routed through a programmable clock divider from

which the MCU core clock operating frequency is generated.

The microcontroller core is an ARM7TDMI, 16/32-bit RISC

machine, offering up to 45 MIPS peak performance. 62k Bytes

of non-volatile Flash/EE are provided on-chip as well as 8k

Bytes of SRAM. Both the Flash/EE and SRAM memory arrays

are mapped into a single linear array.

Long multiple (M)

The ARM7TDMI instruction set includes four extra

instructions which perform 32-bit by 32-bit multiplication with

64-bit result and 32-bit by 32-bit multiplication-accumulation

(MAC) with 64-bit result.

EmbeddedICE (I)

O n-chip factory firmware supports in-circuit serial download

via the UART and JTAG serial interface ports while non-

intrusive emulation is also supported via the JTAG interface.

These features are incorporated into a low cost QuickStart

system supporting this MicroConverter family.

EmbeddedICE provides integrated on-chip support for the core.

The EmbeddedICE module contains the breakpoint and

watchpoint registers which allow code to be halted for

debugging purposes. These registers are controlled through the

JTAG test port.

The parts operate from 2.7V to 3.6V and are specified over an

industrial temperature range of -40°C to 85°C. When operating

@45MHz the power dissipation is 300mW. The

ADuC7020/21/22 are available in a 40-lead LFCSP package.

When a breakpoint or watchpoint is encountered, the processor

halts and enters debug state. Once in a debug state, the

processor registers may be inspected as well as the Flash/EE, the

SRAM and the Memory Mapped Registers.

OVERVIEW OF THE ARM7TDMI CORE

Exceptions

The ARM7 core is a 32-bit Reduced Instruction Set Computer

(RISC). It uses a single 32-bit bus for instruction and data. The

length of the data can be 8, 16 or 32 bits and the length of the

instruction word is 32 bits.

ARM supports five types of exceptions, and a privileged

processing mode for each type. The five type of exceptions are:

- Normal interrupt or IRQ. It is provided to service general-

purpose interrupt handling of internal and external events

- Fast interrupt or FIQ. It is provided to service data transfer or

communication channel with low latency. FIQ has priority

over IRQ

The ARM7TDMI is an ARM7 core with 4 additional features:

- T support for the Thumb (16 bit) instruction set.

- D support for debug

- Memory abort

- M support for long multiplies

- Attempted execution of an undefined instruction

- Software interrupt (SWI) instruction which can be used to

make a call to an operating system.

- I include the EmbeddedICE module to support embedded

system debugging.

Thumb mode (T)

Typically the programmer will define interrupts as IRQ but for

higher priority interrupt, i.e. faster response time, the

programmer can define interrupt as FIQ.

An ARM instruction is 32-bits long. The ARM7TDMI

processor supports a second instruction set that has been

Rev. PrC | Page 10 of 16

Preliminary Technical Data

ADuC7020/ADuC7021/ADuC7022

The maximum IRQ latency calculation is similar, but must

allow for the fact that FIQ has higher priority and could delay

entry into the IRQ handling routine for an arbitrary length of

time.

ARM Registers

ARM7TDMI has a total of 37 registers, of which 31 are general

purpose registers and six are status registers. Each operating

mode has dedicated banked registers.

The minimum latency for FIQ or IRQ interrupts is four cycles

in total which consists of the shortest time the request can take

through the synchronizer plus the time to enter the exception

mode.

When writing user-level programs, 15 general purpose 32-bit

registers (r0 to r14), the program counter (r15) and the current

program status register (CPSR) are usable. The remaining

registers are used only for system-level programming and for

exception handling.

Note that the ARM7TDMI will always be run in ARM (32-bit)

mode when in privileged modes, i.e. when executing interrupt

service routines.

When an exception occurs, some of the standard register are

replaced with registers specific to the exception mode. All

exception modes have replacement banked registers for the

stack pointer (r13) and the link register (r14) as represented in

Figure22. The fast interrupt mode has more registers (8 to 12)

for fast interrupt processing, so that the interrupt processing

can begin without the need to save or restore these registers and

thus save critical time in the interrupt handling process.

MEMORY ORGANISATION

The ADuC7020/21/22 incorporate two separate blocks of

memory, 8kByte of SRAM and 64kByte of O n-Chip Flash/EE

memory. 62kByte of On-Chip Flash/EE memory are available to

the user, and the remaining 2kBytes are reserved for the factory

configured boot page. These two blocks are mapped as shown

Figure 3.

r0

r1

r2

usable in user mode

Note that by default, after a reset, the Flash/EE memory is

mirrored at address 0x00000000. It is possible to remap the

SRAM at address 0x00000000 by clearing bit 0 of the REMAP

MMR. This remap function is described in more details in the

Flash/EE memory chapter.

r3

r4

system modes only

r5

r6

r7

r8_fiq

r9_fiq

r8

r9

FFFFFFFFh

MMRs

r10_fiq

r11_fiq

r12_fiq

r13_fiq

r14_fiq

FFFF0000h

r10

r11

r12

r13

r13_und

r13_irq

Reserved

r13_abt

r14_abt

r14_und

r13_svc

r14_svc

r14_irq

0008FFFFh

r14

Flash/EE

r15 (PC)

00080000h

SPSR_und

SPSR_irq

SPSR_abt

Reserved

SPSR_svc

CPSR

SPSR_fiq

00011FFFh

SRAM

00010000h

user mode

fiq

mode

svc

mode

abord

mode

irq undefined

0000FFFFh

mode

Re-mappable Memory Space

(Flash/EE or SRAM)

00000000h

Figure22: register organisation

Figure 3: Physical memory map

Interrupt latency

Memory Access

The worst case latency for an FIQ, assuming that it is enabled,

consists of the longest time the request can take to pass through

the synchronizer, plus the time for the longest instruction to

complete (the longest instruction is an LDM) which loads all

the registers including the PC, plus the time for the data abort

entry, plus the time for FIQ entry. At the end of this time, the

ARM7TDMI will be executing the instruction at 0x1C (FIQ

interrupt vector address). The maximum total time is 44

processor cycles, which is just over 975 nanoseconds in a system

using a continuous 45 MHz processor clock.

32

The ARM7 core sees memory as a linear array of 2 byte

location where the different blocks of memory are mapped as

outlined in Figure 3 above.

The ADuC7020/21/22 memory organisation is configured in

little endian format: the least significant byte is located in the

lowest byte address and the most significant byte in the highest

byte address.

Rev. PrC | Page 11 of 16

ADuC7020/ADuC7021/ADuC7022

Preliminary Technical Data

bit0

0xFFFFFFFF

bit31

Byte3

Byte2 Byte1 Byte0

0xFFFFF820

Flash Control

0xFFFFFFFFh

Interface

0xFFFFF800

B

7

3

A

6

2

9

5

1

8

4

0

0x00000004h

0x00000000h

0xFFFFF46C

GPIO

0xFFFFF400

0xFFFF0B54

32 bits

Figure 4: little endian format

PLA

0xFFFF0B00

0xFFFF0A14

Flash/EE Memory

SPI

0xFFFF0A00

The total 64kBytes of Flash/EE are organised as 32k X 16 bits.

31k X 16 bits are user space and 1k X 16 bits is reserved for boot

loader. The page size of this Flash/EE memory is 256Bytes.

0xFFFF0948

2

I C1

0xFFFF0900

0xFFFF0848

62kBytes of Flash/EE are available to the user as code and non-

volatile data memory. There is no distinction between data and

program as ARM code shares the same space. The real width of

the Flash/EE memory is 16 bits, which means that in ARM

mode (32-bit instruction), two accesses to the Flash/EE are

necessary for each instruction fetch. It is therefore

recommended to use Thumb mode when executing from

Flash/EE memory for optimum access speed. The maximum

access speed for the Flash/EE memory is 45MHz in Thumb

mode and 22.5MHz in full ARM mode. More details on

Flash/EE access time are outlined later in ‘Execution from

SRAM and Flash/EE’ section of this datasheet.

2

I C0

0xFFFF0800

0xFFFF0730

UART

0xFFFF0700

0xFFFF0620

DAC

0xFFFF0600

0xFFFF0538

ADC

0xFFFF0500

0xFFFF0490

Bandgap

Reference

0xFFFF048C

SRAM

0xFFFF0448

Power Supply

8kBytes of SRAM are available to the user, organized as 2k X 32

bits, i.e. 2kWords. ARM code can run directly from SRAM at

45MHz , given that the SRAM array is configured as a 32-bit

wide memory array. More details on SRAM access time are

outlined later in ‘Execution from SRAM and Flash/EE’ section

of this datasheet.

Monitor

0xFFFF0440

0xFFFF0420

PLL &

Oscillator Control

0xFFFF0404

0xFFFF0370

Watchdog

Timer

0xFFFF0360

Memory Mapped Registers

0xFFFF0350

Wake Up

The Memory Mapped Register (MMR) space is mapped into

the upper 2 pages of the Flash/EE space and accessed by

indirect addressing through the ARM7 banked registers.

Timer

0xFFFF0340

0xFFFF0334

General Purpose

Timer

0xFFFF0320

The MMR space provides an interface between the CPU and all

on-chip peripherals. All registers except the core registers

reside in the MMR area. All shaded locations shown in Figure 6

are unoccupied or reserved locations and should not be

accessed by user software. Table 4 shows a full MMR memory

map. The ‘Access’ column corresponds to the access time

reading or writing a MMR. Table 4 shows a full MMR memory

map.

0xFFFF0310

Timer 0

0xFFFF0300

0xFFFF0238

Remap &

System Control

0xFFFF0220

0xFFFF0110

Interrupt

Controller

0xFFFF0000

Figure 5: Memory Mapped

Rev. PrC | Page 12 of 16

Preliminary Technical Data

ADuC7020/ADuC7021/ADuC7022

Table 4. Complete MMRs list

Address Name

Byte

Access

Type

Page

Address Name

Byte

Access

Page

Cycle

Type

RW

W

Cycle

IRQ address base = 0xFFFF0000

0x0414

0x0418

PLLCON

PLLKY2

1

2

0x0000

0x0004

0x0008

0x000C

0x0010

0x0100

0x0104

0x0108

0x010C

IRQSTA

IRQSIG

IRQEN

4

R

1

R

PSM address base = 0xFFFF0440

RW

W

R

0x0440

0x0444

PSMCON

CMPCON

2

RW

2

IRQCLR

SWICFG

FIQSTA

FIQSIG

FIQEN

Reference address base = 0xFFFF0480

0x048C

REFCON

1

RW

2

R

ADC address base = 0xFFFF0500

RW

W

0x0500

0x0504

0x0508

0x050C

0x0510

0x0514

0x0530

0x0534

ADCCON

ADCCP

1

4

1

2

RW

R

2

FIQCLR

ADCCN

ADCSTA

ADCDAT

ADCRST

ADCGN

ADCOF

System Control address base = 0xFFFF0200

0x0220

0x0230

0x0234

REMAP

RSTSTA

RSTCLR

1

RW

R

1

W

RW

Timer address base = 0xFFFF0300

0x0300

0x0304

0x0308

0x030C

0x0320

0x0324

0x0328

0x032C

0x0330

0x0340

0x0344

0x0348

0x034C

0x0360

0x0364

0x0368

0x036C

T0LD

2

1

4

2

1

4

2

1

2

1

RW

R

2

T0VAL

T0CON

T0CLRI

T1LD

DAC address base = 0xFFFF0600

RW

W

0x0600

0x0604

0x0608

0x060C

0x0610

0x0614

0x0618

0x061C

DAC0CON

DAC0DAT

DAC1CON

DAC1DAT

DAC2CON

DAC2DAT

DAC3CON

DAC3DAT

1

4

1

4

1

4

1

4

RW

2

RW

R

T1VAL

T1CON

T1CLRI

T1CAP

T2LD

RW

W

RW

R

T2VAL

T2CON

T2CLRI

T3LD

UART base address = 0xFFFF0700

RW

W

0x0700

COMTX

1

RW

R

2

COMRX

RW

R

COMDIV0

COMIEN0

COMDIV1

COMIID0

COMCON0

COMCON1

COMSTA0

COMSTA1

COMSCR

RW

R/W

R

T3VAL

T3CON

T3CLRI

0x0704

RW

W

0x0708

0x070C

0x0710

0x0714

0x0718

0x071C

RW

R

PLL base address = 0xFFFF0400

0x0404

0x0408

0x040C

0x0410

POWKY1

POWCON

POWKY2

PLLKY1

1

W

2

RW

W

R

W

RW

Rev. PrC | Page 13 of 16

ADuC7020/ADuC7021/ADuC7022

Preliminary Technical Data

Address Name

Byte

Access

Type

RW

Page

Address Name

Byte

Access

Type

RW

Page

Cycle

0x0720

0x0724

0x0728

0X072C

COMIEN1

1

2

0x0944

I2C1ID3

1

2

COMIID1

COMADR

COMDIV2

R

SPI base address = 0xFFFF0A00

RW

0x0A00

0x0A04

0x0A08

0x0A0C

0x0A10

SPISTA

SPIRX

1

2

R

2

RW

R

SPITX

W

I2C0 base address = 0xFFFF0800

SPIDIV

SPICON

RW

0x0800

0x0804

0x0808

0x080C

0x0810

0x0814

0x0818

0x081C

0x0824

0x0828

0x082C

0x0830

0x0834

0x0838

0x083C

0x0840

0x0844

I2C0MSTA

I2C0SSTA

I2C0SRX

I2C0STX

I2C0MRX

I2C0MTX

I2C0CNT

I2C0ADR

I2C0BYTE

I2C0ALT

I2C0CFG

I2C0DIVH

I2C0DIVL

I2C0ID0

1

R

2

R

PLA base address = 0xFFFF0B00

W

0x0B00

0x0B04

0x0B08

0x0B0C

0x0B10

0x0B14

0x0B18

0x0B1C

0x0B20

0x0B24

0x0B28

0x0B2C

0x0B30

0x0B34

0x0B38

0x0B3C

0x0B40

0x0B44

0x0B48

0x0B4C

0x0B50

PLAELM0

PLAELM1

PLAELM2

PLAELM3

PLAELM4

PLAELM5

PLAELM6

PLAELM7

PLAELM8

PLAELM9

PLAELM10

PLAELM11

PLAELM12

PLAELM13

PLAELM14

PLAELM15

PLACLK

2

1

4

RW

R

2

R

W

RW

I2C0ID1

I2C0ID2

I2C0ID3

I2C1 base address = 0xFFFF0900

0x0900

0x0904

0x0908

0x090C

0x0910

0x0914

0x0918

0x091C

0x0924

0x0928

0x092C

0x0930

0x0934

0x0938

0x093C

0x0940

I2C1MSTA

I2C1SSTA

I2C1SRX

I2C1STX

I2C1MRX

I2C1MTX

I2C1CNT

I2C1ADR

I2C1BYTE

I2C1ALT

I2C1CFG

I2C1DIVH

I2C1DIVL

I2C1ID0

1

R

2

R

PLAIRQ

W

PLAADC

R

PLADIN

W

PLADOUT

RW

GPIO base address = 0xFFFFF400

0xF400

0xF404

0xF408

0xF40C

0xF410

0xF420

0xF424

0xF428

0xF430

GP0CON

GP1CON

GP2CON

GP3CON

GP4CON

GP0DAT

GP0SET

GP0CLR

GP1DAT

4

1

4

RW

W

1

I2C1ID1

W

I2C1ID2

RW

Rev. PrC | Page 14 of 16

Preliminary Technical Data

ADuC7020/ADuC7021/ADuC7022

Development Tools

Address Name

Byte

Access

Type

W

Page

An entry level, low cost development system is available for the

ADuC702X family. This system consists of the following PC-

based (Windows® compatible) hardware and software

development tools:

Cycle

0xF434

0xF438

0xF440

0xF444

0xF448

0xF450

0xF454

0xF458

0xF460

0xF464

0xF468

GP1SET

GP1CLR

GP2DAT

GP2SET

GP2CLR

GP3DAT

GP3SET

GP3CLR

GP4DAT

GP4SET

GP4CLR

1

4

1

4

1

4

1

W

RW

W

Hardware:

-

ADuC702X Evaluation board

- Serial Port programming cable

- JTAG emulator

Software:

- Integrated Development Environment, incorporating

assembler, compiler and non intrusive JTAG-based

debugger

- Serial Downloader software

- Example Code

W

RW

W

RW

W

Miscellaneous:

-

CD-ROM Documentation

Flash/EE base address = 0xFFFFF800

0xF800

0xF804

0xF808

0xF80C

0xF810

0xF818

0xF81C

FEESTA

1

2

3

4

R

1

FEEMOD

FEECON

FEEDAT

FEEADR

FEESIGN

FEEPRO

RW

R

In-Circuit Serial Downloader

The Serial Downloader is a Windows application that allows

the user to serially download an assembled program (Intel Hex

format file) to the on-chip program FLASH/EE memory via the

serial port on a standard PC.

RW

The ‘Access’ column corresponds to the access time reading or

writing MMR. It depends on the AMBA (Advanced

a

Microcontroller Bus Architecture) bus used to access the

peripheral. The processor has two AMBA busses, AHB

(Advanced High-performance Bus) used for system modules

and APB (Advanced Peripheral Bus) used for lower

performance peripheral.

Rev. PrC | Page 15 of 16

ADuC7020/ADuC7021/ADuC7022

OUTLINE DIMENSIONS

Preliminary Technical Data

6.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

0.60 MAX

31

30

40

1

PIN 1

INDICATOR

0.50

BSC

4.25

TOP

VIEW

5.75

BSC SQ

BOTTOM

VIEW

3.70 SQ

1.75

0.50

0.40

0.30

21

20

10

11

4.50

REF

128MAX

1.00 MAX

0.65 NOM

0.05 MAX

0.02 NOM

1.00

0.30

0.23

0.18

0.90

0.80

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2

Figure 6. 40-Lead Frame Chip Scale Package [LFCSP] (CP-40)—Dimensions shown in millimetres

Rev. PrC | Page 16 of 16


型号：	ADUC7022BCP
厂家：	ADI
描述：	IC 32-BIT, FLASH, 45.5 MHz, RISC MICROCONTROLLER, QCC40, 6 X 6 MM, MO-220VJJD-2, LFCSP-40, Microcontroller 微控制器外围集成电路
文件：	总16页 (文件大小：199K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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