ADSP2186 [ADI]
DSP Microcomputer; 微电脑DSP
ADI 
a
DSP Microcomputer
ADSP-2186
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
PERFORMANCE
POWER-DOWN
CONTROL
30 ns Instruction Cycle Tim e 33 MIPS Sustained
Perform ance
Single-Cycle Instruction Execution
Single-Cycle Context Sw itch
FULL MEMORY
MODE
MEMORY
PROGRAMMABLE
DATA ADDRESS
GENERATORS
I/O
AND
FLAGS
EXTERNAL
ADDRESS
BUS
8K 24
PROGRAM
MEMORY
8K 16
DATA
MEMORY
PROGRAM
SEQUENCER
DAG 1 DAG 2
3-Bus Architecture Allow s Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
EXTERNAL
DATA
BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
BYTE DMA
CONTROLLER
Pow er-Dow n Mode Featuring Low CMOS Standby
Pow er Dissipation w ith 100 Cycle Recovery from
Pow er-Dow n Condition
PROGRAM MEMORY DATA
DATA MEMORY DATA
OR
EXTERNAL
DATA
BUS
Low Pow er Dissipation in Idle Mode
ARITHMETIC UNITS
ALU SHIFTER
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
INTERNAL
DMA
PORT
MAC
INTEGRATION
ADSP-2100 BASE
ARCHITECTURE
ADSP-2100 Fam ily Code Com patible, w ith Instruction
Set Extensions
HOST MODE
40K Bytes of On-Chip RAM, Configured as
8K Words On-Chip Program Mem ory RAM and
8K Words On-Chip Data Mem ory RAM
Dual Purpose Program Mem ory for Both Instruction
and Data Storage
Six External Interrupts
13 Program m able Flag Pins Provide Flexible System
Signaling
UART Em ulation through Softw are SPORT Reconfiguration
ICE-Port™* Em ulator Interface Supports Debugging
in Final System s
Independent ALU, Multiplier/ Accum ulator and Barrel
Shifter Com putational Units
Tw o Independent Data Address Generators
Pow erful Program Sequencer Provides
Zero Overhead Looping Conditional Instruction
Execution
Program m able 16-Bit Interval Tim er w ith Prescaler
100-Lead TQFP
GENERAL NO TE
T his data sheet represents production grade specifications for
the ADSP-2186 (5 V) processor. T his data sheet also contains
preliminary (x-grade) specifications for the new ADSP-2186
40 MHz processor.
SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to
On-Chip Mem ory (Mode Selectable)
4 MByte Byte Mem ory Interface for Storage of Data
Tables & Program Overlays
GENERAL D ESCRIP TIO N
T he ADSP-2186 is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications.
T he ADSP-2186 combines the ADSP-2100 family base archi-
tecture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities and on-chip program and data
memory.
8-Bit DMA to Byte Mem ory for Transparent Program
and Data Mem ory Transfers (Mode Selectable)
I/ O Mem ory Interface w ith 2048 Locations Supports
Parallel Peripherals (Mode Selectable)
Program m able Mem ory Strobe and Separate I/ O Mem ory
Space Perm its “Glueless” System Design
(Mode Selectable)
Program m able Wait State Generation
Tw o Double-Buffered Serial Ports w ith Com panding
Hardw are and Autom atic Data Buffering
Autom atic Booting of On-Chip Program Mem ory from
Byte-Wide External Mem ory, e.g., EPROM, or
Through Internal DMA Port
T he ADSP-2186 integrates 40K bytes of on-chip memory con-
figured as 8K words (24-bit) of program RAM and 8K words
(16-bit) of data RAM. Power-down circuitry is also provided to
meet the low power needs of battery operated portable equip-
ment. T he ADSP-2186 is available in 100-pin T QFP package.
In addition, the ADSP-2186 supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (x squared),
*ICE -P or t is a tr adem ar k of Analog D evices, Inc.
All tr adem ar ks ar e the pr oper ty of their r espective holder s.
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1997
ADSP-2186
EZ-ICE®* connector, emulation can be supported in final board
designs.
biased rounding, result free ALU operations, I/O memory trans-
fers and global interrupt masking for increased flexibility.
T he EZ-ICE®* performs a full range of functions, including:
Fabricated in a high speed, double metal, low power, CMOS
process, the ADSP-2186 operates with a 30 ns instruction cycle
time. Every instruction can execute in a single processor cycle.
• In-target operation
• Up to 20 breakpoints
• Single-step or full-speed operation
T he ADSP-2186’s flexible architecture and comprehensive
instruction set allow the processor to perform multiple opera-
tions in parallel. In one processor cycle the ADSP-2186 can:
• Registers and memory values can be examined and altered
• PC upload and download functions
• Instruction-level emulation of program booting and execution
• Complete assembly and disassembly of instructions
• C source-level debugging
See Designing An EZ-ICE®*-Compatible T arget System in the
ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections), as
well as the T arget Board Connector for EZ-ICE®* Probe sec-
tion of this data sheet, for the exact specifications of the EZ-
ICE®* target board connector.
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
T his takes place while the processor continues to:
• Receive and transmit data through the two serial ports
• Receive and/or transmit data through the internal DMA port
• Receive and/or transmit data through the byte DMA port
• Decrement timer
Additional Infor m ation
T his data sheet provides a general overview of ADSP-2186
functionality. For additional information on the architecture and
instruction set of the processor, refer to the ADSP-2100 Family
User’s Manual. For more information about the development
tools, refer to the ADSP-2100 Family Development Tools Data
Sheet.
D evelopm ent System
T he ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, sup-
ports the ADSP-2186. T he System Builder provides a high level
method for defining the architecture of systems under develop-
ment. T he Assembler has an algebraic syntax that is easy to
program and debug. T he Linker combines object files into an
executable file. The Simulator provides an interactive instruction-
level simulation with a reconfigurable user interface to display
different portions of the hardware environment. A PROM
Splitter generates PROM programmer compatible files. T he
C Compiler, based on the Free Software Foundation’s GNU
C Compiler, generates ADSP-2186 assembly source code.
T he source code debugger allows programs to be corrected in
the C environment. T he Runtime Library includes over 100
ANSI-standard mathematical and DSP-specific functions.
ARCH ITECTURE O VERVIEW
T he ADSP-2186 instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single pro-
cessor cycle. T he ADSP-2186 assembly language uses an alge-
braic syntax for ease of coding and readability. A comprehensive
set of development tools supports program development.
POWER-DOWN
CONTROL
FULL MEMORY
MODE
MEMORY
PROGRAMMABLE
DATA ADDRESS
GENERATORS
I/O
AND
FLAGS
EXTERNAL
ADDRESS
BUS
8K 24
PROGRAM
MEMORY
816
DATA
PROGRAM
SEQUENCER
T he EZ-KIT Lite is a hardware/software kit offering a complete
development environment for the entire ADSP-21xx family: an
ADSP-218x based evaluation board with PC monitor software
plus Assembler, Linker, Simulator and PROM Splitter software.
The ADSP-21xx EZ-KIT Lite is a low cost, easy to use hardware
platform on which you can quickly get started with your DSP soft-
ware design. T he EZ-KIT Lite includes the following features:
DAG 1 DAG 2
MEMORY
EXTERNAL
DATA
BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
BYTE DMA
CONTROLLER
PROGRAM MEMORY DATA
DATA MEMORY DATA
OR
EXTERNAL
DATA
BUS
• 33 MHz ADSP-2181
ARITHMETIC UNITS
ALU SHIFTER
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
• Full 16-bit Stereo Audio I/O with AD1847 SoundPort®*
Codec
INTERNAL
DMA
PORT
MAC
ADSP-2100 BASE
ARCHITECTURE
• RS-232 Interface to PC with Microsoft® Windows 3.1
Control Software
HOST MODE
• EZ-ICE®* Connector for Emulator Control
• DSP Demo Programs
Figure 1. Block Diagram
Figure 1 is an overall block diagram of the ADSP-2186. T he
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. T he
computational units process 16-bit data directly and have provi-
sions to support multiprecision computations. T he ALU per-
forms a standard set of arithmetic and logic operations; division
primitives are also supported. T he MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with
40 bits of accumulation. T he shifter performs logical and arith-
metic shifts, normalization, denormalization and derive expo-
nent operations.
T he ADSP-218x EZ-ICE®* Emulator aids in the hardware
debugging of an ADSP-2186 system. T he emulator consists of
hardware, host computer resident software, and the target board
connector. T he ADSP-2186 integrates on-chip emulation sup-
port with a 14-pin ICE-Port™* interface. T his interface pro-
vides a simpler target board connection that requires fewer
mechanical clearance considerations than other ADSP-2100
Family EZ-ICE®*s. T he ADSP-2186 device need not be re-
moved from the target system when using the EZ-ICE®*, nor
are any adapters needed. Due to the small footprint of the
*SoundP ort and EZ-ICE are registered tradem arks of Analog Devices, Inc.
REV. 0
–2–
ADSP-2186
and the power-down circuitry. T here is also a master RESET
signal. T he two serial ports provide a complete synchronous
serial interface with optional companding in hardware and a
wide variety of framed or frameless data transmit and receive
modes of operation.
T he shifter can be used to efficiently implement numeric
format control including multiword and block floating-point
representations.
T he internal result (R) bus connects the computational units so
the output of any unit may be the input of any unit on the next
cycle.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. T he sequencer supports conditional jumps, sub-
routine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADSP-2186 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain loops.
T he ADSP-2186 provides up to 13 general-purpose flag pins.
T he data input and output pins on SPORT 1 can be alternatively
configured as an input flag and an output flag. In addition, eight
flags are programmable as inputs or outputs, and three flags are
always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (T COUNT ) decrements every n processor
cycle, where n is a scaling value stored in an 8-bit register
(T SCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (T PERIOD).
T wo data address generators (DAGs) provide addresses for
simultaneous dual operand fetches from data memory and pro-
gram memory. Each DAG maintains and updates four address
pointers. Whenever the pointer is used to access data (indirect
addressing), it is post-modified by the value of one of four pos-
sible modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
circular buffers.
Ser ial P or ts
T he ADSP-2186 incorporates two complete synchronous serial
ports (SPORT 0 and SPORT 1) for serial communications and
multiprocessor communication.
Efficient data transfer is achieved with the use of five internal
buses:
Here is a brief list of the capabilities of the ADSP-2186 SPORTs.
For additional information on Serial Ports, refer to the ADSP-
2100 Family User’s Manual.
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
• SPORT s are bidirectional and have a separate, double-buff-
ered transmit and receive section.
• SPORT s can use an external serial clock or generate their own
serial clock internally.
T he two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
• SPORT s have independent framing for the receive and trans-
mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulse widths and timings.
Program memory can store both instructions and data, permit-
ting the ADSP-2186 to fetch two operands in a single cycle, one
from program memory and one from data memory. T he ADSP-
2186 can fetch an operand from program memory and the next
instruction in the same cycle.
• SPORT s support serial data word lengths from 3 to 16 bits
and provide optional A-law and µ-law companding according
to CCIT T recommendation G.711.
When configured in host mode, the ADSP-2186 has a 16-bit
Internal DMA port (IDMA port) for connection to external
systems. T he IDMA port is made up of 16 data/address pins
and five control pins. T he IDMA port provides transparent,
direct access to the DSPs on-chip program and data RAM.
• SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.
• SPORT s can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.
An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). T he BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
• SPORT 0 has a multichannel interface to selectively receive
and transmit a 24 or 32 word, time-division multiplexed,
serial bitstream.
• SPORT 1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. T he
internally generated serial clock may still be used in this
configuration.
T he byte memory and I/O memory space interface supports
slow memories and I/O memory-mapped peripherals with
programmable wait state generation. External devices can
gain control of external buses with bus request/grant signals
(BR, BGH and BG). One execution mode (Go Mode) allows
the ADSP-2186 to continue running from on-chip memory.
Normal execution mode requires the processor to halt while
buses are granted.
P IN D ESCRIP TIO NS
T he ADSP-2186 will be available in a 100-lead T QFP package.
In order to maintain maximum functionality and reduce pack-
age size and pin count, some serial port, programmable flag,
interrupt and external bus pins have dual, multiplexed function-
ality. T he external bus pins are configured during RESET only,
while serial port pins are software configurable during program
execution. Flag and interrupt functionality is retained
T he ADSP-2186 can respond to eleven interrupts. T here are up
to six external interrupts (one edge-sensitive, two level-sensitive
and three configurable) and seven internal interrupts generated
by the timer, the serial ports (SPORT s), the Byte DMA port
REV. 0
–3–
ADSP-2186
concurrently on multiplexed pins. In cases where pin func-
tionality is reconfigurable, the default state is shown in plain
text; alternate functionality is shown in italics.
Mem or y Inter face P ins
T he ADSP-2186 processor can be used in one of two modes:
Full Memory Mode, which allows BDMA operation with full
external overlay memory and I/O capability, or Host Mode,
which allows IDMA operation with limited external addressing
capabilities. T he operating mode is determined by the state of
the Mode C pin during RESET and cannot be changed while
the processor is running.
Com m on-Mode P ins
#
of
Input/
O ut-
P in
Nam e(s)
P ins put
Function
RESET
BR
1
1
1
1
1
1
1
1
1
1
1
1
I
Processor Reset Input
Full Mem or y Mode Pins (Mode C = 0)
I
Bus Request Input
#
BG
O
O
O
O
O
O
O
O
O
I
Bus Grant Output
of
Input/
BGH
DMS
PMS
IOMS
BMS
CMS
RD
Bus Grant Hung Output
Data Memory Select Output
Program Memory Select Output
Memory Select Output
P in Nam e P ins
O utput Function
A13:0
D23:0
14
24
O
Address Output Pins for Pro-
gram, Data, Byte and I/O Spaces
I/O
Data I/O Pins for Program,
Data, Byte and I/O Spaces
(8 MSBs Are Also Used as
Byte Memory Addresses)
Byte Memory Select Output
Combined Memory Select Output
Memory Read Enable Output
Memory Write Enable Output
WR
IRQ2/
Edge- or Level-Sensitive
Host Mode Pins (Mode C = 1)
Interrupt Request1
#
PF7
I/O
Programmable I/O Pin
Level-Sensitive Interrupt Requests1
Programmable I/O Pin
Level-Sensitive Interrupt Requests1
Programmable I/O Pin
Edge-Sensitive Interrupt Requests1
Programmable I/O Pin
of
Input/
O utput Function
IRQL0/
PF5
1
1
1
I
P in Nam e P ins
I/O
IAD15:0
A0
16
1
I/O
O
IDMA Port Address/Data Bus
IRQL1/
PF6
I
I/O
Address Pin for External I/O,
Program, Data, or Byte Access
IRQE/
PF4
I
I/O
D23:8
16
I/O
Data I/O Pins for Program,
Data Byte and I/O Spaces
PF3
1
1
I/O
I
Programmable I/O Pin
Mode C/
Mode Select Input—Checked
only During RESET
Programmable I/O Pin During
Normal Operation
IWR
IRD
IAL
1
1
1
1
1
I
IDMA Write Enable
IDMA Read Enable
IDMA Address Latch Pin
IDMA Select
I
PF2
I/O
I
IS
I
Mode B/
PF1
1
1
I
Mode Select Input—Checked
only During RESET
Programmable I/O Pin During
Normal Operation
IACK
O
IDMA Port Acknowledge
I/O
In Host Mode, external peripheral addresses can be decoded using the A0,
CMS, PMS, DMS, and IOMS signals.
Mode A/
PF0
I
Mode Select Input—Checked
only During RESET
Programmable I/O Pin During
Normal Operation
Setting Mem or y Mode
Memory Mode selection for the ADSP-2186 is made during
chip reset through the use of the Mode C pin. T his pin is multi-
plexed with the DSP’s PF2 pin, so care must be taken in how
the mode selection is made. T he two methods for selecting the
value of Mode C are active and passive.
I/O
CLKIN, XTAL
CLKOUT
2
1
5
5
I
Clock or Quartz Crystal Input
Processor Clock Output
Serial Port I/O Pins
O
SPORT 0
I/O
I/O
Passive configuration involves the use a pull-up or pull-down
resistor connected to the Mode C pin. T o minimize power
consumption, or if the PF2 pin is to be used as an output in the
DSP application, a weak pull-up or pull-down, on the order of
100 kΩ, can be used. T his value should be sufficient to pull the
pin to the desired level and still allow the pin to operate as a
programmable flag output without undue strain on the processor’s
output driver. For minimum power consumption during
power-down, reconfigure PF2 to be an input, as the pull-up or
pull-down will hold the pin in a known state, and will not switch.
SPORT 1
IRQ1:0
FI, FO
Serial Port I/O Pins
Edge- or Level-Sensitive Interrupts,
Flag In, Flag Out2
PWD
1
I
Power-Down Control Input
Power-Down Control Output
Output Flags
PWDACK
FL0, FL1, FL2
VDD and GND
EZ-Port
1
O
O
I
3
16
9
Power and Ground
I/O
For Emulation Use
NOT ES
1Interrupt/Flag pins retain both functions concurrently. If IMASK is set to
enable the corresponding interrupts, the DSP will vector to the appropriate
interrupt vector address when the pin is asserted, either by external devices or
set as a programmable flag.
Active configuration involves the use of a three-stateable exter-
nal driver connected to the Mode C pin. A driver’s output en-
able should be connected to the DSP’s RESET signal such that
it only drives the PF2 pin when RESET is active (low). After
RESET is deasserted, the driver should three-state, thus allow-
ing full use of the PF2 pin as either an input or output.
2SPORT configuration determined by the DSP System Control Register. Soft-
ware configurable.
REV. 0
–4–
ADSP-2186
T o minimize power consumption during power-down, configure
the programmable flag as an output when connected to a three-
stated buffer. T his ensures that the pin will be held at a constant
level and not oscillate should the three-state driver’s level hover
around the logic switching point.
T he IFC register is a write-only register used to force and clear
interrupts.
On-chip stacks preserve the processor status and are automati-
cally maintained during interrupt handling. The stacks are twelve
levels deep to allow interrupt, loop and subroutine nesting.
Inter r upts
T he following instructions allow global enable or disable servic-
ing of the interrupts (including power-down), regardless of the
state of IMASK. Disabling the interrupts does not affect serial
port autobuffering or DMA.
T he interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
T he ADSP-2186 provides four dedicated external interrupt
input pins, IRQ2, IRQL0, IRQL1 and IRQE (shared with the
PF7:4 pins). In addition, SPORT 1 may be reconfigured for
IRQ0, IRQ1, FLAG_IN and FLAG_OUT , for a total of six
external interrupts. T he ADSP-2186 also supports internal
interrupts from the timer, the byte DMA port, the two serial
ports, software and the power-down control circuit. T he inter-
rupt levels are internally prioritized and individually maskable
(except power-down and reset). T he IRQ2, IRQ0 and IRQ1
input pins can be programmed to be either level- or edge-sensitive.
IRQL0 and IRQL1 are level-sensitive and IRQE is edge-sensitive.
T he priorities and vector addresses of all interrupts are shown in
T able I.
ENA INTS;
DIS INTS;
When the processor is reset, interrupt servicing is enabled.
LO W P O WER O P ERATIO N
T he ADSP-2186 has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. T hese modes are:
• Power-Down
• Idle
• Slow Idle
Table I. Interrupt P riority & Interrupt Vector Addresses
T he CLKOUT pin may also be disabled to reduce external
power dissipation.
Source O f Interrupt
Interrupt Vector Address (Hex)
P ower -D own
Reset (or Power-Up with
PUCR = 1)
T he ADSP-2186 processor has a low power feature that lets the
processor enter a very low power dormant state through hard-
ware or software control. Here is a brief list of power-down
features. Refer to the ADSP-2100 Family User’s Manual, “System
Interface” chapter, for detailed information about the power-
down feature.
0000 (Highest Priority)
Power-Down (Nonmaskable) 002C
IRQ2
0004
0008
000C
0010
0014
0018
001C
IRQL1
IRQL0
SPORT 0 T ransmit
SPORT 0 Receive
IRQE
•
Quick recovery from power-down. T he processor begins
executing instructions in as few as 100 CLKIN cycles.
•
Support for an externally generated T T L or CMOS proces-
sor clock. T he external clock can continue running during
power-down without affecting the lowest power rating and
100 CLKIN cycle recovery.
BDMA Interrupt
SPORT 1 T ransmit or IRQ1 0020
SPORT 1 Receive or IRQ0
0024
•
Support for crystal operation includes disabling the oscillator
to save power (the processor automatically waits approxi-
mately 4096 CLKIN cycles for the crystal oscillator to start
or stabilize), and letting the oscillator run to allow 100 CLKIN
cycle start-up.
T imer
0028 (Lowest Priority)
Interrupt routines can either be nested, with higher priority
interrupts taking precedence, or processed sequentially. Inter-
rupts can be masked or unmasked with the IMASK register.
Individual interrupt requests are logically ANDed with the bits
in IMASK; the highest priority unmasked interrupt is then
selected. T he power-down interrupt is nonmaskable.
•
•
Power-down is initiated by either the power-down pin (PWD)
or the software power-down force bit.
Interrupt support allows an unlimited number of instructions
to be executed before optionally powering down. T he power-
down interrupt also can be used as a nonmaskable, edge-
sensitive interrupt.
T he ADSP-2186 masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. T his does not affect serial port autobuffering
or DMA transfers.
•
Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
power-down state.
T he interrupt control register, ICNT L, controls interrupt nest-
ing and defines the IRQ0, IRQ1 and IRQ2 external interrupts to
be either edge- or level-sensitive. T he IRQE pin is an external
edge-sensitive interrupt and can be forced and cleared. T he
IRQL0 and IRQL1 pins are external level-sensitive interrupts.
•
•
T he RESET pin also can be used to terminate power-down.
Power-down acknowledge pin indicates when the processor
has entered power-down.
REV. 0
–5–
ADSP-2186
FULL MEMORY MODE
ADSP-2186
Idle
When the ADSP-2186 is in the Idle Mode, the processor waits
indefinitely in a low power state until an interrupt occurs. When
an unmasked interrupt occurs, it is serviced; execution then
continues with the instruction following the IDLE instruction.
In Idle mode IDMA, BDMA and autobuffer cycle steals still
occur.
A
14
13-0
1/2x CLOCK
OR
CRYSTAL
CLKIN
ADDR13-0
XTAL
D
A0-A21
DATA
23-16
FL0-2
BYTE
D
24
15-8
PF3
MEMORY
DATA23-0
/PF7
/PF4
/PF5
/PF6
A
10-0
Slow Idle
ADDR
DATA
D
MODE C/PF2
MODE B/PF1
MODE A/PF0
23-8
I/O SPACE
(PERIPHERALS)
2048 LOCATIONS
T he IDLE instruction is enhanced on the ADSP-2186 to let the
processor’s internal clock signal be slowed, further reducing
power consumption. T he reduced clock frequency, a program-
mable fraction of the normal clock rate, is specified by a select-
able divisor given in the IDLE instruction. T he format of the
instruction is
A
13-0
ADDR
DATA
SPORT1
SCLK1
RFS1 O
TFS1 O
DT1 OR FO
DR1 OR FI
OVERLAY
MEMORY
D
23-0
SERIAL
DEVICE
TWO 8K
PM SEGMENTS
TWO 8K
DM SEGMENTS
IDLE (n);
SPORT0
SCLK0
RFS0
TFS0
DT0
SERIAL
DEVICE
where n = 16, 32, 64 or 128. T his instruction keeps the proces-
sor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals,
such as SCLK, CLKOUT and timer clock, are reduced by the
same ratio. T he default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.
DR0
HOST MEMORY MODE
ADSP-2186
1/2x CLOCK
OR
CRYSTAL
CLKIN
ADDR0
XTAL
1
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to in-
coming interrupts. T he one-cycle response time of the standard
idle state is increased by n, the clock divisor. When an enabled
interrupt is received, the ADSP-2186 will remain in the idle
state for up to a maximum of n processor cycles (n = 16, 32, 64
or 128) before resuming normal operation.
FL0-2
PF3
16
DATA23-8
/PF7
/PF4
/PF5
/PF6
MODE C/PF2
MODE B/PF1
MODE A/PF0
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
SPORT1
SCLK1
RFS1 O
TFS1 O
DT1 OR FO
DR1 OR FI
SERIAL
DEVICE
SPORT0
SCLK0
RFS0
TFS0
DT0
SERIAL
DEVICE
DR0
IDMA PORT
/D6
/D7
/D4
IAL/D5
/D3
SYSTEM INTERFACE
SYSTEM
INTERFACE
OR
Figure 2 shows typical basic system configurations with the
ADSP-2186, two serial devices, a byte-wide EPROM and optional
external program and data overlay memories (mode selectable).
Programmable wait state generation allows the processor to
connect easily to slow peripheral devices. T he ADSP-2186 also
provides four external interrupts and two serial ports or six
external interrupts and one serial port. Host Memory Mode
allows access to the full external data bus, but limits addressing
to a single address bit (A0). Additional system peripherals can
be added in this mode through the use of external hardware to
generate and latch address signals.
µCONTROLLER
16
IAD15-0
Figure 2. Basic System Configuration
REV. 0
–6–
ADSP-2186
Clock Signals
T he master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MST AT
register. When RESET is released, if there is no pending bus
request and the chip is configured for booting, the boot-loading
sequence is performed. T he first instruction is fetched from
on-chip program memory location 0x0000 once boot loading
completes.
T he ADSP-2186 can be clocked by either a crystal or a T T L-
compatible clock signal.
T he CLKIN input cannot be halted, changed during operation
or operated below the specified frequency during normal opera-
tion. T he only exception is while the processor is in the power-
down state. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual, for detailed information on
this power-down feature.
MEMO RY ARCH ITECTURE
T he ADSP-2186 provides a variety of memory and peripheral
interface options. The key functional groups are Program Memory,
Data Memory, Byte Memory and I/O.
If an external clock is used, it should be a T T L-compatible
signal running at half the instruction rate. T he signal is con-
nected to the processor’s CLKIN input. When an external clock
is used, the XT AL input must be left unconnected.
P rogram Mem ory (Full Mem ory Mode) is a 24-bit-wide space
for storing both instruction opcodes and data. The ADSP-2186
has 8K words of Program Memory RAM on chip, and the capabil-
ity of accessing up to two 8K external memory overlay spaces using
the external data bus. Both an instruction opcode and a data value
can be read from on-chip program memory in a single cycle.
T he ADSP-2186 uses an input clock with a frequency equal to
half the instruction rate; a 16.67 MHz input clock yields a 30 ns
processor cycle (which is equivalent to 33 MHz). Normally,
instructions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.
D ata Mem or y (Full Mem or y Mode) is a 16-bit-wide space
used for the storage of data variables and for memory-mapped
control registers. T he ADSP-2186 has 8K words on Data
Memory RAM on chip, consisting of 8160 user-accessible
locations and 32 memory-mapped registers. Support also exists
for up to two 8K external memory overlay spaces through the
external data bus.
Because the ADSP-2186 includes an on-chip oscillator circuit,
an external crystal may be used. T he crystal should be con-
nected across the CLKIN and XT AL pins, with two capacitors
connected as shown in Figure 3. Capacitor values are dependent
on crystal type and should be specified by the crystal manufac-
turer. A parallel-resonant, fundamental frequency, microproces-
sor-grade crystal should be used.
Byte Mem or y (Full Mem or y Mode) provides access to an
8-bit wide memory space through the Byte DMA (BDMA) port.
T he Byte Memory interface provides access to 4 MBytes of
memory by utilizing eight data lines as additional address lines.
T his gives the BDMA Port an effective 22-bit address range. On
power-up, the DSP can automatically load bootstrap code from
byte memory.
A clock output (CLKOUT ) signal is generated by the proces-
sor at the processor’s cycle rate. T his can be enabled and
disabled by the CLKODIS bit in the SPORT 0 Autobuffer
Control Register.
I/O Space (Full Mem or y Mode) allows access to 2048 loca-
tions of 16-bit-wide data. It is intended to be used to communi-
cate with parallel peripheral devices such as data converters and
external registers or latches.
XTAL
CLKIN
CLKOUT
DSP
P r ogr am Mem or y
T he ADSP-2186 contains an 8K × 24 on-chip program RAM.
T he on-chip program memory is designed to allow up to two
accesses each cycle so that all operations can complete in a
single cycle. In addition, the ADSP-2186 allows the use of 8K
external memory overlays.
Figure 3. External Crystal Connections
Reset
T he RESET signal initiates a master reset of the ADSP-2186.
T he RESET signal must be asserted during the power-up
sequence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
T he program memory space organization is controlled by the
Mode B pin and the PMOVLAY register. Normally, the ADSP-
2186 is configured with Mode B = 0 and program memory
organized as shown in Figure 4.
PROGRAM MEMORY
ADDRESS
0x3FFF
T he power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is
applied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked, but does
not include the crystal oscillator start-up time. During this
power-up sequence the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the mini-
EXTERNAL 8K
(PMOVLAY = 1 or 2,
MODE B = 0)
0x2000
0x1FFF
8K INTERNAL
mum pulse width specification, tRSP
.
T he RESET input contains some hysteresis; however, if you use
an RC circuit to generate your RESET signal, the use of an
external Schmidt trigger is recommended.
0x0000
Figure 4. Program Mem ory (Mode B = 0)
REV. 0
–7–
ADSP-2186
T here are 8K words of memory accessible internally when the
PMOVLAY register is set to 0. When PMOVLAY is set to some-
thing other than 0, external accesses occur at addresses 0x2000
through 0x3FFF. T he external address is generated as shown in
T able II.
T here are 8160 words of memory accessible internally when the
DMOVLAY register is set to 0. When DMOVLAY is set to
something other than 0, external accesses occur at addresses
0x0000 through 0x1FFF. T he external address is generated as
shown in T able III.
Table II.
Table III.
P MO VLAY Mem ory A13
A12:0
D MO VLAY Mem ory A13
A12:0
0
1
Internal
Not Applicable Not Applicable
13 LSBs of Address
0
1
Internal
Not Applicable Not Applicable
13 LSBs of Address
External
Overlay 1
External
Overlay 1
0
Between 0x2000
and 0x3FFF
0
Between 0x2000
and 0x3FFF
2
External
Overlay 2
13 LSBs of Address
Between 0x2000
and 0x3FFF
2
External
Overlay 2
13 LSBs of Address
Between 0x2000
and 0x3FFF
1
1
NOT E: Addresses 0x2000 through 0x3FFF should not be accessed when
PMOVLAY = 0.
T his organization allows for two external 8K overlays using only
the normal 14 address bits. All internal accesses complete in one
cycle. Accesses to external memory are timed using the wait
states specified by the DWAIT register.
T his organization provides for two external 8K overlay segments
using only the normal 14 address bits, which allows for simple
program overlays using one of the two external segments in
place of the on-chip memory. Care must be taken in using this
overlay space in that the processor core (i.e., the sequencer)
does not take into account the PMOVLAY register value. For
example, if a loop operation was occurring on one of the exter-
nal overlays and the program changes to another external over-
lay or internal memory, an incorrect loop operation could occur.
In addition, care must be taken in interrupt service routines as
the overlay registers are not automatically saved and restored on
the processor mode stack.
I/O Space (Full Mem or y Mode)
T he ADSP-2186 supports an additional external memory space
called I/O space. T his space is designed to support simple con-
nections to peripherals or to bus interface ASIC data registers.
I/O space supports 2048 locations. T he lower eleven bits of the
external address bus are used; the upper three bits are unde-
fined. T wo instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. T he I/O space also has four dedicated three-bit wait state
registers, IOWAIT 0-3, which specify up to seven wait states to
be automatically generated for each of four regions. T he wait
states act on address ranges as shown in T able IV.
When Mode B = 1, booting is disabled and overlay memory is
disabled (PMOVLAY must be 0). Figure 5 shows the memory
map in this configuration.
PROGRAM MEMORY
ADDRESS
Table IV.
0x3FFF
Address Range
Wait State Register
RESERVED
0x000–0x1FF
0x200–0x3FF
0x400–0x5FF
0x600–0x7FF
IOWAIT 0
IOWAIT 1
IOWAIT 2
IOWAIT 3
0x2000
0x1FFF
8K EXTERNAL
0x0000
Com posite Mem or y Select (CMS)
T he ADSP-2186 has a programmable memory select signal that
is useful for generating memory select signals for memories
mapped to more than one space. T he CMS signal is generated
to have the same timing as each of the individual memory select
signals (PMS, DMS, BMS, IOMS), but can combine their
functionality.
Figure 5. Program Mem ory (Mode B = 1)
D ata Mem or y
T he ADSP-2186 has 8160 16-bit words of internal data memory.
In addition, the ADSP-2186 allows the use of 8K external memory
overlays. Figure 6 shows the organization of the data memory.
DATA MEMORY
ADDRESS
Each bit in the CMSSEL register, when set, causes the CMS
signal to be asserted when the selected memory select is as-
serted. For example, to use a 32K word memory to act as both
program and data memory, set the PMS and DMS bits in the
CMSSEL register and use the CMS pin to drive the chip select
of the memory and use either DMS or PMS as the additional
address bit.
0x3FFF
32 MEMORY–
MAPPED REGISTERS
0x3FEO
0x3FDF
INTERNAL
8160 WORDS
0x2000
0x1FFF
T he CMS pin functions as the other memory select signals, with
the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the
selected memory select signal. All enable bits, except the BMS
bit, default to 1 at reset.
EXTERNAL 8K
(DMOVLAY = 1, 2)
0x0000
Figure 6. Data Mem ory
REV. 0
–8–
ADSP-2186
Byte Mem or y
When the BWCOUNT register is written with a nonzero value,
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT . T hese accesses continue until the
count reaches zero. When enough accesses have occurred to
create a destination word, it is transferred to or from on-chip
memory. T he transfer takes one DSP cycle. DSP accesses to
external memory have priority over BDMA byte memory
accesses.
T he byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. T he byte memory space
consists of 256 pages, each of which is 16K × 8.
T he byte memory space on the ADSP-2186 supports read and
write operations as well as four different data formats. T he byte
memory uses data bits 15:8 for data. T he byte memory uses
data bits 23:16 and address bits 13:0 to create a 22-bit address.
T his allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be
used without glue logic. All byte memory accesses are timed by
the BMWAIT register.
T he BDMA Context Reset bit (BCR) controls whether the
processor is held off while the BDMA accesses are occurring.
Setting the BCR bit to 0 allows the processor to continue opera-
tions. Setting the BCR bit to 1 causes the processor to stop
execution while the BDMA accesses are occurring, to clear the
context of the processor and start execution at address 0 when
the BDMA accesses have completed.
Byte Mem or y D MA (BD MA, Full Mem or y Mode)
T he Byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
T he BDMA circuit is able to access the byte memory space
while the processor is operating normally and steals only one
DSP cycle per 8-, 16- or 24-bit word transferred.
Internal Mem ory DMA P ort (IDMA P ort; Host Mem ory Mode)
T he IDMA Port provides an efficient means of communication
between a host system and the ADSP-2186. T he port is used to
access the on-chip program memory and data memory of the
DSP with only one DSP cycle per word overhead. T he IDMA
port cannot, however, be used to write to the DSP’s memory-
mapped control registers.
T he BDMA circuit supports four different data formats, which
are selected by the BT YPE register field. T he appropriate num-
ber of 8-bit accesses are done from the byte memory space to
build the word size selected. T able V shows the data formats
supported by the BDMA circuit.
T he IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. T he IDMA port is com-
pletely asynchronous and can be written to while the ADSP-
2186 is operating at full speed.
Table V.
Internal
T he DSP memory address is latched and then automatically
incremented after each IDMA transaction. An external device
can therefore access a block of sequentially addressed memory
by specifying only the starting address of the block. T his in-
creases throughput as the address does not have to be sent for
each memory access.
BTYP E
Mem ory Space
Word Size
Alignm ent
00
01
10
11
Program Memory
Data Memory
Data Memory
Data Memory
24
16
8
Full Word
Full Word
MSBs
8
LSBs
IDMA Port access occurs in two phases. T he first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a 14-bit
address and 1-bit destination type can be driven onto the bus by
an external device. T he address specifies an on-chip memory
location, the destination type specifies whether it is a DM or
PM access. T he falling edge of the address latch signal latches
this value into the IDMAA register.
Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address for
the on-chip memory involved with the transfer. The 14-bit BEAD
register specifies the starting address for the external byte memory
space. The 8-bit BMPAGE register specifies the starting page for
the external byte memory space. T he BDIR register field selects
the direction of the transfer. Finally the 14-bit BWCOUNT
register specifies the number of DSP words to transfer and
initiates the BDMA circuit transfers.
Once the address is stored, data can then either be read from or
written to the ADSP-2186’s on-chip memory. Asserting the
select line (IS) and the appropriate read or write line (IRD and
IWR respectively) signals the ADSP-2186 that a particular
transaction is required. In either case, there is a one-processor-
cycle delay for synchronization. T he memory access consumes
one additional processor cycle.
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
T he BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is gener-
ated. T he BMPAGE and BEAD registers must not be accessed
by the DSP during BDMA operations.
Once an access has occurred, the latched address is automati-
cally incremented and another access can occur.
T hrough the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation.
T he source or destination of a BDMA transfer will always be
on-chip program or data memory, regardless of the values of
Mode B, PMOVLAY or DMOVLAY.
REV. 0
–9–
ADSP-2186
Bootstr ap Loading (Booting)
gram execution to be held off until all 32 words are loaded into
on-chip program memory. Execution then begins at address 0.
T he ADSP-2186 has two mechanisms to allow automatic load-
ing of the internal program memory after reset. T he method for
booting is controlled by the Mode A, B and C configuration bits
as shown in T able VI. T hese four states can be compressed into
two-state bits by allowing an IDMA boot with Mode C = 1.
However, three bits are used to ensure future compatibility with
parts containing internal program memory ROM.
T he ADSP-2100 Family development software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate byte memory space compatible boot code.
T he IDLE instruction can also be used to allow the processor to
hold off execution while booting continues through the BDMA
interface. For BDMA accesses while in H ost Mode, the ad-
dresses to boot memory must be constructed externally to the
ADSP-2186. T he only memory address bit provided by the
processor is A0.
BD MA Booting
When the MODE pins specify BDMA booting, the ADSP-2186
initiates a BDMA boot sequence when RESET is released.
ID MA P or t Booting
Table VI. Boot Sum m ary Table
T he ADSP-2186 can also boot programs through its Internal
DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1, the
ADSP-2186 boots from the IDMA port. IDMA feature can load
as much on-chip memory as desired. Program execution is held
off until on-chip program memory location 0 is written to.
MO D E C MO D E B MO D E A Booting Method
0
0
0
BDMA feature is used to load
the first 32 program memory
words from the byte memory
space. Program execution is
held off until all 32 words
have been loaded. Chip is
configured in Full Memory
Mode.
Bus Request & Bus Gr ant
T he ADSP-2186 can relinquish control of the data and address
buses to an external device. When the external device requires
access to memory, it asserts the bus request (BR) signal. If the
ADSP-2186 is not performing an external memory access, it
responds to the active BR input in the following processor cycle
by:
0
1
0
No Automatic boot opera-
tions occur. Program execu-
tion starts at external memory
location 0. Chip is config-
ured in Full Memory Mode.
BDMA can still be used but
the processor does not auto-
matically use or wait for these
operations.
• T hree-stating the data and address buses and the PMS, DMS,
BMS, CMS, IOMS, RD, WR output drivers,
• Asserting the bus grant (BG) signal, and
• Halting program execution.
If Go Mode is enabled, the ADSP-2186 will not halt program
execution until it encounters an instruction that requires an
external memory access.
1
0
0
BDMA feature is used to load
the first 32 program memory
words from the byte memory
space. Program execution is
held off until all 32 words
have been loaded. Chip is
configured in Host Mode.
Additional interface hardware
is required.
If the ADSP-2186 is performing an external memory access
when the external device asserts the BR signal, then it will not
three-state the memory interfaces or assert the BG signal until
the processor cycle after the access completes. T he instruction
does not need to be completed when the bus is granted. If a
single instruction requires two external memory accesses, the
bus will be granted between the two accesses.
When the BR signal is released, the processor releases the BG
signal, reenables the output drivers and continues program
execution from the point where it stopped.
1
0
1
IDMA feature is used to load
any internal memory as de-
sired. Program execution is
held off until internal pro-
gram memory location 0 is
written to. Chip is configured
in Host Mode.
T he bus request feature operates at all times, including when
the processor is booting and when RESET is active.
T he BGH pin is asserted when the ADSP-2186 is ready to
execute an instruction but is stopped because the external bus is
already granted to another device. T he other device can release
the bus by deasserting bus request. Once the bus is released, the
ADSP-2186 deasserts BG and BGH and executes the external
memory access.
The BDMA interface is set up during reset to the following de-
faults when BDMA booting is specified: the BDIR, BMPAGE,
BIAD and BEAD registers are set to 0; the BT YPE register is
set to 0 to specify program memory 24 bit words; and the
BWCOUNT register is set to 32. T his causes 32 words of on-
chip program memory to be loaded from byte memory. T hese
32 words are used to set up the BDMA to load in the remaining
program code. T he BCR bit is also set to 1, which causes pro-
Flag I/O P ins
The ADSP-2186 has eight general purpose programmable input/
output flag pins. T hey are controlled by two memory mapped
registers. T he PFT YPE register determines the direction,
1 = output and 0 = input. T he PFDAT A register is used to read
and write the values on the pins. Data being read from a pin
REV. 0
–10–
ADSP-2186
configured as an input is synchronized to the ADSP-2186’s
clock. Bits that are programmed as outputs will read the value
being output. T he PF pins default to input during reset.
•
•
Sixteen condition codes are available. For conditional jump,
call, return or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.
In addition to the programmable flags, the ADSP-2186 has five
fixed-mode flags, FLAG_IN, FLAG_OUT , FL0, FL1 and
FL2. FL0-FL2 are dedicated output flags. FLAG_IN and
FLAG_OUT are available as an alternate configuration of
SPORT 1.
Multifunction instructions allow parallel execution of an
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.
I/O Space Instr uctions
Note: Pins PF0, PF1 and PF2 are also used for device configu-
ration during reset.
T he instructions used to access the ADSP-2186’s I/O memory
space are as follows:
Syntax: IO(addr) = dreg
dreg = IO(addr);
BIASED RO UND ING
A mode is available on the ADSP-2186 to allow biased round-
ing in addition to the normal unbiased rounding. When the
BIASRND bit is set to 0, the normal unbiased rounding opera-
tions occur. When the BIASRND bit is set to 1, biased round-
ing occurs instead of the normal unbiased rounding. When
operating in biased rounding mode all rounding operations with
MR0 set to 0x8000 will round up, rather than only rounding up
odd MR1 values.
where addr is an address value between 0 and 2047 and dreg is
any of the 16 data registers.
Exam ples: IO(23) = AR0;
AR1 = IO(17);
D escr iption: T he I/O space read and write instructions move
data between the data registers and the I/O
memory space.
For example:
D ESIGNING AN EZ-ICE ®*-CO MP ATIBLE SYSTEM
T he ADSP-2186 has on-chip emulation support and an
ICE-Port™*, a special set of pins that interface to the EZ-ICE®*.
T hese features allow in-circuit emulation without replacing the
target system processor by using only a 14-pin connection from
the target system to the EZ-ICE®*. T arget systems must have a
14-pin connector to accept the EZ-ICE®*’s in-circuit probe, a
14-pin plug. See the ADSP-2100 Family EZ-Tools data sheet for
complete information on ICE products.
Table VII.
MR Value
Before RND
Biased
RND Result
Unbiased
RND Result
00-0000-8000
00-0001-8000
00-0000-8001
00-0001-8001
00-0000-7FFF
00-0001-7FFF
00-0001-8000
00-0002-8000
00-0001-8001
00-0002-8001
00-0000-7FFF
00-0001-7FFF
00-0000-8000
00-0002-8000
00-0001-8001
00-0002-8001
00-0000-7FFF
00-0001-7FFF
T he ICE-Port™* interface consists of the following ADSP-2186
pins:
T his mode only has an effect when the MR0 register contains
0x8000; all other rounding operations work normally. T his
mode allows more efficient implementation of bit-specified
algorithms that use biased rounding, for example the GSM
speech compression routines. Unbiased rounding is preferred
for most algorithms.
EBR
EBG
ERESET
EMS
EINT
ECLK
ELIN
ELOUT
EE
Note: BIASRND bit is Bit 12 of the SPORT 0 Autobuffer Con-
trol register.
Instr uction Set D escr iption
These ADSP-2186 pins must be connected only to the EZ-ICE®*
connector in the target system. T hese pins have no function
except during emulation, and do not require pull-up or
pull-down resistors. T he traces for these signals between the
ADSP-2186 and the connector must be kept as short as pos-
sible, no longer than three inches.
T he ADSP-2186 assembly language instruction set has an alge-
braic syntax that was designed for ease of coding and readabil-
ity. T he assembly language, which takes full advantage of the
processor’s unique architecture, offers the following benefits:
•
T he algebraic syntax eliminates the need to remember cryptic
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.
T he following pins are also used by the EZ-ICE®*:
BR
BG
RESET
GND
•
•
Every instruction assembles into a single, 24-bit word that
can execute in a single instruction cycle.
T he syntax is a superset ADSP-2100 Family assembly lan-
guage and is completely source and object code compatible
with other family members. Programs may need to be relo-
cated to utilize on-chip memory and conform to the ADSP-
2186’s interrupt vector and reset vector map.
T he EZ-ICE®* uses the EE (emulator enable) signal to take
control of the ADSP-2186 in the target system. T his causes the
processor to use its ERESET, EBR and EBG pins instead of
the RESET, BR and BG pins. T he BG output is three-stated.
T hese signals do not need to be jumper-isolated in your system.
REV. 0
–11–
ADSP-2186
T he EZ-ICE®* connects to your target system via a ribbon cable
and a 14-pin female plug. T he female plug is plugged onto the
14-pin connector (a pin strip header) on the target board.
trouble manufacturing your system as DSP components statisti-
cally vary in switching characteristic and timing requirements
within published limits.
Tar get Boar d Connector for EZ-ICE ®* P r obe
Restriction: All memory strobe signals on the ADSP-2186 (RD,
WR, PMS, DMS, BMS, CMS and IOMS) used in your target
system must have 10 kΩ pull-up resistors connected when the
EZ-ICE®* is being used. T he pull-up resistors are necessary
because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE®* debugging sessions. T hese resistors may be removed
at your option when the EZ-ICE®* is not being used.
T he EZ-ICE®* connector (a standard pin strip header) is shown
in Figure 7. You must add this connector to your target board
design if you intend to use the EZ-ICE®*. Be sure to allow
enough room in your system to fit the EZ-ICE®* probe onto the
14-pin connector.
1
3
5
2
4
BG
GND
Tar get System Inter face Signals
When the EZ-ICE®* board is installed, the performance on
some system signals change. Design your system to be compat-
ible with the following system interface signal changes intro-
duced by the EZ-ICE®* board:
EBG
BR
6
EBR
EINT
ELIN
ECLK
EMS
7
×
8
• EZ-ICE®* emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the RESET
signal.
• EZ-ICE®* emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the BR signal.
• EZ-ICE®* emulation ignores RESET and BR when single-
stepping.
KEY (NO PIN)
9
10
12
14
ELOUT
EE
11
13
RESET
ERESET
• EZ-ICE®* emulation ignores RESET and BR when in Emu-
TOP VIEW
lator Space (DSP halted).
Figure 7. Target Board Connector for EZ-ICE®*
• EZ-ICE®* emulation ignores the state of target BR in certain
modes. As a result, the target system may take control of the
DSP’s external memory bus only if bus grant (BG) is asserted
by the EZ-ICE®* board’s DSP.
T he 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-
tion—you must remove Pin 7 from the header. T he pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spac-
ing should be 0.1 × 0.1 inches. T he pin strip header must have
at least 0.15-inch clearance on all sides to accept the EZ-ICE®*
probe plug. Pin strip headers are available from vendors such as
3M, McKenzie and Samtec.
Tar get Mem or y Inter face
For your target system to be compatible with the EZ-ICE®*
emulator, it must comply with the memory interface guidelines
listed below.
P M, D M, BM, IO M, & CM
Design your Program Memory (PM), Data Memory (DM), Byte
Memory (BM), I/O Memory (IOM) and Composite Memory
(CM) external interfaces to comply with worst case device tim-
ing requirements and switching characteristics as specified in
this DSP’s data sheet. The performance of the EZ-ICE®* may
approach published worst case specification for some memory
access timing requirements and switching characteristics.
Note: If your target does not meet the worst case chip specifica-
tion for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency. Depend-
ing on the severity of the specification violation, you may have
REV. 0
–12–
ADSP-2186
ADSP-2186 SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade
B Grade
P aram eter
Min
Max
Min
Max
Unit
VDD
T AMB
4.5
0
5.5
+70
4.5
–40
5.5
+85
V
°C
ELECTRICAL CHARACTERISTICS
K/B Grades
Typ
P aram eter
Test Conditions
Min
Max
Unit
VIH
VIH
VIL
VOH
Hi-Level Input Voltage1, 2
Hi-Level CLKIN Voltage
Lo-Level Input Voltage1, 3
Hi-Level Output Voltage1, 4, 5
@ VDD = max
@ VDD = max
@ VDD = min
@ VDD = min
IOH = –0.5 mA
@ VDD = min
IOH = –100 µA6
@ VDD = min
IOL = 2 mA
@ VDD = max
VIN = VDDmax
@ VDD = max
VIN = 0 V
2.0
2.2
V
V
V
0.8
2.4
V
VDD – 0.3
V
VOL
IIH
Lo-Level Output Voltage1, 4, 5
Hi-Level Input Current3
0.4
10
10
10
10
V
µA
µA
µA
IIL
Lo-Level Input Current3
IOZH
IOZL
T hree-State Leakage Current7
T hree-State Leakage Current7
@ VDD = max
VIN = VDDmax8
@ VDD = max
VIN = 0 V8
µA
mA
IDD
IDD
Supply Current (Idle)9
@ VDD = 5.0
@ VDD = 5.0
T AMB = +25°C
tCK = 30 ns11
tCK = 25 ns11
@ VIN = 2.5 V,
fIN = 1.0 MHz,
T AMB = +25°C
@ VIN = 2.5 V,
fIN = 1.0 MHz,
T AMB = +25°C
12.4
Supply Current (Dynamic)10
55
[65]
mA
mA
CI
Input Pin Capacitance3, 6, 12
8
8
pF
CO
Output Pin Capacitance6, 7, 12, 13
pF
Parameters displayed inside brackets, [ ], represent preliminary 40 MHz specifications.
NOT ES
1 Bidirectional pins: D0-D23, RFS0, RFS1, SCLK0, SCLK1, T FS0, T FS1, A1-A13, PF0-PF7.
2 Input only pins: RESET, BR, DR0, DR1, PWD.
3 Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.
4 Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT 0, DT 1, CLKOUT , FL2-0, BGH.
5 Although specified for T T L outputs, all ADSP-2186 outputs are CMOS-compatible and will drive to V DD and GND, assuming no dc loads.
6 Guaranteed but not tested.
7 T hree-statable pins: A0-A13, D0-D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT 0, DT 1, SCLK0, SCLK1, T FS0, T FS1, RFS0, RSF1, PF0–PF7.
8 0 V on BR, CLKIN Inactive.
9 Idle refers to ADSP-2186 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND.
10
I
measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2
DD
and type 6, and 20% are idle instructions.
11
V
= 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.
IN
12 Applies to T QFP package type.
13 Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
REV. 0
–13–
ADSP-2186
ABSO LUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating T emperature Range (Ambient) . . –40°C to +85°C
Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (5 sec) T QFP . . . . . . . . . . . . . . . +280°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. T hese are stress ratings only; functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ESD SENSITIVITY
T he ADSP-2186 is an ESD (electrostatic discharge) sensitive device. Electrostatic charges readily
accumulate on the human body and equipment and can discharge without detection. Permanent
damage may occur to devices subjected to high energy electrostatic discharges.
WARNING!
T he ADSP-2186 features proprietary ESD protection circuitry to dissipate high energy discharges
(H uman Body Model) per method 3015 of MIL-ST D-883. Proper ESD precautions are recom-
mended to avoid performance degradation or loss of functionality. Unused devices must be stored in
conductive foam or shunts, and the foam should be discharged to the destination before devices are
removed.
ESD SENSITIVE DEVICE
ADSP-2186 TIMING PARAMETERS
MEMO RY TIMING SP ECIFICATIO NS
GENERAL NO TES
T he table below shows common memory device specifications
and the corresponding ADSP-2186 timing parameters, for your
convenience.
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add up parameters to derive longer times.
Mem ory
AD SP -2186 Tim ing
D evice
Tim ing
P aram eter
Specification
P aram eter D efinition
TIMING NO TES
Address Setup to
Write Start
tASW
tAW
A0–A13, xMS Setup
before WR Low
Switching characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Address Setup to
Write End
A0–A13, xMS Setup
before WR Deasserted
Address Hold T ime tWRA
A0–A13, xMS Hold before
WR Low
Data Setup T ime
tDW
Data Setup before WR
High
T iming requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. T iming requirements guarantee that the proces-
sor operates correctly with other devices.
Data Hold T ime
tDH
Data Hold after WR High
RD Low to Data Valid
OE to Data Valid
tRDD
Address Access T ime tAA
A0–A13, xMS to Data
Valid
xMS = PMS, DMS, BMS, CMS, IOMS.
FREQ UENCY D EP END ENCY FO R TIMING
SP ECIFICATIO NS
tCK is defined as 0.5 tCKI. T he ADSP-2186 uses an input clock
with a frequency equal to half the instruction rate: a 16.67 MHz
input clock (which is equivalent to 60 ns) yields a 30 ns proces-
sor cycle (equivalent to 33 MHz). tCK values within the range of
0.5 tCKI period should be substituted for all relevant timing para-
meters to obtain the specification value.
Example: tCKH = 0.5 tCK – 7 ns = 0.5 (30 ns) – 7 ns = 8 ns
REV. 0
–14–
ADSP-2186
1, 3, 4, 5
ENVIRO NMENTAL CO ND ITIO NS
2186 POWER, INTERNAL
450
425
400
375
350
Ambient T emperature Rating:
V
= 5.5V
DD
430mW
325mW
TAMB
TCASE
PD
θCA
θJA
=
=
=
=
=
=
T CASE – (PD x θCA)
Case T emperature in °C
Power Dissipation in W
T hermal Resistance (Case-to-Ambient)
T hermal Resistance (Junction-to-Ambient)
T hermal Resistance (Junction-to-Case)
370mW
330mW
245mW
325
300
275
250
225
200
175
150
V
= 5.0V
= 4.5V
DD
275mW
195mW
θJC
235mW
V
DD
P ackage
CA
JA
JC
175mW
32
T QFP
50°C/W
2°C/W
48°C/W
30
34
36
38
40
42
1/f – MHz
CK
1, 2, 3, 5
P O WER D ISSIP ATIO N
POWER, IDLE
85
80
75
70
65
60
55
50
45
40
35
30
84mW
T o determine total power dissipation in a specific application,
the following equation should be applied for each output:
76mW
V
= 5.5V
DD
69mW
2
C × VDD × f
67mW
54mW
61mW
49mW
C = load capacitance, f = output switching frequency.
V
= 5.0V
= 4.5V
56mW
45mW
DD
DD
Exam ple
In an application where external data memory is used and no
other outputs are active, power dissipation is calculated as follows:
V
Assumptions
• External data memory is accessed every cycle with 50% of the
address pins switching.
30
32
34
36
1/f – MHz
38
40
42
CK
• External data memory writes occur every other cycle with
50% of the data pins switching.
3, 5
POWER, IDLE n MODES
70
65
60
55
50
45
40
35
30
25
20
IDLE
67mW
• Each address and data pin has a 10 pF total load at the pin.
• T he application operates at VDD = 5.0 V and tCK = 30 ns.
61mW
56mW
2
Total Power Dissipation = PINT + (C × VDD × f)
n
PINT = internal power dissipation from Power vs. Frequency
graph (Figure 8).
2
(C × VDD × f) is calculated for each output:
32mW
30mW
34mW
32mW
IDLE (16)
IDLE (128)
30mW
28mW
# of
P ins
؋
C 2
؋
VD D ؋
f Address, DMS
Data Output, WR 9
8
× 10 pF × 52 V × 33.3 MHz = 66.6 mW
× 10 pF × 52 V × 16.67 MHz = 37.5 mW
× 10 pF × 52 V × 16.67 MHz = 4.2 mW
× 10 pF × 52 V × 33.3 MHz = 8.3 mW
116.6 mW
28
30
32
34
36
38
40
42
1/f – MHz
CK
VALID FOR ALL TEMPERATURE GRADES.
1
RD
1
1
POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
2
IDLE REFERS TO ADSP-2186 STATE OF OPERATION DURING EXECUTION OF IDLE
INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V OR GND.
CLKOUT
DD
AND T = 25°C EXCEPT WHERE SPECIFIED.
3
TYPICAL POWER DISSIPATION AT 5.0V V
A
DD
4
I
MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL
DD
T otal power dissipation for this example is PINT + 116.6 mW.
MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1, 4, 5, 12, 13, 14
30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS.
5
SPECIFICATIONS AT 40MHz ARE PRELIMINARY AT THIS PRINTING.
Figure 8. Power vs. Frequency
REV. 0
–15–
ADSP-2186
t
DECAY, is dependent on the capacitive load, CL, and the current
CAP ACITIVE LO AD ING
load, iL, on the output pin. It can be approximated by the fol-
lowing equation:
Figures 9 and 10 show the capacitive loading characteristics of
the ADSP-2186.
30
CL × 0.5V
tDECAY
=
T = +85°C
iL
V
= 4.5V
DD
25
from which
tDIS = tMEASURED – tDECAY
20
15
is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.
10
5
INPUT
1.5V
0
2.0V
1.5V
0.8V
0
100
150
– pF
200
250
300
50
OUTPUT
C
L
Figure 9. Typical Output Rise Tim e vs. Load Capacitance,
CL (at Maxim um Am bient Operating Tem perature)
Figure 11. Voltage Reference Levels for AC Measure-
m ents (Except Output Enable/Disable)
O utput Enable Tim e
18
16
14
12
10
Output pins are considered to be enabled when that have made
a transition from a high-impedance state to when they start
driving. T he output enable time (tENA) is the interval from when
a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram. If multiple pins (such as
the data bus) are enabled, the measurement value is that of the
first pin to start driving.
8
6
4
2
NOMINAL
REFERENCE
SIGNAL
–2
–4
–6
tMEASURED
tDIS
tENA
V
V
OH
OH
(MEASURED)
0
100
150
200
250
50
(MEASURED)
C
– pF
L
V
V
(MEASURED) – 0.5V
(MEASURED) +0.5V
2.0V
1.0V
OH
OL
OUTPUT
Figure 10. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maxim um Am bient Operating
Tem perature)
V
V
OL
OL
(MEASURED)
tDECAY
(MEASURED)
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
TEST CO ND ITIO NS
O utput D isable Tim e
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. T he out-
put disable time (tDIS) is the difference of tMEASURED and tDECAY
Figure 12. Output Enable/Disable
I
OL
,
as shown in the Output Enable/Disable diagram. T he time is the
interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage. T he decay time,
TO
OUTPUT
PIN
+1.5V
50pF
I
OH
Figure 13. Equivalent Device Loading for AC Measure-
m ents (Including All Fixtures)
REV. 0
–16–
ADSP-2186
TIMING PARAMETERS
P aram eter
Min
Max
Unit
Clock Signals and Reset
Timing Requirements:
tCKI
tCKIL
tCKIH
CLKIN Period
CLKIN Width Low
CLKIN Width High
60 [50]
20
20
150
ns
ns
ns
Switching Characteristics:
tCKL
tCKH
tCKOH
CLKOUT Width Low
CLKOUT Width High
CLKIN High to CLKOUT High
0.5 tCK – 7
0.5 tCK – 7
0
ns
ns
ns
20
Contr ol Signals
Timing Requirements:
tRSP
tMS
tMH
RESET Width Low1
Mode Setup Before RESET High
Mode Setup After RESET High
5 tCK
2
5
ns
ns
ns
NOT ES
Parameters displayed inside brackets [ ] represent preliminary 40 MHz specifications.
1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
tCKI
tCKIH
CLKIN
tCKIL
tCKOH
tCKH
CLKOUT
tCKL
PF(2:0)
*
tMH
tMS
RESET
*PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A
Figure 14. Clock Signals
–17–
REV. 0
ADSP-2186
TIMING PARAMETERS
P aram eter
Min
Max
Unit
Inter r upts and Flag
Timing Requirements:
tIFS
tIFH
IRQx, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4
IRQx, FI, or PFx Hold after CLKOUT High1, 2, 3, 4
0.25 tCK + 15
0.25 tCK
ns
ns
Switching Characteristics:
tFOH
Flag Output Hold after CLKOUT Low5
tFOD
Flag Output Delay from CLKOUT Low5
0.25 tCK – 7
ns
ns
0.5 tCK + 5
NOT ES
1If IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-2100 Family User’s Manual for further information on
interrupt servicing.)
2Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.
4PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.
5Flag outputs = PFx, FL0, FL1, FL2, Flag_out4.
tFOD
CLKOUT
tFOH
FLAG
OUTPUTS
tIFH
IRQx
FI
PFx
tIFS
Figure 15. Interrupts and Flags
REV. 0
–18–
ADSP-2186
P aram eter
Min
Max
Unit
Bus Request/Gr ant
Timing Requirements:
tBH
tBS
BR Hold after CLKOUT High1
BR Setup before CLKOUT Low1
0.25 tCK + 2
0.25 tCK + 17
ns
ns
Switching Characteristics:
tSD
tSDB
tSE
tSEC
tSDBH
tSEH
CLKOUT High to xMS, RD, WR Disable
0.25 tCK + 10
ns
ns
ns
ns
ns
ns
xMS, RD, WR Disable to BG Low
BG High to xMS, RD, WR Enable
xMS, RD, WR Enable to CLKOUT High
xMS, RD, WR Disable to BGH Low2
BGH High to xMS, RD, WR Enable2
0
0
0.25 tCK – 7
0
0
NOT ES
xMS = PMS, DMS, CMS, IOMS, BMS.
1BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.
2BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
tSD
tSEC
WR
BG
tSDB
tSE
BGH
tSDBH
tSEH
Figure 16. Bus Request–Bus Grant
–19–
REV. 0
ADSP-2186
TIMING PARAMETERS
P aram eter
Min
Max
Unit
Mem or y Read
Timing Requirements:
tRDD
tAA
tRDH
RD Low to Data Valid
A0–A13, xMS to Data Valid
Data Hold from RD High
0.5 tCK – 9 + w
0.75 tCK – 10.5 + w
ns
ns
ns
0
Switching Characteristics:
tRP
RD Pulse Width
CLKOUT High to RD Low
A0–A13, xMS Setup before RD Low
A0–A13, xMS Hold after RD Deasserted
RD High to RD or WR Low
0.5 tCK – 5 + w
0.25 tCK – 5
0.25 tCK – 6
0.25 tCK – 3
0.5 tCK – 5
ns
ns
ns
ns
ns
tCRD
tASR
tRDA
tRWR
0.25 tCK + 7
w = wait states × tCK
.
xMS = PMS, DMS, CMS, IOMS, BMS.
CLKOUT
A0 – A13
DMS, PMS,
BMS, IOMS,
CMS
tRDA
RD
D
tASR
tCRD
tRP
tRWR
tRDD
tRDH
tAA
WR
Figure 17. Mem ory Read
REV. 0
–20–
ADSP-2186
P aram eter
Min
Max
Unit
Mem or y Wr ite
Switching Characteristics:
tDW
tDH
tWP
tWDE
tASW
tDDR
tCWR
tAW
Data Setup before WR High
Data Hold after WR High
WR Pulse Width
WR Low to Data Enabled
A0-A13, xMS Setup before WR Low
Data Disable before WR or RD Low
CLKOUT High to WR Low
A0-A13, xMS, Setup before WR Deasserted
A0-A13, xMS Hold after WR Deasserted
WR High to RD or WR Low
0.5 tCK – 7+ w
0.25 tCK – 2
0.5 tCK – 5 + w
0
0.25 tCK – 6
0.25 tCK – 7
0.25 tCK – 5
0.75 tCK – 9 + w
0.25 tCK – 3
0.5 tCK – 5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.25 tCK + 7
tWRA
tWWR
w = wait states × tCK
.
xMS = PMS, DMS, CMS, IOMS, BMS.
CLKOUT
A0–A13
DMS, PMS,
BMS, CMS,
IOMS
tWRA
WR
tWWR
tASW
tWP
tAW
tDH
tDDR
tCWR
D
tDW
tWDE
RD
Figure 18. Mem ory Write
–21–
REV. 0
ADSP-2186
TIMING PARAMETERS
P aram eter
Min
Max
Unit
Ser ial P or ts
Timing Requirements:
tSCK
tSCS
tSCH
tSCP
SCLK Period
50
4
7
ns
ns
ns
ns
DR/T FS/RFS Setup before SCLK Low
DR/T FS/RFS Hold after SCLK Low
SCLKIN Width
20
Switching Characteristics:
tCC
CLKOUT High to SCLKOUT
SCLK High to DT Enable
SCLK High to DT Valid
T FS/RFSOUT Hold after SCLK High
T FS/RFSOUT Delay from SCLK High
DT Hold after SCLK High
T FS (Alt) to DT Enable
T FS (Alt) to DT Valid
0.25 tCK
0
0.25 tCK + 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCDE
tSCDV
tRH
15
15
0
tRD
tSCDH
tT DE
tT DV
tSCDD
tRDV
0
0
14
15
15
SCLK High to DT Disable
RFS (Multichannel, Frame Delay Zero) to DT Valid
CLKOUT
tCC
tCC
tSCK
SCLK
tSCP
tSCP
tSCS
tSCH
DR
TFS
IN
RFS
IN
tRD
tRH
RFS
TFS
OUT
OUT
tSCDD
tSCDV
tSCDH
tSCDE
DT
tTDE
tTDV
TFS
OUT
ALTERNATE
FRAME MODE
tRDV
RFS
OUT
MULTICHANNEL MODE,
FRAME DELAY 0
(MFD = 0)
tTDE
tTDV
TFS
IN
ALTERNATE
FRAME MODE
tRDV
RFS
IN
MULTICHANNEL MODE,
FRAME DELAY 0
(MFD = 0)
Figure 19. Serial Ports
REV. 0
–22–
ADSP-2186
P aram eter
Min
Max
Unit
ID MA Addr ess Latch
Timing Requirements:
tIALP
tIASU
tIAH
tIKA
tIALS
Duration of Address Latch1, 3
10
5
2
0
3
ns
ns
ns
ns
ns
IAD15–0 Address Setup before Address Latch End3
IAD15–0 Address Hold after Address Latch End3
IACK Low before Start of Address Latch2, 3
Start of Write or Read after Address Latch End2, 3
NOT ES
1Start of Address Latch = IS Low and IAL High.
2Start of Write or Read = IS Low and IWR Low or IRD Low.
3End of Address Latch = IS High or IAL Low.
IACK
tIKA
IAL
tIALP
IS
tIASU
tIAH
IAD 15–0
tIALS
IRD
OR
IWR
Figure 20. IDMA Address Latch
–23–
REV. 0
ADSP-2186
TIMING PARAMETERS
P aram eter
Min
Max
Unit
ID MA Wr ite, Shor t Wr ite Cycle
Timing Requirements:
tIKW
tIWP
tIDSU
tIDH
IACK Low before Start of Write1
0
15
5
ns
ns
ns
ns
Duration of Write1, 2
IAD15–0 Data Setup before End of Write2, 3, 4
IAD15–0 Data Hold after End of Write2, 3, 4
2
Switching Characteristics:
tIKHW
Start of Write to IACK High
15
ns
NOT ES
1Start of Write = IS Low and IWR Low.
2End of Write = IS High or IWR High.
3If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH
.
4If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH
.
tIKW
IACK
tIKHW
IS
tIWP
IWR
tIDH
tIDSU
DATA
IAD 15–0
Figure 21. IDMA Write, Short Write Cycle
REV. 0
–24–
ADSP-2186
P aram eter
Min
Max
Unit
ID MA Wr ite, Long Wr ite Cycle
Timing Requirements:
tIKW
tIKSU
tIKH
IACK Low before Start of Write1
0
ns
ns
ns
IAD15–0 Data Setup before IACK Low2, 3, 4
IAD15–0 Data Hold after IACK Low2, 3, 4
0.5 tCK + 10
2
Switching Characteristics:
tIKLW
Start of Write to IACK Low4
tIKHW Start of Write to IACK High
1.5 tCK
ns
ns
15
NOT ES
1Start of Write = IS Low and IWR Low.
2If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH
.
3If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH
.
4T his is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual.
tIKW
IACK
tIKHW
tIKLW
IS
IWR
tIKSU
tIKH
DATA
IAD 15–0
Figure 22. IDMA Write, Long Write Cycle
–25–
REV. 0
ADSP-2186
TIMING PARAMETERS
P aram eter
Min
Max
Unit
ID MA Read, Long Read Cycle
Timing Requirements:
tIKR
tIRP
IACK Low before Start of Read1
0
15
ns
ns
Duration of Read1
Switching Characteristics:
tIKHR
tIKDS
tIKDH
tIKDD
tIRDE
tIRDV
tIRDH1
tIRDH2
IACK High after Start of Read1
15
ns
ns
ns
ns
ns
ns
ns
ns
IAD15–0 Data Setup before IACK Low
0.5 tCK – 10
0
IAD15–0 Data Hold after End of Read2
IAD15–0 Data Disabled after End of Read2
10
15
IAD15–0 Previous Data Enabled after Start of Read
IAD15–0 Previous Data Valid after Start of Read
IAD15–0 Previous Data Hold after Start of Read (DM/PM1)3
IAD15–0 Previous Data Hold after Start of Read (PM2)4
0
2 tCK – 5
tCK – 5
NOT ES
1Start of Read = IS Low and IRD Low.
2End of Read = IS High or IRD High.
3DM read or first half of PM read.
4Second half of PM read.
IACK
IS
tIKHR
tIKR
tIRP
IRD
tIKDS
tIKDH
tIRDE
PREVIOUS
DATA
READ
DATA
IAD 15–0
tIRDV
tIKDD
tIRDH
Figure 23. IDMA Read, Long Read Cycle
REV. 0
–26–
ADSP-2186
P aram eter
Min
Max
Unit
ID MA Read, Shor t Read Cycle
Timing Requirements:
tIKR
tIRP
IACK Low before Start of Read1
Duration of Read
0
15
ns
ns
Switching Characteristics:
tIKHR
tIKDH
tIKDD
tIRDE
tIRDV
IACK High after Start of Read1
15
10
15
ns
ns
ns
ns
ns
IAD15–0 Data Hold after End of Read2
0
0
IAD15–0 Data Disabled after End of Read2
IAD15–0 Previous Data Enabled after Start of Read
IAD15–0 Previous Data Valid after Start of Read
NOT ES
1Start of Read = IS Low and IRD Low.
2End of Read = IS High or IRD High.
IACK
IS
tIKR
tIKHR
tIRP
IRD
tIKDH
tIRDE
PREVIOUS
DATA
IAD 15–0
tIKDD
tIRDV
Figure 24. IDMA Read, Short Read Cycle
–27–
REV. 0
ADSP-2186
100-Lead TQFP P ackage P inout
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
A4/IAD3
A5/IAD4
GND
1
2
D15
D14
D13
PIN 1
IDENTIFIER
3
4
A6/IAD5
A7/IAD6
A8/IAD7
A9/IAD8
A10/IAD9
A11/IAD10
A12/IAD11
A13/IAD12
GND
D12
5
GND
6
D11
D10
7
8
D9
9
VDD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
GND
D8
D7/IWR
D6/IRD
ADSP-2186
CLKIN
TOP VIEW
(Not to Scale)
XTAL
D5/IAL
D4/IS
VDD
CLKOUT
GND
VDD
GND
VDD
D3/IACK
D2/IAD15
WR
RD
56 D1/IAD14
55
54
53
52
51
D0/IAD13
BG
BMS
DMS
PMS
IOMS
CMS
EBG
BR
EBR
REV. 0
–28–
ADSP-2186
T he ADSP-2186 package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when
Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in
brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET.
TQFP P in Configurations
TQFP
P in
TQFP
P in
TQFP
P in
TQFP
P in
Num ber
Nam e
Num ber
Nam e
Num ber
Nam e
Num ber
Nam e
1
2
3
4
5
6
7
8
A4/IAD 3
A5/IAD 4
GND
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
IRQE + PF4
IRQL0 + PF5
GND
IRQL1 + PF6
IRQ2 + PF7
DT 0
T FS0
RFS0
DR0
SCLK0
VDD
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
EBR
BR
EBG
BG
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
D16
D17
D18
D19
GND
D20
D21
D22
D23
FL2
FL1
FL0
PF3
PF2 [Mode C]
VDD
PWD
GND
PF1 [Mode B]
PF0 [Mode A]
BGH
PWDACK
A0
A1/IAD 0
A2/IAD 1
A3/IAD 2
A6/IAD 5
A7/IAD 6
A8/IAD 7
A9/IAD 8
A10/IAD 9
A11/IAD 10
A12/IAD 11
A13/IAD 12
GND
CLKIN
XT AL
VDD
CLKOUT
GND
VDD
WR
RD
BMS
DMS
PMS
IOMS
CMS
D0/IAD 13
D1/IAD 14
D2/IAD 15
D3/IACK
VDD
GND
D4/IS
D5/IAL
D6/IRD
D7/IWR
D8
GND
VDD
D9
D10
D11
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
DT 1
T FS1
RFS1
DR1
GND
SCLK1
ERESET
RESET
EMS
EE
GND
D12
D13
D14
D15
ECLK
ELOUT
ELIN
EINT
–29–
REV. 0
ADSP-2186
O RD ERING GUID E
Am bient
Tem perature
Range
Instruction
Rate
(MH z)
P ackage
D escription
P ackage
O ption*
P art Num ber
ADSP-2186KST -115
ADSP-2186BST -115
ADSP-2186KST -133
ADSP-2186BST -133
ADSP-2186KST -160x
ADSP-2186BST -160x
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
28.8
28.8
33.3
33.3
40.0
40.0
100-Lead T QFP
100-Lead T QFP
100-Lead T QFP
100-Lead T QFP
100-Lead T QFP
100-Lead T QFP
ST -100
ST -100
ST -100
ST -100
ST -100
ST -100
*ST = Plastic T hin Quad Flatpack (T QFP).
O UTLINE D IMENSIO NS
D imensions shown in mm and (inches).
100-Lead Metric Thin P lastic Quad Flatpack (TQFP )
(ST-100)
0.640 (16.25)
0.630 (16.00)
0.620 (15.75)
TYP SQ
TYP SQ
TYP SQ
0.555 (14.05)
0.551 (14.00)
0.547 (13.90)
0.476 (12.10)
0.474 (12.05)
0.472 (12.00)
0.063 (1.60) MAX
0.024 (0.75)
0.022 (0.60) TYP
0.020 (0.50)
100
1
76
75
12°
TYP
SEATING
PLANE
TOP VIEW
(PINS DOWN)
0.004
(0.102)
MAX LEAD
COPLANARITY
25
51
50
26
6° ± 4°
0° – 10°
0.020 (0.50)
BSC
0.007 (0.177)
0.010 (0.27)
0.005 (0.127) TYP
0.003 (0.077)
0.009 (0.22) TYP
0.006 (0.17)
LEAD PITCH
LEAD WIDTH
REV. 0
–30–
–31–
–32–
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