ADSP-2163BP-662 [ADI]
ADSP-2100 Family DSP Microcomputers; ADSP -2100系列的DSP微型计算机型号: | ADSP-2163BP-662 |
厂家: | ADI |
描述: | ADSP-2100 Family DSP Microcomputers |
文件: | 总64页 (文件大小:389K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ADSP-2100 Family
DSP Microcomputers
a
ADSP-21xx
FUNCTIO NAL BLO CK D IAGRAM
SUMMARY
16-Bit Fixed-Point DSP Microprocessors w ith
On-Chip Mem ory
Enhanced Harvard Architecture for Three-Bus
Perform ance: Instruction Bus & Dual Data Buses
Independent Com putation Units: ALU, Multiplier/
Accum ulator, and Shifter
Single-Cycle Instruction Execution & Multifunction
Instructions
On-Chip Program Mem ory RAM or ROM
& Data Mem ory RAM
MEMORY
FLAGS
DATA ADDRESS
GENERATORS
(ADSP-2111)
PROGRAM
SEQUENCER
DATA
MEMORY
PROGRAM
MEMORY
DAG 1
DAG 2
EXTERNAL
ADDRESS
BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
EXTERNAL
DATA
BUS
Integrated I/ O Peripherals: Serial Ports, Tim er,
Host Interface Port (ADSP-2111 Only)
HOST
INTERFACE
PORT
SERIAL PORTS
SPORT 0 SPORT 1
ARITHMETIC UNITS
MAC
TIMER
SHIFTER
ALU
FEATURES
(ADSP-2111)
25 MIPS, 40 ns Maxim um Instruction Rate
Separate On-Chip Buses for Program and Data Mem ory
Program Mem ory Stores Both Instructions and Data
(Three-Bus Perform ance)
Dual Data Address Generators w ith Modulo and
Bit-Reverse Addressing
ADSP-2100 CORE
T his data sheet describes the following ADSP-2100 Family
processors:
ADSP-2101
Efficient Program Sequencing w ith Zero-Overhead
Looping: Single-Cycle Loop Setup
ADSP-2103
ADSP-2105
ADSP-2111
ADSP-2115
3.3 V Version of ADSP-2101
Low Cost DSP
DSP with Host Interface Port
Autom atic Booting of On-Chip Program Mem ory from
Byte-Wide External Mem ory (e.g., EPROM )
Double-Buffered Serial Ports w ith Com panding Hardw are,
Autom atic Data Buffering, and Multichannel Operation
ADSP-2111 Host Interface Port Provides Easy Interface
to 68000, 80C51, ADSP-21xx, Etc.
ADSP-2161/62/63/64 Custom ROM-programmed DSPs
T he following ADSP-2100 Family processors are not included
in this data sheet:
Autom atic Booting of ADSP-2111 Program Mem ory
Through Host Interface Port
Three Edge- or Level-Sensitive Interrupts
Low Pow er IDLE Instruction
PGA, PLCC, PQFP, and TQFP Packages
MIL-STD-883B Versions Available
ADSP-2100A
DSP Microprocessor
ADSP-2165/66
ROM-programmed ADSP-216x processors
with powerdown and larger on-chip
memories (12K Program Memory ROM,
1K Program Memory RAM, 4K Data
Memory RAM)
ADSP-21msp5x
ADSP-2171
Mixed-Signal DSP Processors with
integrated on-chip A/D and D/A plus
powerdown
GENERAL D ESCRIP TIO N
T he ADSP-2100 Family processors are single-chip micro-
computers optimized for digital signal processing (DSP)
and other high speed numeric processing applications. T he
ADSP-21xx processors are all built upon a common core. Each
processor combines the core DSP architecture—computation
units, data address generators, and program sequencer—with
differentiating features such as on-chip program and data
memory RAM, a programmable timer, one or two serial ports,
and, on the ADSP-2111, a host interface port.
Speed and feature enhanced ADSP-2100
Family processor with host interface port,
powerdown, and instruction set extensions
for bit manipulation, multiplication, biased
rounding, and global interrupt masking
ADSP-2181
ADSP-21xx processor with ADSP-2171
features plus 80K bytes of on-chip RAM
configured as 16K words of program
memory and 16K words of data memory.
Refer to the individual data sheet of each of these processors for
further information.
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
ADSP-21xx
Fabricated in a high speed, submicron, double-layer metal
CMOS process, the highest-performance ADSP-21xx proces-
sors operate at 25 MHz with a 40 ns instruction cycle time.
Every instruction can execute in a single cycle. Fabrication in
CMOS results in low power dissipation.
•
•
Receive and transmit data via one or two serial ports
Receive and/or transmit data via the host interface port
(ADSP-2111 only)
T he ADSP-2101, ADSP-2105, and ADSP-2115 comprise the
basic set of processors of the family. Each of these three devices
contains program and data memory RAM, an interval timer,
and one or two serial ports. T he ADSP-2103 is a 3.3 volt
power supply version of the ADSP-2101; it is identical to the
ADSP-2101 in all other characteristics. T able I shows the
features of each ADSP-21xx processor.
T he ADSP-2100 Family’s flexible architecture and compre-
hensive instruction set support a high degree of parallelism.
In one cycle the ADSP-21xx can perform all of the following
operations:
•
•
•
•
•
Generate the next program address
Fetch the next instruction
Perform one or two data moves
Update one or two data address pointers
Perform a computation
T he ADSP-2111 adds a 16-bit host interface port (HIP) to the
basic set of ADSP-21xx integrated features. T he host port
provides a simple interface to host microprocessors or
microcontrollers such as the 8031, 68000, or ISA bus.
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
T est Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TABLE O F CO NTENTS
GENERAL DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . . . 1
Development T ools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SPECIFICAT IONS (ADSP-2103/2162/2164) . . . . . . . . . 25
Recommended Operating Conditions . . . . . . . . . . . . . . . . 25
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Supply Current & Power . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Power Dissipation Example . . . . . . . . . . . . . . . . . . . . . . . . 27
Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 27
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
T est Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ARCHIT ECT URE OVERVIEW . . . . . . . . . . . . . . . . . . . . 4
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Host Interface Port (ADSP-2111) . . . . . . . . . . . . . . . . . . . . 6
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SYST EM INT ERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TIMING PARAMETERS
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Program Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . 10
Program Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Boot Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Low Power IDLE Instruction . . . . . . . . . . . . . . . . . . . . . . 13
ADSP-216x Prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Ordering Procedure for ADSP-216x ROM Processors . . . . 13
Wafer Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Functional Differences for Older Revision Devices . . . . . . 14
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
(ADSP-2101/2105/2111/2115/2161/2163) . . . . . . . . . . . . 29
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Interrupts & Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Bus Request–Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Host Interface Port (ADSP-2111) . . . . . . . . . . . . . . . . . . . 36
T IMING PARAMET ERS (ADSP-2103/2162/2164) . . . . 44
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Interrupts & Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Bus Request–Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SPECIFICAT IONS
(ADSP-2101/2105/2115/2161/2163) . . . . . . . . . . . . . . . 17
Recommended Operating Conditions . . . . . . . . . . . . . . . . 17
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Supply Current & Power (ADSP-2101/2161/2163) . . . . . . 18
Power Dissipation Example . . . . . . . . . . . . . . . . . . . . . . . . 19
Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 19
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
T est Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PIN CONFIGURAT IONS
68-Pin PGA (ADSP-2101) . . . . . . . . . . . . . . . . . . . . . . . . 51
68-Lead PLCC (ADSP-2101/2103/2105/2115/216x) . . . . 52
80-Lead PQFP (ADSP-2101/2103/2115/216x) . . . . . . . . . 53
80-Lead T QFP (ADSP-2115) . . . . . . . . . . . . . . . . . . . . . . 53
100-Pin PGA (ADSP-2111) . . . . . . . . . . . . . . . . . . . . . . . 54
100-Lead PQFP (ADSP-2111) . . . . . . . . . . . . . . . . . . . . . 55
SPECIFICAT IONS
PACKAGE OUT LINE DIMENSIONS
(ADSP-2111) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Recommended Operating Conditions . . . . . . . . . . . . . . . . 21
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Supply Current & Power . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power Dissipation Example . . . . . . . . . . . . . . . . . . . . . . . . 23
Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 23
68-Pin PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
68-Lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
80-Lead PQFP, 80-Lead T QFP . . . . . . . . . . . . . . . . . . . . 58
100-Pin PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
100-Lead PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . 61-62
–2–
REV. B
ADSP-21xx
Table I. AD SP -21xx P rocessor Features
Feature
2101
2103
2105
2115
2111
Data Memory (RAM)
Program Memory (RAM)
T imer
Serial Port 0 (Multichannel)
Serial Port 1
Host Interface Port
Speed Grades (Instruction Cycle Time)
10.24 MHz (76.9 ns)
13.0 MHz (76.9 ns)
13.824 MHz (72.3 ns)
16.67 MHz (60 ns)
20.0 MHz (50 ns)
25 MHz (40 ns)
1K
2K
1K
2K
1⁄2 K
1K
1⁄2 K
1K
1K
2K
• • • • •
–
• •
• •
• • • • •
–
–
–
–
•
–
–
–
–
–
–
–
–
–
•
–
•
–
–
•
–
–
–
–
•
•
• •
• • •
–
–
5 V
•
•
Supply Voltage
Packages
5 V
3.3 V
5 V
5 V
68-Pin PGA
68-Lead PLCC
80-Lead PQFP
80-Lead T QFP
100-Pin PGA
100-Lead PQFP
T emperature Grades
K Commercial 0°C to +70°C
B Industrial
T Extended
–
–
–
–
–
–
–
•
–
–
–
• • • •
–
• •
•
–
–
–
–
–
–
•
–
•
•
–
• • • • •
–40°C to +85°C
–55°C to +125°C
• • • • •
–
–
–
•
•
Table II. AD SP -216x RO M-P rogram m ed P rocessor Features
Feature
2161
2162
2163
2164
Data Memory (RAM)
Program Memory (ROM)
Program Memory (RAM)
T imer
Serial Port 0 (Multichannel)
Serial Port 1
1⁄2 K
8K
–
1⁄2 K
8K
–
1⁄2 K
4K
–
1⁄2 K
4K
–
• • • •
• • • •
• • • •
Supply Voltage
5 V
–
3.3 V
5 V
3.3 V
Speed Grades (Instruction Cycle Time)
10.24 MHz (97.6 ns)
16.67 MHz (60 ns)
25 MHz (40 ns)
Packages
68-Lead PLCC
–
•
•
–
–
•
•
•
–
–
–
• • • •
80-Lead PQFP
• • • •
T emperature Grades
K Commercial 0°C to +70°C
B Industrial –40°C to +85°C
• • • •
• • • •
REV. B
–3–
ADSP-21xx
T he ADSP-216x series are memory-variant versions of the
ADSP-2101 and ADSP-2103 that contain factory-programmed
on-chip ROM program memory. T hese devices offer different
amounts of on-chip memory for program and data storage.
T able II shows the features available in the ADSP-216x series of
custom ROM-coded processors.
ARCH ITECTURE O VERVIEW
Figure 1 shows a block diagram of the ADSP-21xx architecture.
T he processors contain three independent computational units:
the ALU, the multiplier/accumulator (MAC), and the shifter.
T he computational units process 16-bit data directly and have
provisions to support multiprecision computations. T he ALU
performs a standard set of arithmetic and logic operations;
division primitives are also supported. T he MAC performs
single-cycle multiply, multiply/add, and multiply/subtract
operations. T he shifter performs logical and arithmetic shifts,
normalization, denormalization, and derive exponent operations.
The shifter can be used to efficiently implement numeric format
control including multiword floating-point representations.
T he ADSP-216x products eliminate the need for an external
boot EPROM in your system, and can also eliminate the need
for any external program memory by fitting the entire applica-
tion program in on-chip ROM. T hese devices thus provide an
excellent option for volume applications where board space and
system cost constraints are of critical concern.
D evelopm ent Tools
T he internal result (R) bus directly connects the computational
units so that the output of any unit may be used as the input of
any unit on the next cycle.
T he ADSP-21xx processors are supported by a complete set of
tools for system development. T he ADSP-2100 Family Devel-
opment Software includes C and assembly language tools that
allow programmers to write code for any of the ADSP-21xx
processors. T he ANSI C compiler generates ADSP-21xx
assembly source code, while the runtime C library provides
ANSI-standard and custom DSP library routines. T he ADSP-
21xx assembler produces object code modules which the linker
combines into an executable file. T he processor simulators
provide an interactive instruction-level simulation with a
reconfigurable, windowed user interface. A PROM splitter
utility generates PROM programmer compatible files.
EZ-ICE® in-circuit emulators allow debugging of ADSP-21xx
systems by providing a full range of emulation functions such as
modification of memory and register values and execution
breakpoints. EZ-LAB® demonstration boards are complete DSP
systems that execute EPROM-based programs.
A powerful program sequencer and two dedicated data address
generators ensure efficient use of these computational units.
T he sequencer supports conditional jumps, subroutine calls,
and returns in a single cycle. With internal loop counters and
loop stacks, the ADSP-21xx executes looped code with zero
overhead—no explicit jump instructions are required to
maintain the loop.
T wo data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
circular buffers. T he circular buffering feature is also used by
the serial ports for automatic data transfers to (and from) on-
chip memory.
T he EZ-Kit Lite is a very low-cost evaluation/development
platform that contains both the hardware and software needed
to evaluate the ADSP-21xx architecture.
Efficient data transfer is achieved with the use of five internal
buses:
Additional details and ordering information is available in the
ADSP-2100 Family Software & Hardware Development Tools data
sheet (ADDS-21xx-T OOLS). T his data sheet can be requested
from any Analog Devices sales office or distributor.
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
Additional Infor m ation
T his data sheet provides a general overview of ADSP-21xx
processor functionality. For detailed design information on the
architecture and instruction set, refer to the ADSP-2100 Family
User’s Manual, available from Analog Devices.
T he two address buses (PMA, DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD, DMD) share a single external data bus.
T he BMS, DMS, and PMS signals indicate which memory
space is using the external buses.
Program memory can store both instructions and data, permit-
ting the ADSP-21xx to fetch two operands in a single cycle, one
from program memory and one from data memory. T he
processor can fetch an operand from on-chip program memory
and the next instruction in the same cycle.
T he memory interface supports slow memories and memory-
mapped peripherals with programmable wait state generation.
External devices can gain control of the processor’s buses with
the use of the bus request/grant signals (BR, BG).
EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc.
–4–
REV. B
ADSP-21xx
FLAGS
(ADSP-2111 Only)
INSTRUCTION
REGISTER
PROGRAM
MEMORY
DATA
MEMORY
3
BOOT
ADDRESS
GENERATOR
DATA
ADDRESS
GENERATOR
#2
DATA
ADDRESS
GENERATOR
#1
SRAM
or ROM
SRAM
TIMER
PROGRAM
SEQUENCER
24
16
PMA BUS
DMA BUS
14
PMA BUS
DMA BUS
14
EXTERNAL
ADDRESS
BUS
MUX
14
24
PMD BUS
PMD BUS
DMD BUS
24
EXTERNAL
DATA
BUS
EXCHANGE
MUX
BUS
16 DMD BUS
COMPANDING
CIRCUITRY
INPUT REGS
INPUT REGS
MAC
INPUT REGS
11
HOST
PORT
CONTROL
SHIFTER
ALU
EXTERNAL
HOST PORT
TRANSMIT REG
RECEIVE REG
TRANSMIT REG
RECEIVE REG
OUTPUT REGS
OUTPUT REGS
OUTPUT REGS
16
BUS
HOST
PORT
DATA
16
SERIAL
PORT 0
(Not on ADSP-2105)
SERIAL
PORT 1
R Bus
HOST INTERFACE PORT
(ADSP-2111 Only)
5
5
Figure 1. ADSP-21xx Block Diagram
Ser ial P or ts
One bus grant execution mode (GO Mode) allows the ADSP-
21xx to continue running from internal memory. A second
execution mode requires the processor to halt while buses are
granted.
T he ADSP-21xx processors include two synchronous serial
ports (“SPORT s”) for serial communications and multiproces-
sor communication. All of the ADSP-21xx processors have two
serial ports (SPORT 0, SPORT 1) except for the ADSP-2105,
which has only SPORT 1.
Each ADSP-21xx processor can respond to several different
interrupts. T here can be up to three external interrupts,
configured as edge- or level-sensitive. Internal interrupts can be
generated by the timer, serial ports, and, on the ADSP-2111,
the host interface port. T here is also a master RESET signal.
T he serial ports provide a complete synchronous serial interface
with optional companding in hardware. A wide variety of
framed or frameless data transmit and receive modes of opera-
tion are available. Each SPORT can generate an internal
programmable serial clock or accept an external serial clock.
Booting circuitry provides for loading on-chip program memory
automatically from byte-wide external memory. After reset,
three wait states are automatically generated. T his allows, for
example, a 60 ns ADSP-2101 to use a 200 ns EPROM as
external boot memory. Multiple programs can be selected and
loaded from the EPROM with no additional hardware.
Each serial port has a 5-pin interface consisting of the following
signals:
Signal Nam e
Function
SCLK
RFS
T FS
DR
Serial Clock (I/O)
T he data receive and transmit pins on SPORT 1 (Serial Port 1)
can be alternatively configured as a general-purpose input flag
and output flag. You can use these pins for event signalling to
and from an external device. T he ADSP-2111 has three
additional flag outputs whose states are controlled through
software.
Receive Frame Synchronization (I/O)
T ransmit Frame Synchronization (I/O)
Serial Data Receive
DT
Serial Data T ransmit
T he ADSP-21xx serial ports offer the following capabilities:
A programmable interval timer can generate periodic interrupts.
A 16-bit count register (T COUNT ) is decremented every n
cycles, where n–1 is a scaling value stored in an 8-bit register
(T SCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (T PERIOD).
Bidir ectional—Each SPORT has a separate, double-buffered
transmit and receive function.
Flexible Clocking—Each SPORT can use an external serial
clock or generate its own clock internally.
REV. B
–5–
ADSP-21xx
Flexible Fr am ing—T he SPORT s have independent framing
for the transmit and receive functions; each function can run in
a frameless mode or with frame synchronization signals inter-
nally generated or externally generated; frame sync signals may
be active high or inverted, with either of two pulse widths and
timings.
of the ADSP-2111. T he two status registers provide status
information to both the ADSP-2111 and the host processor.
HSR7 contains a software reset bit which can be set by both the
ADSP-2111 and the host.
HIP transfers can be managed using either interrupts or polling.
T he HIP generates an interrupt whenever an HDR register
receives data from a host processor write. It also generates an
interrupt when the host processor has performed a successful
read of any HDR. T he read/write status of the HDRs is also
stored in the HSR registers.
D iffer ent Wor d Lengths—Each SPORT supports serial data
word lengths from 3 to 16 bits.
Com panding in H ar dwar e—Each SPORT provides optional
A-law and µ-law companding according to CCIT T recommen-
dation G.711.
T he HMASK register bits can be used to mask the generation of
read or write interrupts from individual HDR registers. Bits in
the IMASK register enable and disable all HIP read interrupts
or all HIP write interrupts. So, for example, a write to HDR4
will cause an interrupt only if both the HDR4 Write bit in
HMASK and the HIP Write interrupt enable bit in IMASK are
set.
Flexible Inter r upt Schem e—Receive and transmit functions
can generate a unique interrupt upon completion of a data word
transfer.
Autobuffer ing with Single-Cycle O ver head—Each SPORT
can automatically receive or transmit the contents of an entire
circular data buffer with only one overhead cycle per data word;
an interrupt is generated after the transfer of the entire buffer is
completed.
T he HIP provides a second method of booting the ADSP-2111
in which the host processor loads instructions into the HIP. T he
ADSP-2111 automatically transfers the data, in this case
opcodes, to internal program memory. T he BMODE pin
determines whether the ADSP-2111 boots from the host
processor through the HIP or from external EPROM over the
data bus.
Multichannel Capability (SP O RT0 O nly)—SPORT 0
provides a multichannel interface to selectively receive or
transmit a 24-word or 32-word, time-division multiplexed serial
bit stream; this feature is especially useful for T 1 or CEPT
interfaces, or as a network communication scheme for multiple
processors. (Note that the ADSP-2105 includes only SPORT 1,
not SPORT 0, and thus does not offer multichannel operation.)
Inter r upts
T he ADSP-21xx’s interrupt controller lets the processor
respond to interrupts with a minimum of overhead. Up to three
external interrupt input pins, IRQ0, IRQ1, and IRQ2, are
provided. IRQ2 is always available as a dedicated pin; IRQ1 and
IRQ0 may be alternately configured as part of Serial Port 1. T he
ADSP-21xx also supports internal interrupts from the timer, the
serial ports, and the host interface port (on the ADSP-2111).
T he interrupts are internally prioritized and individually
maskable (except for RESET which is non-maskable). T he
IRQx input pins can be programmed for either level- or edge-
sensitivity. T he interrupt priorities for each ADSP-21xx
processor are shown in T able III.
Alter nate Configur ation—SPORT 1 can be alternatively
configured as two external interrupt inputs (IRQ0, IRQ1) and
the Flag In and Flag Out signals (FI, FO).
H ost Inter face P or t (AD SP -2111)
T he ADSP-2111 includes a Host Interface Port (HIP), a
parallel I/O port that allows easy connection to a host processor.
T hrough the HIP, the ADSP-2111 can be accessed by the host
processor as a memory-mapped peripheral. T he host interface
port can be thought of as an area of dual-ported memory, or
mailbox registers, that allows communication between the
computational core of the ADSP-2111 and the host computer.
T he host interface port is completely asynchronous. T he host
processor can write data into the HIP while the ADSP-2111 is
operating at full speed.
T he ADSP-21xx uses a vectored interrupt scheme: when an
interrupt is acknowledged, the processor shifts program control
to the interrupt vector address corresponding to the interrupt
received. Interrupts can be optionally nested so that a higher
priority interrupt can preempt the currently executing interrupt
service routine. Each interrupt vector location is four instruc-
tions in length so that simple service routines can be coded
entirely in this space. Longer service routines require an
additional JUMP or CALL instruction.
T hree pins configure the HIP for operation with different types
of host processors. T he HSIZE pin configures HIP for 8- or 16-
bit communication with the host processor. HMD0 configures
the bus strobes, selecting either separate read and write strobes
or a single read/write select and a host data strobe. HMD1
selects either separate address (3-bit) and data (16-bit) buses or
a multiplexed 16-bit address/data bus with address latch enable.
T ying these pins to appropriate values configures the ADSP-
2111 for straight-wire interface to a variety of industry-standard
microprocessors and microcomputers.
Individual interrupt requests are logically ANDed with the bits
in the IMASK register; the highest-priority unmasked interrupt
is then selected.
T he interrupt control register, ICNT L, allows the external
interrupts to be set as either edge- or level-sensitive. Depending
on bit 4 in ICNT L, interrupt service routines can either be
nested (with higher priority interrupts taking precedence) or be
processed sequentially (with only one interrupt service active at
a time).
T he HIP contains six data registers (HDR5-0) and two status
registers (HSR7-6) with an associated HMASK register for
masking interrupts from individual HIP data registers. T he HIP
data registers are memory-mapped in the internal data memory
–6–
REV. B
ADSP-21xx
T he interrupt force and clear register, IFC, is a write-only
register that contains a force bit and a clear bit for each inter-
rupt (except for level-sensitive interrupts and the ADSP-2111
HIP interrupts—these cannot be forced or cleared in software).
SYSTEM INTERFACE
Figure 3 shows a typical system for the ADSP-2101, ADSP-
2115, or ADSP-2103, with two serial I/O devices, a boot
EPROM, and optional external program and data memory. A
total of 15K words of data memory and 16K words of program
memory is addressable for the ADSP-2101 and ADSP-2103. A
total of 14.5K words of data memory and 15K words of
program memory is addressable for the ADSP-2115.
When responding to an interrupt, the AST AT , MST AT , and
IMASK status registers are pushed onto the status stack and
the PC counter is loaded with the appropriate vector address.
T he status stack is seven levels deep (nine levels deep on the
ADSP-2111) to allow interrupt nesting. T he stack is automati-
cally popped when a return from the interrupt instruction is
executed.
Figure 4 shows a system diagram for the ADSP-2105, with one
serial I/O device, a boot EPROM, and optional external
program and data memory. A total of 14.5K words of data
memory and 15K words of program memory is addressable for
the ADSP-2105.
P in D efinitions
T able IV (on next page) shows pin definitions for the ADSP-
21xx processors. Any inputs not used must be tied to VDD
.
Figure 5 shows a system diagram for the ADSP-2111, with two
serial I/O devices, a host processor, a boot EPROM, and
optional external program and data memory. A total of 15K
words of data memory and 16K words of program memory is
addressable.
Table III. Interrupt Vector Addresses & P riority
AD SP -2105
Interrupt
Source
Interrupt
Vector Address
Programmable wait-state generation allows the processors to
easily interface to slow external memories.
RESET Startup
IRQ2
SPORT 1 T ransmit or IRQ1
SPORT 1 Receive or IRQ0
T imer
0x0000
0x0004 (High Priority)
0x0010
0x0014
0x0018 (Low Priority)
T he ADSP-2101, ADSP-2103, ADSP-2115, and ADSP-2111
processors also provide either: one external interrupt (IRQ2)
and two serial ports (SPORT 0, SPORT 1), or three external
interrupts (IRQ2, IRQ1, IRQ0) and one serial port (SPORT 0).
T he ADSP-2105 provides either: one external interrupt (IRQ2)
and one serial port (SPORT 1), or three external interrupts
(IRQ2, IRQ1, IRQ0) with no serial port.
AD SP -2101/2103/2115/216x
Interrupt
Interrupt
Source
Vector Address
Clock Signals
T he ADSP-21xx processors’ CLKIN input may be driven by a
crystal or by a T T L-compatible external clock signal. T he
CLKIN input may not be halted or changed in frequency during
operation, nor operated below the specified low frequency limit.
RESET Startup
IRQ2
0x0000
0x0004 (High Priority)
0x0008
0x000C
0x0010
SPORT 0 T ransmit
SPORT 0 Receive
SPORT 1 T ransmit or IRQ1
SPORT 1 Receive or IRQ0
T imer
If an external clock is used, it should be a T T L-compatible
signal running at the instruction rate. T he signal should be
connected to the processor’s CLKIN input; in this case, the
XT AL input must be left unconnected.
0x0014
0x0018 (Low Priority)
AD SP -2111
Interrupt
Source
Because the ADSP-21xx processors include an on-chip oscilla-
tor circuit, an external crystal may also be used. T he crystal
should be connected across the CLKIN and XT AL pins, with
two capacitors connected as shown in Figure 2. A parallel-
resonant, fundamental frequency, microprocessor-grade crystal
should be used.
Interrupt
Vector Address
RESET Startup
IRQ2
0x0000
0x0004 (High Priority)
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020 (Low Priority)
HIP Write from Host
HIP Read to Host
SPORT 0 T ransmit
SPORT 0 Receive
SPORT 1 T ransmit or IRQ1
SPORT 1 Receive or IRQ0
T imer
XTAL
ADSP-21xx
CLKIN
CLKOUT
Figure 2. External Crystal Connections
REV. B
–7–
ADSP-21xx
A clock output signal (CLKOUT ) is generated by the processor,
synchronized to the processor’s internal cycles.
T he power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is
applied to the processor and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 tCK cycles will ensure that the PLL has locked (this does
not, however, include the crystal oscillator start-up time).
During this power-up sequence the RESET signal should be
held low. On any subsequent resets, the RESET signal must
Reset
The RESET signal initiates a complete reset of the ADSP-21xx.
T he RESET signal must be asserted when the chip is powered
up to assure proper initialization. If the RESET signal is applied
during initial power-up, it must be held long enough to allow
the processor’s internal clock to stabilize. If RESET is activated
at any time after power-up and the input clock frequency does
not change, the processor’s internal clock continues and does
not require this stabilization time.
meet the minimum pulse width specification, tRSP
.
T o generate the RESET signal, use either an RC circuit with an
external Schmidt trigger or a commercially available reset IC.
(Do not use only an RC circuit.)
Table IV. AD SP -21xx P in D efinitions
P in
Nam e(s)
# of
P ins
Input /
O utput
Function
Address
Data1
14
24
O
I/O
Address outputs for program, data and boot memory.
Data I/O pins for program and data memories. Input only for
boot memory, with two MSBs used for boot memory addresses.
Unused data lines may be left floating.
Processor Reset Input
External Interrupt Request # 2
External Bus Request Input
External Bus Grant Output
External Program Memory Select
External Data Memory Select
Boot Memory Select
External Memory Read Enable
External Memory Write Enable
Memory Map Select Input
External Clock or Quartz Crystal Input
Processor Clock Output
Power Supply Pins
RESET
1
1
1
1
1
1
1
1
1
1
2
1
I
I
I
O
O
O
O
O
O
I
IRQ2
BR2
BG
PMS
DMS
BMS
RD
WR
MMAP
CLKIN, XT AL
CLKOUT
VDD
I
O
GND
Ground Pins
SPORT 03
SPORT 1
or Interrupts & Flags:
IRQ0 (RFS1)
IRQ1 (TFS1)
FI (DR1)
FO (DT1)
FL2–0 (ADSP-2111 Only)
5
5
I/O
I/O
Serial Port 0 Pins (TFS0, RFS0, DT0, DR0, SCLK0)
Serial Port 1 Pins (TFS1, RFS1, DT1, DR1, SCLK1)
1
1
1
1
3
I
I
I
O
O
External Interrupt Request # 0
External Interrupt Request # 1
Flag Input Pin
Flag Output Pin
General Purpose Flag Output Pins
Host Interface Port
(ADSP-2111 Only)
HSEL
HACK
1
1
I
O
HIP Select Input
HIP Acknowledge Output
HSIZE
BMODE
HMD0
HMD1
HRD/HRW
HWR/HDS
HD15–0/HAD15-0
HA2/ALE
HA1–0/Unused
1
1
1
1
1
1
16
1
2
I
I
I
I
I
I
8/16-Bit Host Select (0 = 16-Bit, 1 = 8-Bit)
Boot Mode Select (0 = Standard EPROM Booting, 1 = HIP Booting)
Bus Strobe Select (0 = RD/WR, 1 = RW/DS)
HIP Address/Data Mode Select (0 = Separate, 1 = Multiplexed)
HIP Read Strobe or Read/Write Select
HIP Write Strobe or Host Data Strobe Select
HIP Data or HIP Data and Address
I/O
I
I
Host Address 2 Input or Address Latch Enable Input
Host Address 1 and 0 Inputs
NOT ES
1Unused data bus lines may be left floating.
2BR must be tied high (to VDD) if not used.
3ADSP-2105 does not have SPORT 0. (SPORT 0 pins are No Connects on the ADSP-2105.)
–8–
REV. B
ADSP-21xx
ADSP-2101
or ADSP-2103
or ADSP-2115
A13-0
14
ADDR13-0
BOOT
MEMORY
1x CLOCK
or
CRYSTAL
D
CLKIN
ADDR
23-22
XTAL
e.g. EPROM
D15-8
24
2764
27128
27256
27512
CLKOUT
RESET
DATA23-0
DATA
OE
CS
BMS
IRQ2
BR
A13-0
D23-0
BG
ADDR
DATA
MMAP
PROGRAM
MEMORY
OE
WE
CS
RD
SPORT 1
SCLK1
RFS1 or IRQ0
TFS1 or IRQ1
DT1 or FO
DR1 or FI
WR
(OPTIONAL)
SERIAL
DEVICE
A13-0
D23-8
(OPTIONAL)
ADDR
DATA
DATA
MEMORY
&
SPORT 0
SCLK0
RFS0
TFS0
DT0
PMS
DMS
PERIPHERALS
OE
WE
CS
SERIAL
DEVICE
(OPTIONAL)
(OPTIONAL)
DR0
THE TWO MSBs OF THE DATA BUS (D23-22) ARE USED TO SUPPLY THE TWO MSBs OF THE
BOOT MEMORY EPROM ADDRESS. THIS IS ONLY REQUIRED FOR THE 27256 AND 27512.
Figure 3. ADSP-2101/ADSP-2103/ADSP-2115 System
ADSP-2105
A
14
13-0
ADDR
13-0
23-0
BOOT
MEMORY
1x CLOCK
or
CRYSTAL
D
CLKIN
XTAL
ADDR
23-22
e.g. EPROM
D
24
15-8
2764
27128
27256
27512
CLKOUT
RESET
IRQ2
DATA
DATA
OE
CS
BMS
BR
BG
A
13-0
ADDR
DATA
D
MMAP
23-0
PROGRAM
MEMORY
RD
OE
WE
CS
SPORT 1
SCLK1
RFS1 or IRQ0
TFS1 or IRQ1
DT1 or FO
DR1 or FI
WR
(OPTIONAL)
SERIAL
DEVICE
A
D
13-0
(OPTIONAL)
ADDR
DATA
DATA
MEMORY
&
23-8
PMS
DMS
PERIPHERALS
OE
WE
CS
(OPTIONAL)
THE TWO MSBs OF THE DATA BUS (D
) ARE USED TO SUPPLY THE TWO MSBs OF THE
23-22
BOOT MEMORY EPROM ADDRESS. THIS IS ONLY REQUIRED FOR THE 27256 AND 27512.
Figure 4. ADSP-2105 System
REV. B
–9–
ADSP-21xx
ADSP-2111
A13-0
14
BOOT
MEMORY
ADDR13-0
1x CLOCK
or
CRYSTAL
D
CLKIN
ADDR
23-22
(OPTIONAL)
XTAL
e.g. EPROM
D15-8
24
2764
27128
27256
27512
CLKOUT
RESET
DATA23-0
DATA
OE
CS
BMS
IRQ2
BR
A13-0
D23-0
ADDR
DATA
BG
MMAP
PROGRAM
MEMORY
OE
WE
CS
RD
SPORT 1
SCLK1
RFS1 or IRQ0
TFS1 or IRQ1
DT1 or FO
DR1 or FI
WR
(OPTIONAL)
SERIAL
DEVICE
A13-0
D23-8
(OPTIONAL)
ADDR
DATA
DATA
MEMORY
&
SPORT 0
SCLK0
RFS0
TFS0
DT0
PMS
DMS
PERIPHERALS
OE
WE
CS
SERIAL
DEVICE
(OPTIONAL)
(OPTIONAL)
DR0
FL0
FL1
FL2
HOST
PROCESSOR
HOST INTERFACE PORT
CONTROL
7
(OPTIONAL)
16
DATA / ADDR
THE TWO MSBs OF THE DATA BUS (D23-22) ARE USED TO SUPPLY THE TWO MSBs OF THE
BOOT MEMORY EPROM ADDRESS. THIS IS ONLY REQUIRED FOR THE 27256 AND 27512.
Figure 5. ADSP-2111 System
T he data lines are bidirectional. T he program memory select
(PMS) signal indicates accesses to program memory and can be
used as a chip select signal. T he write (WR) signal indicates a
write operation and is used as a write strobe. T he read (RD)
signal indicates a read operation and is used as a read strobe or
output enable signal.
T he RESET input resets all internal stack pointers to the empty
stack condition, masks all interrupts, and clears the MST AT
register. When RESET is released, the boot loading sequence is
performed (provided there is no pending bus request and the
chip is configured for booting, with MMAP = 0). T he first
instruction is then fetched from internal program memory
location 0x0000.
T he ADSP-21xx processors write data from their 16-bit
registers to 24-bit program memory using the PX register to
provide the lower eight bits. When the processor reads 16-bit
data from 24-bit program memory to a 16-bit data register, the
lower eight bits are placed in the PX register.
P r ogr am Mem or y Inter face
T he on-chip program memory address bus (PMA) and on-chip
program memory data bus (PMD) are multiplexed with the on-
chip data memory buses (DMA, DMD), creating a single
external data bus and a single external address bus. T he external
data bus is bidirectional and is 24 bits wide to allow instruction
fetches from external program memory. Program memory may
contain code and data.
T he program memory interface can generate 0 to 7 wait states
for external memory devices; default is to 7 wait states after
RESET.
P r ogr am Mem or y Maps
T he external address bus is 14 bits wide. For the ADSP-2101,
ADSP-2103, and ADSP-2111, these lines can directly address
up to 16K words, of which 2K are on-chip. For the ADSP-2105
and ADSP-2115, the address lines can directly address up to
15K words, of which 1K is on-chip.
Program memory can be mapped in two ways, depending on the
state of the MMAP pin. Figure 6 shows the two program
memory maps for the ADSP-2101, ADSP-2103, and
ADSP-2111. Figure 8 shows the program memory maps for the
ADSP-2105 and ADSP-2115. Figures 7 and 9 show the
program memory maps for the ADSP-2161/62 and ADSP-2163/
64, respectively.
–10–
REV. B
ADSP-21xx
AD SP -2101/AD SP -2103/AD SP -2111
AD SP -2105/AD SP -2115
When MMAP = 0, on-chip program memory RAM occupies
2K words beginning at address 0x0000. Off-chip program
memory uses the remaining 14K words beginning at address
0x0800. In this configuration–when MMAP = 0–the boot
loading sequence (described below in “Boot Memory Inter-
face”) is automatically initiated when RESET is released.
When MMAP = 0, on-chip program memory RAM occupies
1K words beginning at address 0x0000. Off-chip program
memory uses the remaining 14K words beginning at address
0x0800. In this configuration–when MMAP = 0–the boot
loading sequence (described below in “Boot Memory Inter-
face”) is automatically initiated when RESET is released.
When MMAP = 1, 14K words of off-chip program memory
begin at address 0x0000 and on-chip program memory RAM is
located in the upper 2K words, beginning at address 0x3800. In
this configuration, program memory is not booted although it
can be written to and read under program control.
When MMAP = 1, 14K words of off-chip program memory
begin at address 0x0000 and on-chip program memory RAM is
located in the 1K words between addresses 0x3800–0x3BFF. In
this configuration, program memory is not booted although it
can be written to and read under program control.
0x0000
0x0000
0x0000
0x0000
INTERNAL RAM
1K
INTERNAL
RAM
LOADED FROM
EXTERNAL
2K
BOOT MEMORY
0x03FF
0x0400
LOADED FROM
EXTERNAL
EXTERNAL
14K
BOOT MEMORY
0x07FF
0x0800
RESERVED
1K
EXTERNAL
14K
0x07FF
0x0800
0x37FF
0x3800
EXTERNAL
14K
INTERNAL RAM
1K
EXTERNAL
14K
0x37FF
0x3800
0x3BFF
0x3C00
INTERNAL
RAM
RESERVED
1K
2K
0x3FFF
0x3FFF
0x3FFF
0x3FFF
MMAP=1
No Booting
MMAP=0
MMAP=0
MMAP=1
No Booting
Figure 6. ADSP-2101/ADSP-2103/ADSP-2111 Program
Mem ory Maps
Figure 8. ADSP-2105/ADSP-2115 Program Mem ory Maps
0x0000
0x0000
0x0000
0x0000
2K
2K
EXTERNAL
EXTERNAL
8K
4K
0x07FF
0x0800
0x07FF
0x0800
INTERNAL
ROM
INTERNAL
ROM
2K
6K
INTERNAL
ROM
INTERNAL
ROM
0x0FF0
0x0FF0
RESERVED
0x1FF0
RESERVED
0x1FF0
0x0FFF
0x1000
0x0FFF
0x1000
RESERVED
RESERVED
0x1FFF
0x2000
0x1FFF
0x2000
10K
EXTERNAL
6K
EXTERNAL
12K
EXTERNAL
8K
EXTERNAL
0x37FF
0x3800
0x37FF
0x3800
2K
2K
INTERNAL
ROM
INTERNAL
ROM
0x3FFF
0x3FFF
0x3FFF
0x3FFF
MMAP=0
MMAP=1
MMAP=0
MMAP=1
Figure 7. ADSP-2161/62 Program Mem ory Maps
REV. B
Figure 9. ADSP-2163/64 Program Mem ory Maps
–11–
ADSP-21xx
D ata Mem or y Inter face
All P r ocessor s
T he data memory address bus (DMA) is 14 bits wide. T he
bidirectional external data bus is 24 bits wide, with the upper 16
bits used for data memory data (DMD) transfers.
T he remaining 14K of data memory is located off-chip. T his
external data memory is divided into five zones, each associated
with its own wait-state generator. T his allows slower peripherals
to be memory-mapped into data memory for which wait states
are specified. By mapping peripherals into different zones, you
can accommodate peripherals with different wait-state require-
ments. All zones default to seven wait states after RESET.
T he data memory select (DMS) signal indicates access to data
memory and can be used as a chip select signal. T he write (WR)
signal indicates a write operation and can be used as a write
strobe. T he read (RD) signal indicates a read operation and can
be used as a read strobe or output enable signal.
Boot Mem or y Inter face
On the ADSP-2101, ADSP-2103, and ADSP-2111, boot
memory is an external 64K by 8 space, divided into eight
separate 8K by 8 pages. On the ADSP-2105 and ADSP-2115,
boot memory is a 32K by 8 space, divided into eight separate
4K by 8 pages. T he 8-bit bytes are automatically packed into
24-bit instruction words by each processor, for loading into on-
chip program memory.
T he ADSP-21xx processors support memory-mapped I/O, with
the peripherals memory-mapped into the data memory address
space and accessed by the processor in the same manner as data
memory.
D ata Mem or y Map
AD SP -2101/AD SP -2103/AD SP -2111
For the ADSP-2101, ADSP-2103, and ADSP-2111, on-chip
data memory RAM resides in the 1K words beginning at
address 0x3800, as shown in Figure 10. Data memory locations
from 0x3C00 to the end of data memory at 0x3FFF are
reserved. Control and status registers for the system, timer,
wait-state configuration, and serial port operations are located in
this region of memory.
T hree bits in the processors’ System Control Register select
which page is loaded by the boot memory interface. Another bit
in the System Control Register allows the forcing of a boot
loading sequence under software control. Boot loading from
Page 0 after RESET is initiated automatically if MMAP = 0.
T he boot memory interface can generate zero to seven wait
states; it defaults to three wait states after RESET. T his allows
the ADSP-21xx to boot from a single low cost EPROM such as
a 27C256. Program memory is booted one byte at a time and
converted to 24-bit program memory words.
AD SP -2105/AD SP -2115
For the ADSP-2105 and ADSP-2115, on-chip data memory
RAM resides in the 512 words beginning at address 0x3800,
also shown in Figure 10. Data memory locations from 0x3A00
to the end of data memory at 0x3FFF are reserved. Control and
status registers for the system, timer, wait-state configuration,
and serial port operations are located in this region of memory.
T he BMS and RD signals are used to select and to strobe the
boot memory interface. Only 8-bit data is read over the data
bus, on pins D8-D15. T o accommodate up to eight pages of
boot memory, the two MSBs of the data bus are used in the
boot memory interface as the two MSBs of the boot memory
address: D23, D22, and A13 supply the boot page number.
0x0000
1K EXTERNAL
DWAIT0
T he ADSP-2100 Family Assembler and Linker allow the
creation of programs and data structures requiring multiple boot
pages during execution.
0x0400
1K EXTERNAL
DWAIT1
T he BR signal is recognized during the booting sequence. T he
bus is granted after loading the current byte is completed. BR
during booting may be used to implement booting under control
of a host processor.
0x0800
EXTERNAL
10K EXTERNAL
RAM
DWAIT2
Bus Inter face
T he ADSP-21xx processors can relinquish control of their data
and address buses to an external device. When the external
device requires control of the buses, it asserts the bus request
signal (BR). If the ADSP-21xx is not performing an external
memory access, it responds to the active BR input in the next
cycle by:
0x3000
0x3400
1K EXTERNAL
DWAIT3
1K EXTERNAL
DWAIT4
0x3800
0x3A00
0x3C00
•
T hree-stating the data and address buses and the PMS,
DMS, BMS, RD, WR output drivers,
512 for ADSP-2105
ADSP-2115
1K for ADSP-2101
ADSP-2103
ADSP-216x
•
•
Asserting the bus grant (BG) signal,
and halting program execution.
ADSP-2111
INTERNAL
RAM
If the Go mode is set, however, the ADSP-21xx will not halt
program execution until it encounters an instruction that
requires an external memory access.
MEMORY-MAPPED
CONTROL REGISTERS
& RESERVED
0x3FFF
Figure 10. Data Mem ory Map (All Processors)
–12–
REV. B
ADSP-21xx
If the ADSP-21xx is performing an external memory access
when the external device asserts the BR signal, it will not three-
state the memory interfaces or assert the BG signal until the
cycle after the access completes (up to eight cycles later depend-
ing on the number of wait states). T he instruction does not need
to be completed when the bus is granted; the ADSP-21xx will
grant the bus in between two memory accesses if an instruction
requires more than one external memory access.
Devices for conversion into a ADSP-216x ROM product.
T he ADSP-2101 EZ-ICE emulator can be used for develop-
ment of ADSP-216x systems. For the 3.3 V ADSP-2162 and
ADSP-2164, a voltage converter interface board provides 3.3 V
emulation.
Additional overlay memory is used for emulation of ADSP-
2161/62 systems. It should be noted that due to the use of off-
chip overlay memory to emulate the ADSP-2161/62, a perfor-
mance loss may be experienced when both executing instruc-
tions and fetching program memory data from the off-chip
overlay memory in the same cycle. T his can be overcome by
locating program memory data in on-chip memory.
When the BR signal is released, the processor releases the BG
signal, re-enables the output drivers and continues program
execution from the point where it stopped.
T he bus request feature operates at all times, including when
the processor is booting and when RESET is active. If this
feature is not used, the BR input should be tied high (to VDD).
O r der ing P r ocedur e for AD SP -216x RO M P r ocessor s
T o place an order for a custom ROM-coded ADSP-2161,
ADSP-2162, ADSP-2163, or ADSP-2164 processor, you must:
Low P ower ID LE Instr uction
T he IDLE instruction places the ADSP-21xx processor in low
power state in which it waits for an interrupt. When an interrupt
occurs, it is serviced and execution continues with instruction
following IDLE. T ypically this next instruction will be a JUMP
back to the IDLE instruction. T his implements a low-power
standby loop.
1. Complete the following forms contained in the ADSP ROM
Ordering Package, available from your Analog Devices sales
representative:
ADSP-216x ROM Specification Form
ROM Release Agreement
ROM NRE Agreement & Minimum Quantity Order (MQO)
Acceptance Agreement for Pre-Production ROM Products
T he IDLE n instruction is a special version of IDLE that slows
the processor’s internal clock signal to further reduce power
consumption. T he reduced clock frequency, a programmable
fraction of the normal clock rate, is specified by a selectable
divisor, n, given in the IDLE instruction. T he syntax of the
instruction is:
2. Return the forms to Analog Devices along with two copies of
the Memory Image File (.EXE file) of your ROM code. T he
files must be supplied on two 3.5" or 5.25" floppy disks for
the IBM PC (DOS 2.01 or higher).
3. Place a purchase order with Analog Devices for non-recurring
engineering changes (NRE) associated with ROM product
development.
IDLE n;
where n = 16, 32, 64, or 128.
T he instruction leaves the chip in an idle state, operating at the
slower rate. While it is in this state, the processor’s other
internal clock signals, such as SCLK, CLKOUT , and the timer
clock, are reduced by the same ratio. Upon receipt of an
enabled interrupt, the processor will stay in the IDLE state for
up to a maximum of n CLKIN cycles, where n is the divisor
specified in the instruction, before resuming normal operation.
After this information is received, it is entered into Analog
Devices’ ROM Manager System which assigns a custom ROM
model number to the product. T his model number will be
branded on all prototype and production units manufactured to
these specifications.
T o minimize the risk of code being altered during this process,
Analog Devices verifies that the .EXE files on both floppy disks
are identical, and recalculates the checksums for the .EXE file
entered into the ROM Manager System. T he checksum data, in
the form of a ROM Memory Map, a hard copy of the .EXE file,
and a ROM Data Verification form are returned to you for
inspection.
When the IDLE n instruction is used, it slows the processor’s
internal clock and thus its response time to incoming interrupts–
the 1-cycle response time of the standard IDLE state is in-
creased by n, the clock divisor. When an enabled interrupt is
received, the ADSP-21xx will remain in the IDLE state for up
to a maximum of n CLKIN cycles (where n = 16, 32, 64, or
128) before resuming normal operation.
When the IDLE n instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the IDLE state (a maximum of n
CLKIN cycles).
AD SP -216x P r ototyping
You can prototype your ADSP-216x system with either the
ADSP-2101 or ADSP-2103 RAM-based processors. When code
is fully developed and debugged, it can be submitted to Analog
REV. B
–13–
ADSP-21xx
A signed ROM Verification Form and a purchase order for
production units are required prior to any product being
manufactured. Prototype units may be applied toward the
minimum order quantity.
Functional D iffer ences for O lder Revision D evices
Older revisions of the ADSP-21xx processors have slight
differences in functionality. T he two differences are as follows:
•
Bus Grant (BG) is asserted in the same cycle that Bus
Request (BR) is recognized (i.e. when setup and hold time
requirements are met for the BR input). Bus Request input is
a synchronous input rather than asynchronous. (In newer
revision devices, BG is asserted in the cycle after BR is
recognized.)
Upon completion of prototype manufacture, Analog Devices
will ship prototype units and a delivery schedule update for
production units. An invoice against your purchase order for the
NRE charges is issued at this time.
T here is a charge for each ROM mask generated and a mini-
mum order quantity. Consult your sales representative for
details. A separate order must be placed for parts of a specific
package type, temperature range, and speed grade.
•
Only the standard IDLE instruction is available, not the
clock-reducing IDLE n instruction.
T o determine the revision of a particular ADSP-21xx device,
inspect the marking on the device. For example, an ADSP-2101
of revision 6.0 will have the following marking:
a
ADSP-2101
KS-66
EE/A12345-6.0
Package & Speed
Lot # & Revision Code
Date Code
←
←
←
∆
9234
T he revision codes for the older versions of each ADSP-21xx
device are as follows:
P rocessor
O ld Functionality
New Functionality
ADSP-2101
ADSP-2105
ADSP-2115
ADSP-2111
ADSP-2103
Revision Code ≤ 5.0
No Revision Code
Revision Code < 1.0
RevisionCode < 2.0
Revision code ≤ 5.0
Revision Code ≥ 6.0
Revision Code ≥ 1.0
Revision Code ≥ 1.0
Revision Code ≥ 2.0
Revision code ≥ 6.0
–14–
REV. B
ADSP-21xx
Instr uction Set
operational parallelism. T here are five basic categories of
instructions: data move instructions, computational instruc-
tions, multifunction instructions, program flow control instruc-
tions and miscellaneous instructions. Multifunction instructions
perform one or two data moves and a computation.
T he ADSP-21xx assembly language uses an algebraic syntax for
ease of coding and readability. T he sources and destinations of
computations and data movements are written explicitly in each
assembly statement, eliminating cryptic assembler mnemonics.
Every instruction assembles into a single 24-bit word and
executes in a single cycle. T he instructions encompass a wide
variety of instruction types along with a high degree of
T he instruction set is summarized below. T he ADSP-2100
Family Users Manual contains a complete reference to the
instruction set.
ALU Instructions
[IF cond] AR| AF
=
=
=
=
=
=
=
=
=
=
=
=
=
=
xop + yop [+ C] ;
xop – yop [+ C– 1] ;
yop – xop [+ C– 1] ;
xop AND yop ;
xop OR yop ;
xop XOR yop ;
PASS xop ;
– xop ;
NOT xop ;
ABS xop ;
yop + 1 ;
Add/Add with Carry
Subtract X – Y/Subtract X – Y with Borrow
Subtract Y – X/Subtract Y – X with Borrow
AND
OR
XOR
Pass, Clear
Negate
NOT
Absolute Value
Increment
Decrement
Divide
yop – 1 ;
DIVS yop, xop ;
DIVQ xop ;
MAC Instructions
[IF cond] MR| MF
=
=
=
=
=
xop yop ;
*
Multiply
MR + xop yop ;
*
Multiply/Accumulate
Multiply/Subtract
Transfer MR
MR – xop yop ;
*
MR ;
0 ;
Clear
IF MV SAT MR ;
Conditional MR Saturation
Shifter Instructions
[IF cond] SR = [SR OR] ASHIFT xop ;
[IF cond] SR = [SR OR] LSHIFT xop ;
SR = [SR OR] ASHIFT xop BY <exp>;
SR = [SR OR] LSHIFT xop BY <exp>;
[IF cond] SE = EXP xop ;
Arithmetic Shift
Logical Shift
Arithmetic Shift Immediate
Logical Shift Immediate
Derive Exponent
[IF cond] SB = EXPADJ xop
[IF cond] SR = [SR OR] NORM xop ;
;
Block Exponent Adjust
Normalize
D ata Move Instructions
reg = reg ;
reg = <data> ;
Register-to-Register Move
Load Register Immediate
reg = DM (<addr>) ;
dreg = DM (Ix , My) ;
dreg = PM (Ix , My) ;
DM (<addr>) = reg ;
DM (Ix , My) = dreg ;
PM (Ix , My) = dreg ;
Data Memory Read (Direct Address)
Data Memory Read (Indirect Address)
Program Memory Read (Indirect Address)
Data Memory Write (Direct Address)
Data Memory Write (Indirect Address)
Program Memory Write (Indirect Address)
Multifunction Instructions
<ALU>| <MAC>| <SHIFT > , dreg = dreg ;
Computation with Register-to-Register Move
<ALU>| <MAC>| <SHIFT > , dreg = DM (Ix , My) ;
<ALU>| <MAC>| <SHIFT > , dreg = PM (Ix , My) ;
DM (Ix , My) = dreg , <ALU>| <MAC>| <SHIFT > ;
PM (Ix , My) = dreg , <ALU>| <MAC>| <SHIFT > ;
dreg = DM (Ix , My) , dreg = PM (Ix , My) ;
Computation with Memory Read
Computation with Memory Read
Computation with Memory Write
Computation with Memory Write
Data & Program Memory Read
<ALU>| <MAC> , dreg = DM (Ix , My) , dreg = PM (Ix , My) ;
ALU/MAC with Data & Program Memory Read
REV. B
–15–
ADSP-21xx
P rogram Flow Instructions
DO <addr> [UNT IL term] ;
[IF cond] JUMP (Ix) ;
Do Until Loop
Jump
[IF cond] JUMP <addr>;
[IF cond] CALL (Ix) ;
Call Subroutine
[IF cond] CALL <addr>;
IF [NOT ] FLAG_IN
IF [NOT ] FLAG_IN
JUMP <addr>;
CALL <addr>;
Jump/Call on Flag In Pin
[IF cond] SET | RESET | T OGGLE
[IF cond] RT S ;
[IF cond] RT I ;
FLAG_OUT [, ...] ;
Modify Flag Out Pin
Return from Subroutine
Return from Interrupt Service Routine
Idle
IDLE [(n)] ;
Miscellaneous Instructions
NOP ;
MODIFY (Ix , My);
No Operation
Modify Address Register
[PUSH ST S] [, POP CNT R] [, POP PC] [, POP LOOP] ;
Stack Control
Mode Control
ENA| DIS
SEC_REG [, ...] ;
BIT _REV
AV_LAT CH
AR_SAT
M_MODE
T IMER
G_MODE
Notation Conventions
Ix
Index registers for indirect addressing
My
Modify registers for indirect addressing
Immediate data value
Immediate address value
Exponent (shift value) in shift immediate instructions (8-bit signed number)
Any ALU instruction (except divide)
Any multiply-accumulate instruction
Any shift instruction (except shift immediate)
Condition code for conditional instruction
T ermination code for DO UNT IL loop
Data register (of ALU, MAC, or Shifter)
Any register (including dregs)
<data>
<addr>
<exp>
<ALU>
<MAC>
<SHIFT >
cond
term
dreg
reg
;
,
[
A semicolon terminates the instruction
Commas separate multiple operations of a single instruction
Optional part of instruction
]
[, ...]
option1 | option2
Optional, multiple operations of an instruction
List of options; choose one.
Assem bly Code Exam ple
T he following example is a code fragment that performs the filter tap update for an adaptive filter based on a least-mean-squared
algorithm. Notice that the computations in the instructions are written like algebraic equations.
MF=MX0 MY1(RND), MX0=DM(I2,M1);
{MF=error beta}
*
*
MR=MX0 MF(RND), AY0=PM(I6,M5);
*
DO adapt UNTIL CE;
AR=MR1+AY0, MX0=DM(I2,M1), AY0=PM(I6,M7);
adapt:
PM(I6,M6)=AR, MR=MX0 MF(RND);
*
MODIFY(I2,M3);
MODIFY(I6,M7);
{Point to oldest data}
{Point to start of data}
–16–
REV. B
ADSP-21xx
ADSP-2101/2105/2115/2161/2163–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade
B Grade
T Grade
P aram eter
Min
Max
Min
Max
Min
Max
Unit
VDD
T AMB
Supply Voltage
Ambient Operating T emperature
4.50
0
5.50
+70
4.50
–40
5.50
+85
4.50
–55
5.50
+125
V
°C
See “Environmental Conditions” for information on thermal specifications.
ELECTRICAL CHARACTERISTICS
P aram eter
Test Conditions
Min
Max
Unit
VIH
VIH
VIL
VOH
Hi-Level Input Voltage3, 5
Hi-Level CLKIN Voltage
Lo-Level Input Voltage1, 3
Hi-Level Output Voltage2, 3, 7
@ VDD = max
@ VDD = max
@ VDD = min
2.0
2.2
V
V
V
V
V
V
µA
µA
µA
µA
pF
pF
0.8
@ VDD = min, IOH = –0.5 mA
@ VDD = min, IOH = –100 µA8
@ VDD = min, IOL = 2 mA
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
2.4
VDD – 0.3
VOL
IIH
IIL
IOZH
IOZL
CI
Lo-Level Output Voltage2, 3, 7
Hi-Level Input Current1
0.4
10
10
10
10
8
Lo-Level Input Current1
T ristate Leakage Current4
T ristate Leakage Current4
Input Pin Capacitance1, 8, 9
Output Pin Capacitance4, 8, 9, 10
@ VDD = max, VIN = VDD max6
@ VDD = max, VIN = 0 V6
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C
CO
8
NOT ES
1Input-only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR1, DR0 (not on ADSP-2105).
2Output pins: BG, PMS, DMS, BMS, RD, WR, A0–A13, CLKOUT , DT 1, DT 0 (not on ADSP-2105).
3Bidirectional pins: D0–D23, SCLK1, RFS1, T FS1, SCLK0 (not on ADSP-2105), RFS0 (not on ADSP-2105), T FS0 (not on ADSP-2105).
4T ristatable pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT 1, SCLK1, RSF1, T FS1, DT 0 (not on ADSP-2105), SCLK0 (not on ADSP-2105),
RFS0 (not on ADSP-2105), T FS0 (not on ADSP-2105).
5Input-only pins: RESET, IRQ2, BR, MMAP, DR1, DR0 (not on ADSP-2105).
60 V on BR, CLKIN Active (to force tristate condition).
7Although specified for T T L outputs, all ADSP-21xx outputs are CMOS-compatible and will drive to V DD and GND, assuming no dc loads.
8Guaranteed but not tested.
9Applies to PGA, PLCC, PQFP package types.
10Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
ABSO LUTE MAXIMUM RATINGS
*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating T emperature Range (Ambient) . . . –55ºC to +125ºC
Storage T emperature Range . . . . . . . . . . . . . –65ºC to +150ºC
Lead T emperature (10 sec) PGA . . . . . . . . . . . . . . . . . +300ºC
Lead T emperature (5 sec) PLCC, PQFP, T QFP . . . . +280ºC
*Stresses greater than those listed above may cause permanent damage to the
device. T hese are stress ratings only, and functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-21xx processors feature proprietary ESD protection circuitry to dissipate high energy
electrostatic discharges (H uman Body Model), permanent damage may occur to devices subjected
to such discharges. T herefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality. Unused devices must be stored in conductive foam or shunts,
and the foam should be discharged to the destination socket before the devices are removed. Per
method 3015 of MIL-ST D-883, the ADSP-21xx processors have been classified as Class 1 devices.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–17–
ADSP-21xx
SPECIFICATIONS (ADSP-2101/2105/2115/2161/2163)
SUPPLY CURRENT & POWER (ADSP-2101/2105/2115/2161/2163)
P aram eter
IDD
Supply Current (Dynamic)1
Test Conditions
Min
Max
Unit
@ VDD = max, tCK = 40 ns2
@ VDD = max, tCK = 50 ns2
@ VDD = max, tCK = 72.3 ns2
@ VDD = max, tCK = 40 ns4
@ VDD = max, tCK = 50 ns
@ VDD = max, tCK = 72.3 ns
38
31
24
12
11
10
mA
mA
mA
mA
mA
mA
IDD
Supply Current (Idle)1, 3
NOT ES
1Current reflects device operating with no output loads.
2VIN = 0.4 V and 2.4 V.
3Idle refers to ADSP-21xx state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND.
4ADSP-2105 is not available in a 25 MHz speed grade.
For typical supply current (internal power dissipation) figures, see Figure 11.
IDD DYNAMIC
220
1
205mW
200
180
160
157mW
VDD = 5.5V
140
129mW
120
VDD = 5.0V
118mW
100
100mW
74mW
VDD = 4.5V
20.00
80
60
10.00
13.83
25.00
30.00
FREQUENCY – MHz
IDD IDLE
IDD IDLE n MODES3
70
65
60
55
50
45
40
35
64mW
1,2
64mW
60
50
40
30
20
10
0
VDD = 5.5V
IDD IDLE
51mW
49mW
35mW
51mW
VDD = 5.0V
VDD = 4.5V
38mW
28mW
IDLE 16
43mW
42mW
41mW
40mW
IDLE 128
30
10.00
13.83
20.00
25.00
30.00
10.00
13.83
20.00
25.00
30.00
FREQUENCY – MHz
FREQUENCY – MHz
VALID FOR ALL TEMPERATURE GRADES.
1 POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
2 IDLE REFERS TO ADSP-21xx OPERATION DURING EXECUTION OF IDLE INSTRUCTION.
DEASSERTED PINS ARE DRIVEN TO EITHER VDD OR GND.
3 MAXIMUM POWER DISSIPATION AT VDD = 5.5V DURING EXECUTION OF IDLE n INSTRUCTION.
Figure 11. ADSP-2101 Power (Typical) vs. Frequency
–18–
REV. B
ADSP-21xx
SPECIFICATIONS (ADSP-2101/2105/2115/2161/2163)
P O WER D ISSIP ATIO N EXAMP LE
CAP ACITIVE LO AD ING
Figures 12 and 13 show capacitive loading characteristics for the
ADSP-2101, ADSP-2105, ADSP-2115, and ADSP-2161/2163.
T o determine total power dissipation in a specific application,
the following equation should be applied for each output:
2
C × VDD × f
8
7
C = load capacitance, f = output switching frequency.
Exam ple:
V
= 4.5V
DD
In an ADSP-2101 application where external data memory is
used and no other outputs are active, power dissipation is
calculated as follows:
6
5
4
3
2
1
0
Assumptions:
•
•
External data memory is accessed every cycle with 50% of the
address pins switching.
External data memory writes occur every other cycle with
50% of the data pins switching.
•
•
Each address and data pin has a 10 pF total load at the pin.
T he application operates at VDD = 5.0 V and tCK = 50 ns.
0
25
50
75
C
100 125 150 175
– pF
2
L
Total Power Dissipation = PINT + (C × VDD × f )
PINT = internal power dissipation (from Figure 11).
Figure 12. Typical Output Rise Tim e vs. Load Capacitance, CL
(at Maxim um Am bient Operating Tem perature)
2
(C × VDD × f ) is calculated for each output:
5
4
# of
P ins × C
2
O utput
× VD D × f
Address, DMS 8
× 10 pF × 52 V × 20 MHz = 40.0 mW
× 10 pF × 52 V × 10 MHz = 22.5 mW
× 10 pF × 52 V × 10 MHz = 2.5 mW
× 10 pF × 52 V × 20 MHz = 5.0 mW
V
= 4.5V
3
2
DD
Data, WR
RD
9
1
1
CLKOUT
1
70.0 mW
0
T otal power dissipation for this example = PINT + 70.0 mW.
–1
–2
–3
ENVIRO NMENTAL CO ND ITIO NS
Ambient T emperature Rating:
TAMB = T CASE – (PD × θC A
)
0
25
50
75
100 125
– pF
150 175
TCASE = Case T emperature in °C
PD = Power Dissipation in W
C
L
θC A = T hermal Resistance (Case-to-Ambient)
θJA = T hermal Resistance (Junction-to-Ambient)
θJC = T hermal Resistance (Junction-to-Case)
Figure 13. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maxim um Am bient Operating Tem perature)
P ackage
θJA
θJC
θCA
PGA
18°C/W
27°C/W
60°C/W
60°C/W
9°C/W
9°C/W
PLCC
PQFP
T QFP
16°C/W
18°C/W
18°C/W
11°C/W
42°C/W
42°C/W
REV. B
–19–
ADSP-21xx
SPECIFICATIONS (ADSP-2101/2105/2115/2161/2163)
TEST CO ND ITIO NS
Figure 14 shows voltage reference levels for ac measurements.
T he decay time, tDECAY, is dependent on the capacitative load,
CL , and the current load, iL , on the output pin. It can be
approximated by the following equation:
CL × 0.5 V
3.0V
1.5V
0.0V
tDECAY
=
INPUT
iL
from which
2.0V
1.5V
0.8V
tDIS = tMEASURED – tDECAY
OUTPUT
is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.
Figure 14. Voltage Reference Levels for AC Measurem ents
(Except Output Enable/Disable)
O utput Enable Tim e
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. T he output enable time (t E NA) is the interval from
when a reference signal reaches a high or low voltage level to
when the output has reached a specified high or low trip point,
as shown in Figure 15. If multiple pins (such as the data bus)
are enabled, the measurement value is that of the first pin to
start driving.
O utput D isable Tim e
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. T he
output disable time (tDIS) is the difference of tMEASURED and
t
DECAY, as shown in Figure 15. T he time tMEASURED is the
interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage.
REFERENCE
SIGNAL
tMEASURED
tDIS
tENA
V
V
(MEASURED)
(MEASURED)
V
V
(MEASURED)
(MEASURED)
OH
OL
OH
2.0V
1.0V
V
(MEASURED) – 0.5V
(MEASURED) +0.5V
OH
OUTPUT
tDECAY
V
OL
OL
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE
APPROXIMATELY 1.5V.
Figure 15. Output Enable/Disable
I
OL
TO
OUTPUT
PIN
+1.5V
50pF
I
OH
Figure 16. Equivalent Device Loading for AC Measurem ents
(Except Output Enable/Disable)
–20–
REV. B
ADSP-2111–SPECIFICATIONS
ADSP-21xx
RECOMMENDED OPERATING CONDITIONS
K Grade
B Grade
T Grade
Min
P aram eter
Min
Max
Min
Max
Max
5.50
Unit
VDD
T AMB
Supply Voltage
Ambient Operating T emperature
4.50
0
5.50
+70
4.50
–40
5.50
+85
4.50
–55
V
°C
+125
See “Environmental Conditions” for information on thermal specifications.
ELECTRICAL CHARACTERISTICS
P aram eter
Test Conditions
Min
Max
Unit
VIH
VIH
VIL
VOH
Hi-Level Input Voltage3, 5
Hi-Level CLKIN Voltage
Lo-Level Input Voltage1, 3
Hi-Level Output Voltage2, 3, 7
@ VDD = max
@ VDD = max
@ VDD = min
2.0
2.2
V
V
V
V
V
V
µA
µA
µA
µA
pF
pF
0.8
@ VDD = min, IOH = –0.5 mA
@ VDD = min, IOH = –100 µA8
@ VDD = min, IOL = 2 mA
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0V
2.4
VDD – 0.3
VOL
IIH
IIL
IOZH
IOZL
CI
Lo-Level Output Voltage2, 3, 7
Hi-Level Input Current1
Lo-Level Input Current1
T ristate Leakage Curren4
T ristate Leakage Current4
Input Pin Capacitance1, 8, 9
Output Pin Capacitance4, 8, 9, 10
0.4
10
10
10
10
8
@ VDD = max, VIN = VDD max6
@ VDD = max, VIN = 0V6
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C
CO
8
NOT ES
1Input-only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR1, DR0, HSEL, HSIZE, BMODE, HMD0, HMD1, HRD/HRW, HWR/HDS, HA2/ALE, HA1-0.
2Output pins: BG, PMS, DMS, BMS, RD, WR, A0–A13, CLKOUT , DT 1, DT 0, HACK, FL2-0.
3Bidirectional pins: D0–D23, SCLK1, RFS1, T FS1, SCLK0, RFS0, T FS0, HD0–HD15/HAD0–HAD15.
4T ristatable pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT 1, SCLK1, RSF1, T FS1, DT 0, SCLK0, RFS0, T FS0, HD0–HD15/HAD0–HAD15.
5Input-only pins: RESET, IRQ2, BR, MMAP, DR1, DR0, HSEL, HSIZE, BMODE, HMD0, HMD1, HRD/HRW, HWR/HDS, HA2/ALE, HA1-0.
6 0 V on BR, CLKIN Active (to force tristate condition).
7Although specified for T T L outputs, all ADSP-2111 outputs are CMOS-compatible and will drive to V DD and GND, assuming no dc loads.
8Guaranteed but not tested.
9Applies to ADSP-2111 PGA and PQFP packages.
10Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
ABSO LUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating T emperature Range (Ambient) . . . –55ºC to +125ºC
Storage T emperature Range . . . . . . . . . . . . . –65ºC to +150ºC
Lead T emperature (10 sec) PGA . . . . . . . . . . . . . . . . . +300ºC
Lead T emperature (5 sec) PQFP . . . . . . . . . . . . . . . . . +280ºC
*Stresses greater than those listed above may cause permanent damage to the
device. T hese are stress ratings only, and functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
REV. B
–21–
ADSP-21xx
SPECIFICATIONS (ADSP-2111)
SUPPLY CURRENT & POWER (ADSP-2111)
P aram eter
Test Conditions
Min
Max
Unit
IDD
Supply Current (Dynamic)1
@ VDD = max, tCK = 50 ns2
@ VDD = max, tCK = 60 ns2
@ VDD = max, tCK = 76.9 ns2
@ VDD = max, tCK = 50 ns
@ VDD = max, tCK = 60 ns
@ VDD = max, tCK = 76.9 ns
60
52
46
18
16
14
mA
mA
mA
mA
mA
mA
IDD
Supply Current (Idle)1, 3
NOT ES
1Current reflects device operating with no output loads.
2VIN = 0.4 V and 2.4 V.
3Idle refers to ADSP-21xx state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND.
For typical supply current (internal power dissipation) figures, see Figure 17.
1
POWER, INTERNAL
330
330mW
310
290
270
V
= 5.5V
DD
260mW
200mW
250mW
250
230
V
V
= 5.0V
= 4.5V
210
190
DD
DD
200mW
155mW
170
150
14 15 16 17 18 19 20
1/ tCK – MHz
1,2
POWER, IDLE
3
POWER, IDLE n MODES
IDLE;
70
70mW
100mW
100
90
80
70
60
50
40
30
65
60
55
50
45
40
35
30
V
= 5.5V
DD
80mW
55mW
n
V
= 5.0V
70mW
DD
V
V
= 5.0V
= 4.5V
55mW
40mW
DD
DD
50mW
38mW
36mW
IDLE 16;
IDLE 128;
34mW
32mW
14 15 16 17 18 19 20
1/ tCK – MHz
14 15 16 17 18 19 20
1/ tCK – MHz
VALID FOR ALL TEMPERATURE GRADES.
1
POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
2
IDLE REFERS TO ADSP-21xx OPERATION DURING EXECUTION OF IDLE INSTRUCTION.
DEASSERTED PINS ARE DRIVEN TO EITHER V OR GND.
DD
3
MAXIMUM POWER DISSIPATION AT V = 5.0V DURING EXECUTION OF IDLE n INSTRUCTION.
DD
Figure 17. ADSP-2111 Power (Typical) vs. Frequency
–22–
REV. B
ADSP-21xx
SPECIFICATIONS (ADSP-2111)
P O WER D ISSIP ATIO N EXAMP LE
CAP ACITIVE LO AD ING
T o determine total power dissipation in a specific application,
the following equation should be applied for each output:
Figures 18 and 19 show capacitive loading characteristics for the
ADSP-2111.
2
C × VDD × f
C = load capacitance, f = output switching frequency.
14
Exam ple:
VDD = 4.5V
In an ADSP-2111 application where external data memory is
used and no other outputs are active, power dissipation is
calculated as follows:
12
10
8
Assumptions:
6
•
•
External data memory is accessed every cycle with 50% of the
address pins switching.
4
External data memory writes occur every other cycle with
50% of the data pins switching.
2
25
50
75
100 125 150
•
•
Each address and data pin has a 10 pF total load at the pin.
T he application operates at VDD = 5.0 V and tCK = 50 ns.
CL – pF
2
Figure 18. Typical Output Rise Tim e vs. Load Capacitance, CL
(at Maxim um Am bient Operating Tem perature)
Total Power Dissipation = PINT + (C × VDD × f )
PINT = internal power dissipation (from Figure 17).
2
(C × VDD × f ) is calculated for each output:
# of
P ins × C
+12
+10
2
O utput
× VD D × f
V
= 4.5V
DD
+8
Address, DMS 8
Data, WR
RD
× 10 pF × 52 V × 20 MHz = 40.0 mW
× 10 pF × 52 V × 10 MHz = 22.5 mW
× 10 pF × 52 V × 10 MHz = 2.5 mW
× 10 pF × 52 V × 20 MHz = 5.0 mW
+6
9
1
1
+4
+2
CLKOUT
NOMINAL
70.0 mW
–2
–4
–6
T otal power dissipation for this example = PINT + 70.0 mW.
ENVIRO NMENTAL CO ND ITIO NS
Ambient T emperature Rating:
25
50
75 100
– pF
125 150
C
L
TAMB = T CASE – (PD × θC A
)
TCASE = Case T emperature in °C
PD = Power Dissipation in W
θC A = T hermal Resistance (Case-to-Ambient)
θJA = T hermal Resistance (Junction-to-Ambient)
θJC = T hermal Resistance (Junction-to-Case)
Figure 19. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maxim um Am bient Operating Tem perature)
P ackage
θJA
θJC
θCA
PGA
PQFP
35°C/W
42°C/W
18°C/W
18°C/W
17°C/W
23°C/W
REV. B
–23–
ADSP-21xx
SPECIFICATIONS (ADSP-2111)
T he decay time, tDECAY, is dependent on the capacitative load,
CL , and the current load, iL , on the output pin. It can be
approximated by the following equation:
TEST CO ND ITIO NS
Figure 20 shows voltage reference levels for ac measurements.
CL × 0.5 V
3.0V
1.5V
0.0V
tDECAY =
iL
INPUT
from which
tDIS = tMEASURED – tDECAY
2.0V
1.5V
0.8V
OUTPUT
is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.
Figure 20. Voltage Reference Levels for AC Measurem ents
(Except Output Enable/Disable)
O utput Enable Tim e
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. T he output enable time (t E NA) is the interval from
when a reference signal reaches a high or low voltage level to
when the output has reached a specified high or low trip point,
as shown in Figure 21. If multiple pins (such as the data bus)
are enabled, the measurement value is that of the first pin to
start driving.
O utput D isable Tim e
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. T he
output disable time (tDIS) is the difference of tMEASURED and
t
DECAY, as shown in Figure 21. T he time tMEASURED is the
interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage.
REFERENCE
SIGNAL
tMEASURED
tENA
tDIS
VOH (MEASURED)
VOH (MEASURED)
2.0V
1.0V
VOH (MEASURED) – 0.5V
VOL (MEASURED) +0.5V
OUTPUT
tDECAY
VOL (MEASURED)
VOL (MEASURED)
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE
APPROXIMATELY 1.5V.
Figure 21. Output Enable/Disable
I
OL
TO
OUTPUT
PIN
+1.5V
50pF
I
OH
Figure 22. Equivalent Device Loading for AC Measurem ents
(Except Output Enable/Disable)
–24–
REV. B
ADSP-2103/2162/2164–SPECIFICATIONS
ADSP-21xx
RECOMMENDED OPERATING CONDITIONS
K Grade
Min
B Grade
Min Max
P aram eter
Max
Unit
VDD
T AMB
Supply Voltage
Ambient Operating T emperature
3.00
0
3.60
+70
3.00
–40
3.60
+85
V
°C
See “Environmental Conditions” for information on thermal specifications.
ELECTRICAL CHARACTERISTICS
P aram eter
Test Conditions
Min
Max
Unit
VIH
VIL
VOH
VOL
IIH
Hi-Level Input Voltage1, 3
@ VDD = max
@ VDD = min
2.0
V
V
V
V
µA
µA
µA
µA
pF
pF
Lo-Level Input Voltage1, 3
Hi-Level Output Voltage2, 3, 6
Lo-Level Output Voltage2, 3, 6
Hi-Level Input Current1
0.4
@ VDD = min, IOH = –0.5 mA6
@ VDD = min, IOL = 2 mA6
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
2.4
0.4
10
10
10
10
8
IIL
Lo-Level Input Current1
T ristate Leakage Current4
T ristate Leakage Current4
Input Pin Capacitance1, 7, 8
Output Pin Capacitance4, 7, 8, 9
IOZH
IOZL
CI
@ VDD = max, VIN = VDD max5
@ VDD = max, VIN = 0 V5
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C
CO
8
NOT ES
1Input-only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR1, DR0.
2
Output pins: BG, PMS, DMS, BMS, RD, WR, A0–A13, CLKOUT, DT1, DT0.
Bidirectional pins: D0–D23, SCLK1, RFS1, TFS1, SCLK0, RFS0, TFS0.
Tristatable pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT1, SCLK1, RSF1, TFS1, DT0, SCLK0, RFS0, TFS0.
0 V on BR, CLKIN Active (to force tristate condition).
All ADSP-2103, ADSP-2162, and ADSP-2164 outputs are CMOS and will drive to VDD and GND with no dc loads.
Guaranteed but not tested.
3
4
5
6
7
8
Applies to PLCC and PQFP package types.
9Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
ABSO LUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.5 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating T emperature Range (Ambient) . . . . –40ºC to +85ºC
Storage T emperature Range . . . . . . . . . . . . . –65ºC to +150ºC
Lead T emperature (5 sec) PLCC, PQFP . . . . . . . . . . . +280ºC
*Stresses greater than those listed above may cause permanent damage to the
device. T hese are stress ratings only, and functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
REV. B
–25–
ADSP-21xx
SPECIFICATIONS (ADSP-2103/2162/2164)
SUPPLY CURRENT & POWER (ADSP-2103/2162/2164)
P aram eter
Test Conditions
Min
Max
Unit
IDD
IDD
Supply Current (Dynamic)1
Supply Current (Idle)1, 3
@ VDD = max, tCK = 72.3 ns2
@ VDD = max, tCK = 72.3 ns
14
4
mA
mA
NOT ES
1Current reflects device operating with no output loads.
2VIN = 0.4 V and 2.4 V.
3Idle refers to ADSP-21xx state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND.
For typical supply current (internal power dissipation) figures, see Figure 23.
1,2
IDLE DYNAMIC
50
48mW
45
40
35
30
25
20
15
10
5
V
= 3.6V
DD
V
= 3.30V
37mW
DD
29mW
24mW
V
= 3.0V
13.83
DD
19mW
15mW
0
5.00
7.00
10.00
15.00
FREQUENCY – MHz
IDD IDLE n MODES 3
13mW
IDD IDLE1
= 3.6V
14
14
12
10
8
13mW
V
12
10
8
DD
IDD IDLE
10mW
8mW
9mW
9mW
V
= 3.30V
7mW
6mW
DD
IDLE 16
6
6mW
5mW
6
V
= 3.0V
5mW
4mW
DD
IDLE 128
4
4
2
2
0
5.00
0
5.00
7.00
10.00
13.83
15.00
7.00
10.00
13.83
15.00
FREQUENCY – MHz
FREQUENCY – MHz
VALID FOR ALL TEMPERATURE GRADES.
1
POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
2
IDLE REFERS TO ADSP-21xx OPERATION DURING EXECUTION OF IDLE INSTRUCTION.
DEASSERTED PINS ARE DRIVEN TO EITHER V OR GND.
DD
3
MAXIMUM POWER DISSIPATION AT V = 3.6V DURING EXECUTION OF IDLE n INSTRUCTION.
DD
Figure 23. ADSP-2103 Power (Typical) vs. Frequency
–26–
REV. B
ADSP-21xx
SPECIFICATIONS (ADSP-2103/2162/2164)
P O WER D ISSIP ATIO N EXAMP LE
CAP ACITIVE LO AD ING
T o determine total power dissipation in a specific application,
the following equation should be applied for each output:
Figures 24 and 25 show capacitive loading characteristics for the
ADSP-2103, ADSP-2162, and ADSP-2164.
2
C × VDD × f
C = load capacitance, f = output switching frequency.
Exam ple:
30
25
In an ADSP-2103 application where external data memory is
used and no other outputs are active, power dissipation is
calculated as follows:
V
= 3.0V
DD
20
15
10
5
Assumptions:
•
•
External data memory is accessed every cycle with 50% of the
address pins switching.
External data memory writes occur every other cycle with
50% of the data pins switching.
25
50
75
C
100 125 150
– pF
L
•
•
Each address and data pin has a 10 pF total load at the pin.
T he application operates at VDD = 3.3 V and tCK = 100 ns.
2
Figure 24. Typical Output Rise Tim e vs. Load Capacitance, CL
(at Maxim um Am bient Operating Tem perature)
Total Power Dissipation = PINT + (C × VDD × f )
PINT = internal power dissipation (from Figure 23).
2
(C × VDD × f ) is calculated for each output:
# of
P ins × C
+8
+6
+4
2
O utput
× VD D
× f
Address, DMS 8
× 10 pF × 3.32 V × 10 MHz = 8.71 mW
× 10 pF × 3.32 V × 5 MHz = 4.90 mW
× 10 pF × 3.32 V × 5 MHz = 0.55 mW
× 10 pF × 3.32 V × 10 MHz = 1.09 mW
V
= 3.0V
Data, WR
RD
CLKOUT
9
1
1
DD
+2
NOMINAL
–2
15.25 mW
T otal power dissipation for this example = PINT + 15.25 mW.
25
50
75
100 125 150
C
L
– pF
ENVIRO NMENTAL CO ND ITIO NS
Ambient T emperature Rating:
Figure 25. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maxim um Am bient Operating Tem perature)
TAMB = T CASE – (PD × θC A
)
TCASE = Case T emperature in °C
PD = Power Dissipation in W
θC A = T hermal Resistance (Case-to-Ambient)
θJA = T hermal Resistance (Junction-to-Ambient)
θJC = T hermal Resistance (Junction-to-Case)
P ackage
θJA
θJC
θCA
PGA
PQFP
27°C/W
60°C/W
16°C/W
18°C/W
11°C/W
42°C/W
REV. B
–27–
ADSP-21xx
SPECIFICATIONS (ADSP-2103/2162/2164)
TEST CO ND ITIO NS
Figure 26 shows voltage reference levels for ac measurements.
The decay time, tDECAY, is dependent on the capacitative load,
CL, and the current load, iL, on the output pin. It can be
approximated by the following equation:
V
DD
INPUT
CL × 0.5 V
2
tDECAY
=
iL
from which
V
DD
OUTPUT
2
tDIS = tMEASURED – tDECAY
is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.
Figure 26. Voltage Reference Levels for AC Measurem ents
(Except Output Enable/Disable)
O utput Enable Tim e
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. T he output enable time (t E NA) is the interval from
when a reference signal reaches a high or low voltage level to
when the output has reached a specified high or low trip point,
as shown in Figure 27. If multiple pins (such as the data bus)
are enabled, the measurement value is that of the first pin to
start driving.
O utput D isable Tim e
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. T he
output disable time (tDIS) is the difference of tMEASURED and
t
DECAY, as shown in Figure 27. T he time tMEASURED is the
interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage.
REFERENCE
SIGNAL
tMEASURED
tDIS
tENA
V
V
(MEASURED)
(MEASURED)
V
V
(MEASURED)
(MEASURED)
OH
OL
OH
OL
2.0V
1.0V
V
(MEASURED) – 0.5V
(MEASURED) +0.5V
OH
OUTPUT
tDECAY
V
OL
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE
APPROXIMATELY 1.5V.
Figure 27. Output Enable/Disable
I
OL
TO
OUTPUT
PIN
V
DD
2
50pF
I
OH
Figure 28. Equivalent Device Loading for AC Measurem ents
(Except Output Enable/Disable)
–28–
REV. B
ADSP-21xx
TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)
GENERAL NO TES
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. T iming requirements guarantee that the
processor operates correctly with other devices.
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add parameters to derive longer times.
TIMING NO TES
MEMO RY REQ UIREMENTS
Switching characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
T he table below shows common memory device specifications
and the corresponding ADSP-21xx timing parameters, for your
convenience.
Mem ory
D evice
Specification
AD SP -21xx
Tim ing
P aram eter
Tim ing
P aram eter
D efinition
Address Setup to Write Start
Address Setup to Write End
Address Hold Time
Data Setup Time
tASW
tAW
tWRA
tDW
tDH
A0–A13, DMS, PMS Setup before WR Low
A0–A13, DMS, PMS Setup before WR Deasserted
A0–A13, DMS, PMS Hold after WR Deasserted
Data Setup before WR High
Data Hold Time
Data Hold after WR High
OE to Data Valid
Address Access Time
tRDD
tAA
RD Low to Data Valid
A0–A13, DMS, PMS, BMS to Data Valid
REV. B
–29–
ADSP-21xx
TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)
CLO CK SIGNALS & RESET
Frequency
13 MH z
Min Max Min
13.824 MH z 16.67 MH z
20 MH z
Min
25 MH z
Min Max
D ependency
P aram eter
Max Min
Max
Max
Min
Max Unit
Timing Requirement:
tCK
CLKIN Period
76.9 150
20
20
384.5
72.3
20
20
150
60
20
20
300
150
50
20
20
250
150
40
15
15
200
150
ns
ns
ns
ns
tCKL
tCKH
tRSP
CLKIN Width Low
CLKIN Width High
RESET Width Low
20
20
5tCK
1
361.5
Switching Characteristic:
tCPL
tCPH
tCKOH
CLKOUT Width Low
28.5
28.5
0
26.2
26.2
0
20
20
0
15
15
0
10
10
0
0.5tCK – 10
0.5tCK – 10
ns
ns
ns
CLKOUT Width High
CLKIN High to CLKOUT
High
20
20
20
20
15
NOT ES
1Applies after powerup sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles, assuming stable CLKIN (not including crystal
oscillator startup time).
tCK
tCKH
CLKIN
tCKL
tCKOH
tCPH
CLKOUT
tCPL
Figure 29. Clock Signals
–30–
REV. B
ADSP-21xx
TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)
INTERRUP TS & FLAGS
Frequency
D ependency
Min Max Min Max Min
13 MH z
Min Max Min
13.824 MH z 16.67 MH z 20 MH z
25 MH z
P aram eter
Max Min Max
Max Unit
Timing Requirement:
tIFS
tIFS
tIFH
IRQx1 or FI Setup before
34.2
33.1
36.1
18.1
30
33
15
27.5
30.5
12.5
25
28
10
0.25tCK + 154
0.25tCK + 184
0.25tCK
ns
ns
ns
CLKOUT Low2, 3
IRQx1 or FI Setup before
CLKOUT Low (ADSP-2111)2, 3
37.2
IRQx1 or FI Hold after CLKOUT 19.2
High2, 3
Switching Characteristic:
tFOH FO Hold after CLKOUT High5
tFOD FO Delay from CLKOUT High
0
0
0
0
0
0
ns
ns
15
15
15
15
12
NOTES
1IRQx=IRQ0, IRQ1, and IRQ2.
2If IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise they will be recognized
during the following cycle. (Refer to the “Interrupt Controller” section in Chapter 3, Program Control, of the ADSP-2100 Family User’s Manual for further
information on interrupt servicing.)
3Edge-sensitive interrupts require pulse widths greater than 10 ns. Level-sensitive interrupts must be held low until serviced.
4tIFS (min) = 0.25tCK + 20 ns for ADSP-2101TG-50, ADSP-2101TG/883B-50, ADSP-2111TG-52, and ADSP-2111TG/883B-52 ( Extended Temperature Range
devices).
5tFOH (min) = –5 ns for ADSP-2111TG-52 and ADSP-2111TG/883B-52 (Extended Temperature Range devices).
CLKOUT
tFOD
tFOH
FLAG
OUTPUT(S)
tIFH
IRQx
FI
tIFS
Figure 30. Interrupts & Flags
REV. B
–31–
ADSP-21xx
TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)
BUS REQ UEST/GRANT
Frequency
13 MH z
13.824 MH z 16.67 MH z 20 MH z
25 MH z
D ependency
P aram eter
Min Max Min Max
Min Max Min Max Min Max Min
Max
Unit
Timing Requirement:
tBH BR Hold after CLKOUT High1
24.2
23.1
38.1
20
35
17.5
32.5
15
30
0.25tCK + 5
0.25tCK + 20
ns
ns
tBS BR Setup before CLKOUT Low1 39.2
Switching Characteristic:
tSD CLKOUT High to DMS,
PMS, BMS, RD, WR Disable
39.2
38.1
35
32.5
30
0.25tCK + 20 ns
tSDB DMS, PMS, BMS, RD, WR
Disable to BG Low
tSE BG High to DMS, PMS,
BMS, RD, WR Enable
tSEC DMS, PMS, BMS, RD, WR
Enable to CLKOUT High
0
0
0
0
5
0
0
0
ns
ns
ns
0
0
0
0
0
9.2
8.1
2.5
1.52
0.25tCK – 102
NOTES
1If BR meets the tBS and tBH setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR requires
a pulse width greater than 10 ns.
2For 25 MHz only the minimum frequency dependency formula for tSEC = (0.25tCK – 8.5).
Section 10.2.4, “Bus Request/Grant,” on page 212 of the ADSP-2100 Family User’s Manual (1st Edition, 1993) states that “When BR is recognized, the processor
responds immediately by asserting BG during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors: BG is asserted in the cycle after
BR is recognized. No external synchronization circuit is needed when BR is generated as an asynchronous signal.
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
tSD
tSEC
WR
BG
tSDB
tSE
Figure 31. Bus Request/Grant
–32–
REV. B
ADSP-21xx
TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)
MEMO RY READ
13 MH z
13.824 MH z 16.67 MH z
20 MH z
25 MH z
P aram eter
Min Max Min
Max Min
Max Min Max Min Max Unit
Timing Requirement:
tRDD RD Low to Data Valid
23.5
37.7
23.2
36.2
0
17
27
12
19.5
7
12
ns
ns
ns
tAA
A0–A13, PMS, DMS, BMS to Data Valid
tRDH Data Hold from RD High
0
0
0
0
Switching Characteristic:
tRP
RD Pulse Width
33.5
28.2
22
17
7.5
2.5
12
5
ns
ns
ns
tCRD CLKOUT High to RD Low
tASR A0–A13, PMS, DMS, BMS Setup before
RD Low
14.2 29.2 13.1 28.1 10
9.2
25
22.5
20
8.1
5
1.51
tRDA A0–A13, PMS, DMS, BMS Hold after RD
Deasserted
tRWR RD High to RD or WR Low
10.2
33.5
9.1
6
3.5
20
1
ns
ns
31.2
25
15
Frequency D ependency
(CLKIN ≤ 25 MH z)
Min
P aram eter
Max
Unit
Timing Requirement:
tRDD RD Low to Data Valid
0.5tCK – 13 + w
0.75tCK – 18 + w
ns
ns
tAA
A0–A13, PMS, DMS, BMS to Data Valid
tRDH Data Hold from RD High
0
Switching Characteristic:
tRP
RD Pulse Width
0.5tCK – 8 + w
0.25tCK – 5
ns
ns
tCRD CLKOUT High to RD Low
tASR A0–A13, PMS, DMS, BMS Setup before
RD Low
0.25tCK + 10
0.25tCK – 101
ns
tRDA A0–A13, PMS, DMS, BMS Hold after RD
Deasserted
tRWR RD High to RD or WR Low
0.25tCK – 9
0.5tCK – 5
ns
ns
NOT ES
1For 25 MHz only minimum frequency dependency formula for t ASR = (0.25tCK – 8.5).
w = wait states × tCK.
CLKOUT
A0 – A13
DMS, PMS
BMS
tRDA
RD
tASR
tCRD
tRP
tRWR
D
tRDD
tRDH
tAA
WR
Figure 32. Mem ory Read
–33–
REV. B
ADSP-21xx
TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)
MEMO RY WRITE
13 MH z
13.824 MH z 16.67 MH z
20 MH z
25 MH z
P aram eter
Min Max Min Max Min
Max Min Max Min Max Unit
Switching Characteristic:
tDW
tDH
tWP
Data Setup before WR High
Data Hold after WR High
WR Pulse Width
25.5
9.2
30.5
0
23.2
8.1
28.2
0
17
5
22
0
12
2.5
17
0
7
0
ns
ns
ns
ns
ns
12
0
tWDE WR Low to Data Enabled
tASW A0–A13, DMS, PMS Setup before
WR Low
tDDR Data Disable before WR or RD Low
tCWR CLKOUT High to WR Low
9.2
8.1
5
2.5
1.51
9.2
8.1
5
2.5
7.5
15.5
1.51
5
8
ns
ns
ns
14.2 29.2 13.1 28.1 10
25
22.5
20
tAW
A0–A13, DMS, PMS, Setup before WR
Deasserted
35.7
10.2
33.5
32.2
9.1
23
6
tWRA A0–A13, DMS, PMS Hold after WR
Deasserted
tWWR WR High to RD or WR Low
3.5
20
1
ns
ns
31.2
25
15
Frequency D ependency
(CLKIN ≤ 25 MH z)
P aram eter
Min
Max
Unit
Switching Characteristic:
tDW Data Setup before WR High
0.5tCK – 13 + w
0.25tCK – 10
0.5tCK – 8 + w
0
ns
ns
ns
tDH
tWP
Data Hold after WR High
WR Pulse Width
tWDE WR Low to Data Enabled
tASW A0–A13, DMS, PMS Setup before WR Low
tDDR Data Disable before WR or RD Low
tCWR CLKOUT High to WR Low
0.25tCK – 101
0.25tCK – 101
0.25tCK – 5
ns
ns
ns
0.25tCK + 10
tAW
A0–A13, DMS, PMS, Setup before WR
Deasserted
0.75tCK – 22 + w
ns
tWRA A0–A13, DMS, PMS Hold after WR
Deasserted
tWWR WR High to RD or WR Low
0.25tCK – 9
0.5tCK – 5
ns
ns
NOT ES
1For 25 MHz only the minimum frequency dependency formula for t ASW and tDDR = (0.25tCK – 8.5).
w = wait states × tCK
.
CLKOUT
A0 – A13
DMS, PMS
tWRA
WR
tASW
tWP
tWWR
tAW
tDH
tDDR
tCWR
D
tDW
tWDE
RD
Figure 33. Mem ory Write
–34–
REV. B
ADSP-21xx
TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)
SERIAL P O RTS
Frequency
D ependency
Min
12.5 MH z
Min Max
13.0 MH z
Min Max
13.824 MH z*
Min Max
P aram eter
Max
Unit
Timing Requirement:
tSCK
tSCS
tSCH
tSCP
SCLK Period
80
8
10
30
76.9
8
10
28
72.3
8
10
28
ns
ns
ns
ns
DR/T FS/RFS Setup before SCLK Low
DR/T FS/RFS Hold after SCLK Low
SCLKIN Width
Switching Characteristic:
tCC
CLKOUT High to SCLKOUT
20
0
35
20
20
19.2 34.2
0
18.1 33.1
0
0.25tCK 0.25tCK + 15ns
tSCDE SCLK High to DT Enable
tSCDV SCLK High to DT Valid
tRH
tRD
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
20
20
T FS/RFSOUT Hold after SCLK High
T FS/RFSOUT Delay from SCLK High
0
0
0
tSCDH DT Hold after SCLK High
tT DE T FS (Alt) to DT Enable
tT DV T FS (Alt) to DT Valid
tSCDD SCLK High to DT Disable
tRDV RFS (Multichannel, Frame Delay Zero)
to DT Valid
0
0
0
0
0
0
18
25
20
18
25
20
18
25
20
*Maximum serial port operating frequency is 13.824 MHz for all processor speed grades except the 12.5 MHz ADSP-2101 and 13.0 MHz ADSP-2111.
CLKOUT
tCC
tCC
tSCK
SCLK
tSCP
tSCS
tSCH
tSCP
DR
RFS
IN
TFS
IN
tRD
tRH
RFS
TFS
OUT
OUT
tSCDD
tSCDV
tSCDE
tSCDH
DT
tTDE
tTDV
TFS
( ALTERNATE
FRAME MODE )
tRDV
RFS
( MULTICHANNEL MODE,
FRAME DELAY 0 {MFD = 0} )
Figure 34. Serial Ports
REV. B
–35–
ADSP-21xx
TIMING PARAMETERS (ADSP-2111)
H O ST INTERFACE P O RT
Separ ate D ata & Addr ess (H MD 1 = 0 )
Read Str obe & Wr ite Str obe (H MD 0 = 0)
13.0 MH z
Min Max
16.67 MH z
Min Max
20 MH z
Min Max
No Frequency
Dependency
P aram eter
Unit
Timing Requirement:
tHSU HA2-0 Setup before Start of Write or Read1, 2
tHDSU Data Setup before End of Write3
tHWDH Data Hold after End of Write3
8
8
3
3
8
8
3
3
8
8
3
3
ns
ns
ns
ns
ns
tHH
HA2-0 Hold after End of Write or Read3, 4
tHRWP Read or Write Pulse Width5
30
30
30
Switching Characteristic:
tHSHK HACK Low after Start of Write or Read1, 2
tHKH HACK Hold after End of Write or Read3, 4
tHDE Data Enabled after Start of Read2
tHDD Data Valid after Start of Read2
tHRDH Data Hold after End of Read4
tHRDD Data Disabled after End of Read4
0
0
0
20
20
0
0
0
20
20
0
0
0
20
20
ns
ns
ns
ns
ns
ns
23
10
23
10
23
10
0
0
0
NOTES
1Start of Write = HWR Low and HSEL Low.
2Start of Read = HRD Low and HSEL Low.
3End of Write = HWR High or HSEL High.
4End of Read = HRD High or HSEL High.
5Read Pulse Width = HRD Low and HSEL Low, Write Pulse Width = HWR Low and HSEL Low.
–36–
REV. B
ADSP-21xx
HA2–0
ADDRESS
tHRWP
HSEL
tHSU
Host Write Cycle
HWR
HACK
tHH
tHSHK
tHKH
DATA
HD15–0
tHWDH
tHDSU
ADDRESS
tHRWP
HA2–0
HSEL
tHSU
HRD
tHH
Host Read Cycle
HACK
tHKH
tHSHK
DATA
HD15–0
tHDE
tHDD
tHRDH
tHRDD
Figure 35. Host Interface Port (HMD1 = 0, HMD0 = 0)
REV. B
–37–
ADSP-21xx
TIMING PARAMETERS (ADSP-2111)
H O ST INTERFACE P O RT
Separ ate D ata & Addr ess (H MD 1 = 0)
Read/Wr ite Str obe & D ata Str obe (H MD 0 = 1)
13.0 MH z
Min Max
16.67 MH z
Min Max
20 MH z
Min Max
No Frequency
Dependency
P aram eter
Unit
Timing Requirement:
tHSU HA2-0, HRW Setup before Start of Write or Read1
tHDSU Data Setup before End of Write2
tHWDH Data Hold after End of Write2
8
8
3
3
8
8
3
3
8
8
3
3
ns
ns
ns
ns
ns
tHH
HA2-0, HRW Hold after End of Write or Read2
tHRWP Read or Write Pulse Width3
30
30
30
Switching Characteristic:
tHSHK HACK Low after Start of Write or Read1
tHKH HACK Hold after End of Write or Read2
tHDE Data Enabled after Start of Read1
tHDD Data Valid after Start of Read1
tHRDH Data Hold after End of Read2
tHRDD Data Disabled after End of Read2
0
0
0
20
20
0
0
0
20
20
0
0
0
20
20
ns
ns
ns
ns
ns
ns
23
10
23
10
23
10
0
0
0
NOTES
1Start of Write or Read = HDS Low and HSEL Low.
2End of Write or Read = HDS High or HSEL High.
3Read or Write Pulse Width = HDS Low and HSEL Low.
–38–
REV. B
ADSP-21xx
ADDRESS
tHRWP
HA2–0
HSEL
tHSU
HRW
Host Write Cycle
HDS
tHH
HACK
tHSHK
tHKH
DATA
HD15–0
tHWDH
tHDSU
ADDRESS
tHRWP
HA2–0
HSEL
tHSU
HRW
Host Read Cycle
tHH
HDS
HACK
tHKH
tHSHK
DATA
HD15–0
tHDE
tHDD
tHRDH
tHRDD
Figure 36. Host Interface Port (HMD1 = 0, HMD0 =1)
REV. B
–39–
ADSP-21xx
TIMING PARAMETERS (ADSP-2111)
H O ST INTERFACE P O RT
Multiplexed D ata & Addr ess (H MD 1 = 1)
Read Str obe & Wr ite Str obe (H MD 0 = 0)
13.0 MH z
Min Max
16.67 MH z
Min Max
20 MH z
Min Max
No Frequency
Dependency
P aram eter
Unit
Timing Requirement:
tHALP ALE Pulse Width
15
5
2
15
8
3
15
5
2
15
8
3
15
5
2
15
8
3
ns
ns
ns
ns
ns
ns
ns
tHASU HAD15-0 Address Setup before ALE Low
tHAH HAD15-0 Address Hold after ALE Low
tHALS Start of Write or Read after ALE Low1, 2
tHDSU HAD15-0 Data Setup before End of Write3
tHWDH HAD15-0 Data Hold after End of Write3
tHRWP Read or Write Pulse Width5
30
30
30
Switching Characteristic:
tHSHK HACK Low after Start of Write or Read1, 2
tHKH HACK Hold after End of Write or Read3, 4
tHDE HAD15-0 Data Enabled after Start of Read2
tHDD HAD15-0 Data Valid after Start of Read2
tHRDH HAD15-0 Data Hold after End of Read4
tHRDD HAD15-0 Data Disabled after End of Read4
0
0
0
20
20
0
0
0
20
20
0
0
0
20
20
ns
ns
ns
ns
ns
ns
23
10
23
10
23
10
0
0
0
NOTES
1Start of Write = HWR Low and HSEL Low.
2Start of Read = HRD Low and HSEL Low.
3End of Write = HWR High or HSEL High.
4End of Read = HRD High or HSEL High.
5Read Pulse Width = HRD Low and HSEL Low, Write Pulse Width = HWR Low and HSEL Low.
–40–
REV. B
ADSP-21xx
ALE
tHALP
tHRWP
HSEL
HWR
tHALS
Host Write Cycle
tHKH
tHSHK
HACK
tHASU
tHAH
ADDRESS
DATA
HD15–0
tHDSU
tHWDH
ALE
tHALP
tHRWP
HSEL
HRD
tHALS
Host Read Cycle
tHKH
tHSHK
tHDE
tHASU tHAH
ADDRESS
HACK
HAD15–0
DATA
tHRDH
tHRDD
tHDD
Figure 37. Host Interface Port (HMD1 = 1, HMD0 = 0)
REV. B
–41–
ADSP-21xx
TIMING PARAMETERS (ADSP-2111)
H O ST INTERFACE P O RT
Multiplexed D ata & Addr ess (H MD 1 = 1)
Read/Wr ite Str obe & D ata Str obe (H MD 0 = 1 )
13.0 MH z
Min Max
16.67 MH z
Min Max
20 MH z
Min Max
No Frequency
Dependency
P aram eter
Unit
Timing Requirement:
tHALP ALE Pulse Width
15
5
2
15
8
5
3
3
30
15
5
2
15
8
5
3
3
30
15
5
2
15
8
5
3
3
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHASU HAD15-0 Address Setup before ALE Low
tHAH HAD15-0 Address Hold after ALE Low
tHALS Start of Write or Read after ALE Low1
tHSU HRW Setup before Start of Write or Read1
tHDSU HAD15-0 Data Setup before End of Write2
tHWDH HAD15-0 Data Hold after End of Write2
tHH
HRW Hold after End of Write or Read2
tHRWP Read or Write Pulse Width3
Switching Characteristic:
tHSHK HACK Low after Start of Write or Read1
tHKH HACK Hold after End of Write or Read2
tHDE HAD15-0 Data Enabled after Start of Read1
tHDD HAD15-0 Data Valid after Start of Read1
tHRDH HAD15-0 Data Hold after End of Read2
tHRDD HAD15-0 Data Disabled after End of Read2
0
0
0
20
20
0
0
0
20
20
0
0
0
20
20
ns
ns
ns
ns
ns
ns
23
10
23
10
23
10
0
0
0
NOTES
1Start of Write or Read = HDS Low and HSEL Low.
2End of Write or Read = HDS High or HSEL High.
3Read or Write Pulse Width = HDS Low and HSEL Low.
–42–
REV. B
ADSP-21xx
ALE
tHALP
tHRWP
HSEL
tHH
tHALS
HRW
tHSU
HDS
Host Write Cycle
tHSHK
tHKH
tHASU
tHAH
HACK
HD15–0
ADDRESS
DATA
tHDSU
tHWDH
ALE
tHALP
tHALS
tHRWP
HSEL
tHH
HRW
HDS
tHSU
Host Read Cycle
tHKH
tHSHK
tHASU
HACK
HD15–0
tHAH
tHDE
ADDRESS
DATA
tHRDH
tHDD
tHRDD
Figure 38. Host Interface Port (HMD1 = 1, HMD0 = 1)
REV. B
–43–
ADSP-21xx
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. T iming requirements guarantee that the
processor operates correctly with other devices.
TIMING PARAMETERS (ADSP-2103/2162/2164)
GENERAL NO TES
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add parameters to derive longer times.
MEMO RY REQ UIREMENTS
T he table below shows common memory device specifications
and the corresponding ADSP-21xx timing parameters, for your
convenience.
TIMING NO TES
Switching characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
AD SP -21xx
Mem ory Specification
Tim ing P aram eter
Tim ing P aram eter D efinition
Address Setup to Write Start
Address Setup to Write End
Address Hold Time
Data Setup Time
tASW
tAW
tWRA
tDW
tDH
A0–A13, DMS, PMS Setup before WR Low
A0–A13, DMS, PMS Setup before WR Deasserted
A0–A13, DMS, PMS Hold after WR Deasserted
Data Setup before WR High
Data Hold Time
Data Hold after WR High
OE to Data Valid
Address Access Time
tRDD
tAA
RD Low to Data Valid
A0–A13, DMS, PMS, BMS to Data Valid
–44–
REV. B
ADSP-21xx
TIMING PARAMETERS (ADSP-2103/2162/2164)
CLO CK SIGNALS & RESET
Frequency
D ependency
Min
10.24 MH z
P aram eter
Min
Max
Max
Unit
Timing Requirement:
tCK
CLKIN Period
97.6
20
20
150
ns
ns
ns
ns
tCKL
tCKH
tRSP
CLKIN Width Low
CLKIN Width High
RESET Width Low
1
488
5tCK
Switching Characteristic:
tCPL
tCPH
tCKOH
CLKOUT Width Low
CLKOUT Width High
CLKIN High to CLKOUT High
38.8
38.8
0
0.5tCK – 10
0.5tCK – 10
ns
ns
ns
20
NOTES
1Applies after powerup sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator startup time).
tCK
tCKH
CLKIN
tCKL
tCKOH
tCPH
CLKOUT
tCPL
Figure 39. Clock Signals
REV. B
–45–
ADSP-21xx
TIMING PARAMETERS (ADSP-2103/2162/2164)
INTERRUP TS & FLAGS
Frequency
D ependency
Min
10.24 MH z
P aram eter
Min
Max
Max
Unit
Timing Requirement:
tIFS
tIFH
IRQx1 or FI Setup before CLKOUT Low2, 3
44.4
24.4
0.25tCK + 20
0.25tCK
ns
ns
IRQx1 or FI Hold after CLKOUT High2, 3
Switching Characteristic:
tFOH FO Hold after CLKOUT High
tFOD FO Delay from CLKOUT High
0
ns
ns
15
NOTES
1IRQx=IRQ0, IRQ1, and IRQ2.
2If IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise they will be recognized during the
following cycle. (Refer to the “Interrupt Controller” section in Chapter 3, Program Control, of the ADSP-2100 Family User’s Manual for further information on
interrupt servicing.)
3Edge-sensitive interrupts require pulse widths greater than 10 ns. Level-sensitive interrupts must be held low until serviced.
CLKOUT
tFOD
tFOH
FLAG
OUTPUT(S)
tIFH
IRQx
FI
tIFS
Figure 40. Interrupts & Flags
–46–
REV. B
ADSP-21xx
TIMING PARAMETERS (ADSP-2103/2162/2164)
BUS REQ UEST/GRANT
Frequency
D ependency
Min
10.24 MH z
P aram eter
Min
Max
Max
Unit
Timing Requirement:
tBH
tBS
BR Hold after CLKOUT High1
29.4
44.4
0.25tCK + 5
0.25tCK + 20
ns
ns
BR Setup before CLKOUT Low1
Switching Characteristic:
tSD
tSDB
tSE
CLKOUT High to DMS, PMS, BMS, RD, WR Disable
DMS, PMS, BMS, RD, WR Disable to BG Low
BG High to DMS, PMS, BMS, RD, WR Enable
44.4
0.25tCK + 20
ns
ns
ns
ns
0
0
tSEC
DMS, PMS, BMS, RD, WR Enable to CLKOUT High 14.4
0.25tCK – 10
NOTES
1If BR meets the tBS and tBH setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR
requires a pulse width greater than 10 ns.
Section 10.2.4, “Bus Request/Grant,” of the ADSP-2100 Family User’s Manual (1st Edition, ©1993) states that “When BR is recognized, the processor
responds immediately by asserting BG during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors: BG is asserted in the
cycle after BR is recognized. No external synchronization circuit is needed when BR is generated as an asynchronous signal.
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
tSD
tSEC
WR
BG
tSDB
tSE
Figure 41. Bus Request/Grant
REV. B
–47–
ADSP-21xx
TIMING PARAMETERS (ADSP-2103/2162/2164)
MEMO RY READ
Frequency
D ependency
Min
10.24 MH z
P aram eter
Min
Max
Max
Unit
Timing Requirement:
tRDD
tAA
tRDH
RD Low to Data Valid
A0–A13, PMS, DMS, BMS to Data Valid
Data Hold from RD High
33.8
49.2
0.5tCK – 15 + w
0.75tCK – 24 + w
ns
ns
ns
0
Switching Characteristic:
tRP
RD Pulse Width
CLKOUT High to RD Low
A0–A13, PMS, DMS, BMS Setup before RD Low
A0–A13, PMS, DMS, BMS Hold after RD Deasserted
RD High to RD or WR Low
43.8
19.4
12.4
14.4
38.8
0.5tCK – 5 + w
0.25tCK – 5
0.25tCK – 12
0.25tCK – 10
0.5tCK – 10
ns
ns
ns
ns
ns
tCRD
tASR
tRDA
tRWR
34.4
0.25tCK + 10
w = wait states × tCK.
CLKOUT
A0 – A13
DMS, PMS
BMS
tRDA
RD
tASR
tCRD
tRP
tRWR
D
tRDD
tRDH
tAA
WR
Figure 42. Mem ory Read
–48–
REV. B
ADSP-21xx
TIMING PARAMETERS (ADSP-2103/2162/2164)
MEMO RY WRITE
Frequency
D ependency
Min
10.24 MH z
P aram eter
Min
Max
Max
Unit
Switching Characteristic:
tDW
tDH
tWP
tWDE
tASW
tDDR
tCWR
tAW
Data Setup before WR High
Data Hold after WR High
WR Pulse Width
WR Low to Data Enabled
A0–A13, DMS, PMS Setup before WR Low
Data Disable before WR or RD Low
CLKOUT High to WR Low
A0–A13, DMS, PMS, Setup before WR Deasserted
A0–A13, DMS, PMS Hold After WR Deasserted
WR High to RD or WR Low
38.8
14.4
43.8
0
12.4
14.4
19.4
58.2
14.4
38.8
0.5tCK – 10 + w
0.25tCK – 10
0.5tCK – 5 + w
ns
ns
ns
0.25tCK – 12
0.25tCK – 10
0.25tCK – 5
0.75tCK – 15 + w
0.25tCK – 10
0.5tCK – 10
ns
ns
ns
ns
ns
ns
34.4
0.25tCK + 10
tWRA
tWWR
w = wait states × tCK.
CLKOUT
A0 – A13
DMS, PMS
tWRA
WR
tASW
tWP
tWWR
tAW
tDH
tDDR
tCWR
D
tDW
tWDE
RD
Figure 43. Mem ory Write
REV. B
–49–
ADSP-21xx
TIMING PARAMETERS (ADSP-2103/2162/2164)
SERIAL P O RTS
Frequency
D ependency
Min
10.24 MH z
P aram eter
Min
Max
Max
Unit
Timing Requirement:
tSCK
tSCS
tSCH
tSCP
SCLK Period
97.6
8
10
28
tCK
ns
ns
ns
ns
DR/T FS/RFS Setup before SCLK Low
DR/T FS/RFS Hold after SCLK Low
SCLKin Width
Switching Characteristic:
tCC
CLKOUT High to SCLKout
SCLK High to DT Enable
SCLK High to DT Valid
T FS/RFSout Hold after SCLK High
T FS/RFSout Delay from SCLK High
DT Hold after SCLK High
T FS (alt) to DT Enable
24.4
0
39.4
28
0.25tCK
0.25tCK + 15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCDE
tSCDV
tRH
0
tRD
28
tSCDH
tT DE
tT DV
tSCDD
tRDV
0
0
T FS (alt) to DT Valid
18
30
20
SCLK High to DT Disable
RFS (Multichannel, Frame Delay Zero)
to DT Valid
CLKOUT
SCLK
tCC
tCC
tSCK
tSCP
tSCS
tSCH
tSCP
DR
RFSIN
TFSIN
tRD
tRH
RFSOUT
TFSOUT
tSCDD
tSCDV
tSCDE
tSCDH
DT
tTDE
tTDV
TFS
( ALTERNATE
FRAME MODE )
tRDV
RFS
( MULTICHANNEL MODE,
FRAME DELAY 0 {MFD = 0} )
Figure 44. Serial Ports
–50–
REV. B
ADSP-21xx
P IN CO NFIGURATIO NS
68-P in P GA
A
B
C
D
E
F
G
H
J
K
L
L
K
J
H
G
F
E
D
C
B
A
1
1
BR
GND
BR
1
2
A3
A1
RESET
VDD
D22
D20
1
2
D20
D22
VDD
RESET
A1
A3
VDD
GND
VDD
2
2
IRQ2
D18
D16
D14
D12
D11
D9
IRQ2
A5
GND
A8
A4
A2
A0
D19
D17
D15
D13
GND
D10
D8
MMAP
A0
A2
A4
A5
GND
A8
A6
A7
MMAP
D23
D21
D21
D23
A6
A7
D19
D17
D15
D13
GND
D10
D8
D18
D16
D14
D12
D11
D9
INDEX
(NC)
INDEX
(NC)
3
3
3
3
4
4
4
4
A9
A9
PGA PACKAGE
ADSP-2101
PGA PACKAGE
ADSP-2101
5
5
5
A10
5
A10
A11
A13
DMS
BG
A11
A13
DMS
BG
6
6
A12
A12
6
6
7
7
7
PMS
BMS
XTAL
7
PMS
BMS
XTAL
TOP VIEW
(PINS DOWN)
BOTTOM VIEW
(PINS UP)
D7
8
8
8
8
D7
CLK
IN
CLK
IN
D5
9
9
D6
9
9
D6
D5
IRQ1
(TFS1)
IRQ1
(TFS1)
FI
(DR1)
CLK
OUT
CLK
OUT
FI
(DR1)
10
11
D3
10
11
D4
SCLK0 GND
TFS0
10
11
RD
10
11
RD
TFS0
GND SCLK0
VDD
D1
D4
D1
VDD
D3
IRQ0
(RFS1)
IRQ0
(RFS1)
FO
(DT1)
FO
(DT1)
D2
B
DR0
G
RFS0
H
DT0
J
WR
D2
B
WR
DT0
J
RFS0
H
DR0
G
SCLK1
D
D0
C
D0
C
SCLK1
D
L
K
F
E
A
A
E
F
K
L
NC = NO CONNECT
P GA
P in
P GA
P in
P GA
P in
P GA
P in
Num ber Nam e
Num ber Nam e
Num ber Nam e
Num ber Nam e
B1
B2
C1
C2
D1
D2
E1
E2
F1
F2
G1
G2
H1
H2
J1
GND
D19
D20
D21
D22
D23
VDD
MMAP
BR
IRQ2
RESET
A0
A1
A2
A3
K11
K10
J11
WR
RD
A10
B10
A9
B9
A8
B8
A7
B7
A6
B6
A5
B5
A4
B4
A3
B3
A2
D3
D4
D5
D6
D7
D8
D9
D10
D11
GND
D12
D13
D14
D15
D16
D17
D18
L2
K2
L3
K3
L4
K4
L5
K5
L6
K6
L7
K7
L8
K8
L9
K9
L10
C3
A5
A6
GND
A7
A8
DT 0
T FS0
RFS0
GND
DR0
SCLK0
FO
IRQ1 (TFS1)
IRQ0 (RFS1)
FI
SCLK1
VDD
D0
D1
D2
J10
H11
H10
G11
G10
F11
F10
E11
E10
D11
D10
C11
C10
B11
A9
A10
A11
A12
A13
PMS
DMS
BMS
BG
XT AL
CLKIN
CLKOUT
Index (NC)
(DT1)
(DR1)
J2
K1
A4
VDD
REV. B
–51–
ADSP-21xx
P IN CO NFIGURATIO NS
68-Lead P LCC
PIN 1
IDENTIFIER
GND
D19
D20
D21
D22
D23
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
D2
D1
D0
V
DD
SCLK1
PLCC PACKAGE
FI (DR1)
V
IRQ0 (RFS1)
DD
ADSP-2101
ADSP-2103
MMAP
BR
IRQ1 (TFS1)
ADSP-2105
FO (DT1)
ADSP-2115
IRQ2
RESET
A0
SCLK0 (NC on ADSP-2105)
DR0 (NC on ADSP-2105)
GND
ADSP-2161/62/63/64
TOP VIEW
(PINS DOWN)
A1
RFS0 (NC on ADSP-2105)
TFS0 (NC on ADSP-2105)
DT0 (NC on ADSP-2105)
RD
A2
A3
A4
V
WR
DD
NC = NO CONNECT
P LCC
P in
P LCC
P in
P LCC
P in
P LCC
P in
Num ber Nam e
Num ber Nam e
Num ber Nam e
Num ber Nam e
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
A12
A13
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
FO
(DT1)
1
2
3
4
5
6
7
8
D11
GND
D12
D13
D14
D15
D16
D17
D18
GND
D19
D20
D21
D22
D23
VDD
18
BR
IRQ1 (TFS1)
IRQ0 (RFS1)
FI
SCLK1
VDD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
IRQ2
RESET
A0
A1
A2
A3
A4
VDD
A5
A6
GND
A7
A8
A9
A10
A11
PMS
DMS
BMS
BG
XT AL
CLKIN
CLKOUT
WR
(DR1)
9
10
11
12
13
14
15
16
17
RD
DT 0
(NC on ADSP-2105)
T FS0 (NC on ADSP-2105)
RFS0 (NC on ADSP-2105)
GND
DR0
(NC on ADSP-2105)
SCLK0 (NC on ADSP-2105)
MMAP
–52–
REV. B
ADSP-21xx
P IN CO NFIGURATIO NS
80-Lead P Q FP
80-Lead TQ FP
A5
A6
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
D18
D17
D16
D15
D14
D13
D12
GND
GND
D11
D10
D9
2
GND
GND
A7
3
4
5
A8
6
PQFP PACKAGE
A9
7
A10
A11
A12
A13
PMS
DMS
BMS
BG
8
ADSP-2101
ADSP-2103
ADSP-2115
9
10
11
12
13
14
15
16
17
18
19
20
ADSP-2161/62/63/64
D8
TOP VIEW
(PINS DOWN)
D7
D6
XTAL
CLKIN
NC
D5
D4
NC
NC
NC
NC
NC
D(1T)
D(1R)
T(SF1)
R(SF1)
NC = NO CONNECT
P QFP /
TQFP
Num ber Nam e
P QFP /
TQFP
Num ber Nam e
P QFP /
TQFP
Num ber Nam e
P QFP /
TQFP
Num ber Nam e
P in
P in
P in
P in
1
2
3
4
5
6
7
8
A5
A6
GND
GND
A7
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
CLKOUT
WR
RD
DT 0
T FS0
RFS0
GND
GND
DR0
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
NC
NC
NC
D4
D5
D6
D7
D8
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
GND
GND
D19
D20
D21
D22
D23
VDD
VDD
MMAP
BR
IRQ2
RESET
A0
A1
A2
A3
A4
VDD
VDD
A8
A9
A10
A11
A12
A13
PMS
DMS
BMS
BG
XT AL
CLKIN
NC
NC
NC
9
D9
10
11
12
13
14
15
16
17
18
19
20
SCLK0
D10
D11
GND
GND
D12
D13
D14
D15
D16
D17
D18
FO
(DT1)
IRQ1 (TFS1)
IRQ0 (RFS1)
FI
(DR1)
SCLK1
VDD
D0
D1
D2
D3
REV. B
–53–
ADSP-21xx
P IN CO NFIGURATIO NS
100-P in P GA
13
D23
12
D21
11
D20
D22
10
D18
D19
9
8
7
6
D10
D9
5
4
3
2
1
1
2
3
4
5
6
7
8
9
10
11
12
13
VDD
D1
D3
D5
D7
D10
D12
D13
D16
D18
D20
D21
D23
N
M
L
D16
D17
D13
D14
D15
D12
D11
GND
D7
D6
D5
D4
D3
D2
D1
D0
FL2
VDD
FL1
FL0
N
M
L
N
M
L
N
M
L
FL1
FL0
D0
D2
D4
D6
D9
D8
D11
D14
D15
D17
D19
D22
GND
MMAP
BR
MMAP
BR
GND
RESET
VDD
GND
D8
FL2
RESET
VDD
F1
(DR1)
F1
(DR1)
PMS
SCLK1
PMS
BMS
BG
SCLK1
K
J
K
J
K
J
K
J
IRQ0
(RFS1)
IRQ1
(TFS1)
IRQ1
(TFS1)
IRQ0
(RFS1)
BMS
BG
DMS
WR
A0
DMS
WR
A0
PGA PACKAGE
ADSP-2111
PGA PACKAGE
ADSP-2111
FO
(DT1)
FO
(DT1)
GND
TFS0
SCLK0
RD
A1
RD
A1
GND SCLK0
H
G
F
H
G
F
H
G
F
H
G
F
A2
A2
RFSO TFS0
CLK
DR0
DT0
DR0
DT0
RFSO
HACK
CLK
OUT
A5
A4
A3
A3
A4
A5
HACK
OUT
TOP VIEW
(PINS DOWN)
BOTTOM VIEW
(PINS UP)
IRQ2 BMODE
HMD0 HMD1
A6
GND
A7
GND
A6
BMODE
IRQ2
E
D
C
B
A
E
D
C
B
A
E
D
C
B
A
E
D
C
B
A
A8
A7
A9
A8
A11
A12
HMD1 HMD0
HRD/
INDEX
PIN
(NC)
INDEX
PIN
(NC)
HRD/
HSIZE
XTAL
HD7
VDD
HD6
HD9
A11
A9
HD9
HD8
HD7
VDD
XTAL
HD4
HSIZE
HRW
HRW
HWR/
HSEL
HDS
HWR/
HSEL
HA1
HD0
HD1
HD2
HD3
HD4
HD5
HD8
HD11 HD13 HD15
A12
A13
A10
A10
HD15 HD13
HD14 HD12
HD11
HD3
HD1
HA1
HDS
HA2/
HA0
CLK
IN
HA2/
HA0
ALE
CLK
IN
V
GND
HD10
HD12
HD14
VDD
A13
HD10
GND
HD6
HD5
HD2
HD0
DD
ALE
13
12
11
10
9
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
9
10
11
12
13
NC = NO CONNECT
P GA
P in
P GA
P in
P GA
P in
P GA
P in
Num ber Nam e
Num ber Nam e
Num ber Nam e
Num ber Nam e
N13
N12
M13
M12
L13
L12
K13
K12
J13
D23
D21
MMAP
GND
BR
RESET
PMS
VDD
BMS
DMS
BG
WR
RD
A2
A0
A1
A3
A4
A5
GND
A6
A7
A8
A9
A11
C3
A2
A1
B1
B2
C1
C2
D1
D2
E1
E2
F1
F2
F3
G1
G2
G3
H1
H2
H3
J1
Index (NC)
HA2/ALE
HA0
HWR/HDS
HSEL
HSIZE
HRD/HRW
HMD0
HMD1
IRQ2
BMODE
DT0
CLKOUT
HACK
DR0
B13
A13
A12
B12
A11
B11
A10
B10
A9
B9
A8
B8
C8
A7
B7
C7
A6
B6
C6
A5
B5
A4
B4
A3
A10
VDD
A13
A12
L2
FL2
FL1
VDD
D1
D0
D3
D2
D5
D4
D7
M1
N1
N2
M2
N3
M3
N4
M4
N5
M5
N6
M6
L6
N7
M7
L7
N8
M8
L8
HD14
HD15
HD12
HD13
HD10
HD11
GND
HD8
HD9
HD6
VDD
HD7
HD5
HD4
XT AL
CLKIN
HD3
HD2
HD1
HD0
HA1
J12
H13
H12
H11
G13
G12
G11
F13
F12
F11
E13
E12
D13
D12
C13
C12
D6
D10
D9
D8
D12
D11
GND
D13
D14
D15
D16
D17
D18
D19
D20
D22
T FS0
RFS0
SCLK0
GND
FO
(DT1)
IRQ1 (TFS1)
IRQ0 (RFS1)
N9
M9
N10
M10
N11
M11
J2
K1
K2
L1
FI
(DR1)
SCLK1
FL0
B3
–54–
REV. B
ADSP-21xx
P IN CO NFIGURATIO NS
100-Lead Bum per ed P Q FP
GND
MMAP
RESET
BR
VDD
PMS
DMS
BMS
RD
WR
BG
A0
A1
A2
A3
A4
A5
GND
A6
A7
A8
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
VDD
FL2
FL1
FL0
SCLK1
FI (DR1)
IRQ0 (RFS1)
IRQ1 (TFS1)
FO (DT1)
GND
SCLK0
DR0
RFS0
TFS0
DT0
CLKOUT
HACK
IRQ2
BMODE
HMD0
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
BEVELED EDGE
PQFP PACKAGE
ADSP-2111
TOP VIEW
(PINS DOWN)
HMD1
A9
HSIZE
HRD/HRW
HWR/HDS
HSEL
A10
A11
VDD
NOTE: PIN 1 IS LOCATED AT THE CENTER OF THE BEVELED-EDGE SIDE OF THE PACKAGE.
P QFP
P in
P QFP
P in
P QFP
P in
P QFP
P in
Num ber Nam e
Num ber Nam e
Num ber Nam e
Num ber Nam e
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
A1
A2
A3
A4
A5
GND
A6
A7
A8
1
2
3
4
5
6
7
8
GND
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
GND
MMAP
RESET
BR
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
HD7
HD6
HD5
HD4
XT AL
CLKIN
HD3
HD2
HD1
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
RFS0
DR0
SCLK0
GND
FO
(DT1)
IRQ1 (TFS1)
IRQ0 (RFS1)
FI
SCLK1
FL0
FL1
FL2
VDD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
(DR1)
9
A9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
HD0
HA2/ALE
HA1
A10
A11
VDD
HA0
A12
A13
HD15
HD14
HD13
HD12
HD11
HD10
HD9
HD8
GND
VDD
HSEL
HWR/HDS
HRD/HRW
HSIZE
HMD1
HMD0
BMODE
IRQ2
VDD
PMS
DMS
BMS
RD
WR
BG
HACK
CLKOUT
DT 0
A0
T FS0
REV. B
–55–
ADSP-21xx
O UTLINE D IMENSIO NS
AD SP -2101
68-P in Gr id Ar r ay (P GA)
PGA LOCATION A1 QUADRANT MARKING
e
e
1
2
1
2
3
4
GUIDE
PIN ONLY
5
6
7
8
e
1
e
D
2
TOP VIEW
9
10
11
L
K J
H
G
F
E
D C
B A
D
A
1
A
SEATING
PLANE
L
3
φ
b
e
φ
b1
INCHES
MILLIMETERS
SYMBOL MIN
TYP
MAX
0.164
MIN
3.12
TYP
MAX
4.17
A
0.123
A1
φb
φb1
D
0.50
1.27
0.46
1.27
0.016 0.018 0.020
0.050
1.086
0.988
0.788
1.110
1.012
0.812
27.58
25.10
20.02
28.19
25.70
20.62
e1
e2
e
0.100
0.180
2.54
4.57
L3
–56–
REV. B
ADSP-21xx
O UTLINE D IMENSIO NS
AD SP -21xx
68-Lead P lastic Leaded Chip Car r ier (P LCC)
9
61
e
PIN 1 IDENTIFIER
D
2
b
BOTTOM VIEW
(PINS UP)
TOP VIEW
(PINS DOWN)
b
1
A
D
1
1
D
A
INCHES
TYP
MILLIMETERS
SYMBOL MIN
MAX
MIN
TYP
MAX
A
A1
b
0.169 0.172 0.175
0.104
4.29 14.37
12.64
4.45
0.017 0.018 0.019
0.027 0.028 0.029
0.985 0.990 0.995
0.950 0.952 0.954
0.895 0.910 0.925
0.050
0.43 10.46
0.69 10.71
0.48
0.74
b1
D
D1
D2
e
25.02 25.15 25.27
24.13 24.18 24.23
22.73 23.11 23.50
11.27
0.004
10.10
REV. B
–57–
ADSP-21xx
O UTLINE D IMENSIO NS
AD SP -21xx
80-Lead Metr ic P lastic Q uad Flatpack (P Q FP )
80-Lead Metr ic Thin Q uad Flatpack (TQ FP )
D
SEATING
PLANE
D
1
A
D
3
L
80
1
61
60
TOP VIEW
(PINS DOWN)
E
E
E
1
3
20
21
41
40
A2
A1
B
e
P QFP
TQFP
MILLIMETERS
TYP MAX
INCHES
TYP
MILLIMETERS
INCHES
SYMBOL MIN
A
MIN
MAX
0.096
MIN TYP
MAX
1.60
0.15
1.45
MIN
TYP MAX
2.45
0.063
0.006
A1
0.25
1.90
0.010
0.05
0.002
A2
2.00
2.10
0.075 0.079 0.083
0.667 0.678 0.690
0.547 0.551 0.555
0.486 0.490
1.35 1.40
0.053 0.055 0.057
0.620 0.630 0.640
0.549 0.551 0.553
0.486 0.490
D, E
D1, E1
D3, E3
L
16.95 17.20 17.45
13.90 14.00 14.10
12.35 12.43
15.75 16.00 16.25
13.95 14.00 14.05
12.35 12.43
0.65
0.57
0.22
0.80
0.65
0.30
0.95
0.73
0.38
0.10
0.026 0.031 0.037
0.023 0.026 0.029
0.009 0.012 0.015
0.004
0.50 0.60
0.57 0.65
0.25 0.30
0.75
0.73
0.35
0.10
0.020 0.024 0.030
0.022 0.026 0.029
0.010 0.012 0.014
0.004
e
B
–58–
REV. B
ADSP-21xx
O UTLINE D IMENSIO NS
AD SP -2111
100-P in Gr id Ar r ay (P GA)
e
e
1
2
PGA LOCATION A1 QUADRANT MARKING
1
2
3
4
INDEX
PIN
ONLY
5
6
e
e
D
2
1
7
TOP VIEW
8
9
10
11
12
13
N
M
L
K
J
H
G
F
E
D
C
B A
D
A
1
A
L
3
e
SEATING
PLANE
φ b
φ b
1
INCHES
TYP
MILLIMETERS
SYMBOL MIN
MAX
0.169
MIN
3.12
TYP
MAX
4.29
A
0.123
A1
φb
φb1
D
0.050
1.27
0.016 0.018 0.020
0.050
0.41
0.46
1.27
0.51
1.308 1.32
1.188 1.20
0.988 1.00
0.100
1.342
1.212
1.012
33.22 33.53 34.09
30.18 30.48 30.78
e1
e2
e
25.10 25.4
2.54
4.57
25.70
L3
0.180
REV. B
–59–
ADSP-21xx
O UTLINE D IMENSIO NS
AD SP -2111
100-Lead Bum per ed P lastic Q uad Flatpack (P Q FP )
D
2
SEATING
PLANE
D
D
1
A
89
13
L
1
88
14
Beveled
Edge
E
E
E
2
TOP VIEW
(PINS DOWN)
1
D
3
, E
3
64
38
39
63
A
2
e
B
NOTE: PIN 1 IS THE CENTER PIN ON THE BEVELED-EDGE SIDE OF THE PACKAGE.
A
1
INCHES
TYP
MILLIMETERS
MIN TYP
SYMBOL MIN
A
MAX
0.180
MAX
4.572
1.016
3.810
A1
0.020
0.130
0.875
0.747
0.897
0.030 0.040
0.140 0.150
0.880 0.885
0.750 0.753
0.900 0.903
0.600 0.603
0.046
0.508
3.302
0.762
3.556
A2
D, E
D1, E1
D2, E2
D3, E3
L
22.225 22.352 22.479
18.974 19.050 19.126
22.784 22.860 22.936
15.240 15.316
0.036
0.022
0.008
0.914
0.559
0.203
1.168
0.711
0.305
0.102
e
0.025 0.028
0.012
0.635
B
0.004
–60–
REV. B
ADSP-21xx
O RD ERING GUID E
Am bient
Tem perature
Range
Instruction
Rate (MH z)
P ackage
D escription
P ackage
O ption
P art Num ber1
ADSP-2101KG-66
ADSP-2101BG-66
ADSP-2101KP-66
ADSP-2101BP-66
ADSP-2101KS-66
ADSP-2101BS-66
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
16.67 MHz
16.67 MHz
16.67 MHz
16.67 MHz
16.67 MHz
16.67 MHz
68-Pin PGA
68-Pin PGA
68-Lead PLCC
68-Lead PLCC
80-Lead PQFP
80-Lead PQFP
G-68A
G-68A
P-68A
P-68A
S-80
S-80
ADSP-2101KG-80
ADSP-2101BG-80
ADSP-2101KP-80
ADSP-2101BP-80
ADSP-2101KS-80
ADSP-2101BS-80
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
20.0 MHz
20.0 MHz
20.0 MHz
20.0 MHz
20.0 MHz
20.0 MHz
68-Pin PGA
68-Pin PGA
68-Lead PLCC
68-Lead PLCC
80-Lead PQFP
80-Lead PQFP
G-68A
G-68A
P-68A
P-68A
S-80
S-80
ADSP-2101KP-100
ADSP-2101BP-100
ADSP-2101KS-100
ADSP-2101BS-100
ADSP-2101KG-100
ADSP-2101BG-100
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
25.0 MHz
25.0 MHz
25.0 MHz
25.0 MHz
25.0 MHz
25.0 MHz
68-Pin PLCC
68-Pin PLCC
80-Lead PQFP
80-Lead PQFP
68-Lead PGA
68-Lead PGA
P-68A
P-68A
S-80
S-80
G-68A
G-68A
ADSP-2101T G-50
–55°C to +125°C
12.5 MHz
68-Pin PGA
G-68A
ADSP-2103KP-40 (3.3 V)
ADSP-2103BP-40 (3.3 V)
ADSP-2103KS-40 (3.3 V)
ADSP-2103BS-40 (3.3 V)
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
10.24 MHz
10.24 MHz
10.24 MHz
10.24 MHz
68-Lead PLCC
68-Lead PLCC
80-Lead PQFP
80-Lead PQFP
P-68A
P-68A
S-80
S-80
ADSP-2105KP-55
ADSP-2105BP-55
ADSP-2105KP-80
ADSP-2105BP-80
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
13.824 MHz
13.824 MHz
20.0 MHz
68-Lead PLCC
68-Lead PLCC
68-Lead PLCC
68-Lead PLCC
P-68A
P-68A
P-68A
P-68A
20.0 MHz
ADSP-2115KP-66
ADSP-2115BP-66
ADSP-2115KS-66
ADSP-2115BS-66
ADSP-2115KST -66
ADSP-2115BST -66
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
16.67 MHz
16.67 MHz
16.67 MHz
16.67 MHz
16.67 MHz
16.67 MHz
68-Lead PLCC
68-Lead PLCC
80-Lead PQFP
80-Lead PQFP
80-Lead T QFP
80-Lead T QFP
P-68A
P-68A
S-80
S-80
ST -80
ST -80
ADSP-2115KP-80
ADSP-2115BP-80
ADSP-2115KS-80
ADSP-2115BS-80
ADSP-2115KST -80
ADSP-2115BST -80
ADSP-2115KP-100
ADSP-2115BP-100
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
20.0 MHz
20.0 MHz
20.0 MHz
20.0 MHz
20.0 MHz
20.0 MHz
25.0 MHz
25.0 MHz
68-Lead PLCC
68-Lead PLCC
80-Lead PQFP
80-Lead PQFP
80-Lead T QFP
80-Lead T QFP
68-Lead PLCC
68-Lead PLCC
P-68A
P-68A
S-80
S-80
ST -80
ST -80
P-68A
P-68A
NOT ES
1K = Commercial T emperature Range (0°C to +70°C).
B
T
G
P
= Industrial T emperature Range (–40°C to +85°C).
= Extended T emperature Range (–55°C to +125°C).
= Ceramic PGA (Pin Grid Array).
= PLCC (Plastic Leaded Chip Carrier).
= PQFP (Plastic Quad Flatpack).
S
ST = T QFP (T hin Quad Flatpack)
REV. B
–61–
ADSP-21xx
O RD ERING GUID E
Am bient
Tem perature
Range
Instruction
Rate (MH z)
P ackage
D escription
P ackage
O ption
P art Num ber1
ADSP-2111KG-52
ADSP-2111BG-52
ADSP-2111KS-52
ADSP-2111BS-52
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
13.0 MHz
13.0 MHz
13.0 MHz
13.0 MHz
100-Pin PGA
100-Pin PGA
100-Lead PQFP
100-Lead PQFP
G-100A
G-100A
S-100A
S-100A
ADSP-2111KG-66
ADSP-2111BG-66
ADSP-2111KS-66
ADSP-2111BS-66
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
16.67 MHz
16.67 MHz
16.67 MHz
16.67 MHz
100-Pin PGA
100-Pin PGA
100-Lead PQFP
100-Lead PQFP
G-100A
G-100A
S-100A
S-100A
ADSP-2111KG-80
ADSP-2111BG-80
ADSP-2111KS-80
ADSP-2111BS-80
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
20.0 MHz
20.0 MHz
20.0 MHz
20.0 MHz
100-Pin PGA
100-Pin PGA
100-Lead PQFP
100-Lead PQFP
G-100A
G-100A
S-100A
S-100A
ADSP-2111T G-52
–55°C to +125°C
13.0 MHz
100-Pin PGA
G-100A
ADSP-2161KP-662
ADSP-2161BP-662
ADSP-2161KS-662
ADSP-2161BS-662
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
16.67 MHz
16.67 MHz
16.67 MHz
16.67 MHz
68-Lead PLCC
68-Lead PLCC
80-Lead PQFP
80-Lead PQFP
P-68A
P-68A
S-80
S-80
ADSP-2162KP-40 (3.3 V)2
ADSP-2162BP-40 (3.3 V)2
ADSP-2162KS-40 (3.3 V)2
ADSP-2162BS-40 (3.3 V)2
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
10.24 MHz
10.24 MHz
10.24 MHz
10.24 MHz
68-Lead PLCC
68-Lead PLCC
80-Lead PQFP
80-Lead PQFP
P-68A
P-68A
S-80
S-80
ADSP-2163KP-662
ADSP-2163BP-662
ADSP-2163KS-662
ADSP-2163BS-662
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
16.67 MHz
16.67 MHz
16.67 MHz
16.67 MHz
68-Lead PLCC
68-Lead PLCC
80-Lead PQFP
80-Lead PQFP
P-68A
P-68A
S-80
S-80
ADSP-2163KP-1002
ADSP-2163BP-1002
ADSP-2163KS-1002
ADSP-2163BS-1002
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
25 MHz
25 MHz
25 MHz
25 MHz
68-Lead PLCC
68-Lead PLCC
80-Lead PQFP
80-Lead PQFP
P-68A
P-68A
S-80
S-80
ADSP-2164KP-40 (3.3 V)2
ADSP-2164BP-40 (3.3 V)2
ADSP-2164KS-40 (3.3 V)2
ADSP-2164BS-40 (3.3 V)2
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
10.24 MHz
10.24 MHz
10.24 MHz
10.24 MHz
68-Lead PLCC
68-Lead PLCC
80-Lead PQFP
80-Lead PQFP
P-68A
P-68A
S-80
S-80
NOT ES
1K
B
T
G
P
=
=
=
=
=
=
Commercial T emperature Range (0°C to +70°C).
Industrial T emperature Range (–40°C to +85°C).
Extended T emperature Range (–55°C to +125°C).
Ceramic PGA (Pin Grid Array).
PLCC (Plastic Leaded Chip Carrier).
PQFP (Plastic Quad Flatpack).
S
2Minimum order quantities required. Contact factory for further information.
–62–
REV. B
–63–
–64–
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