ADSP-21567WCBCZ8 [ADI]
SHARC Single Core High Performance DSP (Up to 1 GHz);型号: | ADSP-21567WCBCZ8 |
厂家: | ADI |
描述: | SHARC Single Core High Performance DSP (Up to 1 GHz) |
文件: | 总104页 (文件大小:2719K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SHARC+ Single Core
High Performance DSP (Up to 1 GHz)
ADSP-21562/21563/21565/21566/21567/21569
SYSTEM FEATURES
MEMORY
Enhanced SHARC+ high performance floating-point core
Up to 1 GHz
Large on-chip Level 2 (L2) SRAM with ECC protection, up to
8 Mb (1 MB)
One Level 3 (L3) interface optimized for low system power,
providing 16-bit interface to DDR3/DDR3L SDRAM devices
5 Mb (640 kB) Level 1 (L1) SRAM memory with parity
(optional ability to configure as cache)
32-bit, 40-bit, and 64-bit floating-point support
32-bit fixed point
Byte, short word, word, long word addressed
Powerful DMA system
On-chip memory protection
Integrated safety features
17 mm × 17 mm, 400-ball CSP_BGA (0.8 mm pitch), RoHS
compliant
ADDITIONAL FEATURES
Security and Protection
Crypto hardware accelerators
Fast secure boot with IP protection
Enhanced FIR and IIR accelerators running up to 1 GHz
AEC-Q100 qualified for automotive applications
APPLICATIONS
120-lead LQFP_EP (0.4 mm pitch), RoHS compliant
Low system power across automotive temperature range
Automotive: audio amplifier, head unit, ANC/RNC, rear seat
entertainment, digital cockpit, ADAS
Consumer: speakers, sound bars, AVRs, conferencing sys-
tems, mixing consoles, microphone arrays, headphones
SYSTEM CONTROL
SECURITY AND PROTECTION
SHARC+ CORE
SYSTEM PROTECTION UNIT (SPU)
UP TO
SYSTEM MEMORY
PROTECTION UNIT (SMPU)
1 GHz
FLOATING-POINT
DSP
S
ENCRYPTION/DECRYPTION
FAULT MANAGEMENT (FMU)
PERIPHERALS
ACCELERATORS
SIGNAL ROUTING UNIT (SRU)
FIR
IIR
2×2 PRECISION CLOCK
GENERATORS
DUAL CRC (WITH MemDMA)
WATCHDOGS
L1 SRAM (PARITY)
(UP TO (UP TO
1 GHz) 1 GHz)
5 Mb (640 kB)
SRAM/CACHE
2x DAI
2x PIN
2×4 ASRC
PAIRS
FULL SPORT
2×4
OTP MEMORY
BUFFER
24–28
THERMAL MONITOR UNIT (TMU)
2×1 S/PDIF Rx/Tx
6× I2C
PROGRAM FLOW
SYSTEM EVENT CONTROLLER
(SEC)
SYSTEM CROSSBAR AND DMA SUBSYSTEM
1× SPI + 2× QUAD SPI +
1× OCTAL SPI
G
P
I
TRIGGER ROUTING UNIT (TRU)
3× UARTs
2× LINK PORTS
22–40
O
CLOCK, RESET, AND POWER
L3 MEMORY
INTERFACES
SYSTEM
L2 MEMORY
CLOCK GENERATION UNIT (CGU)
10× TIMERS + 1× COUNTER
MLB 3-PIN
CLOCK DISTRIBUTION UNIT (CDU)
RESET CONTROL UNIT (RCU)
DDR3/DDR3L
BGA ONLY
SRAM
(ECC)
UP TO 8 Mb (1 MB)
HADC (4 CHAN, 12-BIT)
2–4
DYNAMIC POWER MANAGEMENT
(DPM)
16
DEBUG UNIT
DATA
TM
®
Arm CoreSight
DEBUG AND TRACE
SYSTEM WATCHPOINT UNIT
(SWU)
Figure 1. ADSP-21569 (Full-Featured Model) Processor Block Diagram
SHARC, SHARC+, and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. B Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
Technical Support
©2021 Analog Devices, Inc. All rights reserved.
www.analog.com
ADSP-21562/21563/21565/21566/21567/21569
TABLE OF CONTENTS
System Features ....................................................... 1
Memory ................................................................ 1
Additional Features .................................................. 1
Applications ........................................................... 1
Table of Contents ..................................................... 2
Revision History ...................................................... 3
General Description ................................................. 4
SHARC Processor ................................................. 5
SHARC+ Core Architecture .................................... 7
System Infrastructure ............................................. 9
System Memory Map ............................................. 9
Security Features ................................................ 12
Security Features Disclaimer .................................. 13
Safety Features ................................................... 13
Processor Peripherals ........................................... 14
System Acceleration ............................................ 17
System Design .................................................... 17
System Debug .................................................... 19
Development Tools ............................................. 20
Additional Information ........................................ 21
Related Signal Chains .......................................... 21
ADSP-2156x Detailed Signal Descriptions ................... 22
400-Ball CSP_BGA Signal Descriptions ....................... 25
GPIO Multiplexing for 400-Ball CSP_BGA Package ....... 31
120-Lead LQFP Signal Descriptions ........................... 33
GPIO Multiplexing for 120-Lead LQFP Package ............ 36
ADSP-2156x Designer Quick Reference ...................... 37
Specifications ........................................................ 45
Operating Conditions ........................................... 45
Electrical Characteristics ....................................... 48
HADC .............................................................. 52
TMU ................................................................ 52
Absolute Maximum Ratings ................................... 53
ESD Caution ...................................................... 53
Timing Specifications ........................................... 54
Output Drive Currents ......................................... 87
Test Conditions .................................................. 88
Environmental Conditions .................................... 89
ADSP-2156x 400-Ball BGA Ball Assignments ................ 91
Numerical by Ball Number .................................... 91
Alphabetical by Pin Name ..................................... 94
Configuration of the 400-Ball CSP_BGA ................... 97
ADSP-2156x 120-Lead LQFP Lead Assignments ............ 98
Numerical by Lead Number ................................... 98
Alphabetical by Pin Name ..................................... 99
Configuration of the 120-Lead LQFP Lead
Configuration ................................................ 100
Outline Dimensions .............................................. 101
Surface-Mount Design ........................................ 102
Automotive Products ............................................ 103
Planned Automotive Production Products .................. 103
Planned Production Products .................................. 104
Ordering Guide ................................................... 104
Rev. B
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REVISION HISTORY
2/2021—Rev. A to Rev. B
Changes to Power-Up Reset Timing ........................... 54
Changes to EZ-KIT Evaluation System ......................... 20
Changes to OSPI Port—Master Timing ....................... 74
Changes to JTAG Emulation Port Timing .................... 86
Added missing IDD_IDLE, IDD_TYP, and IDD_INT parameters to
Electrical Characteristics ........................................... 48
Changes to figure captions for Figure 42 and Figure 43 in
Output Drive Currents ............................................ 87
Changes to footnotes 1 and 3 in Table 64, JTAG Emulation Port
Timing ................................................................. 86
Changes to figure captions for Figure 51 and Figure 52 in
Capacitive Loading ................................................. 88
Changes to Table 68, Automotive Products ................. 103
Added Planned Automotive Production Products ......... 103
Added Planned Production Products ......................... 104
Changes to Ordering Guide ..................................... 104
Changes to Environmental Conditions ........................ 89
Changes to
ADSP-2156x 400-Ball BGA Ball Assignments ................ 91
Changes to
ADSP-2156x 120-Lead LQFP Lead Assignments ............ 98
12/2020—Rev. 0 to Rev. A
Changes to Automotive Products .............................. 103
Changes to Ordering Guide ..................................... 104
Changes to Additional Features ................................... 1
Changes to ADSP-21569 (Full-Featured Model) Processor
Block Diagram ........................................................ 1
Changes to Processor Features .................................... 4
Changes to L1 Master and Slave Ports ........................... 6
Added SHARC Fabric ............................................... 9
Changes to Dynamic Memory Controller (DMC) ........... 14
Added
Housekeeping Analog-to-Digital Converter (HADC) ...... 16
Added Thermal Monitoring Unit (TMU) ..................... 19
Changes to Power Supplies ........................................ 19
Changes to Power Domains ....................................... 19
Changes to Power-Up and Power-Down Sequencing ....... 19
Changes to Development Tools .................................. 20
Changes to ADSP-2156x Detailed Signal Descriptions ..... 22
Changes to
ADSP-2156x 400-Ball CSP_BGA Signal Descriptions ...... 25
Changes to Signal Multiplexing for Port A .................... 31
Changes to Signal Multiplexing for Port C .................... 32
Changes to
ADSP-2156x 120-Lead LQFP Signal Descriptions ........... 33
Changes to Signal Multiplexing for Port A .................... 36
Changes to ADSP-2156x Designer Quick Reference ........ 37
Changes to Operating Conditions ............................... 45
Changes to Electrical Characteristics ........................... 48
Added HADC ........................................................ 52
Added TMU .......................................................... 52
Changes to Absolute Maximum Ratings ....................... 53
Added Maximum Duty Cycle for Input Transient Voltage for
VDD_INT and VDD_EXT ........................................ 53
Added
Maximum Duty Cycle for Input Transient Voltage ......... 53
Rev. B
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GENERAL DESCRIPTION
Reaching speeds of up to 1 GHz, the ADSP-2156x processors
are members of the SHARC® family of products. The ADSP-
2156x processor is based on the SHARC+® single core. The
ADSP-2156x SHARC processors are members of the SIMD
SHARC family of digital signal processors (DSPs) that feature
Analog Devices, Inc., Super Harvard Architecture. These 32-
bit/40-bit/64-bit floating-point processors are optimized for
high performance audio/floating-point applications with large
on-chip static random-access memory (SRAM), multiple inter-
nal buses that eliminate input/output (I/O) bottlenecks, and
innovative digital audio interfaces (DAI). New additions to the
SHARC+ core include cache enhancements and branch predic-
tion, while maintaining instruction set compatibility to previous
SHARC products.
By integrating a rich set of industry-leading system peripherals
and memory (see Table 1), the SHARC+ processor is the plat-
form of choice for applications that require programmability
similar to reduced instruction set computing (RISC), multime-
dia support, and leading edge signal processing in one
integrated package. These applications span a wide array of
markets, including automotive, professional audio, and indus-
trial-based applications that require high floating-point
performance.
Table 1. Processor Features1
Processor Feature
SHARC+ Core (MHz Maximum)2
SHARC L1 SRAM (kB)
System Memory
ADSP-21562 ADSP-21563 ADSP-21565 ADSP-21566 ADSP-21567 ADSP-21569
400
600, 800
800, 1000
400
600, 800
800, 1000
640
L2 SRAM (kB)
256
512
N/A
1024
256
512
1
1024
DDR3 and DDR3L Controller (16-Bit)
DAI (Includes SRU)
Full SPORTs
S/PDIF Rx/Tx
ASRCs
2
2 × 4
2 × 1
2 × 4
2 × 2
Precision Clock Generators
Buffers
Hardware Accelerators
FIR/IIR
2 × 12
2 × 14
Yes
Yes
Security Crypto Engine
I2C (TWI)
4
6
SPI
1
2
1
Quad SPI
Octal SPI
UARTs
2
0
6
3
2
Link Port
General-Purpose Timer3
General-Purpose Counter
Multichannel 12-bit ADC
Watchdog Timer
MLB 3-pin
10
1
2
2-ch
4-ch
Automotive models only
GPIO Ports
Port A to Port B
22 + 24
Port A to Port C
40 + 28
GPIO + DAI Pins
Package Options
120-lead LQFP_EP
400-ball CSP_BGA
1 N/A means not applicable.
2 The values refer to different speed grades.
3 Refer to Table 14 for internal timer signal routing.
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The SHARC processor supports a modified Harvard architec-
SHARC PROCESSOR
ture in combination with a hierarchical memory structure. L1
The SHARC processor integrates a SHARC+ SIMD core, L1
memory crossbar, I-cache/D-cache controller, L1 memory
blocks, and the master/slave ports, as shown in Figure 2. The
SHARC+ SIMD core block diagram is shown in Figure 3.
memories typically operate at the full processor speed with little
or no latency.
I-CACHE
D-CACHE
D-CACHE
B0
RAM
S
SIMD Processor
B3
RAM
B2
RAM
B1
RAM
CCLK DOMAIN
I/O (32)
I/O (32)
I/O (32)
SLAVE
PORT 1
INTERNAL MEMORY INTERFACE (IMIF)
I-CACHE/D-CACHE CONTROL
SLAVE
I/O (32)
PORT 2
(MDMA AND
ACCELERATORS)
SYSTEM FABRIC
CORE
MMR
SYSCLK
DOMAIN
(32)
DM (64)
PM (64)
CMD (64)
CMI (64)
MASTER
PORT DATA
SHARC+®
SIMD CORE
PS (64/48)
MASTER
PORT INSTRUCTION
INTERRUPT
SYSTEM
EVENT
CONTROLLER
Figure 2. SHARC Processor Block Diagram
The SRAM of the processor can be configured as a maximum of
160k words of 32-bit data, 320k words of 16-bit data,
106.7k words of 48-bit instructions (or 40-bit data), or combi-
nations of different word sizes up to 5 Mb. All of the memory
can be accessed as 8-bit, 16-bit, 32-bit, 48-bit, or 64-bit words.
Support of a 16-bit floating-point storage format doubles the
amount of data that can be stored on chip.
L1 Memory
Figure 4 shows the ADSP-2156x memory map. The SHARC+
core has a tightly coupled 5 Mb L1 SRAM. The SHARC+ core
can access code and data in a single cycle from this memory
space.
In the SHARC+ core private address space, the core has L1
memory.
Conversion between the 32-bit floating-point and 16-bit float-
ing-point formats is performed in a single instruction. Whereas
each memory block can store combinations of code and data,
accesses are most efficient when one block stores data using the
DM bus for transfers, and the other block stores instructions
and data using the PM bus for transfers.
SHARC+ core memory-mapped register (CMMR) address
space is 0x0000 0000 through 0x0003 FFFF in normal word
(32-bit). Each block can be configured for different combina-
tions of code and data storage. Of the 5 Mb SRAM, up to 1 Mb
can be configured for data memory (DM), program memory
(PM), and instruction cache each. Each memory block supports
single-cycle, independent accesses by the core processor and I/O
processor. The memory architecture, in combination with its
separate on-chip buses, allows two data transfers from the core
and one from the direct memory access (DMA) engine in a
single cycle.
Using the DM and PM buses, with each bus dedicated to a
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache. The system configuration is flexible, but a typical config-
uration is 512 kb DM, 128 kb PM, and 128 kb of instruction
Rev. B
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S
DEBUG
TRACE
BTB
BP
CONFLICT
CACHE
CEC
FLAGS
SIMD Core
PM DATA 48
DMD/PMD 64
11-STAGE
PROGRAM SEQUENCER
PM ADDRESS 24
DAG2
16 × 32
DAG1
16 × 32
PM ADDRESS 32
SYSTEM
I/F
DM ADDRESS 32
PM DATA 64
TO
IMIF
USTAT
PX
DM DATA 64
DATA
SWAP
PEx
PEy
DATA
DATA
ALU
SHIFTER
MULTIPLIER
ALU
SHIFTER MULTIPLIER
REGISTER
Rx
16 × 40-BIT
REGISTER
Sx
16 × 40-BIT
ASTATy
STYKy
ASTATx
STYKx
MSB
80-BIT
MSF
80-BIT
MRB
80-BIT
MRF
80-BIT
Figure 3. SHARC+ SIMD Core Block Diagram
cache, with the remaining L1 memory configured as SRAM.
Each addressable memory space outside the L1 memory can be
accessed either directly or via cache.
L1 On-Chip Memory Bandwidth
The internal memory architecture allows programs to have four
accesses at the same time to any of the four blocks, assuming no
block conflicts. The total bandwidth is realized using both the
DMD and PMD buses (2 × 64-bits CCLK speed and 2 × 32-bit
SYSCLK speed).
The memory map in Table 2 gives the L1 memory address space
and shows multiple L1 memory blocks offering a configurable
mix of SRAM and cache.
L1 Master and Slave Ports
Instruction and Data Cache
The SHARC+ core has two master/slave ports to and from the
system fabric. One master port fetches instructions. The second
master port drives data to the system world. Slave Port 1
together with Slave Port 2 memory direct memory access (high
speed MDMA) run conflict free access to the individual mem-
ory blocks. For the slave port addresses, refer to the L1 memory
address map in Table 2.
The ADSP-2156x processors also include a traditional instruc-
tion cache (I-cache) and two data caches (D-caches, one each
for PM/DM) with parity support for all caches. These caches
support one instruction access and two data accesses over the
DM and PM buses per CCLK cycle. The cache controllers auto-
matically manage the configured L1 memory. The system can
configure part of the L1 memory for automatic management by
the cache controllers. The sizes of these caches are inde-
pendently configurable from 0 to 128 kB each. The memory not
managed by the cache controllers is directly addressable by the
processors. The controllers ensure the data coherence between
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SHARC+ CORE ARCHITECTURE
0x FFFF FFFF
0x C000 0000
RESERVED
DMC0 (1GB)
The ADSP-2156x processors are assembly code compatible with
all previous SHARC processors featuring the SHARC or
SHARC+ core, beginning with the first generation ADSP-2106x
SHARC processors and including the ADSP-2116x, ADSP-
2126x, ADSP-213xx, ADSP-214xx, and ADSP-SC5xx/ADSP-
215xx processors.
0x 8000 0000
0x 6000 0000
SPI2/OSPI0 FLASH ADDRESS SPACE (512MB)
0x 5000 0000
0x 4C00 0000
0x 4800 0000
0x 4400 0000
The SIMD architecture featured on the ADSP-2156xprocessors
is identical to all previous SIMD SHARC processors, namely the
ADSP-2116x, ADSP-2126x, ADSP-213xx, ADSP-214xx, and
ADSP-SC5xx/ADSP-215xx processors, as shown in Figure 3
and as described in the following sections.
RESERVED
0x 4000 0000
0x 3000 0000
SYSTEM MMR
RESERVED
Single-Instruction, Multiple Data (SIMD) Computational
Engine
The SHARC+ core contains two computational processing ele-
ments that operate as a single-instruction, multiple data (SIMD)
engine.
0x 2840 0000
0x 2824 0000
0x 202B FFFF
0x 2028 0000
SHARC1 L1 ADDRESS SPACE VIA SLAVE 1/SLAVE 2 PORTS
RESERVED
The processing elements are referred to as PEx and PEy, each
containing an arithmetic logic unit (ALU), multiplier, shifter,
and register file. PEx is always active, and PEy is enabled by set-
ting the PEYEN mode bit in the mode control register
(MODE1).
RESERVED
0x 2011 8000
0x 2011 0000
L2 BOOT ROM 2 (0.25Mb)
L2 BOOT ROM 1 (0.25Mb)
SIMD mode allows the processors to execute the same instruc-
tion in both processing elements, but each processing element
operates on different data. This architecture efficiently executes
math intensive DSP algorithms. In addition to all the features of
previous generation SHARC cores, the SHARC+ core also pro-
vides a new and simpler way to execute an instruction only on
the PEy data register.
0x 2010 8000
0x 2010 0000
L2 BOOT ROM 0 (0.25Mb)
L2 SRAM (8Mb)
RESERVED
0x 2000 0000
0x 0039 FFFF
L1 BLOCK 3 SRAM (1Mb)
RESERVED
SIMD mode also doubles the bandwidth between memory and
the processing elements, as required for sustained computa-
tional operation of two processing elements. When using the
data address generators (DAGs) to transfer data in SIMD mode,
two data values transfer with each memory or register file
access.
0x 0038 0000
0x 0031 FFFF
0x 0030 0000
0x 002E FFFF
L1 BLOCK 2 SRAM (1Mb)
RESERVED
L1 BLOCK 1 SRAM (1.5Mb)
0x 002C 0000
0x 0026 FFFF
Independent Parallel Computation Units
RESERVED
Within each processing element is a set of pipelined computa-
tional units. The computational units consist of a multiplier, an
ALU, and a shifter. These units are arranged in parallel, maxi-
mizing computational throughput. These computational units
support IEEE 32-bit single-precision floating-point; 40-bit
extended-precision floating-point; IEEE 64-bit double-preci-
sion floating-point; and 32-bit fixed-point data formats.
L1 BLOCK 0 SRAM (1.5Mb)
0x 0024 0000
0x 0000 0000
RESERVED/CORE MMRs/
OTHER MEMORY ALIASES
Figure 4. ADSP-2156x Memory Map
the two data caches. The caches provide user controllable fea-
tures such as full and partial locking, range bound invalidation,
and flushing.
A multifunction instruction set supports parallel execution of
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele-
ments per core.
Core Memory-Mapped Registers (CMMR)
The core memory-mapped registers control the L1 instruction
and data cache, branch target buffer (BTB), parity error, system
control, debug, and monitor functions.
All processing operations take one cycle to complete. For all
floating-point operations, the processor takes two cycles to
complete in case of data dependency. Double-precision float-
ing-point data take two to six cycles to complete. The processor
stalls for the appropriate number of cycles for an interlocked
pipeline plus data dependency check.
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Additionally, the double-precision floating-point instruction set
Core Timer
is new to the SHARC+ core, as compared with the previous
SHARC core.
The SHARC+ processor core includes an extra timer. This extra
timer is clocked by the internal processor clock and is typically
used as a system tick clock for generating periodic operating
system interrupts.
Variable Instruction Set Architecture (VISA)
In addition to supporting the standard 48-bit instructions from
previous SHARC core processors, the SHARC+ core processors
support 16-bit and 32-bit opcodes for many instructions, for-
merly 48-bit in the ISA. This variable instruction set
architecture (VISA) feature drops redundant or unused bits
within the 48-bit instruction to create more efficient and com-
pact code. The program sequencer supports fetching these
16-bit and 32-bit instructions from both internal and external
memories. VISA is not an operating mode; rather, it is address
dependent (refer to the ISA/VISA address spaces in Table 5).
Finally, the processor allows jumps between ISA and VISA
instruction fetches.
Data Register File
Each processing element contains a general-purpose data regis-
ter file. The register files transfer data between the computation
units and the data buses, and store intermediate results. These
10-port, 32-register register files (16 primary, 16 secondary),
combined with the enhanced Harvard architecture of the pro-
cessor, allow unconstrained data flow between computation
units and internal memory. The registers in the PEx data regis-
ter file are referred to as R0–R15 and in the PEy data register file
as S0–S15.
Context Switch
Single-Cycle Fetch of Instructional Four Operands
Many of the registers of the processor have secondary registers
that can activate during interrupt servicing for a fast context
switch. The data, DAG, and multiplier result registers have sec-
ondary registers. The primary registers are active at reset,
whereas control bits in MODE1 activate the secondary registers.
The ADSP-2156x processors feature an enhanced Harvard
architecture in which the DM bus transfers data and the PM bus
transfers both instructions and data.
With the separate program memory bus, data memory buses,
and on-chip instruction conflict cache, the processor can simul-
taneously fetch four operands (two over each data bus) and one
instruction from the conflict cache in a single cycle.
Universal Registers
General-purpose tasks use the universal registers. The four uni-
versal status (USTAT) registers allow easy bit manipulations
(set, clear, toggle, test, XOR) for all control and status peripheral
registers.
Core Event Controller (CEC)
The SHARC+ core event controller (CEC) can be configured to
service various interrupts generated by the core (including
arithmetic and circular buffer instruction flow exceptions) and
system event controller (SEC) events (peripheral interrupt
request, debug or monitor, and software-raised), responding
only to interrupts enabled in the IMASK register. The output of
the SEC is forwarded to the CEC to respond directly to any
enabled system interrupts. For all SEC channels, the processor
automatically stacks the arithmetic status (ASTATx and
ASTATy) registers and mode (MODE1) register in parallel with
interrupt servicing.
The data bus exchange register (PX) permits data to pass
between the 64-bit PM data bus and the 64-bit DM data bus or
between the 40-bit register file and the PM or DM data bus.
These registers contain hardware to handle the data width
difference.
Data Address Generators (DAG) With Zero Overhead
Hardware Circular Buffer Support
For indirect addressing and implementing circular data buffers
in hardware, the ADSP-2156x processor uses two data address
generators (DAGs). Circular buffers allow efficient program-
ming of delay lines and other data structures required in digital
signal processing and are commonly used in digital filters and
fast Fourier transforms (FFT). The DAGs contain sufficient reg-
isters to allow the creation of up to 32 circular buffers (16
primary register sets and 16 secondary sets). The DAGs auto-
matically handle address pointer wraparound, reduce overhead,
increase performance, and simplify implementation. Circular
buffers can start and end at any memory location.
Instruction Conflict Cache
The processors include a 32-entry instruction cache that enables
three-bus operation for fetching an instruction and four data
values. The cache is selective—only the instructions that require
fetches conflict with the PM bus data access cache. This cache
allows full speed execution of core looped operations, such as
digital filter multiply accumulates and FFT butterfly processing.
The conflict cache serves for bus conflicts within the SHARC+
core only.
Flexible Instruction Set Architecture (ISA)
Addressing Spaces
The flexible instruction set architecture (ISA), a 48-bit instruc-
tion word, accommodates various parallel operations for
concise programming. For example, the processors can condi-
tionally execute a multiply, an add, and a subtract in both
processing elements while branching and fetching up to four
32-bit values from memory—all in a single instruction.
In addition to traditionally supported long word, normal word,
extended precision word, and short word addressing aliases, the
processors support byte addressing for the data and instruction
accesses. The enhanced ISA/VISA provides new instructions for
accessing all sizes of data from byte space, as well as converting
word addresses to byte addresses and byte addresses to word
addresses.
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support concurrent access to the L2 memory ports. Memory
accesses to the L2 memory space are multicycle accesses by the
SHARC+ core.
Branch Target Buffer (BTB)/Branch Predictor (BP)
Implementation of a hardware-based branch predictor (BP) and
branch target buffer (BTB) reduce branch delay. The program
sequencer supports efficient branching using the BTB for condi-
tional and unconditional instructions.
The memory space is used for various situations including
• Accelerator and peripheral sources and destination mem-
ory to avoid accessing data in the external memory
SHARC Fabric
• A location for DMA descriptors
The FIR/IIR accelerators on the ADSP-2156x processors are
integrated closely with the SHARC+ core with the help of a ded-
icated SHARC fabric and run at CCLK speed. This allows the
FIR/IIR accelerator master ports to directly access the SHARC
L1 memory with reduced latency, as these accesses do not go
through the main system fabric. The SHARC+ core can also
access the FIR/IIR accelerator MMR registers directly.
• Storage for additional data for the SHARC+ core to avoid
external memory latencies and reduce external memory
bandwidth
• Storage for data coefficient tables cached by the
SHARC+ core
See the System Memory Protection Unit (SMPU) section for
options in limiting access by the core and DMA masters.
Additional Features
To enhance the reliability of the application, L1 data RAMs sup-
port parity error detection for every byte, and illegal opcodes are
also detected (core interrupts flag both errors). Master ports of
the core also detect failed external accesses.
One Time Programmable Memory (OTP)
The processors feature 7 kb of one time programmable (OTP)
memory that is memory-map accessible. This memory can be
programmed with custom keys and supports secure boot and
secure operation.
SYSTEM INFRASTRUCTURE
The following sections describe the system infrastructure of the
ADSP-2156x processors.
I/O Memory Space
Mapped I/Os include SPI2 or OSPI0 memory address spaces
(see Table 5).
System L2 Memory
A system L2 SRAM memory of up to 8 Mb (1 MB) is available to
the SHARC+ core and the system DMA channels (see Table 3).
The L2 SRAM block is subdivided into up to eight banks to
SYSTEM MEMORY MAP
Table 2. L1 Block 0, Block 1, Block 2, and Block 3 SHARC+® Addressing Memory Map (Private Address Space)
Extended Precision/
Short Word/
Memory
Long Word (64 Bits) ISA Code (48 Bits)
Normal Word (32 Bits) VISA Code (16 Bits) Byte Access (8 Bits)
L1 Block 0 SRAM 0x00048000–
(1.5 Mb) 0x0004DFFF
L1 Block 1 SRAM 0x00058000–
(1.5 Mb) 0x0005DFFF
L1 Block 2 SRAM 0x00060000–
(1 Mb) 0x00063FFF
L1 Block 3 SRAM 0x00070000–
(1 Mb) 0x00073FFF
0x00090000–
0x00097FFF
0x00090000–
0x0009BFFF
0x00120000–
0x00137FFF
0x00240000–
0x0026FFFF
0x000B0000–
0x000B7FFF
0x000B0000–
0x000BBFFF
0x00160000–
0x00177FFF
0x002C0000–
0x002EFFFF
0x000C0000–
0x000C5554
0x000C0000–
0x000C7FFF
0x00180000–
0x0018FFFF
0x00300000–
0x0031FFFF
0x000E0000–
0x000E5554
0x000E0000–
0x000E7FFF
0x001C0000–
0x001CFFFF
0x00380000–
0x0039FFFF
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Table 3. L2 Memory Addressing Map
Byte Address Space
SHARC+ Data Access
Normal Word Address Space VISA Address Space
ISA Address Space
Memory1
SHARC+ Data Address
SHARC+ Instruction Fetch SHARC+ Instruction Fetch
L2 RAM (2 Mb) 0x200C0000–
0x200FFFFF
0x08030000–
0x0803FFFF
0x00BE0000–
0x00BFFFFF
0x005E0000–
0x005EAAAA
L2 RAM (4 Mb) 0x20080000–
0x200FFFFF
0x08020000–
0x0803FFFF
0x00BC0000–
0x00BFFFFF
0x005D5556–
0x005EAAAA
L2 RAM (8 Mb) 0x20000000–
0x200FFFFF
0x08000000–
0x0803FFFF
0x00B80000–
0x00BFFFFF
0x005C0000–
0x005EAAAA
SHARC/DMA:
L2 Boot ROM0 0x20100000–0x20107FFF
0x08040000–
0x08041FFF
0x00B20000–
0x00B23FFF
0x00580000–
0x00581555
L2 Boot ROM1 0x20108000–
0x2010FFFF
0x08042000–
0x08043FFF
0x00B00000–
0x00B03FFF
0x00500000–
0x00501555
L2 Boot ROM2 0x20110000–
0x20117FFF
0x08044000–
0x08045FFF
0x00B40000–
0x00B43FFF
0x00540000–
0x00541555
1
The L2 RAM blocks are subdivided into banks—the 8 Mb L2 models have eight banks, the 4 Mb models have four banks, and there are two banks for the 2 Mb models.
Table 4. SHARC+® L1 Memory Space
Memory
Block
Byte Address Space SHARC+ Normal Word Address Space SHARC+
L1 Memory Space Address via Slave1/Slave2 Port Block 0
0x28240000–0x2826FFFF
0x282C0000–0x282EFFFF
0x28300000–0x2831FFFF
0x28380000–0x2839FFFF
0x0A090000–0x0A09BFFF
0x0A0B0000–0x0A0BBFFF
0x0A0C0000–0x0A0C7FFF
0x0A0E0000–0x0A0E7FFF
Block 1
Block 2
Block 3
Table 5. Memory Map of Mapped I/Os1
Byte Address Space
SHARC+ Data Access
Normal Word Address Space VISA Address Space
ISA Address Space
SHARC+ Data Access
SHARC+ Instruction Fetch SHARC+ Instruction Fetch
SPI2/OSPI0
Memory
(512 MB)
0x60000000–0x600FFFFF
0x60100000–0x602FFFFF
0x60300000–0x6FFFFFFF
0x00F80000–0x00FFFFFF
0x00780000–0x007FFFFF
Not applicable
0x04000000–0x07FFFFFF
Not applicable
Not applicable
Not applicable
Not applicable
0x70000000–0x7FFFFFFF Not applicable
1 The SHARC+ VISA/ISA address space for instruction fetch and the normal word address space for data access do not cover the entire byte address space.
Table 6. DMC Memory Map1
Byte Address Space
SHARC+ Data Access
Normal Word Address Space VISA Address Space
ISA Address Space
SHARC+ Data Access
0x10000000–0x17FFFFFF
Not applicable
SHARC+ Instruction Fetch SHARC+ Instruction Fetch
DMC0 (1 GB) 0x80000000–0x805FFFFF
0x80600000–0x809FFFFF
Not applicable
0x00400000–0x004FFFFF
Not applicable
Not applicable
0x80A00000–0x80FFFFFF
0x00800000–0x00AFFFFF
Not applicable
Not applicable
0x81000000–0x9FFFFFFF
Not applicable
0xA0000000–0xBFFFFFFF
Not applicable
Not applicable
1 The SHARC+ VISA/ISA address space for instruction fetch and the normal word address space for data access do not cover the entire byte address space.
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• The 1D DMA uses a linked list of four-word descriptor sets
System Crossbars (SCBs)
containing a link pointer, an address, a length, and a
The system crossbars (SCBs) are the fundamental building
blocks of a switch fabric style for on-chip system bus intercon-
nection. The SCBs connect system bus masters to system bus
slaves, providing concurrent data transfer between multiple bus
masters and multiple bus slaves. A hierarchical model—built
from multiple SCBs—provides a power and area efficient sys-
tem interconnection.
configuration
• The 2D DMA uses an array of one-word descriptor sets,
specifying only the base DMA address
• The 2D DMA uses a linked list of multiword descriptor
sets, specifying all configurable parameters
Memory Direct Memory Access (MDMA)
The SCBs provide the following features:
The processor supports various memory direct memory access
(MDMA) operations, including,
• Highly efficient, pipelined bus transfer protocol for sus-
tained throughput
• Enhanced bandwidth MDMA channels with cyclic redun-
dancy check (CRC) protection (32-bit bus width, run on
SYSCLK)
• Full-duplex bus operation for flexibility and reduced
latency
• Concurrent bus transfer support to allow multiple bus
masters to access bus slaves simultaneously
• Enhanced bandwidth MDMA channel (32-bit bus width,
runs on SYSCLK)
• Protection model (secure) support for selective bus inter-
connect protection
• Maximum bandwidth MDMA channel (64-bit bus width,
runs on SYSCLK)
Direct Memory Access (DMA)
Extended Memory DMA
The processors use direct memory access (DMA) to transfer
data within memory spaces or between a memory space and a
peripheral. The processors can specify data transfer operations
and return to normal processing while the fully integrated DMA
controller carries out the data transfers independent of proces-
sor activity.
Extended memory DMA supports various operating modes,
such as delay line (which allows processor reads and writes to
external delay line buffers and to the external memory), with
limited core interaction and scatter/gather DMA (writes to and
from noncontiguous memory blocks).
Cyclic Redundancy Check (CRC) Protection
DMA transfers can occur between memory and a peripheral or
between one memory and another memory. Each memory to
memory DMA stream uses two channels: the source channel
and the destination channel.
The cyclic redundancy check (CRC) protection modules allow
system software to calculate the signature of code, data, or both
in memory, the content of memory-mapped registers, or peri-
odic communication message objects. Dedicated hardware
circuitry compares the signature with precalculated values and
triggers appropriate fault events.
All DMA channels can transport data to and from all on-chip
and off-chip memories. Programs can use two types of DMA
transfers: descriptor-based or register-based. Register-based
DMA allows the processors to program DMA control registers
directly to initiate a DMA transfer. On completion, the DMA
control registers automatically update with original setup values
for continuous transfer. Descriptor-based DMA transfers
require a set of parameters stored within memory to initiate a
DMA sequence. Descriptor-based DMA transfers allow
multiple DMA sequences to be chained together. Program a
DMA channel to set up and start another DMA transfer auto-
matically after the current sequence completes.
For example, the system software initiates the signature calcula-
tion of the entire memory contents every 100 ms and compares
this with expected, precalculated values. If a mismatch occurs, a
fault condition is generated through the processor core or the
trigger routing unit.
The CRC is a hardware module based on a CRC32 engine that
computes the CRC value of the 32-bit data-words presented to
it. The source channel of the memory to memory DMA (in
memory scan mode) provides data. The data can be optionally
forwarded to the destination channel (memory transfer mode).
The main features of the CRC peripheral are as follows:
The DMA engine supports the following DMA operations:
• A single linear buffer that stops on completion
• Memory scan mode
• A linear buffer with negative, positive, or zero stride length
• Memory transfer mode
• A circular autorefreshing buffer that interrupts when each
buffer becomes full
• Data verify mode
• A similar circular buffer that interrupts on fractional buf-
fers, such as at the halfway point
• Data fill mode
• User-programmable CRC32 polynomial
• Bit and byte mirroring option (endianness)
• Fault and error interrupt mechanisms
• The 1D DMA uses a set of identical ping pong buffers
defined by a linked ring of two-word descriptor sets, each
containing a link pointer and an address
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• 1D and 2D fill block to initialize an array with constants
triggers). Slave endpoints can be configured to respond to trig-
gers in various ways. Common applications enabled by the TRU
include,
• 32-bit CRC signature of a block of memory or an MMR
block
• Automatically triggering the start of a DMA sequence after
a sequence from another DMA channel completes
Event Handling
The processors provide event handling that supports both nest-
ing and prioritization. Nesting allows multiple event service
routines to be active simultaneously. Prioritization ensures that
servicing a higher priority event takes precedence over servicing
a lower priority event.
• Software triggering
• Synchronization of concurrent activities
SECURITY FEATURES
The following sections describe the security features of the
ADSP-2156x processors.
The processors provide support for four different types of
events:
Cryptographic Hardware Accelerators
• An emulation event causes the processors to enter emula-
tion mode, allowing command and control of the
processors through the JTAG interface.
The ADSP-2156x processors support standards-based hardware
accelerated encryption, decryption, authentication, and true
random number generation.
• A reset event resets the processors.
Support for the hardware accelerated cryptographic ciphers
includes the following:
• An exception event occurs synchronously to program flow
(in other words, the exception is taken before the instruc-
tion is allowed to complete). Conditions triggered by the
SHARC+ core, such as data alignment (SIMD or long
word) or compute violations (fixed or floating point) and
illegal instructions, cause core exceptions. Conditions trig-
gered by the SEC, such as error correcting code (ECC),
parity, watchdog, or system clock, cause system exceptions.
• AES in ECB, CBC, ICM, and CTR modes with 128-bit,
192-bit, and 256-bit keys
• DES in ECB and CBC mode with 56-bit key
• 3DES in ECB and CBC mode with 3x 56-bit key
• ARC4 in stateful, stateless mode, up to 128-bit key
• An interrupt event occurs asynchronously to program
flow. Interrupts are caused by input signals, timers, and
other peripherals, as well as by an explicit software
instruction.
Support for the hardware accelerated hash functions includes
the following:
• SHA-1
• SHA-2 with 224-bit and 256-bit digests
• HMAC transforms for SHA-1 and SHA-2
• MD5
System Event Controller (SEC)
The SHARC+ core event controller receives interrupt requests
from the system event controller (SEC). The SEC features
include the following:
Public key accelerator (PKA) is available to offload computation
intensive public key cryptography operations.
• Comprehensive system event source management, includ-
ing interrupt enable, fault enable, priority, and source
grouping
Both a hardware-based nondeterministic random number gen-
erator and pseudorandom number generator are available.
• A distributed programming model where each system
event source control and all status fields are independent of
each other
Secure boot is also available with 224-bit and 256-bit elliptic
curve digital signatures ensuring integrity and authenticity of
the boot stream. Optionally, ensuring confidentiality through
AES-128 encryption is available.
• Determinism where all system events have the same propa-
gation delay and provide unique identification of a specific
system event source
Employ secure debug to allow only trusted users to access the
system with debug tools.
• A slave control port that provides access to all SEC registers
for configuration, status, and interrupt and fault services
CAUTION
• Global locking that supports a register level protection
model to prevent writes to locked registers
This product includes security features that can be
used to protect embedded nonvolatile memory
contents and prevent execution of unauthorized
code. When security is enabled on this device
(either by the ordering party or the subsequent
receiving parties), the ability of Analog Devices to
conduct failure analysis on returned devices is
limited. Contact Analog Devices for details on the
failure analysis limitations for this device.
• Fault management including fault action configuration,
time out, external indication, and system reset
Trigger Routing Unit (TRU)
The trigger routing unit (TRU) provides system-level sequence
control without core intervention. The TRU maps trigger
masters (generators of triggers) to trigger slaves (receivers of
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transparently. If enabled, dual-bit errors can issue a system
System Protection Unit (SPU)
event or fault. ECC protection is fully transparent to the user,
The system protection unit (SPU) guards against accidental or
unwanted access to an MMR space of the peripheral by provid-
ing a write protection mechanism. The user can choose and
configure the protected peripherals as well as configure which of
the three system MMR masters (SHARC+ core, memory DMA,
and Arm® CoreSightTM debug) the peripherals are guarded
against.
even if L2 memory is read or written by 8-bit or 16-bit entities.
Parity Protected Peripheral Memories
Parity protection is added to the following peripheral memories:
• ASRC
• IIR
The SPU is also part of the security infrastructure. Along with
providing write protection functionality, the SPU is employed
to define which resources in the system are secure or nonsecure
as well as block access to secure resources from nonsecure
masters.
• FIR
• CRYPTO
• MLB
• TRACE
System Memory Protection Unit (SMPU)
Cyclic Redundancy Check (CRC) Protected Memories
The system memory protection unit (SMPU) provides memory
protection against read and/or write transactions to defined
regions of memory. There are SMPU units in the ADSP-2156x
processors for each memory space, except for SHARC L1
memory.
Whereas parity bit and ECC protection mainly protect against
random soft errors in L1 and L2 memory cells, the CRC engines
can protect against systematic errors (pointer errors) and static
content (instruction code) of L1, L2, and even L3 memories
(DDR3, DDR3L). The processors feature two CRC engines that
are embedded in the memory to memory DMA controllers.
The SMPU is also part of the security infrastructure. It allows
the user to protect against arbitrary read and/or write transac-
tions and allows regions of memory to be defined as secure and
prevent nonsecure masters from accessing those memory
regions.
CRC checksums can be calculated or compared automatically
during memory transfers. Alternatively, single or multiple
memory regions can be continuously scrubbed by a single DMA
work unit as per DMA descriptor chain instructions. The CRC
engine also protects data loaded during the boot process.
SECURITY FEATURES DISCLAIMER
Signal Watchdogs
Analog Devices does not guarantee that the Security Features
described herein provide absolute security. ACCORDINGLY,
ANALOG DEVICES HEREBY DISCLAIMS ANY AND ALL
EXPRESS AND IMPLIED WARRANTIES THAT THE
SECURITY FEATURES CANNOT BE BREACHED,
COMPROMISED, OR OTHERWISE CIRCUMVENTED AND
IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR
ANY LOSS, DAMAGE, DESTRUCTION, OR RELEASE OF
DATA, INFORMATION, PHYSICAL PROPERTY, OR
INTELLECTUAL PROPERTY.
The 10 general-purpose timers feature modes to monitor off-
chip signals. The watchdog period mode monitors whether
external signals toggle with a period within an expected range.
The watchdog width mode monitors whether the pulse widths
of external signals are within an expected range. Both modes
help detect undesired toggling or lack of toggling of system level
signals.
System Event Controller (SEC)
Besides system events, the system event controller (SEC) further
supports fault management, including fault action configura-
tion as timeout, internal indication by system interrupt, or
external indication through the SYS_FAULT pin and system
reset.
SAFETY FEATURES
The ADSP-2156x processors are designed to support functional
safety applications. Whereas the level of safety is mainly domi-
nated by the system concept, the following primitives are
provided by the processors to build a robust safety concept.
Memory Error Controller (MEC)
Multiparity Bit Protected SHARC+ Core L1 Memories
The memory error controller (MEC) manages memory par-
ity/ECC errors and warnings from the cores and peripherals
and sends out interrupts and triggers.
In the SHARC+ core L1 memory space, whether SRAM or
cache, multiple parity bits protect each word to detect the single
event upsets that occur in all RAMs. Parity also protects the
cache tags and BTB.
Error Correcting Code (ECC) Protected L2 Memories
Error correcting code (ECC) corrects single event upsets. A sin-
gle error correct/double error detect (SEC/DED) code protects
the L2 memory. By default, ECC is enabled, but it can be dis-
abled on a per bank basis. Single-bit errors correct
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SPORT provides two transmit data signals, and the other half
SPORT provides two receive data signals. The frame sync and
clock are shared.
PROCESSOR PERIPHERALS
The following sections describe the peripherals of the ADSP-
2156x processors.
Serial ports operate in the following six modes:
• Standard DSP serial mode
• Multichannel time division multiplexing (TDM) mode
• I2S mode
Dynamic Memory Controller (DMC)
The 16-bit dynamic memory controller (DMC) interfaces to
• DDR3 (JESD79-3), 512 Mb to 8 Gb
• DDR3L (JESD79-3-1A), 512 Mb to 8 Gb
See Table 6 for the DMC memory map.
• Packed I2S mode
• Left justified mode
Digital Audio Interface (DAI)
• Right justified mode
The processors support two digital audio interface (DAI) units.
The DAI can connect various peripherals to any of the DAI
pins.
Asynchronous Sample Rate Converter (ASRC)
The asynchronous sample rate converter (ASRC) contains eight
ASRC blocks. The ASRC provides up to 140 dB signal-to-noise
ratio (SNR). The ASRC block performs synchronous or asyn-
chronous sample rate conversion across independent stereo
channels, without using internal processor resources. The ASRC
blocks can also be configured to operate together to convert
multichannel audio data without phase mismatches. Finally, the
ASRC can clean up audio data from jittery clock sources such as
the S/PDIF receiver.
The application code makes these connections using the signal
routing unit (SRU), shown in Figure 1.
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to interconnect
under software control. This functionality allows easy use of the
DAI associated peripherals for a wider variety of applications by
using a larger set of algorithms than is possible with nonconfig-
urable signal paths.
S/PDIF-Compatible Digital Audio Receiver/Transmitter
The DAI includes the peripherals described in the following sec-
tions (SPORTs, ASRC, S/PDIF, and PCG). DAI Pin Buffer 20
and DAI Pin Buffer 19 can change the polarity of the input sig-
nals. Most signals of the peripherals belonging to different DAIs
cannot be interconnected, with few exceptions.
The Sony/Philips Digital Interface Format (S/PDIF) is a stan-
dard audio data transfer format that allows the transfer of digital
audio signals from one device to another. There are two S/PDIF
transmit/receive blocks on the processor. The digital audio
interface carries three types of information: audio data, nonau-
dio data (compressed data), and timing information.
The DAI_PINx pin buffers may also be used as GPIO pins. DAI
input signals allow the triggering of interrupts on the rising
edge, falling edge, or both.
The S/PDIF interface supports one stereo channel or com-
pressed audio streams. The S/PDIF transmitter and receiver are
AES3 compatible and support the sample rate from 24 kHz to
192 kHz. The S/PDIF receiver supports professional jitter
standards.
See the ADSP-2156x SHARC+ Processor Hardware Reference
manual for complete information on the use of the DAIs and
SRUs.
Serial Port (SPORT)
The S/PDIF receiver/transmitter has no separate DMA chan-
nels. The S/PDIF transmitter receives audio data in serial format
and converts it into a biphase encoded signal. The serial data
input to the transmitter can be formatted as left justified, I2S, or
right justified with word widths of 16, 18, 20, or 24 bits. The
S/PDIF receiver converts a biphase encoded signal into I2S serial
format.The serial data, clock, and frame sync outputs/inputs
from/to the S/PDIF receiver/transmitter are routed through the
SRU. They can be connected to various peripherals, such as the
SPORTs, external pins, and the precision clock generators
(PCGs), and are controlled by the SRU control registers.
The processors feature eight synchronous serial ports
(SPORTs), providing an inexpensive interface to a wide variety
of digital and mixed-signal peripheral devices. These devices
include Analog Devices AD19xx and ADAU19xx families of
audio codecs, analog-to-digital converters (ADCs) and digital-
to-analog converters (DACs). Two data lines, a clock, and a
frame sync comprise a SPORT half. The data lines can be pro-
grammed to either transmit or receive data, and each SPORT
half has a dedicated DMA channel.
An individual SPORT module consists of two independently
configurable SPORT halves with identical functionality. Two
bidirectional data lines—primary (0) and secondary (1)—are
available per SPORT half and are configurable as either trans-
mitters or receivers. Therefore, each SPORT half permits two
unidirectional streams into or out of the same SPORT. This
bidirectional functionality provides greater flexibility for serial
communications. For full-duplex configuration, one half
Precision Clock Generators (PCG)
The precision clock generators (PCG) consist of four units: Unit
A and Unit B located in the DAI0 block, and Unit C and Unit D
located in the DAI1 block. The PCG can generate a pair of sig-
nals (clock and frame sync) derived from a clock input signal
(SCLK0, SYS_CLKIN0, or DAI pin buffer). Each unit can also
output to the pin buffers of the opposite DAI unit. All units are
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identical in functionality and operate independently of each
Octal Serial Peripheral Interface (OSPI) Port
other. The two signals generated by each unit are normally used
as a serial bit clock/frame sync pair.
The octal serial peripheral interface (OSPI) port provides an
increased external memory data bus width (up to eight bits in
parallel). The OSPI port supports DDR modes of operation,
which enable the transfer of up to 16 bits of data each clock
cycle. The OSPI port provides overall data throughput and per-
formance improvement, including faster boot time.
Universal Asynchronous Receiver/Transmitter
(UART) Ports
The processors provide full-duplex universal asynchronous
receiver/transmitter (UART) ports, fully compatible with PC
standard UARTs. Each UART port provides a simplified UART
interface to other peripherals or hosts, supporting full-duplex,
DMA supported, asynchronous transfers of serial data. A UART
port includes support for five to eight data bits as well as no par-
ity, even parity, or odd parity.
Features of the OSPI port include:
• Support for single-, dual-, quad-, or octal-I/O transfers
• Multiple modes of operation including direct and software
triggered instruction generator (STIG)
• Support for execute in place (XIP): continuous mode
• Programmable page and block sizes
• Programmable write protected regions
• Programmable memory timing
Optionally, an additional address bit can be transferred to inter-
rupt only addressed nodes in multidrop bus (MDB) systems. A
frame is terminated by a configurable number of stop bits.
The UART ports support automatic hardware flow control
through the clear to send (CTS) input and request to send (RTS)
output with programmable assertion first in, first out (FIFO)
levels.
• Support for DDR commands
Link Port (LP)
To help support the Local Interconnect Network (LIN) proto-
cols, a special command causes the transmitter to queue a break
command of programmable bit length into the transmit buffer.
Similarly, the number of stop bits can be extended by a pro-
grammable interframe space.
Two 8-bit wide link ports (LP) for the BGA package can connect
to the link ports of other DSPs or peripherals. Link ports are
bidirectional and have eight data lines, an acknowledge line, and
a clock line.
Timers
Serial Peripheral Interface (SPI) Ports
The processors include several timers that are described in the
following sections.
The processors have four industry-standard SPI-compatible
ports that allow the processors to communicate with multiple
SPI-compatible devices.
General-Purpose (GP) Timers (TIMER)
There is one general-purpose (GP) timer unit, providing 10
general-purpose programmable timers. Each timer has an exter-
nal pin that can be configured as PWM or timer output, as an
input to clock the timer, or as a mechanism for measuring pulse
widths and periods of external events. These timers can be syn-
chronized to an external clock input on the TM_TMR[n] pins,
an external TM_CLK input pin, or to the internal SCLK0.
The baseline SPI peripheral is a synchronous, 4-wire interface
consisting of two data pins, one device select pin, and a gated
clock pin. The two data pins allow full-duplex operation to
other SPI-compatible devices. An extra two (optional) data pins
are provided to support quad-SPI operation. Enhanced modes
of operation, such as flow control, fast mode, and dual-I/O
mode (DIOM), are also supported. DMA mode allows for trans-
ferring several words with minimal central processing unit
(CPU) interaction.
These timer units can be used in conjunction with the UARTs to
measure the width of the pulses in the data stream to provide a
software autobaud detect function for the respective serial
channels.
With a range of configurable options, the SPI ports provide a
glueless hardware interface with other SPI-compatible devices
in master mode, slave mode, and multimaster environments.
The SPI peripheral includes programmable baud rates, clock
phase, and clock polarity. The peripheral can operate in a
multimaster environment by interfacing with several other
devices, acting as either a master device or a slave device. In a
multimaster environment, the SPI peripheral uses open-drain
outputs to avoid data bus contention. The flow control features
enable slow slave devices to interface with fast master devices by
providing an SPI ready pin (SPI_RDY), which flexibly controls
the transfers.
The GP timers can generate interrupts to the processor core,
providing periodic events for synchronization to either the sys-
tem clock or to external signals. Timer events can also trigger
other peripherals via the TRU (for instance, to signal a fault).
Each timer can also be started and stopped by any TRU master
without core intervention.
Watchdog Timer (WDT)
Two on-chip software watchdog timers (WDT) can be used by
the SHARC+ core. A software watchdog can improve system
availability by forcing the processors to a known state, via a gen-
eral-purpose interrupt, or a fault, if the timer expires before
being reset by software.
The baud rate and clock phase and polarities of the SPI port are
programmable. The port has integrated DMA channels for both
transmit and receive data streams.
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The programmer initializes the count value of the timer, enables
HADC_VIN0
the appropriate interrupt, then enables the timer. Thereafter,
the software must reload the counter before it counts down to
HADC_VIN1
ADC SAMPLING CAP
zero from the programmed value, protecting the system from
HADC_VIN2
remaining in an unknown state where software that normally
HADC_VIN3
resets the timer stops running due to an external noise condi-
tion or software error.
General-Purpose Counters (CNT)
A 32-bit general-purpose counter (CNT) is provided that can
operate in general-purpose up/down count modes and can
sense 2-bit quadrature or binary codes as typically emitted by
industrial drives or manual thumbwheels. Count direction is
controlled by a level-sensitive input pin or by two edge
detectors.
HADC_REFN
Figure 5. Channel Multiplex of HADC Input Pins for BGA Package
Figure 6 shows the channel multiplex diagram for the HADC
input pins for the LQFP package (ADSP-21562, ADSP-21563,
and ADSP-21565).
A third counter input can provide flexible zero marker support
and can input the push button signal of thumbwheel devices. All
three CNT0 pins have a programmable debouncing circuit.
Internal signals forwarded to a GP timer enable the timer to
measure the intervals between count events. Boundary registers
enable auto-zero operation or simple system warning by inter-
rupts when programmed count values are exceeded.
HADC_VIN0
HADC_VIN1
ADC SAMPLING CAP
Housekeeping Analog-to-Digital Converter (HADC)
The housekeeping analog-to-digital converter (HADC) pro-
vides a general-purpose, multichannel successive
approximation ADC. It supports the following set of features:
• 12-bit ADC core with built in sample and hold.
HADC_REFN
• Four single-ended input channels for the BGA package;
two single-ended input channels for the LQFP package.
Figure 6. Channel Multiplex of HADC Input Pins for LQFP Package
• Throughput rates up to 1 MSPS.
Figure 7 shows the input impedance of the HADC, represented
with internal resistance and capacitance. The VIN signal rep-
resents the HADC input pins (HADC_VINx).
• Single external reference with analog inputs between
0 V and 1.8 V.
• Selectable ADC clock frequency including the ability to
program a prescaler.
MAX RESISTANCE (INCLUDING CHANNEL-MUX)
• Adaptable conversion type; allows single or continuous
conversion with option of autoscan.
1kȍ
VIN
• Autosequencing capability with up to four autoconversions
in a single session. Each conversion can be programmed to
select one to four input channels.
PIN + PAD
2.5pF
ADC SAMPLING CAP
10pF
• Four data registers for the BGA package and two data regis-
ters for the LQFP package (all individually addressable) to
store conversion values.
Figure 7. HADC Internal Circuit Schematic
Figure 5 shows the channel multiplex diagram for the HADC
input pins for the BGA package (ADSP-21566, ADSP-21567,
and ADSP-21569).
Media Local Bus (MediaLB)
The automotive models have a MediaLB (MLB) slave interface
that allows the processors to function as a media local bus
device. It includes support for 3-pin media local bus protocols.
The MLB 3-pin configuration supports speeds up to 1024 × FS.
The MLB also supports up to 64 logical channels with up to
468 bytes of data per MLB frame.
The MLB interface supports MOST25, MOST50, and MOST150
data rates and operates in slave mode only.
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2-Wire Controller Interface (TWI)
SYSTEM ACCELERATION
The processors include 2-wire interface (TWI) modules that
provide a simple exchange method of control data between mul-
tiple devices. The TWI module is compatible with the widely
used I2C bus standard. The TWI module offers the capabilities
of simultaneous master and slave operation and support for
both 7-bit addressing and multimedia data arbitration. The
TWI interface utilizes two pins for transferring clock
(TWI_SCL) and data (TWI_SDA) and supports the protocol at
speeds up to 400 kbps. The TWI interface pins are compatible
with 3.3 V logic levels.
The following sections describe the system acceleration blocks
of the ADSP-2156x processors.
Finite Impulse Response (FIR) Accelerator
The finite impulse response (FIR) accelerator consists of a
1024 word coefficient memory, a 1024 word deep delay line for
the data, and four multiplier-accumulator (MAC) units. A con-
troller manages the accelerator. The FIR accelerator runs at the
core clock frequency. The FIR accelerator can access all memory
spaces and can run concurrently with the IIR accelerator on the
processor.
Additionally, the TWI module is fully compatible with serial
camera control bus (SCCB) functionality for easier control of
various CMOS camera sensor devices.
Infinite Impulse Response (IIR) Accelerator
The infinite impulse response (IIR) accelerator consists of a
1440 word coefficient memory for storage of biquad coeffi-
cients, a data memory for storing the intermediate data, and one
MAC unit. A controller manages the accelerator. The IIR
accelerator runs at the core clock frequency. The IIR accelerator
can access all memory spaces and run concurrently with the
other accelerators on the processor.
General-Purpose I/O (GPIO)
Each general-purpose port pin can be individually controlled by
manipulating the port control, status, and interrupt registers:
• The GPIO direction control register specifies the direction
of each individual GPIO pin as input or output.
• GPIO control and status registers have a write-one-to-
modify mechanism that allows any combination of individ-
ual GPIO pins to be modified in a single instruction,
without affecting the level of any other GPIO pins.
In addition to operating at core clock, the FIR/IIR accelerators
support various enhanced features, including the ability to halt
the accelerator for dynamic queuing of unlimited FIR/IIR chan-
nels, selective interrupt generation for each channel, and trigger
master/slave support.
• GPIO interrupt mask registers allow each individual GPIO
pin to function as an interrupt to the processors. GPIO pins
defined as inputs can be configured to generate hardware
interrupts, whereas output pins can be triggered by soft-
ware interrupts.
SYSTEM DESIGN
The following sections provide an introduction to system design
features and power supply issues.
• GPIO interrupt sensitivity registers specify whether indi-
vidual pins are level or edge sensitive and specify, if edge
sensitive, whether the rising edge or both the rising and
falling edges of the signal are significant.
Clock Management
The processors provide three operating modes, each with a dif-
ferent performance and power profile. Control of clocking to
each of the processor peripherals reduces power consumption.
The processors do not support any low power operation modes.
Control of clocking to each of the processor peripherals can
reduce the power consumption.
Pin Interrupts
Every port pin on the processors can request interrupts in either
an edge sensitive or a level sensitive manner with programmable
polarity. Interrupt functionality is decoupled from GPIO opera-
tion. Three system-level interrupt channels (PINT0–PINT2) are
reserved for this purpose. Each of these interrupt channels can
manage up to 32 interrupt pins. The assignment from pin to
interrupt is not performed on a pin by pin basis. Rather, groups
of eight pins (half ports) are flexibly assigned to interrupt
channels.
Reset Control Unit (RCU)
Reset is the initial state of the whole processor, or the core, and
is the result of a hardware or software triggered event. In this
state, all control registers are set to default values and functional
units are idle. Exiting a full system reset begins with the core
ready to boot.
Every pin interrupt channel features a special set of 32-bit mem-
ory-mapped registers that enable half port assignment and
interrupt management. This functionality includes masking,
identification, and clearing of requests. These registers also
enable access to the respective pin states and use of the interrupt
latches, regardless of whether the interrupt is masked. Most
control registers feature multiple MMR address entries to write-
one-to-set or write-one-to-clear them individually.
The reset control unit (RCU) controls how all the functional
units enter and exit reset. Differences in functional require-
ments and clocking constraints define how reset signals are
generated. Programs must guarantee that none of the reset
functions put the system into an undefined state or cause
resources to stall. This requirement is particularly important
when the core resets (programs must ensure that there is no
pending system activity involving the core when it is reset).
From a system perspective, reset is defined by both the reset tar-
get and the reset source.
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The reset target is defined as the following:
SHARC® PROCESSOR
• System reset—all functional units except the RCU are set to
default states.
TO PLL
CIRCUITRY
• Hardware reset—all functional units are set to default states
without exception. History is lost.
• Core only reset—affects the core only. When in reset state,
the core is not accessed by any bus master.
SYS_CLKIN0
ꢃꢄꢄNȍ*
SYS_XTAL0
The reset source is defined as the following:
• System reset—can be triggered by software (writing to the
RCU_CTL register) or by another functional unit, such as
the dynamic power management (DPM) unit or any of the
SEC, TRU, or emulator inputs.
ꢀꢁꢂNȍ*
27pF*
27pF*
• Hardware reset—the SYS_HWRST input signal asserts
active (pulled down).
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING
ON THE CRYSTAL AND LAYOUT. ANALYZE CAREFULLY. VALID
FREQUENCY RANGE IS 20 MHz TO 30 MHz FOR SYS_CLKIN0.
• Core only reset—can be triggered by software (writing to
the RCU_CTL register).
Figure 8. External Crystal Connection
• Trigger request (peripheral).
For fundamental frequency operation, use the circuit shown in
Figure 8. A parallel resonant, fundamental frequency, micro-
processor grade crystal is connected across the SYS_CLKIN0
pin and the SYS_XTAL0 pin.
Clock Generation Unit (CGU)
The ADSP-2156x processors support two independent PLLs.
Each PLL is part of a clock generation unit (CGU). Each CGU is
driven externally by the same clock source, thus providing flexi-
bility in determining the internal clocking frequencies for each
clock domain.
The two capacitors and the series resistor, shown in Figure 8,
fine tune phase and amplitude of the sine frequency. The capac-
itor and resistor values shown in Figure 8 are typical values
only. The capacitor values are dependent upon the load
capacitance recommendations of the crystal manufacturer and
the physical layout of the printed circuit board (PCB). The resis-
tor value depends on the drive level specified by the crystal
manufacturer. The user must verify the customized values based
on careful investigations on multiple devices over the required
temperature range.
Frequencies generated by each CGU are derived from a com-
mon multiplier with different divider values available for each
output.
The CGU generates all on-chip clocks and synchronization sig-
nals. Multiplication factors are programmed to define the
PLLCLK frequency.
Programmable values divide the PLLCLK frequency to generate
the core clock (CCLK), the system clocks, the DDR3/DDR3L
clock (DCLK), and the output clock (OCLK). For more infor-
mation on clocking, see the ADSP-2156x SHARC+ Processor
Hardware Reference manual.
Clock Distribution Unit (CDU)
The two clock generation units each provide outputs that feed a
clock distribution unit (CDU). The clock outputs
CLKO0–CLKO1 and the clock generation unit outputs are con-
nected to various targets. For more information, refer to the
ADSP-2156x SHARC+ Processor Hardware Reference manual.
Writing to the CGU control registers does not affect the behav-
ior of the PLL immediately. Registers are first programmed with
a new value and the PLL logic executes the changes to ensure a
smooth transition from the current conditions to the new
conditions.
Clock Out/External Clock
The SYS_CLKOUT output pin has programmable options to
output divided down versions of the on-chip clocks. By default,
the SYS_CLKOUT pin drives a buffered version of the
SYS_ CLKIN0 input. Refer to the ADSP-2156x SHARC+ Pro-
cessor Hardware Reference manual to change the default
mapping of clocks.
System Crystal Oscillator
The processor can be clocked by an external crystal (see
Figure 8), a sine wave input, or a buffered, shaped clock derived
from an external clock oscillator. If using an external clock, it
must be compatible with the VIHCLKIN and VILCLKIN specifica-
tions and must not be halted, changed, or operated below the
specified frequency during normal operation (see the Operating
Conditions section). When using an external clock, the clock
signal is connected to the SYS_CLKIN0 pin of the processor and
the SYS_XTAL0 pin must be left unconnected. Alternatively,
because the processor includes an on-chip oscillator circuit, an
external crystal can be used.
Booting
The processors have several mechanisms for automatically load-
ing internal and external memory after a reset. The boot mode is
defined by the SYS_BMODE[n] input pins. There are two cate-
gories of boot modes. In master boot mode, the processors
actively load data from serial memories. In slave boot modes,
the processors receive data from external host devices.
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The boot modes are shown in Table 7. These modes are imple-
The power dissipated by a processor is largely a function of the
clock frequency and the square of the operating voltage. For
example, reducing the clock frequency by 25% results in a 25%
reduction in dynamic power dissipation.
mented by the SYS_BMODE[n] bits of the reset configuration
register and are sampled during power-on resets and software
initiated resets.
Table 7. Boot Modes
Table 8. Power Domains
SYS_BMODE[n] Setting1
Boot Mode
No boot
Power Domain
All Internal Logic
DDR3/DDR3L
HADC/TMU
VDD Range
VDD_INT
000
001
010
011
100
1012
110
111
SPI2 master
SPI2 slave
VDD_DMC
VDD_ANA
UART0 slave
Link0 slave
Octal SPI master
Reserved
All Other I/O (Includes SYS, JTAG, and VDD_EXT
Ports Pins Except SYS_CLKIN0)
1
SYS_CLKIN0
VDD_REF
1 VDD_REF requires a minimum of 10 nF and 100 nF decoupling capacitance to
meet source/sink requirements.
Reserved
1 SYS_BMODE2 pin is applicable only for the BGA package.
2 Though octal SPI master boot is not supported on the LQFP package, it is
available through the ROM API.
Power-Up and Power-Down Sequencing
At all times (including during power-up/power-down sequenc-
ing), the VDD_REF, VDD_ANA, and VDD_EXT supplies must
stay within the VDELTA_EXT_REF specification listed in the Oper-
ating Conditions table. SYS_XTAL0 oscillations (SYS_CLKIN0)
start when power is applied to the VDD_REF pins. The rising
edge of SYS_HWRST initiates the PLL locking sequence. The
rising edge of SYS_HWRST must occur after all voltage supplies
and SYS_CLKIN0 oscillations are valid. For further details and
information, see the Power-Up Reset Timing section.
In the ADSP-2156x processors, the SHARC+ core controls the
boot process, including loading all internal and external mem-
ory. The option for secure boot is available on all models.
Thermal Monitoring Unit (TMU)
The thermal monitoring unit (TMU) provides on-chip tem-
perature measurement for applications that require substantial
power consumption. The TMU is integrated into the processor
die and digital infrastructure using an MMR-based system
access to measure the die temperature variations in real-time.
Target Board JTAG Emulator Connector
The Analog Devices DSP tools product line of JTAG emulators
uses the IEEE 1149.1 JTAG test access port of the processors to
monitor and control the target board processor during emula-
tion. The Analog Devices DSP tools product line of JTAG
emulators provides emulation at full processor speed, allowing
inspection and modification of memory, registers, and proces-
sor stacks. The processor JTAG interface ensures the emulator
does not affect target system loading or timing.
TMU features include the following:
• On-chip temperature sensing
• Programmable over temperature and under temperature
limits
• Programmable conversion rate
• Averaging feature available
For information on JTAG emulator operation, see the appropri-
ate emulator hardware user’s guide at SHARC Processors
Software and Tools.
Power Supplies
The processors have separate power supply connections for
• Internal (VDD_INT)
SYSTEM DEBUG
• External I/O (VDD_EXT)
The processors include various features that allow easy system
debug. These are described in the following sections.
• External I/O Reference (VDD_REF)
• HADC/TMU (VDD_ANA)
• DMC (VDD_DMC)
System Watchpoint Unit (SWU)
The system watchpoint unit (SWU) is a single module that con-
nects to a single system bus and provides transaction
monitoring. One SWU is attached to the bus going to each
system slave. The SWU provides ports for all system bus address
channel signals. Each SWU contains four match groups of
registers with associated hardware. These four SWU match
groups operate independently but share common event (for
example, interrupt and trigger) outputs.
Power Management
As shown in Table 8, the processors support five different power
domains, which maximizes flexibility while maintaining com-
pliance with industry standards and conventions.
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When a SOM board is mounted to a SOM carrier board,
Debug Access Port (DAP)
embedded system evaluation can be performed. The EZ-KIT
SOM carrier board provides an evaluation platform for various
system peripherals including audio, S/PDIF, CAN, MLB, USB,
10/100/1000 Ethernet, and A2B, as well as an OSPI flash mem-
ory. The EZ-KIT SOM carrier board also features the USB
Debug Agent, which allows for debug and evaluation of the full
system (including the processor/memory on the SOM module)
without an emulator.
The debug access port (DAP) provides IEEE 1149.1 JTAG inter-
face support through the JTAG debug. The DAP provides an
optional instrumentation trace for both the core and system. It
provides a trace stream that conforms to MIPI System Trace
Protocol version 2 (STPv2).
DEVELOPMENT TOOLS
Analog Devices supports its processors with a complete line of
software and hardware development tools, including an inte-
grated development environment, evaluation products,
emulators, and a variety of software add-ins.
For further information, see:
• www.analog.com/cces
• www.analog.com/EV-21569-SOM
• www.analog.com/EV-SOMCRR-EZKIT
Integrated Development Environments (IDEs)
For C/C++ software writing and editing, code generation, and
debug support, Analog Devices offers the CrossCore® Embed-
ded Studio (CCES) integrated development environment (IDE).
Software Add-Ins for CCES
Analog Devices offers software add-ins which seamlessly inte-
grate with CCES to extend the capabilities and reduce
development time. Add-ins include BSPs for evaluation hard-
ware, various middleware packages, and algorithmic modules.
Documentation, help, configuration dialogs, and coding exam-
ples present in these add-ins are viewable through the CCES
IDE upon add-in installation.
CCES is based on the Eclipse framework. Supporting most Ana-
log Devices processor families, CCES is the IDE of choice for
processors, including multicore devices.
CCES seamlessly integrates available software add-ins to sup-
port real-time operating systems, file systems, TCP/IP stacks,
USB stacks, algorithmic software modules, and evaluation hard-
ware board support packages (BSPs). For more information,
visit www.analog.com/cces.
Board Support Packages (BSPs) for Evaluation Hardware
Software support for the EZ-KIT evaluation systems is provided
by software add-ins called board support packages (BSPs). The
BSPs contain the required drivers, pertinent release notes, and
select example code for the given evaluation hardware. A down-
load link for a specific BSP is located on the web page for the
associated SOM product.
EZ-KIT Evaluation System
For processor evaluation, Analog Devices provides an EZ-KIT®
evaluation system (EV-21569-EZKIT), which is a bundle com-
prised of a System on Module (SOM) board (EV-21569-SOM)
and an EZ-KIT SOM carrier board (EV-SOMCRR-EZKIT).
Middleware Packages
SOM boards are small and low cost. The EV-21569-SOM board
has the ADSP-21569 processor, SDRAM and QSPI flash memo-
ries, JTAG debug connection, FTDI USB-to-UART, and USB
power. SOM boards can be used alone or in combination with a
SOM carrier board. SOM carrier boards have high speed con-
nectors for the SOM, a comprehensive set of peripherals, and an
on-board emulator. Each SOM carrier board also comes with a
power supply.
Analog Devices offers middleware add-ins such as real-time
operating systems, file systems, USB stacks, and TCP/IP stacks.
For more information, see the Operating Systems and Middle-
ware page.
Algorithmic Modules
To speed development, Analog Devices offers add-ins that per-
form popular audio and video processing algorithms. These are
available for use with CCES. For more information, visit the
Design Center.
The USB controller on the SOM carrier board connects to the
USB port of the user’s PC, enabling CCES to emulate the on-
board processor in circuit. This permits users to download, exe-
cute, and debug programs. It also supports in-circuit
programming of the on-board flash memory device to store
user-specific boot code, enabling standalone operation.
Designing an Emulator-Compatible DSP Board (Target)
For embedded system test and debug, Analog Devices provides
a family of emulators. On each JTAG DSP, Analog Devices sup-
plies an IEEE 1149.1 JTAG test access port (TAP). In-circuit
emulation is facilitated by use of this JTAG interface. The
emulator accesses the internal features of the processor via the
TAP, allowing the developer to load code, set breakpoints, and
view variables, memory, and registers.
Each EZ-KIT purchased includes an evaluation license for
CCES. The CCES evaluation license type restricts CCES features
to specific evaluation systems. With the full CCES license type
(sold separately), engineers can develop software for any of the
CCES-supported evaluation boards (including the SOM when
used standalone or when connected to a different carrier board)
or any custom system designed around supported Analog
Devices processors. The full CCES license type also enables use
of ICE-2000 or ICE-1000 emulators for higher performance
debugging via JTAG.
The processor must be halted to send data and commands, but
after an operation is completed by the emulator, the DSP system
is set to run at full speed with no impact on system timing. The
emulators require the target board to include a header that sup-
ports connection of the JTAG port of the DSP to the emulator.
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For details on target board design issues including mechanical
layout, single processor connections, signal buffering, signal ter-
mination, and emulator pod logic, see Analog Devices JTAG
Emulation Technical Reference (EE-68).
ADDITIONAL INFORMATION
This data sheet provides a general overview of the ADSP-2156x
architecture and functionality. For detailed information on the
core architecture and instruction set, refer to the SHARC+ Core
Programming Reference.
RELATED SIGNAL CHAINS
A signal chain is a series of signal conditioning electronic com-
ponents that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with the
output of one portion of the chain supplying input to the next.
Signal chains are often used in signal processing applications to
gather and process data or to apply system controls based on
analysis of real-time phenomena.
Analog Devices eases signal processing system development by
providing signal processing components that are designed to
work together. A tool for viewing relationships between specific
applications and related components is available at
www.analog.com\circuits.
The application signal chains page in the Circuits from the Lab®
site (www.analog.com\circuits) provides the following:
• Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications
• Drill down links for components in each chain to selection
guides and application information
• Reference designs applying best practice design techniques
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ADSP-2156x DETAILED SIGNAL DESCRIPTIONS
Table 9 provides a detailed description of each pin.
Table 9. ADSP-2156x Detailed Signal Descriptions
Signal Name
C0_FLG[n]
CNT_DG
Direction
InOut
Description
SHARC Core 0 Flag Pin.
Input
Count Down and Gate. Depending on the mode of operation, this input acts either as a count down
signal or a gate signal.
Count down—this input causes the GP counter to decrement.
Gate—stops the GP counter from incrementing or decrementing.
CNT_UD
Input
Count Up and Direction. Depending on the mode of operation, this input acts either as a count up
signal or a direction signal.
Count up—this input causes the GP counter to increment.
Direction—selects whether the GP counter is incrementing or decrementing.
CNT_ZM
Input
InOut
Count Zero Marker. Input that connects to the zero marker output of a rotary device or detects the
pressing of a pushbutton.
DAI_PIN[nn]
Pin n. The digital applications interface (DAI0) connects various peripherals to any of the DAI0_PINxx
pins. Programs make these connections using the signal routing unit (SRU).
DMC_A[nn]
DMC_BA[n]
Output
Output
Address n. Address bus.
Bank Address n. Defines which internal bank an activate, read, write, or precharge command is
applied to on the dynamic memory. Bank Address n also defines which mode registers (MR, EMR,
EMR2, and/or EMR3) load during the load mode register command.
DMC_CAS
Output
Column Address Strobe. Defines the operation for external dynamic memory to perform in
conjunction with other DMC command signals. Connect to the CAS input of dynamic memory.
DMC_CK
Output
Output
Output
Output
InOut
Clock. Outputs DCLK to external dynamic memory.
DMC_CK
Clock (Complement). Complement of DMC_CK.
DMC_CKE
DMC_CS[n]
DMC_DQ[nn]
DMC_LDM
Clock Enable. Active high clock enable. Connects to the CKE input of the dynamic memory.
Chip Select n. Commands are recognized by the memory only when this signal is asserted.
Data n. Bidirectional data bus.
Output
Data Mask for Lower Byte. Mask for DMC_DQ07:DMC_DQ00 write data when driven high. Sampled
on both edges of the data strobe by the dynamic memory.
DMC_LDQS
InOut
Data Strobe for Lower Byte. DMC_DQ07:DMC_DQ00 data strobe. Output with write data. Input with
read data. Can be single-ended or differential depending on register settings.
DMC_LDQS
DMC_ODT
InOut
Data Strobe for Lower Byte (Complement). Complement of DMC_LDQS.
Output
On Die Termination. Enables dynamic memory termination resistances when driven high (assuming
the memory is properly configured). ODT is enabledor disabled regardless of read or write commands.
DMC_RAS
Output
Row Address Strobe. Defines the operation for external dynamic memory to perform in conjunction
with other DMC command signals. Connect to the RAS input of dynamic memory.
DMC_RESET
DMC_RZQ
DMC_UDM
Output
InOut
Reset.
External Calibration Resistor Connection.
Output
Data Mask for Upper Byte. Mask for DMC_DQ15:DMC_DQ08 write data when driven high. Sampled
on both edges of the data strobe by the dynamic memory.
DMC_UDQS
InOut
Data Strobe for Upper Byte. DMC_DQ15:DMC_DQ08 data strobe. Output with write data. Input with
read data. Can be single-ended or differential depending on register settings.
DMC_UDQS
DMC_VREF
DMC_WE
InOut
Input
Data Strobe for Upper Byte (Complement). Complement of DMC_UDQS.
Voltage Reference. Connects to half of the VDD_DMC voltage. Applies to the DMC0_VREF pins.
Output
Write Enable. Defines the operation for external dynamic memory to perform in conjunction with
other DMC command signals. Connect to the WE input of dynamic memory.
HADC_EOC_DOUT
Output
End of Conversion/Serial Data Out. Transitions high for one cycle of the HADC internal clock at the
end of every conversion. Alternatively, HADC serial data out can be seen by setting the appropriate
bit in HADC_CTL.
Rev. B
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Table 9. ADSP-2156x Detailed Signal Descriptions (Continued)
Signal Name
HADC_VIN[n]
HADC_VREFN
Direction
Input
Description
Analog Input at Channel n. Analog voltage inputs for digital conversion.
Input
Ground Reference for ADC. Connect to an external voltage reference that meets data sheet
specifications.
HADC_VREFP
Input
External Reference for ADC. Connect to an external voltage reference that meets data sheet
specifications.
JTG_TCK
JTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
LP_ACK
Input
Input
Output
Input
Input
InOut
JTAG Clock. JTAG test access port clock.
JTAG Serial Data In. JTAG test access port data input.
JTAG Serial Data Out. JTAG test access port data output.
JTAG Mode Select. JTAG test access port mode select.
JTAG Reset. JTAG test access port reset.
Acknowledge. Provides handshaking. When the link port is configured as a receiver, LP_ACK is an
output. When the link port is configured as a transmitter, LP_ACK is an input.
LP_CLK
InOut
Clock. When the link port is configured as a receiver, LP_CLK is an input. When the link port is
configured as a transmitter, LP_CLK is an output.
LP_D[n]
InOut
InOut
InOut
InOut
Output
InOut
InOut
InOut
InOut
InOut
InOut
InOut
Data n. Data bus. Input when receiving, output when transmitting.
Single-Ended Clock.
MLB_CLK
MLB_DAT
MLB_SIG
OSPI_CLK
OSPI_D2
OSPI_D3
OSPI_D4
OSPI_D5
OSPI_D6
OSPI_D7
OSPI_MISO
Single-Ended Data.
Single-Ended Signal.
SPI Master Clock Output. SPI master clock output.
Data 2. Transfers serial data in quad and octal modes.
Data 3. Transfers serial data in quad and octal modes.
Data 4. Transfers serial data in octal mode.
Data 5. Transfers serial data in octal mode.
Data 6. Transfers serial data in octal mode.
Data 7. Transfers serial data in octal mode.
Master In, Slave Out. Transfers serial data. Operates in the same direction as SPI_MOSI in dual and
quad modes.
OSPI_MOSI
InOut
Master Out, Slave In. Transfers serial data. Operates in the same direction as SPI_MISO in dual and
quad modes.
OSPI_SEL[n]
P_[nn]
Output
InOut
Slave Select Output n. Used in master mode to enable the desired slave.
Position n. General-purpose input/output. See the ADSP-2156x SHARC+ Processor Hardware
Reference manual for programming information.
SPI_CLK
SPI_D2
Output
InOut
InOut
InOut
SPI Master Clock Output. SPI master clock output.
Data 2. Transfers serial data in quad modes.
SPI_D3
Data 3. Transfers serial data in quad modes. Open-drain when ODM mode is enabled.
SPI_MISO
Master In, Slave Out. Transfers serial data. Operates in the same direction as SPI_MOSI in dual and
quad modes. Open-drain when ODM mode is enabled.
SPI_MOSI
InOut
Master Out, Slave In. Transfers serial data. Operates in the same direction as SPI_MISO in dual and
quad modes. Open-drain when ODM mode is enabled.
SPI_RDY
SPI_SEL[n]
SPI_SS
InOut
Output
Input
Ready. Optional flow signal. Output in slave mode, input in master mode.
Slave Select Output n. Used in master mode to enable the desired slave.
Slave Select Input.
Slave mode—acts as the slave select input.
Master mode—optionally serves as an error detection input for the SPI when there are multiple
masters.
SPT_ACLK
SPT_AD0
InOut
InOut
Channel A Clock. Data and frame sync are driven or sampled with respect to this clock. This signal
can be either internally or externally generated.
Channel A Data 0. Primary bidirectional data I/O. This signal can be configured as an output to
transmit serial data or as an input to receive serial data.
Rev. B
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Table 9. ADSP-2156x Detailed Signal Descriptions (Continued)
Signal Name
Direction
Description
SPT_AD1
InOut
Channel A Data 1. Secondary bidirectional data I/O. This signal can be configured as an output to
transmit serial data or as an input to receive serial data.
SPT_AFS
SPT_ATDV
SPT_BCLK
SPT_BD0
SPT_BD1
SPT_BFS
InOut
Output
InOut
InOut
InOut
InOut
Output
Channel A Frame Sync. The frame sync pulse initiates shifting of serial data. This signal is either
generated internally or externally.
Channel A Transmit Data Valid. This signal is optional and only active when SPORT is configured in
multichannel transmit mode. It is asserted during enabled slots.
Channel B Clock. Data and frame sync are driven or sampled with respect to this clock. This signal
can be either internally or externally generated.
Channel B Data 0. Primary bidirectional data I/O. This signal can be configured as an output to
transmit serial data or as an input to receive serial data.
Channel B Data 1. Secondary bidirectional data I/O. This signal can be configured as an output to
transmit serial data or as an input to receive serial data.
Channel B Frame Sync. The frame sync pulse initiates shifting of serial data. This signal is either
generated internally or externally.
SPT_BTDV
Channel B Transmit Data Valid. This signal is optional and only active when SPORT is configured in
multichannel transmit mode. It is asserted during enabled slots.
SYS_BMODE[n]
SYS_CLKIN0
Input
Boot Mode Control n. Selects the boot mode of the processor.
Input
Clock/Crystal Input.
SYS_CLKOUT
Output
Processor Clock Output. Outputs internal clocks. Clocks may be divided down. See the ADSP-2156x
SHARC+ Processor Hardware Reference manual for more details.
SYS_FAULT
SYS_FAULT
InOut
InOut
Active, High, Fault Output. Indicates internal faults or senses external faults depending on the
operating mode.
Active, Low, Fault Output. Indicates internal faults or senses external faults depending on the
operating mode.
SYS_HWRST
SYS_RESOUT
SYS_XTAL0
TM_ACI[n]
TM_ACLK[n]
TM_CLK
Input
Processor Hardware Reset Control. Resets the device when asserted.
Reset Output. Indicates the device is in the reset state.
Crystal Output.
Output
Output
Input
Alternate Capture Input n. Provides an additional input for WIDCAP, WATCHDOG, and PININT modes.
Alternate Clock n. Provides an additional time base for an individual timer.
Clock. Provides an additional global time base for all GP timers.
Timer n. The main input/output signal for each timer.
Trace Clock. Clock output.
Input
Input
TM_TMR[n]
TRACE_CLK
TRACE_D[nn]
TWI_SCL
InOut
Output
Output
InOut
InOut
Input
Trace Data n. Unidirectional data bus.
Serial Clock. Clock output when master, clock input when slave.
Serial Data. Receives or transmits data.
TWI_SDA
UART_CTS
UART_RTS
UART_RX
Clear to Send. Flow control signal.
Output
Input
Request to Send. Flow control signal.
Receive. Receives input. Typically connects to a transceiver that meets the electrical requirements of
the device with which it is communicating.
UART_TX
Output
Transmit. Transmits output. Typically connects to a transceiver that meets the electrical requirements
of the device with which it is communicating.
Rev. B
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400-BALL CSP_BGA SIGNAL DESCRIPTIONS
The processor pin definitions are shown in Table 10 for the
400-ball CSP_BGA package. The columns in this table provide
the following information:
• The pin name column identifies the name of the package
pin (at power-on reset) on which the signal is located (if a
single function pin) or is multiplexed (if a general-purpose
I/O pin).
• The signal name column includes the signal name for every
pin and the GPIO multiplexed pin function, where
applicable.
• The DAI pins and their associated signal routing units
(SRUs) connect inputs and outputs of the DAI peripherals
(SPORT, ASRC, S/PDIF, and PCG). See the ADSP-2156x
SHARC+ Processor Hardware Reference manual for com-
plete information on the use of the DAI and SRUs.
• The description column provides a descriptive name for
each signal.
• The port column shows whether a signal is multiplexed
with other signals on a general-purpose I/O port pin.
Table 10. ADSP-2156x 400-Ball CSP_BGA Signal Descriptions
Signal Name
C0_FLG0
Description
SHARC Core 0 Flag Pin
SHARC Core 0 Flag Pin
SHARC Core 0 Flag Pin
SHARC Core 0 Flag Pin
CNT0 Count Down and Gate
CNT0 Count Up and Direction
CNT0 Count Zero Marker
DAI0 Pin 1
Port
Pin Name
PA_12
A
C0_FLG1
A
PA_13
C0_FLG2
B
PB_03
C0_FLG3
B
PB_02
CNT0_DG
B
PB_05
CNT0_UD
B
PB_03
CNT0_ZM
B
PB_04
DAI0_PIN01
DAI0_PIN02
DAI0_PIN03
DAI0_PIN04
DAI0_PIN05
DAI0_PIN06
DAI0_PIN07
DAI0_PIN08
DAI0_PIN09
DAI0_PIN10
DAI0_PIN11
DAI0_PIN12
DAI0_PIN19
DAI0_PIN20
DAI1_PIN01
DAI1_PIN02
DAI1_PIN03
DAI1_PIN04
DAI1_PIN05
DAI1_PIN06
DAI1_PIN07
DAI1_PIN08
DAI1_PIN09
DAI1_PIN10
DAI1_PIN11
DAI1_PIN12
DAI1_PIN19
DAI1_PIN20
DMC0_A00
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
DAI0_PIN01
DAI0_PIN02
DAI0_PIN03
DAI0_PIN04
DAI0_PIN05
DAI0_PIN06
DAI0_PIN07
DAI0_PIN08
DAI0_PIN09
DAI0_PIN10
DAI0_PIN11
DAI0_PIN12
DAI0_PIN19
DAI0_PIN20
DAI1_PIN01
DAI1_PIN02
DAI1_PIN03
DAI1_PIN04
DAI1_PIN05
DAI1_PIN06
DAI1_PIN07
DAI1_PIN08
DAI1_PIN09
DAI1_PIN10
DAI1_PIN11
DAI1_PIN12
DAI1_PIN19
DAI1_PIN20
DMC0_A00
DAI0 Pin 2
DAI0 Pin 3
DAI0 Pin 4
DAI0 Pin 5
DAI0 Pin 6
DAI0 Pin 7
DAI0 Pin 8
DAI0 Pin 9
DAI0 Pin 10
DAI0 Pin 11
DAI0 Pin 12
DAI0 Pin 19
DAI0 Pin 20
DAI1 Pin 1
DAI1 Pin 2
DAI1 Pin 3
DAI1 Pin 4
DAI1 Pin 5
DAI1 Pin 6
DAI1 Pin 7
DAI1 Pin 8
DAI1 Pin 9
DAI1 Pin 10
DAI1 Pin 11
DAI1 Pin 12
DAI1 Pin 19
DAI1 Pin 20
DMC0 Address 0
Rev. B
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Table 10. ADSP-2156x 400-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
DMC0_A01
DMC0_A02
DMC0_A03
DMC0_A04
DMC0_A05
DMC0_A06
DMC0_A07
DMC0_A08
DMC0_A09
DMC0_A10
DMC0_A11
DMC0_A12
DMC0_A13
DMC0_A14
DMC0_A15
DMC0_BA0
DMC0_BA1
DMC0_BA2
DMC0_CAS
DMC0_CK
Description
Port
Pin Name
DMC0 Address 1
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
DMC0_A01
DMC0_A02
DMC0_A03
DMC0_A04
DMC0_A05
DMC0_A06
DMC0_A07
DMC0_A08
DMC0_A09
DMC0_A10
DMC0_A11
DMC0_A12
DMC0_A13
DMC0_A14
DMC0_A15
DMC0_BA0
DMC0_BA1
DMC0_BA2
DMC0_CAS
DMC0_CK
DMC0 Address 2
DMC0 Address 3
DMC0 Address 4
DMC0 Address 5
DMC0 Address 6
DMC0 Address 7
DMC0 Address 8
DMC0 Address 9
DMC0 Address 10
DMC0 Address 11
DMC0 Address 12
DMC0 Address 13
DMC0 Address 14
DMC0 Address 15
DMC0 Bank Address Input 0
DMC0 Bank Address Input 1
DMC0 Bank Address Input 2
DMC0 Column Address Strobe
DMC0 Clock
DMC0_CK
DMC0 Clock (Complement)
DMC0 Clock Enable
DMC0 Chip Select 0
DMC0 Data 0
DMC0_CK
DMC0_CKE
DMC0_CS0
DMC0_DQ00
DMC0_DQ01
DMC0_DQ02
DMC0_DQ03
DMC0_DQ04
DMC0_DQ05
DMC0_DQ06
DMC0_DQ07
DMC0_DQ08
DMC0_DQ09
DMC0_DQ10
DMC0_DQ11
DMC0_DQ12
DMC0_DQ13
DMC0_DQ14
DMC0_DQ15
DMC0_LDM
DMC0_LDQS
DMC0_LDQS
DMC0_ODT
DMC0_RAS
DMC0_RESET
DMC0_RZQ
DMC0_UDM
DMC0_UDQS
DMC0_CKE
DMC0_CS0
DMC0_DQ00
DMC0_DQ01
DMC0_DQ02
DMC0_DQ03
DMC0_DQ04
DMC0_DQ05
DMC0_DQ06
DMC0_DQ07
DMC0_DQ08
DMC0_DQ09
DMC0_DQ10
DMC0_DQ11
DMC0_DQ12
DMC0_DQ13
DMC0_DQ14
DMC0_DQ15
DMC0_LDM
DMC0_LDQS
DMC0_LDQS
DMC0_ODT
DMC0_RAS
DMC0_RESET
DMC0_RZQ
DMC0_UDM
DMC0_UDQS
DMC0 Data 1
DMC0 Data 2
DMC0 Data 3
DMC0 Data 4
DMC0 Data 5
DMC0 Data 6
DMC0 Data 7
DMC0 Data 8
DMC0 Data 9
DMC0 Data 10
DMC0 Data 11
DMC0 Data 12
DMC0 Data 13
DMC0 Data 14
DMC0 Data 15
DMC0 Data Mask for Lower Byte
DMC0 Data Strobe for Lower Byte
DMC0 Data Strobe for Lower Byte (Complement)
DMC0 On-die Termination
DMC0 Row Address Strobe
DMC0 Reset (DDR3 Only)
DMC0 External Calibration Resistor Connection
DMC0 Data Mask for Upper Byte
DMC0 Data Strobe for Upper Byte
Rev. B
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Page 26 of 104
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Table 10. ADSP-2156x 400-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
DMC0_UDQS
DMC0_VREF
DMC0_WE
HADC0_EOC_DOUT
HADC0_VIN0
HADC0_VIN1
HADC0_VIN2
HADC0_VIN3
HADC0_VREFN
HADC0_VREFP
JTG_TCK
Description
Port
Pin Name
DMC0_UDQS
DMC0_VREF0, DMC0_VREF1
DMC0_WE
PA_11
DMC0 Data Strobe for Upper Byte (Complement)
DMC0 Voltage Reference
DMC0 Write Enable
HADC0 End of Conversion / Serial Data Out
HADC0 Analog Input at channel 0
HADC0 Analog Input at channel 1
HADC0 Analog Input at channel 2
HADC0 Analog Input at channel 3
HADC0 Ground Reference for ADC
HADC0 External Reference for ADC
JTAG Clock
Not Muxed
Not Muxed
Not Muxed
A
Not Muxed
HADC0_VIN0
HADC0_VIN1
HADC0_VIN2
HADC0_VIN3
HADC0_VREFN
HADC0_VREFP
JTG_TCK
JTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
PB_04
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
JTG_TDI
JTAG Serial Data In
JTAG Serial Data Out
JTAG Mode Select
JTAG Reset
Not Muxed
JTG_TDO
Not Muxed
JTG_TMS
Not Muxed
JTG_TRST
LP0_ACK
Not Muxed
LP0 Acknowledge
LP0 Clock
B
B
B
B
B
B
B
B
B
B
B
C
B
C
C
C
C
C
C
C
B
B
B
A
A
A
A
A
A
A
A
A
A
LP0_CLK
PB_06
LP0_D0
LP0 Data 0
PB_07
LP0_D1
LP0 Data 1
PB_08
LP0_D2
LP0 Data 2
PB_09
LP0_D3
LP0 Data 3
PB_10
LP0_D4
LP0 Data 4
PB_11
LP0_D5
LP0 Data 5
PB_12
LP0_D6
LP0 Data 6
PB_13
LP0_D7
LP0 Data 7
PB_14
LP1_ACK
LP1 Acknowledge
LP1 Clock
PB_02
LP1_CLK
PC_07
LP1_D0
LP1 Data 0
PB_15
LP1_D1
LP1 Data 1
PC_00
LP1_D2
LP1 Data 2
PC_01
LP1_D3
LP1 Data 3
PC_02
LP1_D4
LP1 Data 4
PC_03
LP1_D5
LP1 Data 5
PC_04
LP1_D6
LP1 Data 6
PC_05
LP1_D7
LP1 Data 7
PC_06
MLB0_CLK
MLB0_DAT
MLB0_SIG
OSPI0_CLK
OSPI0_D2
OSPI0_D3
OSPI0_D4
OSPI0_D5
OSPI0_D6
OSPI0_D7
OSPI0_MISO/D1
OSPI0_MOSI/D0
OSPI0_SEL1
MLB0 Single-Ended Clock
MLB0 Single-Ended Data
MLB0 Single-Ended Signal
OSPI0 Clock
PB_02
PB_00
PB_01
PA_04
OSPI0 Data 2
PA_02
OSPI0 Data 3
PA_03
OSPI0 Data 4
PA_06
OSPI0 Data 5
PA_07
OSPI0 Data 6
PA_08
OSPI0 Data 7
PA_09
OSPI0 Master In, Slave Out
OSPI0 Master Out, Slave In
OSPI0 Slave Select Output 1
PA_00
PA_01
PA_05
Rev. B
|
Page 27 of 104
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Table 10. ADSP-2156x 400-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
OSPI0_SEL2
OSPI0_SEL3
SPI0_CLK
Description
Port
Pin Name
PC_04
OSPI0 Slave Select Output 2
OSPI0 Slave Select Output 3
SPI0 Clock
C
C
PC_05
A
PA_06
SPI0_MISO
SPI0_MOSI
SPI0_RDY
SPI0_SEL1
SPI0_SEL2
SPI0_SEL3
SPI0_SEL4
SPI0_SS
SPI0 Master In, Slave Out
SPI0 Master Out, Slave In
SPI0 Ready
A
PA_07
A
PA_08
B
PB_11
SPI0 Slave Select Output 1
SPI0 Slave Select Output 2
SPI0 Slave Select Output 3
SPI0 Slave Select Output 4
SPI0 Slave Select Input
SPI1 Clock
A
PA_09
B
PB_05
B
PB_14
B
PB_15
A
PA_09
SPI1_CLK
A
PA_10
SPI1_D2
SPI1 Data 2
A
PA_14
SPI1_D3
SPI1 Data 3
A
PA_15
SPI1_MISO
SPI1_MOSI
SPI1_RDY
SPI1_SEL1
SPI1_SEL2
SPI1_SEL3
SPI1_SEL4
SPI1_SEL5
SPI1_SEL6
SPI1_SEL7
SPI1_SS
SPI1 Master In, Slave Out
SPI1 Master Out, Slave In
SPI1 Ready
A
PA_11
A
PA_12
C
PC_06
SPI1 Slave Select Output 1
SPI1 Slave Select Output 2
SPI1 Slave Select Output 3
SPI1 Slave Select Output 4
SPI1 Slave Select Output 5
SPI1 Slave Select Output 6
SPI1 Slave Select Output 7
SPI1 Slave Select Input
SPI2 Clock
A
PA_13
B
PB_10
B
PB_13
C
PC_00
B
PB_06
C
PC_02
B
PB_08
A
PA_13
SPI2_CLK
A
PA_04
SPI2_D2
SPI2 Data 2
A
PA_02
SPI2_D3
SPI2 Data 3
A
PA_03
SPI2_MISO
SPI2_MOSI
SPI2_RDY
SPI2_SEL1
SPI2_SEL2
SPI2_SEL3
SPI2_SEL4
SPI2_SEL5
SPI2_SEL6
SPI2_SEL7
SPI2_SS
SPI2 Master In, Slave Out
SPI2 Master Out, Slave In
SPI2 Ready
A
PA_00
A
PA_01
B
PB_05
SPI2 Slave Select Output 1
SPI2 Slave Select Output 2
SPI2 Slave Select Output 3
SPI2 Slave Select Output 4
SPI2 Slave Select Output 5
SPI2 Slave Select Output 6
SPI2 Slave Select Output 7
SPI2 Slave Select Input
Boot Mode Control Pin 0
Boot Mode Control Pin 1
Boot Mode Control Pin 2
Clock/Crystal Input
A
PA_05
B
PB_03
B
PB_12
C
PC_01
B
PB_07
C
PC_03
B
PB_09
A
PA_05
SYS_BMODE0
SYS_BMODE1
SYS_BMODE2
SYS_CLKIN0
SYS_CLKOUT
SYS_FAULT
SYS_FAULT
SYS_HWRST
SYS_RESOUT
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
C
SYS_BMODE0
SYS_BMODE1
SYS_BMODE2
SYS_CLKIN0
SYS_CLKOUT
PC_07
Processor Clock Output
Active, High, Fault Output
Active, Low, Fault Output
Processor Hardware Reset Control
Reset Output
Not Muxed
Not Muxed
Not Muxed
SYS_FAULT
SYS_HWRST
SYS_RESOUT
Rev. B
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Page 28 of 104
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Table 10. ADSP-2156x 400-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
SYS_XTAL0
TM0_ACI0
Description
Port
Pin Name
SYS_XTAL0
PA_07
PA_14
PB_11
PB_00
PA_11
PA_06
PA_08
PA_02
PB_02
PB_01
PA_10
PA_12
PA_13
PB_03
PB_04
PB_05
PB_08
PB_09
PC_05
PC_07
PB_06
PB_07
PB_08
PB_09
PB_10
PC_00
PC_01
PC_02
PC_03
PA_10
PA_11
PB_00
PB_01
PA_14
PA_15
PA_02
PA_03
PC_00
PC_01
PC_02
PC_03
PA_09
PA_08
PA_07
PA_06
PB_01
PB_00
Crystal Output
Not Muxed
TIMER0 Alternate Capture Input 0
TIMER0 Alternate Capture Input 1
TIMER0 Alternate Capture Input 2
TIMER0 Alternate Capture Input 3
TIMER0 Alternate Capture Input 4
TIMER0 Alternate Clock 1
TIMER0 Alternate Clock 2
TIMER0 Alternate Clock 3
TIMER0 Alternate Clock 4
TIMER0 Clock
A
A
B
B
A
A
A
A
B
B
A
A
A
B
B
B
B
B
C
C
B
B
B
B
B
C
C
C
C
A
A
B
B
A
A
A
A
C
C
C
C
A
A
A
A
B
B
TM0_ACI1
TM0_ACI2
TM0_ACI3
TM0_ACI4
TM0_ACLK1
TM0_ACLK2
TM0_ACLK3
TM0_ACLK4
TM0_CLK
TM0_TMR0
TM0_TMR1
TM0_TMR2
TM0_TMR3
TM0_TMR4
TM0_TMR5
TM0_TMR6
TM0_TMR7
TM0_TMR8
TM0_TMR9
TRACE0_CLK
TRACE0_D00
TRACE0_D01
TRACE0_D02
TRACE0_D03
TRACE0_D04
TRACE0_D05
TRACE0_D06
TRACE0_D07
TWI0_SCL
TIMER0 Timer 0
TIMER0 Timer 1
TIMER0 Timer 2
TIMER0 Timer 3
TIMER0 Timer 4
TIMER0 Timer 5
TIMER0 Timer 6
TIMER0 Timer 7
TIMER0 Timer 8
TIMER0 Timer 9
TRACE0 Trace Clock
TRACE0 Trace Data 0
TRACE0 Trace Data1
TRACE0 Trace Data2
TRACE0 Trace Data 3
TRACE0 Trace Data4
TRACE0 Trace Data5
TRACE0 Trace Data6
TRACE0 Trace Data 7
TWI0 Serial Clock
TWI0_SDA
TWI1_SCL
TWI0 Serial Data
TWI1 Serial Clock
TWI1_SDA
TWI2_SCL
TWI1 Serial Data
TWI2 Serial Clock
TWI2_SDA
TWI3_SCL
TWI2 Serial Data
TWI3 Serial Clock
TWI3_SDA
TWI4_SCL
TWI3 Serial Data
TWI4 Serial Clock
TWI4_SDA
TWI5_SCL
TWI4 Serial Data
TWI5 Serial Clock
TWI5_SDA
UART0_CTS
UART0_RTS
UART0_RX
UART0_TX
UART1_CTS
UART1_RTS
TWI5 Serial Data
UART0 Clear to Send
UART0 Request to Send
UART0 Receive
UART0 Transmit
UART1 Clear to Send
UART1 Request to Send
Rev. B
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Table 10. ADSP-2156x 400-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
UART1_RX
UART1_TX
UART2_CTS
UART2_RTS
UART2_RX
UART2_TX
Description
Port
A
Pin Name
PA_14
PA_15
PB_14
PB_13
PB_11
PB_12
UART1 Receive
UART1 Transmit
UART2 Clear to Send
UART2 Request to Send
UART2 Receive
A
B
B
B
UART2 Transmit
B
Rev. B
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GPIO MULTIPLEXING FOR 400-BALL CSP_BGA PACKAGE
Table 11 through Table 13 identify the pin functions that are
multiplexed on the general-purpose I/O pins of the 400-ball
CSP_BGA package.
Table 11. Signal Multiplexing for Port A
Multiplexed
Function 0
Multiplexed
Function 1
Multiplexed
Function 2
Multiplexed
Function 3
Multiplexed
Function Input Tap
Signal Name
PA_00
PA_01
PA_02
PA_03
PA_04
PA_05
PA_06
PA_07
PA_08
PA_09
PA_10
PA_11
PA_12
PA_13
PA_14
PA_15
SPI2_MISO
SPI2_MOSI
SPI2_D2
OSPI0_MISO/D1
OSPI0_MOSI/D0
OSPI0_D2
TWI3_SCL
TWI3_SDA
TM0_ACLK3
SPI2_D3
OSPI0_D3
SPI2_CLK
SPI2_SEL1
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_SEL1
TWI0_SCL
TWI0_SDA
C0_FLG0
OSPI0_CLK
OSPI0_SEL1
UART0_TX
UART0_RX
UART0_RTS
UART0_CTS
SPI1_CLK
SPI2_SS
OSPI0_D4
TM0_ACLK1
TM0_ACI0
TM0_ACLK2
SPI0_SS
OSPI0_D5
OSPI0_D6
OSPI0_D7
TM0_TMR0
HADC0_EOC_DOUT
TM0_TMR1
TM0_TMR2
UART1_RX
UART1_TX
SPI1_MISO
SPI1_MOSI
SPI1_SEL1
SPI1_D2
TM0_ACI4
C0_FLG1
SPI1_SS
TWI2_SCL
TWI2_SDA
TM0_ACI1
SPI1_D3
Table 12. Signal Multiplexing for Port B
Multiplexed
Multiplexed
Function 1
Multiplexed
Function 2
Multiplexed
Function 3
Multiplexed
Function Input Tap
Signal Name
PB_00
PB_01
PB_02
PB_03
PB_04
PB_05
PB_06
PB_07
PB_08
PB_09
PB_10
PB_11
PB_12
PB_13
PB_14
PB_15
Function 0
MLB0_DAT
MLB0_SIG
MLB0_CLK
TM0_TMR3
TM0_TMR4
TM0_TMR5
LP0_CLK
LP0_D0
TWI1_SCL
TWI1_SDA
C0_FLG3
UART1_RTS
UART1_CTS
LP1_ACK
TM0_ACI3
TM0_CLK
TM0_ACLK4
CNT0_UD
CNT0_ZM
CNT0_DG
C0_FLG2
SPI2_SEL2
LP0_ACK
SPI1_RDY
SPI2_RDY
SPI1_SEL5
SPI2_SEL5
SPI1_SEL7
SPI2_SEL7
SPI1_SEL2
SPI0_RDY
SPI2_SEL3
SPI1_SEL3
SPI0_SEL3
SPI0_SEL4
SPI0_SEL2
TRACE0_CLK
TRACE0_D00
TRACE0_D01
TRACE0_D02
TRACE0_D03
UART2_RX
LP0_D1
TM0_TMR6
TM0_TMR7
LP0_D2
LP0_D3
LP0_D4
TM0_ACI2
LP0_D5
UART2_TX
LP0_D6
UART2_RTS
UART2_CTS
LP0_D7
LP1_D0
Rev. B
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Table 13. Signal Multiplexing for Port C
Multiplexed
Function 0
Multiplexed
Function 1
Multiplexed
Function 2
Multiplexed
Function 3
Multiplexed
Function Input Tap
Signal Name
PC_00
LP1_D1
LP1_D2
LP1_D3
LP1_D4
LP1_D5
LP1_D6
LP1_D7
LP1_CLK
TWI4_SCL
TWI4_SDA
TWI5_SCL
TWI5_SDA
OSPI0_SEL2
OSPI0_SEL3
SPI1_RDY
TRACE0_D04
TRACE0_D05
TRACE0_D06
TRACE0_D07
SPI1_SEL4
SPI2_SEL4
SPI1_SEL6
SPI2_SEL6
PC_01
PC_02
PC_03
PC_04
PC_05
TM0_TMR8
TM0_TMR9
PC_06
PC_07
SYS_FAULT1
1 The default PC_07 pin function is SYS_FAULT until the PORTC_FER and PORTC_MUX registers are explicitly programmed to change it.
Table 14 shows the internal timer signal routing. This table applies to both the 400-ball CSP_BGA and 120-lead LQFP packages.
Table 14. Internal Timer Signal Routing
Timer Input Signal
TM0_ACLK0
TM0_ACI5
TM0_ACLK5
TM0_ACI6
TM0_ACLK6
TM0_ACI7
TM0_ACLK7
TM0_ACI8
Internal Source
SYS_CLKIN0
DAI0_PB04_O
DAI0_PB03_O
DAI1_PB04_O
DAI1_PB03_O
CNT0_TO signal
SYS_CLKIN0
DAI0_PB06_O
DAI0_PB05_O
DAI1_PB06_O
DAI1_PB05_O
TM0_ACLK8
TM0_ACI9
TM0_ACLK9
Rev. B
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120-LEAD LQFP SIGNAL DESCRIPTIONS
The processor pin definitions are shown Table 15 for the
120-lead LQFP package. The columns in this table provide the
following information:
• The pin name column identifies the name of the package
pin (at power on reset) on which the signal is located (if a
single function pin) or is multiplexed (if a general-purpose
I/O pin).
• The signal name column includes the signal name for every
pin and the GPIO multiplexed pin function, where
applicable.
• The DAI pins and their associated signal routing units
(SRUs) connect inputs and outputs of the DAI peripherals
(SPORT, ASRC, S/PDIF, and PCG). See the Digital Audio
Interface (DAI) chapter of the ADSP-2156x SHARC+ Pro-
cessor Hardware Reference manual for complete
• The description column provides a descriptive name for
each signal.
• The port column shows whether or not a signal is multi-
plexed with other signals on a general-purpose I/O port
pin.
information on the use of the DAIs and SRUs.
Table 15. ADSP-2156x 120-Lead LQFP Signal Descriptions
Signal Name
C0_FLG0
Description
Port
Pin Name
PA_12
SHARC Core 0 Flag Pin
SHARC Core 0 Flag Pin
SHARC Core 0 Flag Pin
SHARC Core 0 Flag Pin
CNT0 Count Down and Gate
CNT0 Count Up and Direction
CNT0 Count Zero Marker
DAI0 Pin 1
A
C0_FLG1
A
PA_13
C0_FLG2
B
PB_03
C0_FLG3
B
PB_02
CNT0_DG
B
PB_05
CNT0_UD
B
PB_03
CNT0_ZM
B
PB_04
DAI0_PIN01
DAI0_PIN02
DAI0_PIN03
DAI0_PIN04
DAI0_PIN05
DAI0_PIN06
DAI0_PIN07
DAI0_PIN08
DAI0_PIN09
DAI0_PIN10
DAI0_PIN19
DAI0_PIN20
DAI1_PIN01
DAI1_PIN02
DAI1_PIN03
DAI1_PIN04
DAI1_PIN05
DAI1_PIN06
DAI1_PIN07
DAI1_PIN08
DAI1_PIN09
DAI1_PIN10
DAI1_PIN19
DAI1_PIN20
HADC0_EOC_DOUT
HADC0_VIN0
HADC0_VIN1
HADC0_VREFN
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
A
DAI0_PIN01
DAI0_PIN02
DAI0_PIN03
DAI0_PIN04
DAI0_PIN05
DAI0_PIN06
DAI0_PIN07
DAI0_PIN08
DAI0_PIN09
DAI0_PIN10
DAI0_PIN19
DAI0_PIN20
DAI1_PIN01
DAI1_PIN02
DAI1_PIN03
DAI1_PIN04
DAI1_PIN05
DAI1_PIN06
DAI1_PIN07
DAI1_PIN08
DAI1_PIN09
DAI1_PIN10
DAI1_PIN19
DAI1_PIN20
PA_11
DAI0 Pin 2
DAI0 Pin 3
DAI0 Pin 4
DAI0 Pin 5
DAI0 Pin 6
DAI0 Pin 7
DAI0 Pin 8
DAI0 Pin 9
DAI0 Pin 10
DAI0 Pin 19
DAI0 Pin 20
DAI1 Pin 1
DAI1 Pin 2
DAI1 Pin 3
DAI1 Pin 4
DAI1 Pin 5
DAI1 Pin 6
DAI1 Pin 7
DAI1 Pin 8
DAI1 Pin 9
DAI1 Pin 10
DAI1 Pin 19
DAI1 Pin 20
HADC0 End of Conversion / Serial Data Out
HADC0 Analog Input at channel 0
HADC0 Analog Input at channel 1
HADC0 Ground Reference for ADC
Not Muxed
Not Muxed
Not Muxed
HADC0_VIN0
HADC0_VIN1
HADC0_VREFN
Rev. B
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Table 15. ADSP-2156x 120-Lead LQFP Signal Descriptions (Continued)
Signal Name
HADC0_VREFP
JTG_TCK
Description
Port
Pin Name
HADC0_VREFP
JTG_TCK
JTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
PB_02
HADC0 External Reference for ADC
JTAG Clock
Not Muxed
Not Muxed
JTG_TDI
JTAG Serial Data In
JTAG Serial Data Out
JTAG Mode Select
JTAG Reset
Not Muxed
JTG_TDO
Not Muxed
JTG_TMS
Not Muxed
JTG_TRST
MLB0_CLK
MLB0_DAT
MLB0_SIG
OSPI0_CLK
OSPI0_D2
OSPI0_D3
OSPI0_D4
OSPI0_D5
OSPI0_D6
OSPI0_D7
OSPI0_MISO/D1
OSPI0_MOSI/D0
OSPI0_SEL1
SPI0_CLK
Not Muxed
MLB0 Single-Ended Clock
MLB0 Single-Ended Data
MLB0 Single-Ended Signal
OSPI0 Clock
B
B
PB_00
B
PB_01
A
PA_04
OSPI0 Data 2
A
PA_02
OSPI0 Data 3
A
PA_03
OSPI0 Data 4
A
PA_06
OSPI0 Data 5
A
PA_07
OSPI0 Data 6
A
PA_08
OSPI0 Data 7
A
PA_09
OSPI0 Master In, Slave Out
OSPI0 Master Out, Slave In
OSPI0 Slave Select Output 1
SPI0 Clock
A
PA_00
A
PA_01
A
PA_05
A
PA_06
SPI0_MISO
SPI0_MOSI
SPI0_SEL1
SPI0_SEL2
SPI0_SS
SPI0 Master In, Slave Out
SPI0 Master Out, Slave In
SPI0 Slave Select Output 1
SPI0 Slave Select Output 2
SPI0 Slave Select Input
SPI1 Clock
A
PA_07
A
PA_08
A
PA_09
B
PB_05
A
PA_09
SPI1_CLK
A
PA_10
SPI1_D2
SPI1 Data 2
A
PA_14
SPI1_D3
SPI1 Data 3
A
PA_15
SPI1_MISO
SPI1_MOSI
SPI1_RDY
SPI1_SEL1
SPI1_SS
SPI1 Master In, Slave Out
SPI1 Master Out, Slave In
SPI1 Ready
A
PA_11
A
PA_12
B
PB_04
SPI1 Slave Select Output 1
SPI1 Slave Select Input
SPI2 Clock
A
PA_13
A
PA_13
SPI2_CLK
A
PA_04
SPI2_D2
SPI2 Data 2
A
PA_02
SPI2_D3
SPI2 Data 3
A
PA_03
SPI2_MISO
SPI2_MOSI
SPI2_RDY
SPI2_SEL1
SPI2_SEL2
SPI2_SS
SPI2 Master In, Slave Out
SPI2 Master Out, Slave In
SPI2 Ready
A
PA_00
A
PA_01
B
PB_05
SPI2 Slave Select Output 1
SPI2 Slave Select Output 2
SPI2 Slave Select Input
Boot Mode Control
Boot Mode Control
Clock/Crystal Input
Processor Clock Output
Active-Low Fault Output
Processor Hardware Reset Control
A
PA_05
B
PB_03
A
PA_05
SYS_BMODE0
SYS_BMODE1
SYS_CLKIN0
SYS_CLKOUT
SYS_FAULT
SYS_HWRST
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
SYS_BMODE0
SYS_BMODE1
SYS_CLKIN0
SYS_CLKOUT
SYS_FAULT
SYS_HWRST
Rev. B
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Table 15. ADSP-2156x 120-Lead LQFP Signal Descriptions (Continued)
Signal Name
SYS_RESOUT
SYS_XTAL0
TM0_ACI0
TM0_ACI1
TM0_ACI3
TM0_ACI4
TM0_ACLK1
TM0_ACLK2
TM0_ACLK3
TM0_ACLK4
TM0_CLK
Description
Port
Pin Name
SYS_RESOUT
SYS_XTAL0
PA_07
PA_14
PB_00
PA_11
PA_06
PA_08
PA_02
PB_02
PB_01
PA_10
PA_12
PA_13
PB_03
PB_04
PB_05
PA_10
PA_11
PB_00
PB_01
PA_14
PA_15
PA_02
PA_03
PA_09
PA_08
PA_07
PA_06
PB_01
PB_00
PA_14
PA_15
Reset Output
Not Muxed
Crystal Output
Not Muxed
TIMER0 Alternate Capture Input 0
TIMER0 Alternate Capture Input 1
TIMER0 Alternate Capture Input 3
TIMER0 Alternate Capture Input 4
TIMER0 Alternate Clock 1
TIMER0 Alternate Clock 2
TIMER0 Alternate Clock 3
TIMER0 Alternate Clock 4
TIMER0 Clock
A
A
B
A
A
A
A
B
B
A
A
A
B
B
B
A
A
B
B
A
A
A
A
A
A
A
A
B
B
A
A
TM0_TMR0
TM0_TMR1
TM0_TMR2
TM0_TMR3
TM0_TMR4
TM0_TMR5
TWI0_SCL
TWI0_SDA
TWI1_SCL
TWI1_SDA
TWI2_SCL
TWI2_SDA
TWI3_SCL
TWI3_SDA
UART0_CTS
UART0_RTS
UART0_RX
UART0_TX
UART1_CTS
UART1_RTS
UART1_RX
UART1_TX
TIMER0 Timer 0
TIMER0 Timer 1
TIMER0 Timer 2
TIMER0 Timer 3
TIMER0 Timer 4
TIMER0 Timer 5
TWI0 Serial Clock
TWI0 Serial Data
TWI1 Serial Clock
TWI1 Serial Data
TWI2 Serial Clock
TWI2 Serial Data
TWI3 Serial Clock
TWI3 Serial Data
UART0 Clear to Send
UART0 Request to Send
UART0 Receive
UART0 Transmit
UART1 Clear to Send
UART1 Request to Send
UART1 Receive
UART1 Transmit
Rev. B
|
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ADSP-21562/21563/21565/21566/21567/21569
GPIO MULTIPLEXING FOR 120-LEAD LQFP PACKAGE
Table 16 and Table 17 identify the pin functions that are multi-
plexed on the general-purpose I/O pins of the 120-lead LQFP
package.
Table 16. Signal Multiplexing for Port A
Signal Name Multiplexed Function 0
Multiplexed Function 1
OSPI0_MISO/D1
OSPI0_MOSI/D0
OSPI0_D2
Multiplexed Function 2
Multiplexed Function Input Tap
PA_00
PA_01
PA_02
PA_03
PA_04
PA_05
PA_06
PA_07
PA_08
PA_09
PA_10
PA_11
PA_12
PA_13
PA_14
PA_15
SPI2_MISO
SPI2_MOSI
SPI2_D2
TWI3_SCL
TWI3_SDA
TM0_ACLK3
SPI2_D3
OSPI0_D3
SPI2_CLK
SPI2_SEL1
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_SEL1
TWI0_SCL
TWI0_SDA
C0_FLG0
OSPI0_CLK
OSPI0_SEL1
UART0_TX
SPI2_SS
OSPI0_D4
TM0_ACLK1
TM0_ACI0
TM0_ACLK2
SPI0_SS
UART0_RX
OSPI0_D5
UART0_RTS
UART0_CTS
SPI1_CLK
OSPI0_D6
OSPI0_D7
TM0_TMR0
HADC0_EOC_DOUT
TM0_TMR1
TM0_TMR2
UART1_RX
UART1_TX
SPI1_MISO
SPI1_MOSI
SPI1_SEL1
TM0_ACI4
C0_FLG1
SPI1_SS
TWI2_SCL
TWI2_SDA
SPI1_D2
TM0_ACI1
SPI1_D3
Table 17. Signal Multiplexing for Port B
Signal Name Multiplexed Function 0
Multiplexed Function 1
TWI1_SCL
Multiplexed Function 2
UART1_RTS
Multiplexed Function Input Tap
TM0_ACI3
PB_00
PB_01
PB_02
PB_03
PB_04
PB_05
MLB0_DAT
MLB0_SIG
MLB0_CLK
TM0_TMR3
TM0_TMR4
TM0_TMR5
TWI1_SDA
UART1_CTS
TM0_CLK
C0_FLG3
TM0_ACLK4
C0_FLG2
SPI2_SEL2
SPI0_SEL2
CNT0_UD
SPI1_RDY
CNT0_ZM
SPI2_RDY
CNT0_DG
Rev. B
|
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ADSP-2156x DESIGNER QUICK REFERENCE
Table 18 provides a quick reference summary of pin related
information for circuit board design. The columns in this table
provide the following information:
• The reset termination column specifies the termination
present when the processor is in the reset state.
• The reset drive column specifies the active drive on the sig-
nal when the processor is in the reset state.
• The signal name column includes the signal name for every
pin and the GPIO multiplexed pin function, where
applicable.
• The power domain column specifies the power supply
domain in which the signal resides.
• The type column identifies the I/O type or supply type of
the pin. The abbreviations used in this column are analog
(a), supply (s), ground (g) and Input, Output, and InOut.
• The description and notes column identifies any special
requirements or characteristics for a signal. These recom-
mendations apply whether or not the hardware block
associated with the signal is featured on the product. If no
special requirements are listed, the signal can be left uncon-
nected if it is not used. For multiplexed GPIO pins, this
column identifies the functions available on the pin.
• The driver type column identifies the driver type used by
the corresponding pin. The driver types are defined in the
Output Drive Currents section of this data sheet.
• The internal termination column specifies the termination
present after the processor is powered up (both during
reset and after reset).
Table 18. ADSP-2156x Designer Quick Reference
Driver Internal
Type Termination
Reset
Termination Reset Drive Power Domain Description and Notes
Signal Name
Type
DAI0_PIN01
InOut
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Programmable
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
Desc: DAI0 Pin 1
Notes: See note2
Desc: DAI0 Pin 2
Notes: See note2
Desc: DAI0 Pin 3
Notes: See note2
Desc: DAI0 Pin 4
Notes: See note2
Desc: DAI0 Pin 5
Notes: See note2
Desc: DAI0 Pin 6
Notes: See note2
Desc: DAI0 Pin 7
Notes: See note2
Desc: DAI0 Pin 8
Notes: See note2
Desc: DAI0 Pin 9
Notes: See note2
Desc: DAI0 Pin 10
Notes: See note2
Desc: DAI0 Pin 11
Notes: See note2
Desc: DAI0 Pin 12
Notes: See note2
Desc: DAI0 Pin 19
Notes: See note2
Desc: DAI0 Pin 20
Notes: See note2
Desc: DAI1 Pin 1
Notes: See note2
pull-up/pull-down1
DAI0_PIN02
DAI0_PIN03
DAI0_PIN04
DAI0_PIN05
DAI0_PIN06
DAI0_PIN07
DAI0_PIN08
DAI0_PIN09
DAI0_PIN10
DAI0_PIN11
DAI0_PIN12
DAI0_PIN19
DAI0_PIN20
DAI1_PIN01
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
Programmable
pull-up/pull-down1
Programmable
pull-up/pull-down1
Programmable
pull-up/pull-down1
Programmable
pull-up/pull-down1
Programmable
pull-up/pull-down1
Programmable
pull-up/pull-down1
Programmable
pull-up/pull-down1
Programmable
pull-up/pull-down1
Programmable
pull-up/pull-down1
Programmable
pull-up/pull-down1
Programmable
pull-up/pull-down1
Programmable
pull-up/pull-down1
Programmable
pull-up/pull-down1
Programmable
pull-up/pull-down1
Rev. B
|
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Table 18. ADSP-2156x Designer Quick Reference (Continued)
Driver Internal
Reset
Signal Name
Type
Type Termination
Termination Reset Drive Power Domain Description and Notes
DAI1_PIN02
InOut
A
A
A
A
A
A
A
A
A
A
A
A
A
Programmable
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
L
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
Desc: DAI1 Pin 2
pull-up/pull-down1
Notes: See note2
Desc: DAI1 Pin 3
DAI1_PIN03
DAI1_PIN04
DAI1_PIN05
DAI1_PIN06
DAI1_PIN07
DAI1_PIN08
DAI1_PIN09
DAI1_PIN10
DAI1_PIN11
DAI1_PIN12
DAI1_PIN19
DAI1_PIN20
DMC0_A00
DMC0_A01
DMC0_A02
DMC0_A03
DMC0_A04
DMC0_A05
DMC0_A06
DMC0_A07
DMC0_A08
DMC0_A09
DMC0_A10
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
Programmable
pull-up/pull-down1
Notes: See note2
Desc: DAI1 Pin 4
Programmable
pull-up/pull-down1
Notes: See note2
Desc: DAI1 Pin 5
Programmable
pull-up/pull-down1
Notes: See note2
Desc: DAI1 Pin 6
Programmable
pull-up/pull-down1
Notes: See note2
Desc: DAI1 Pin 7
Programmable
pull-up/pull-down1
Notes: See note2
Desc: DAI1 Pin 8
Programmable
pull-up/pull-down1
Notes: See note2
Desc: DAI1 Pin 9
Programmable
pull-up/pull-down1
Notes: See note2
Desc: DAI1 Pin 10
Notes: See note2
Desc: DAI1 Pin 11
Notes: See note2
Desc: DAI1 Pin 12
Notes: See note2
Desc: DAI1 Pin 19
Notes: See note2
Desc: DAI1 Pin 20
Notes: See note2
Desc: DMC0 Address 0
Notes: No notes
Programmable
pull-up/pull-down1
Programmable
pull-up/pull-down1
Programmable
pull-up/pull-down1
Programmable
pull-up/pull-down1
Programmable
pull-up/pull-down1
Output B
Output B
Output B
Output B
Output B
Output B
Output B
Output B
Output B
Output B
Output B
None
None
None
None
None
None
None
None
None
None
None
L
Desc: DMC0 Address 1
Notes: No notes
L
Desc: DMC0 Address 2
Notes: No notes
L
Desc: DMC0 Address 3
Notes: No notes
L
Desc: DMC0 Address 4
Notes: No notes
L
Desc: DMC0 Address 5
Notes: No notes
L
Desc: DMC0 Address 6
Notes: No notes
L
Desc: DMC0 Address 7
Notes: No notes
L
Desc: DMC0 Address 8
Notes: No notes
L
Desc: DMC0 Address 9
Notes: No notes
L
Desc: DMC0 Address 10
Notes: No notes
Rev. B
|
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Table 18. ADSP-2156x Designer Quick Reference (Continued)
Driver Internal
Reset
Signal Name
Type
Type Termination
Termination Reset Drive Power Domain Description and Notes
DMC0_A11
Output B
Output B
Output B
Output B
Output B
Output B
Output B
Output B
Output B
Output C
Output C
Output B
Output B
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
L
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
Desc: DMC0 Address 11
Notes: No notes
DMC0_A12
DMC0_A13
DMC0_A14
DMC0_A15
DMC0_BA0
DMC0_BA1
DMC0_BA2
DMC0_CAS
DMC0_CK
L
Desc: DMC0 Address 12
Notes: No notes
L
Desc: DMC0 Address 13
Notes: No notes
L
Desc: DMC0 Address 14
Notes: No notes
L
Desc: DMC0 Address 15
Notes: No notes
L
Desc: DMC0 Bank Address Input 0
Notes: No notes
L
Desc: DMC0 Bank Address Input 1
Notes: No notes
L
Desc: DMC0 Bank Address Input 2
Notes: No notes
L
Desc: DMC0 column address strobe
Notes: No notes
L
Desc: DMC0 clock
Notes: No notes
DMC0_CK
H
Desc: DMC0 clock (complement)
Notes: No notes
DMC0_CKE
DMC0_CS0
DMC0_DQ00
L
Desc: DMC0 clock enable
Notes: No notes
L
Desc: DMC0 Chip Select 0
Notes: No notes
InOut
InOut
InOut
InOut
InOut
InOut
InOut
B
B
B
B
B
B
B
Internal logic
None
Desc: DMC0 Data 0
ensures that input
signal does not float
Notes: No notes
DMC0_DQ01
DMC0_DQ02
DMC0_DQ03
DMC0_DQ04
DMC0_DQ05
DMC0_DQ06
Internal logic
ensures that input
signal does not float
None
None
None
None
None
None
None
None
None
None
None
None
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
Desc: DMC0 Data 1
Notes: No notes
Internal logic
ensures that input
signal does not float
Desc: DMC0 Data 2
Notes: No notes
Internal logic
ensures that input
signal does not float
Desc: DMC0 Data 3
Notes: No notes
Internal logic
ensures that input
signal does not float
Desc: DMC0 Data 4
Notes: No notes
Internal logic
ensures that input
signal does not float
Desc: DMC0 Data 5
Notes: No notes
Internal logic
ensures that input
signal does not float
Desc: DMC0 Data 6
Notes: No notes
Rev. B
|
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Table 18. ADSP-2156x Designer Quick Reference (Continued)
Driver Internal
Reset
Signal Name
Type
Type Termination
Termination Reset Drive Power Domain Description and Notes
DMC0_DQ07
InOut
B
B
B
B
B
B
B
B
B
Internal logic
ensures that input
signal does not float
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
L
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
Desc: DMC0 Data 7
Notes: No notes
DMC0_DQ08
DMC0_DQ09
DMC0_DQ10
DMC0_DQ11
DMC0_DQ12
DMC0_DQ13
DMC0_DQ14
DMC0_DQ15
DMC0_LDM
DMC0_LDQS
DMC0_LDQS
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
Internal logic
ensures that input
signal does not float
Desc: DMC0 Data 8
Notes: No notes
Internal logic
ensures that input
signal does not float
Desc: DMC0 Data 9
Notes: No notes
Internal logic
ensures that input
signal does not float
Desc: DMC0 Data 10
Notes: No notes
Internal logic
ensures that input
signal does not float
Desc: DMC0 Data 11
Notes: No notes
Internal logic
ensures that input
signal does not float
Desc: DMC0 Data 12
Notes: No notes
Internal logic
ensures that input
signal does not float
Desc: DMC0 Data 13
Notes: No notes
Internal logic
ensures that input
signal does not float
Desc: DMC0 Data 14
Notes: No notes
Internal logic
ensures that input
signal does not float
Desc: DMC0 Data 15
Notes: No notes
Output B
None
Desc: DMC0 data mask for lower
byte
Notes: No notes
InOut
InOut
C
C
Internal logic
ensures that input
signal does not float
None
None
Desc: DMC0 data strobe for lower
byte
Notes: No notes
Internal logic
ensures that input
signal does not float
Desc: DMC0 data strobe for lower
byte (complement)
Notes: No notes
DMC0_ODT
DMC0_RAS
DMC0_RESET
DMC0_RZQ
Output B
Output B
Output B
None
None
None
None
None
None
None
None
L
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
Desc: DMC0 on-die termination
Notes: No notes
L
Desc: DMC0 row address strobe
Notes: No notes
L
Desc: DMC0 reset (DDR3 only)
Notes: No notes
a
B
None
Desc: DMC0 external calibration
resistor connection
Notes: 34 Ω external pull-down
must be added
DMC0_UDM
Output B
None
None
L
VDD_DMC
Desc: DMC0 data mask for upper
byte
Notes: No notes
Rev. B
|
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Table 18. ADSP-2156x Designer Quick Reference (Continued)
Driver Internal
Reset
Signal Name
Type
Type Termination
Termination Reset Drive Power Domain Description and Notes
DMC0_UDQS
InOut
C
Internal logic
ensures that input
signal does not float
None
None
None
None
VDD_DMC
VDD_DMC
Desc: DMC0 data strobe for upper
byte
Notes: No notes
DMC0_UDQS
InOut
a
C
Internal logic
ensures that input
signal does not float
Desc: DMC0 data strobe for upper
byte (complement)
Notes: No notes
DMC0_VREF
DMC0_WE
GND
None
None
None
none
None
None
None
none
None
L
VDD_DMC
VDD_DMC
Desc: DMC0 voltage reference
Notes: No notes
Output B
g
Desc: DMC0 write enable
Notes: No notes
None
none
Desc: Ground
Notes: No notes
HADC0_VIN0
a
a
a
a
s
NA
VDD_ANA
VDD_ANA
VDD_ANA
VDD_ANA
VDD_ANA
VDD_ANA
Desc: HADC0 Analog Input at
channel 0
Notes: Connect to GND if not used3.
HADC0_VIN1
HADC0_VIN2
HADC0_VIN3
HADC0_VREFN
HADC0_VREFP
NA
NA
NA
NA
NA
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
Desc: HADC0 Analog Input at
channel 1
Notes: Connect to GND if not used3
Desc: HADC0 Analog Input at
channel 2
Notes: Connect to GND if not used3
Desc: HADC0 Analog Input at
channel 3
Notes: Connect to GND if not used3
Desc: HADC0 Ground Reference for
ADC
Notes: Connect to GND if not used3
s
Desc: HADC0 External Reference
for ADC
Notes: Connect to VDD_REF if
HADC/TMU is not used.
JTG_TCK
JTG_TDI
JTG_TDO
Input
Input
Pull-up
Pull-up
None
Pull-up
Pull-up
None
None
None
VDD_EXT
VDD_EXT
Desc: JTAG clock
Notes: See note2
Desc: JTAG serial data in
Notes: See note2
Output A
High-Zwhen VDD_EXT
JTG_TRST is
Desc: JTAG serial data out
Notes: No notes
low, not
affected by
SYS_HWRST
JTG_TMS
JTG_TRST
PA_00
InOut
Input
InOut
InOut
A
Pull-up
Pull-up
Pull-down
None
None
None
None
None
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
Desc: JTAG mode select
Notes: See note2
Pull-down
Desc: JTAG reset
Notes: See note2
A
A
Programmable
Desc: Port A Position 0
Notes: See note2
pull-up/pull-down1
PA_01
Programmable
None
Desc: Port A Position 1
Notes: See note2
pull-up/pull-down1
Rev. B
|
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Table 18. ADSP-2156x Designer Quick Reference (Continued)
Driver Internal
Reset
Signal Name
Type
Type Termination
Termination Reset Drive Power Domain Description and Notes
PA_02
InOut
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Programmable
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
Desc: Port A Position 2
Notes: See note2
pull-up/pull-down1
PA_03
PA_04
PA_05
PA_06
PA_07
PA_08
PA_09
PA_10
PA_11
PA_12
PA_13
PA_14
PA_15
PB_00
PB_01
PB_02
PB_03
PB_04
PB_05
PB_06
PB_07
PB_08
PB_09
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
Programmable
Desc: Port A Position 3
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port A Position 4
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port A Position 5
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port A Position 6
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port A Position 7
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port A Position 8
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port A Position 9
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port A Position 10
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port A Position 11
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port A Position 12
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port A Position 13
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port A Position 14
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port A Position 15
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port B Position 0
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port B Position 1
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port B Position 2
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port B Position 3
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port B Position 4
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port B Position 5
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port B Position 6
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port B Position 7
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port B Position 8
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port B Position 9
Notes: See note2
pull-up/pull-down1
Rev. B
|
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Table 18. ADSP-2156x Designer Quick Reference (Continued)
Driver Internal
Reset
Signal Name
Type
Type Termination
Termination Reset Drive Power Domain Description and Notes
PB_10
InOut
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Programmable
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
Desc: Port B Position 10
Notes: See note2
pull-up/pull-down1
PB_11
PB_12
PB_13
PB_14
PB_15
PC_00
PC_01
PC_02
PC_03
PC_04
PC_05
PC_06
PC_07
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
InOut
Programmable
Desc: Port B Position 11
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port B Position 12
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port B Position 13
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port B Position 14
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port B Position 15
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port C Position 0
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port C Position 1
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port C Position 2
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port C Position 3
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port C Position 4
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port C Position 5
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port C Position 6
Notes: See note2
pull-up/pull-down1
Programmable
Desc: Port C Position 7 (default is
SYS_FAULT)
pull-up/pull-down1
Notes:Externalpull-downrequired
to keep signal in deasserted state
SYS_BMODE0
SYS_BMODE1
SYS_BMODE2
SYS_CLKIN0
SYS_CLKOUT
SYS_FAULT
Input NA
Input NA
Input NA
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
VDD_EXT
VDD_EXT
VDD_EXT
VDD_REF
VDD_EXT
VDD_EXT
Desc: Boot Mode Control 0
Notes: Cannot be left unconnected
Desc: Boot Mode Control 1
Notes: Cannot be left unconnected
Desc: Boot Mode Control 2
Notes: Cannot be left unconnected
Desc: Clock/crystal input
Notes: Cannot be left unconnected
Desc: Processor clock output
Notes: No notes
a
NA
A
a
InOut
A
Desc: Active low fault output
Notes: External pull-up required to
keep signal in deasserted state
SYS_HWRST
SYS_RESOUT
Input NA
Output A
None
None
None
None
None
L
VDD_EXT
VDD_EXT
Desc: Processor hardware reset
control
Notes: Cannot be left unconnected
Desc: Reset output
Notes: No notes
Rev. B
|
Page 43 of 104
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Table 18. ADSP-2156x Designer Quick Reference (Continued)
Driver Internal
Reset
Signal Name
Type
Type Termination
Termination Reset Drive Power Domain Description and Notes
SYS_XTAL0
a
NA
None
none
None
none
None
none
VDD_REF
Desc: Crystal output
Notes: Leave unconnected if an
oscillator provides SYS_CLKIN0
VDD_ANA
s
Desc: Analog VDD
Notes: VDD_REF can be used to
sourcetheVDD_ANApowersupply
for HADC and TMU.
VDD_DMC
VDD_EXT
VDD_INT
VDD_REF
s
s
s
s
None
None
None
None
None
None
None
None
None
None
None
None
Desc: DMC voltage domain
Notes: No notes
Desc: External voltage domain
Notes: No notes
Desc: Internal voltage domain
Notes: No notes
Desc: External voltage reference
Notes: VDD_REF can be used to
sourcetheVDD_ANApowersupply
for HADC and TMU.
1 Disable by default.
2 When present, the internal pull-up/pull-down design holds the internal path from the pins at the expected logic levels. To pull up or pull down the external pads to the expected
logic levels, use external resistors.
3 All HADC0_VINx pins and the HADC0_VREFN pin can be connected directly to GND if HADC and TMU are not used.
Rev. B
|
Page 44 of 104
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February 2021
ADSP-21562/21563/21565/21566/21567/21569
SPECIFICATIONS
For information about product specifications, contact your Analog Devices, Inc., representative.
OPERATING CONDITIONS
Parameter
Conditions
Min
Nominal
Max
Unit
VDD_INT
VDD_EXT
VDD_ANA
Internal (Core) Supply Voltage
External (I/O) Supply Voltage
Analog Power Supply Voltage
DDR3L Controller Supply Voltage
DDR3 Controller Supply Voltage
External (I/O) Reference Supply Voltage
DDR3 Reference Voltage
400 MHz ≤ CCLK ≤ 1 GHz 0.95
1.00
3.30
1.80
1.350
1.500
1.80
1.05
3.47
1.89
1.418
1.575
1.89
V
V
V
V
V
V
V
V
V
V
V
V
V
V
3.13
1.71
1
VDD_DMC
1.283
1.425
1.71
2
VDD_REF
3
VDDR_VREF
0.49 × VDD_DMC
0.50 × VDD_DMC 0.51 × VDD_DMC
+1.89
4
VDELTA_EXT_REF (VDD_EXT – VDD_REF) and (VDD_EXT – VDD_ANA
)
–1.89
5
VHADC_REF
HADC Reference Voltage
HADC Input Voltage
1.71
1.80
VDD_ANA
VHADC0_VINx
0
VHADC_REF + 0.09
6
VIH
High Level Input Voltage
High Level Clock Input Voltage
Low Level Input Voltage
Low Level Clock Input Voltage
Low Level Input Voltage
Low Level Input Voltage
High Level Input Voltage
High Level Input Voltage
VDD_EXT = 3.47 V
VDD_REF = 1.89 V
VDD_EXT = 3.13 V
VDD_REF = 1.71 V
VDD_DMC = 1.283 V
VDD_DMC = 1.425 V
VDD_DMC = 1.418 V
VDD_DMC = 1.575 V
2.0
2
VIHCLKIN
0.65 × VDD_REF
VDD_REF
6
VIL
0.8
2
VILCLKIN
–0.30
+0.35 × VDD_REF
7
VIL_DDR3L
VDDR_VREF – 0.175 V
7
VIL_DDR3
VDDR_VREF – 0.175 V
7
VIH_DDR3L
VDDR_VREF + 0.175
VDDR_VREF + 0.175
V
V
7
VIH_DDR3
CONSUMER GRADE
TJ
Junction Temperature
400-Ball CSP_BGA
0
0
110
110
°C
TJ
Junction Temperature
120-Lead LQFP_EP
°C
INDUSTRIAL GRADE
TJ
Junction Temperature
400-Ball CSP_BGA
–40
–40
+125
+125
°C
°C
TJ
Junction Temperature
120-Lead LQFP_EP
AUTOMOTIVE GRADE8
TJ
Junction Temperature
400-Ball CSP_BGA
–40
–40
+125
+125
°C
°C
TJ
Junction Temperature
120-Lead LQFP_EP
1 Applies to DDR3L/DDR3 signals.
2 Applies to SYS_CLKIN0 pin.
3 Applies to DMC0_VREF pins.
4 See Figure 11.
5 VHADC_VREF must always be less than VDD_ANA
.
6 Parameter value applies to all input and bidirectional pins except the DMC pins.
7 This parameter applies to all DMC0 pins.
8 Automotive application use profile only. Not supported for nonautomotive use. Contact Analog Devices for more information.
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Clock Related Operating Conditions
Table 19 describes the core clock, system clock, and peripheral clock timing requirements. The data presented in the table applies to all
speed grades except where noted.
Table 19. Clock Operating Conditions
Parameter
fCCLK
Conditions
Min
400
200
30
Typ
Max
1000
500
Unit
MHz
MHz
MHz
Core Clock (CCLK) Frequency
SYSCLK Frequency1
fCCLK = 2 × fSYSCLK
fSYSCLK
fSCLK0
SCLK0 Frequency
fSYSCLK = N × fSCLK0
125
where N = 2 or 4 or 6
fSCLK1
fDCLK
SCLK1 Frequency
DDR3 Clock (DCLK) Frequency2
fSYSCLK ≥ fSCLK1
250
667
MHz
MHz
All combinations are supported 300
except for:
[fCCLK > 800 MHz and Tj < 0°C and
fCCLK:fDCLK = 2:1]
fOCLK
Output Clock (OCLK) Frequency3
125
MHz
%
fSYS_CLKOUTJ SYS_CLKOUT Period Jitter4, 5
fLCLKTPROG Programmed Link Port Transmit Clock
fLCLKREXT
External Link Port Receive Clock6, 7
1
125
125
62.5
MHz
MHz
MHz
fLCLKREXT ≤ fOCLK_0
fSPTCLKPROG Programmed SPT Clock When Transmitting Data
and Frame Sync
fSPTCLKPROG Programmed SPT Clock When Receiving Data or
Frame Sync
31.25
62.5
MHz
MHz
MHz
fSPTCLKEXT
External SPT Clock When Receiving Data and
Frame Sync6, 7
fSPTCLKEXT ≤ fSCLK0
fSPTCLKEXT ≤ fSCLK0
fSPTCLKEXT
External SPT Clock Transmitting Data or
Frame Sync6, 7
31.25
fSPICLKPROG Programmed SPI Clock When Transmitting Data
fSPICLKPROG Programmed SPI Clock When Receiving Data
fSPICLKPROG Programmed SPI Clock When Transmitting Data
fSPICLKPROG Programmed SPI Clock When Receiving Data
fSPICLK:fSCLK0 ratio = 1:1
fSPICLK:fSCLK0 ratio = 1:1
fSPICLK:fSCLK0 ratio = 1:2
fSPICLK:fSCLK0 ratio = 1:2
fSPICLKEXT ≤ fCDU_CLKO0
fSPICLKEXT ≤ fCDU_CLKO0
fTMRCLKEXT ≤ fSCLK0 / 4
75
MHz
MHz
MHz
MHz
MHz
MHz
MHz
75
62.5
62.5
62.5
45
fSPICLKEXT
fSPICLKEXT
fTMRCLKEXT
External SPI Clock When Receiving Data6, 7
External SPI Clock When Transmitting Data6, 7
External Timer Clock (TMx_CLK)
31.25
1 When using MLB, there is a requirement that the fSYSCLK value must be a minimum of 100 MHz for 3-pin mode and for all supported speeds.
2 To ensure proper operation of the DDR3/3L, all the DDR3/3L guidelines must be strictly followed. See ADSP-2156x Board Design Guidelines for Dynamic Memory Controller
(EE-418).
3 fOCLK must not exceed fSCLK0 when selected as SYS_CLKOUT.
4 SYS_CLKOUT jitter is dependent on the application system design including pin switching activity, board layout, and the jitter characteristics of the SYS_CLKIN source. Due
to the dependency on these factors, the measured jitter may be higher or lower than this typical specification for each end application.
5 The value in the Typ field is the percentage of the SYS_CLKOUT period.
6 The maximum achievable frequency for any peripheral in external clock mode is dependent on being able to meet the setup and hold times in the ac timing specifications
section for that peripheral.
7 The peripheral external clock frequency must also be less than or equal to the frequency that clocks the peripheral.
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Table 20. Phase-Locked Loop (PLL) Operating Conditions
Parameter
Min
Max
Unit
fPLLCLK
PLL Clock Frequency
1.20
2.00
GHz
CCLK
CSEL
SYSCLK
SCLK0
SYSSEL
S0SEL
PLLCLK
PLL
SYS_CLKIN
S1SEL
DCLK
DSEL
OSEL
SCLK1
S1SELEX
OUTCLK
S1SELEXEN
REFER TO THE ADSP-2156x SHARC+ PROCESSOR HARDWARE REFERENCE
FOR INFORMATION ABOUT ALLOWED DIVIDER VALUES AND PROGRAMMING MODELS.
Figure 9. Clock Relationships and Divider Values
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ELECTRICAL CHARACTERISTICS
Parameter
Conditions
Min
Typ
Max
Unit
VOH
High Level Output Voltage
Low Level Output Voltage
VDD_EXT = minimum,
2.4
V
(IOH = –2.0 mA, DS1)1, (IOH = –4.0 mA, DS2)2
VOL
VDD_EXT = minimum,
0.4
V
(IOL = 2.0 mA, DS1)1, (IOL = 4.0 mA, DS2)2
3
VOH_XTAL
High Level Output Voltage
Low Level Output Voltage
VDD_REF = minimum, IOH = –1.0 mA
VDD_REF = minimum, IOL = 1.0 mA
1.26
V
V
V
3
VOL_XTAL
0.45
0.32
4
VOH_DDR3L High Level Output Voltage for VDD_DDR = minimum, IOH = –1.0 mA
0.963
DDR3L Drive Strength =100 Ω
4
VOL_DDR3L
Low Level Output Voltage for VDD_DDR = minimum, IOL = 1.0 mA
DDR3L Drive Strength =100 Ω
V
V
V
5
VOH_DDR3
High Level Output Voltage for VDD_DDR = minimum, IOH = –1.0 mA
DDR3 Drive Strength = 100 Ω
1.105
5
VOL_DDR3
Low Level Output Voltage for VDD_DDR = minimum, IOL = 1.0 mA
DDR3 Drive Strength = 100 Ω
0.32
6
IIH
High Level Input Current
Low Level Input Current
VDD_EXT = maximum, VIN = VDD_EXT maximum
VDD_EXT = maximum, VIN = 0 V
10
μA
μA
μA
6
IIL
10
7
IIL_PU
Low Level Input Current
Pull-Up
VDD_EXT = maximum, VIN = 0 V
200
8
IIH_PD
High Level Input Current
Pull-Down
VDD_EXT = maximum, VIN = VDD_EXT maximum
200
10
μA
μA
9
IOZH
Three-State Leakage Current VDD_EXT/VDD_DDR = maximum,
VIN = VDD_EXT/VDD_DDR maximum
9
IOZL
Three-State Leakage Current VDD_EXT/VDD_DDR = maximum, VIN = 0 V
10
5
μA
pF
10
CIN
Input Capacitance
TJ = 25°C
IDD_IDLE
VDD_INT Current in Idle
fCCLK = 1000 MHz
ASFSHARC = 0.35
654
mA
f
SYSCLK = 500 MHz
fSCLK0 = 125 MHz
SCLK1 = 250 MHz
f
(Other clocks are disabled)
No peripheral or DMA activity
TJ = 25°C
VDD_INT = 1.0 V
IDD_TYP
VDD_INT Current
fCCLK = 1000 MHz
ASFSHARC = 1.0
1157
mA
fSYSCLK = 500 MHz
fSCLK0 = 125 MHz
fSCLK1 = 250 MHz
(Other clocks are disabled)
DMA data rate = 456 MB/s
TJ = 25°C
VDD_INT = 1.0 V
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Parameter
Conditions
Min
Typ
Max
Unit
IDD_IDLE
VDD_INT Current in Idle
fCCLK = 800 MHz
ASFSHARC = 0.35
535
mA
f
SYSCLK = 400 MHz
fSCLK0 = 100 MHz
SCLK1 = 228.6 MHz
f
(Other clocks are disabled)
No peripheral or DMA activity
TJ = 25°C
VDD_INT = 1.0 V
IDD_TYP
IDD_IDLE
IDD_TYP
VDD_INT Current
fCCLK = 800 MHz
ASFSHARC = 1.0
946
417
735
mA
mA
mA
f
SYSCLK = 400 MHz
fSCLK0 = 100 MHz
SCLK1 = 228.6 MHz
f
(Other clocks are disabled)
DMA data rate = 456 MB/s
TJ = 25°C
VDD_INT = 1.0 V
VDD_INT Current in Idle
fCCLK = 600 MHz
ASFSHARC = 0.35
f
SYSCLK = 300 MHz
fSCLK0 = 75 MHz
SCLK1 = 240 MHz
f
(Other clocks are disabled)
No peripheral or DMA activity
TJ = 25°C
VDD_INT = 1.0 V
VDD_INT Current
fCCLK = 600 MHz
ASFSHARC = 1.0
f
SYSCLK = 300 MHz
fSCLK0 = 75 MHz
SCLK1 = 240 MHz
f
(Other clocks are disabled)
DMA data rate = 456 MB/s
TJ = 25°C
VDD_INT = 1.0 V
Rev. B
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Parameter
Conditions
Min
Typ
Max
Unit
IDD_IDLE
VDD_INT Current in Idle
fCCLK = 400 MHz
ASFSHARC = 0.35
311
mA
f
SYSCLK = 200 MHz
fSCLK0 = 100 MHz
SCLK1 = 250 MHz
f
(Other clocks are disabled)
No peripheral or DMA activity
TJ = 25°C
VDD_INT = 1.0 V
IDD_TYP
VDD_INT Current
fCCLK = 400 MHz
ASFSHARC = 1.0
536
mA
f
SYSCLK = 200 MHz
fSCLK0 = 100 MHz
SCLK1 = 250 MHz
f
(Other clocks are disabled)
DMA data rate = 456 MB/s
TJ = 25°C
VDD_INT = 1.0 V
11
IDD_INT
VDD_INT Current
fCCLK 0 MHz
IDD_INT_TOT
mA
fSCLK0/1 0 MHz
See equation in
the Total
Internal Power
Dissipation
section.
1 Applies to all output and bidirectional pins operating at less than or equal to 62.5 MHz, except DMC and SYS_XTAL0.
2 Applies to all output and bidirectional pins operating above 62.5 MHz and less than or equal to 125 MHz, except DMC.
3 Applies to SYS_XTAL0 pin.
4 Applies to all DMC output and bidirectional signals in DDR3L mode.
5 Applies to all DMC output and bidirectional signals in DDR3 mode.
6 Applies to input pins: SYS_BMODE2-0, SYS_CLKIN, and SYS_HWRST.
7 Applies to input pins with internal pull-ups: JTG_TDI, JTG_TMS, and JTG_TCK.
8 Applies to JTAG_TRST signal.
9 Applies to signals: PA15 to PA0, PB15 to PB0, PC7 to PC0, DAI0_PINx, DAI1_PINx, DMC0_DQx, DMC0_LDQS, DMC0_UDQS, DMC0_LDQS, DMC0_UDQS,
SYS_FAULT, and JTG_TDO.
10Applies to all signal pins.
11See “Estimating Power for ADSP-2156x SHARC+ Processors” (EE-414) for further information.
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Application Dependent Current
Total Internal Power Dissipation
Total power dissipation has two components:
• Static, including leakage current
The application dependent currents include the dynamic cur-
rent in the core clock domain of the SHARC+ core, as well as
the dynamic current in the accelerator block.
• Dynamic, due to transistor switching characteristics for
each clock domain
Dynamic current consumed by the core is subject to an activity
scaling factor (ASF) that represents application code running on
the processor core (see Table 22). The ASF is combined with the
CCLK frequency and VDD_INT dependent dynamic current data
in Table 23 to calculate this portion of the total dynamic power
dissipation component.
Many operating conditions can also affect power dissipation,
including temperature, voltage, operating frequency, and pro-
cessor activity. The following equation describes the internal
current consumption.
I
DD_INT_TOT = IDD_INT_STATIC + IDD_INT_CCLK_SHARC_DYN
DD_INT_DCLK_DYN + IDD_INT_SYSCLK_DYN
+
I
DD_INT_CCLK_SHARC_DYN = Table 23 × ASFSHARC
I
+
+
Table 22. Activity Scaling Factors for the SHARC+® Core
(ASFSHARC
I
I
DD_INT_SCLK0_DYN + IDD_INT_SCLK1_DYN
DD_INT_OCLK_DYN + IDD_INT_ACCL_DYN
+
)
IDD_INT_DMA_DR_DYN
IDD_INT Power Vector
IDD-LS
ASF
0.21
0.35
0.68
0.81
0.92
1.00
1.09
where IDD_INT_STATIC is the sole contributor to the static power
dissipation component and is specified as a function of voltage
(VDD_INT) and junction temperature (TJ) in Table 21.
IDD-IDLE
IDD-NOP
Table 21. Static Current—IDD_INT_STATIC (mA)
IDD-TYP_3070
IDD-TYP_5050
IDD-TYP_7030
IDD-PEAK_100
Voltage (VDD_INT
)
TJ (°C)
–45
0.95 V
12
1.00 V
15
1.05 V
18
–40
13
15
19
–20
17
21
27
Table 23. Dynamic Current for SHARC+®Core
(mA, with ASF = 1.00)
–10
21
26
32
0
26
32
39
Voltage (VDD_INT
)
+10
+25
+40
+55
+70
+85
+100
+105
+115
+125
33
40
49
fCCLK (MHz)
0.95 V
1.00 V 1.05 V
48
58
70
400
271
285
299
337
374
412
449
487
524
561
599
636
674
711
749
71
84
102
148
217
318
465
530
683
880
450
500
550
600
650
700
750
800
850
900
950
1000
305
339
373
406
440
474
508
542
576
610
643
677
321
357
392
428
463
499
535
570
606
642
677
713
105
157
235
347
397
515
665
124
184
272
401
457
591
762
The other eight addends in the IDD_INT_TOT equation comprise
the dynamic power dissipation component and fall into four
broad categories: application dependent currents, clock cur-
rents, currents from high speed peripheral operation, and data
transmission currents.
Rev. B
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Clock Current
HADC DC Accuracy
The dynamic clock currents provide the total power dissipated
by all transistors switching in the clock paths. The power dissi-
pated by each clock domain is dependent on voltage (VDD_INT),
operating frequency, and a unique scaling factor.
Table 25. HADC DC Accuracy1
Parameter
Typ
10
10
2
Unit2
Bits
Bits
LSB
LSB
LSB
LSB
LSB
LSB
Resolution
IDD_INT_SYSCLK_DYN (mA) = 0.626 × fSYSCLK (MHz) ×
VDD_INT (V)
No Missing Codes (NMC)
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Offset Error
I
DD_INT_SCLK0_DYN (mA) = 0.23 × fSCLK0 (MHz) × VDD_INT (V)
1
I
V
DD_INT_SCLK1_DYN (mA) = 0.018 × fSCLK1 (MHz) ×
5
DD_INT (V)
Offset Error Matching
Gain Error
5
I
I
DD_INT_DCLK_DYN (mA) = 0.125 × fDCLK (MHz) × VDD_INT (V)
DD_INT_OCLK_DYN (mA) = 0.048 × fOCLK (MHz) × VDD_INT (V)
3
Gain Error Matching
3
1 See the Operating Conditions section for the HADC0_VINx specification.
Data Transmission Current
2 LSB = HADC0_VREFP ÷ 1024.
The data transmission current represents the power dissipated
when moving data throughout the system via DMA. This cur-
rent is proportional to the data rate. Refer to the power
calculator available with Estimating Power for ADSP-2156x
SHARC+ Processors (EE-414) to estimate IDD_INT_DMA_DR_DYN
based on the bandwidth of the data transfer.
HADC Timing Specifications
Table 26. HADC Timing Specifications
Parameter
Typ
Max
Unit
μs
Conversion Time1
Throughput Range
TWAKEUP
20 × TSAMPLE
HADC
1
MSPS
HADC Electrical Characteristics
100
μs
1 Refer to the ADSP-2156x SHARC+ Processor Hardware Reference for additional
information about TSAMPLE
Table 24. HADC Electrical Characteristics
.
Parameter
Conditions
Typ Unit
IDD_HADC_IDLE
Current consumption on
VDD_HADC
2.0 mA
TMU
TMU Characteristics
HADC is powered on, but not
converting
Table 27. TMU Characteristics
IDD_HADC_ACTIVE
Current consumption on
VDD_HADC during a conversion
2.5 mA
40 μA
Parameter
Resolution
Accuracy
Typ
1
Unit
°C
IDD_HADC_POWERDOWN Current consumption on
VDD_HADC
6
°C
Analog circuitry of the HADC is
powered down
Table 28. TMU Gain and Offset
Junction Temperature Range TMU_GAIN
TMU_OFFSET
–40°C to +40°C
40°C to 85°C
Contact Analog Devices, Inc.
Contact Analog Devices, Inc.
Contact Analog Devices, Inc.
85°C to 125°C
Rev. B
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Table 30. Maximum Duty Cycle for Input Transient Voltage
for VDD_INT and VDD_EXT
ABSOLUTE MAXIMUM RATINGS
Stresses at or above those listed in Table 29 may cause perma-
nent damage to the product. This is a stress rating only;
functional operation of the product at these or any other condi-
tions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum
operating conditions for extended periods may affect product
reliability.
VDD_INT (V)1
1.120
VDD_EXT (V)1
Maximum Duty Cycle2
5%
1.103
10%
20%
30%
50%
75%
100%
1.086
1.077
1.065
Table 29. Absolute Maximum Ratings
1.056
Parameter
Rating
1.050
3.470
Internal (Core) Supply Voltage
–0.3 V to +1.05 V
1 The individual values cannot be combined for analysis of a single instance of
overshoot or undershoot. The worst case observed value must fall within one of
the voltages specified and the total duration of the overshoot or undershoot
(exceeding the 100% case) must be less than or equal to the corresponding duty
cycle.
(VDD_INT
External (I/O) Supply Voltage
(VDD_EXT
External (I/O) Reference Supply
Voltage (VDD_REF
)
–0.3 V to +3.47 V
–0.3 V to +1.89 V
–1.89 V to +1.89 V
–0.3 V to +1.60 V
–0.3 V to +1.89 V
)
2 Duty cycle refers to the percentage of time the signal exceeds the value for the
100% case. This is equivalent to the measured duration of a single instance of
overshoot or undershoot as a percentage of the period of occurrence.
)
(VDD_EXT – VDD_REF) and
(VDD_EXT – VDD_ANA) (VDELTA_EXT_REF
)
Table 31. Maximum Duty Cycle for Input Transient Voltage
DDR3 Controller Supply Voltage
3.3 V VIN Max (V)1 1.8 V VIN Max (V)1 Maximum Duty Cycle2
(VDD_DMC
)
3.47
1.89
100%
Analog Supply Voltage (VDD_ANA
)
1 The individual values cannot be combined for analysis of a single instance of
overshoot or undershoot. The worst case observed value must fall within one of
the voltages specified and the total duration of the overshoot or undershoot
(exceeding the 100% case) must be less than or equal to the corresponding duty
cycle.
HADC Reference Voltage (VHADC_REF) –0.3 V to +1.89 V
DDR3 Input Voltage1
Digital Input Voltage1, 2
TWI Input Voltage1, 3
Output Voltage Swing
Analog Input Voltage4
–0.3 V to +1.60 V
–0.3 V to +3.47 V
2 Duty cycle refers to the percentage of time the signal exceeds the value for the
100% case. This is equivalent to the measured duration of a single instance of
overshoot or undershoot as a percentage of the period of occurrence.
–0.3 V to +3.47 V
–0.3 V to VDD_EXT +0.5 V
–0.2 V to VDD_ANA +0.09 V
6 mA (maximum)
–65C to +150C
I
OH/IOL Current per Signal2
ESD CAUTION
Storage Temperature Range
Junction Temperature While Biased 125C
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
1 Applies only when the related power supply (VDD_DMC or VDD_EXT) is within
specification. When the power supply is below specification, the range is the
voltage being applied to that power domain 0.2 V.
2 Applies to 100% transient duty cycle.
3 Applies to TWI_SCL and TWI_SDA.
4 Applies only when VDD_ANA is within specifications and ≤ 1.8 V. When VDD_ANA
is within specifications and > 1.8 V, the maximum rating is 1.89 V. When
VDD_ANA is below specifications, the range is VDD_ANA 0.09 V.
Rev. B
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TIMING SPECIFICATIONS
Power-Up Reset Timing
Table 32 and Figure 10 show the relationship between power supply startup and processor reset timing, as relating to the clock generation
unit (CGU) and the reset control unit (RCU).
In Figure 10, the VDD_SUPPLIES are VDD_INT, VDD_EXT, VDD_DMC, VDD_REF, and VDD_ANA. The VDELTA_EXT_REF specification must be met
at all times, including during power-up reset and when powering down the device (Figure 11).
Table 32. Power-Up Reset Timing
Parameter
Min
Max
Unit
Timing Requirement
tRST_IN_PWR
SYS_HWRST Deasserted after VDD_SUPPLIES (VDD_INT, VDD_EXT, VDD_DMC, VDD_REF
,
11 × tCKIN
ns
VDD_ANA) and SYS_CLKIN0 are Stable and Within Specification
SYS_HWRST
tRST_IN_PWR
SYS_CLKIN0
V
DD_SUPPLIES
Figure 10. Power-Up Reset Timing
V
DD_EXT
V
DD_EXT
ޤ
V AND VDD_EXT
ޤ
V DD_REF
MUST NOT EXCEED V
DD_ANA
AT ANY TIME.
DELTA_EXT_REF
V
DD_REF,
V
DD_ANA
0V
POWER-UP
OPERATIONAL
POWER-DOWN
Figure 11. Power-Up and Power-Down Voltage Delta Requirement
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Clock and Reset Timing
Table 33 and Figure 12 describe clock and reset operations related to the CGU and RCU. Per the CCLK, SYSCLK, SCLKx, DCLK, and
OCLK timing specifications in Table 19 (Clock Operating Conditions), combinations of SYS_CLKIN0 and clock multipliers must not
select clock rates in excess of the maximum instruction rate of the processor.
Table 33. Clock and Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
fCKIN
SYS_CLKIN0 Frequency (Crystal)1, 2
SYS_CLKIN0 Frequency (External SYS_CLKIN0)1, 2
SYS_CLKIN0 Low Pulse1
SYS_CLKIN0 High Pulse1
RESET Asserted Pulse Width Low3
20
30
30
MHz
MHz
ns
20
tCKINL
tCKINH
tWRST
16.67
16.67
11 × tCKIN
ns
ns
1 Applies to PLL bypass mode and PLL nonbypass mode.
2 The tCKIN period (see Figure 12) equals 1/fCKIN
.
3 Applies after power-up sequence is complete. See Table 32 and Figure 10 for power-up reset timing.
fCKIN
SYS_CLKIN0
tCKINL
tCKINH
tWRST
SYS_HWRST
Figure 12. Clock and Reset Timing
Dynamic Memory Controller (DMC)—Clock, Control, Write and Read Cycle Timing
The DMC clock, control, write and read timings comply with the JEDEC standards. To ensure proper operation of the DDR3/3L, all
DDR3/3L guidelines must be strictly followed. See ADSP-2156x Board Design Guidelines for Dynamic Memory Controller (EE-418).
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Link Ports (LPs)
In LP receive mode, the LP clock is supplied externally and is called fLCLKREXT, therefore the period can be represented by
1
tLCLKREXT
=
---------------
fLCLKREXT
In LP transmit mode, the programmed LP clock (fLCLKTPROG) frequency in megahertz is set by the following equation where VALUE is a
field in the LP_DIV register that can be set from 1 to 255:
fOCLK_0
VALUE 2
fLCLKTPROG
=
---------------------
In the case where VALUE = 0, fLCLKTPROG = fOCLK_0. For all settings of VALUE, the following equation is true:
1
tLCLKTPROG
=
------------------
fLCLKTPROG
Calculation of the link receiver data setup and hold relative to the link clock is required to determine the maximum allowable skew that
can be introduced in the transmission path length difference between LPx_Dx and LPx_CLK. Setup skew is the maximum delay that can
be introduced in LPx_Dx relative to LPx_CLK (setup skew = tLCLKTWH minimum – tDLDCH – tSLDCL). Hold skew is the maximum delay
that can be introduced in LPx_CLK relative to LPx_Dx (hold skew = tLCLKTWL minimum – tHLDCH – tHLDCL). See Table 35 for LP transmit
timing.
Table 34. LPs—Receive1
Parameter
Min
Max
Unit
Timing Requirements
fLCLKREXT
tSLDCL
LPx_CLK Frequency
125
MHz
ns
Data Setup Before LPx_CLK Low
Data Hold After LPx_CLK Low
LPx_CLK Period2
LPx_CLK Width Low2
LPx_CLK Width High2
1.5
tHLDCL
1.4
ns
tLCLKEW
tLCLKRWL
tLCLKRWH
tLCLKREXT – 1
0.5 × tLCLKREXT
0.5 × tLCLKREXT
ns
ns
ns
Switching Characteristic
tDLALC
LPx_ACK Low Delay After LPx_CLK Low3
1.5 × tOCLK_0 + 4
2.5 × tOCLK_0 + 12
ns
1 Specifications apply to LP0 and LP1.
2 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external LPx_CLK. For the external
LPx_CLK ideal maximum frequency, see the fLCLKRTEXT specification in Table 19.
3 LPx_ACK goes low with tDLALC relative to rise of LPx_CLK after first byte, but does not go low if the link buffer of the receiver is not about to fill.
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tLCLKEW
tLCLKRWH
tLCLKRWL
LPx_CLK
tHLDCL
tSLDCL
LPx_D7–0
IN
tDLALC
LPx_ACK (OUT)
Figure 13. LPs—Receive
Table 35. LPs—Transmit1
Parameter
Min
Max
Unit
Timing Requirements
tSLACH
tHLACH
Switching Characteristics
LPx_ACK Setup Before LPx_CLK Low
2 × tOCLK_0 + 13.5
–2.5
ns
ns
LPx_ACK Hold After LPx_CLK Low
tDLDCH
tHLDCH
tLCLKTWL
Data Delay After LPx_CLK High
2.23
ns
ns
ns
ns
ns
ns
Data Hold After LPx_CLK High
LPx_CLK Width Low
–1.04
2
0.4 × tLCLKTPROG
0.4 × tLCLKTPROG
0.6 × tLCLKTPROG
0.6 × tLCLKTPROG
2
tLCLKTWH
LPx_CLK Width High
2
tLCLKTW
LPx_CLK Period
N × tLCLKTPROG – 0.7
tOCLK_0 + 4
tDLACLK
LPx_CLK Low Delay After LPx_ACK High
2 × tOCLK_0 + 1 × tLPCLK + 10
1 Specifications apply to LP0 and LP1.
2 See Table 19 for details on the minimum period that can be programmed for fLCLKTPROG
.
LAST BYTE
FIRST BYTE
1
tLCLKTWH tLCLKTWL
TRANSMITTED
TRANSMITTED
LPx_CLK
tDLDCH
tHLDCH
LPx_Dx
(DATA)
OUT
tSLACH
tHLACH
tDLACLK
LPx_ACK (IN)
NOTES
The t
and tHLACH specifications apply only to the LPx_CLK falling edge. If these specifications are met,
LPx_CSLLACKH extends and the dotted LPx_CLK falling edge does not occur as shown. The position of the
dotted falling edge can be calculated using the tLCLKTWH specification. tLCLKTWH Min must be used for tSLACH
and tLCLKTWH Max for tHLACH
.
Figure 14. LPs—Transmit
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Serial Ports (SPORTs)
To determine whether a device is compatible with the SPORT at clock speed n, the following specifications must be confirmed: frame sync
delay and frame sync setup and hold; data delay and data setup and hold; and serial clock (SPTx_CLK) width. In Figure 15, either the ris-
ing edge or the falling edge of SPTx_A/BCLK (external or internal) can be used as the active sampling edge.
When externally generated, the SPORT clock is called fSPTCLKEXT
:
1
tSPTCLKEXT
=
-----------------------
fSPTCLKEXT
When internally generated, the programmed SPORT clock (fSPTCLKPROG) frequency in megahertz is set by the following equation:
fSCLK0
CLKDIV + 1
fSPTCLKPROG
=
------------------------
1
tSPTCLKPROG
=
---------------------------
fSPTCLKPROG
where CLKDIV is a field in the SPORT_DIV register that can be set from 0 to 65,535.
Table 36. SPORTs—External Clock1
Parameter
Min
Max
Unit
Timing Requirements
tSFSE
Frame Sync Setup Before SPTx_CLK
2
ns
(Externally Generated Frame Sync in Either Transmit or Receive
Mode)2
tHFSE
Frame Sync Hold After SPTx_CLK
3
ns
(Externally Generated Frame Sync in Either Transmit or Receive
Mode)2
tSDRE
Receive Data Setup Before Receive SPTx_CLK2
Receive Data Hold After SPTx_CLK2
SPTx_CLK Width3
2
ns
ns
ns
ns
tHDRE
3
tSPTCLKW
tSPTCLK
0.5 × tSPTCLKEXT – 1.5
tSPTCLKEXT – 1.5
SPTx_CLK Period3
Switching Characteristics
tDFSE
Frame Sync Delay After SPTx_CLK
11
11
ns
ns
(Internally Generated Frame Sync in Either Transmit or Receive
Mode)4
tHOFSE
Frame Sync Hold After SPTx_CLK
2
2
(Internally Generated Frame Sync in Either Transmit or Receive
Mode)4
tDDTE
tHDTE
Transmit Data Delay After Transmit SPTx_CLK4
Transmit Data Hold After Transmit SPTx_CLK4
ns
ns
1 Specifications apply to all four SPORTs.
2 Referenced to sample edge.
3 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the ideal maximum external SPTx_CLK.
For the external SPTx_CLK ideal maximum frequency, see the fSPTCLKEXT specification in Table 19.
4 Referenced to drive edge.
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Table 37. SPORTs—Internal Clock1
Parameter
Min
Max
Unit
Timing Requirements
tSFSI
Frame Sync Setup Before SPTx_CLK
12
(Externally Generated Frame Sync in Either Transmit or
ns
ns
Receive Mode)2
tHFSI
Frame Sync Hold After SPTx_CLK
(Externally Generated Frame Sync in Either Transmit or
Receive Mode)2
–0.5
tSDRI
tHDRI
Switching Characteristics
Receive Data Setup Before SPTx_CLK2
Receive Data Hold After SPTx_CLK2
3.4
2
ns
ns
tDFSI
Frame Sync Delay After SPTx_CLK (Internally Generated
3.5
3.5
ns
ns
Frame Sync in Transmit or Receive Mode)3
tHOFSI
Frame Sync Hold After SPTx_CLK (Internally Generated
Frame Sync in Transmit or Receive Mode)3
Transmit Data Delay After SPTx_CLK3
Transmit Data Hold After SPTx_CLK3
SPTx_CLK Width4
–3
tDDTI
ns
ns
ns
ns
tHDTI
–3
tSPTCLKIW
tSPTCLKWI
0.5 × tSPTCLKPROG – 2
tSPTCLKPROG – 1.5
SPTx_CLK Period4
1 Specifications apply to all four SPORTs.
2 Referenced to the sample edge.
3 Referenced to drive edge.
4 See Table 19 for details on the minimum period that can be programmed for fSPTCLKPROG
.
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DATA RECEIVE—INTERNAL CLOCK
DATA RECEIVE—EXTERNAL CLOCK
DRIVE EDGE
SAMPLE EDGE
DRIVE EDGE SAMPLE EDGE
tSPTCLKIW
tSPTCLKW
SPTx_A/BCLK
(SPORT CLOCK)
SPTx_A/BCLK
(SPORT CLOCK)
tDFSI
tDFSE
tHOFSI
tSFSI
tHFSI
tHOFSE
tSFSE
tHFSE
SPTx_A/BFS
(FRAME SYNC)
SPTx_A/BFS
(FRAME SYNC)
tSDRI
tHDRI
tSDRE
tHDRE
SPTx_A/BDx
(DATA CHANNEL A/B)
SPTx_A/BDx
(DATA CHANNEL A/B)
DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
DATA TRANSMIT—EXTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
tSPTCLKIW
tSPTCLKW
SPTx_A/BCLK
(SPORT CLOCK)
SPTx_A/BCLK
(SPORT CLOCK)
tDFSI
tDFSE
tHOFSI
tSFSI
tHFSI
tHOFSE
tSFSE
tHFSE
SPTx_A/BFS
(FRAME SYNC)
SPTx_A/BFS
(FRAME SYNC)
tDDTI
tDDTE
tHDTI
tHDTE
SPTx_A/BDx
(DATA CHANNEL A/B)
SPTx_A/BDx
(DATA CHANNEL A/B)
Figure 15. SPORTs
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Table 38. SPORTs—Enable and Three-State1
Parameter
Min
1
Max
Unit
Switching Characteristics
tDDTEN
tDDTTE
tDDTIN
tDDTTI
Data Enable From External Transmit SPTx_CLK2
ns
ns
ns
ns
Data Disable From External Transmit SPTx_CLK2
Data Enable From Internal Transmit SPTx_CLK2
Data Disable From Internal Transmit SPTx_CLK2
14
–2.5
2.8
1 Specifications apply to all four SPORTs.
2 Referenced to drive edge.
DRIVE EDGE
DRIVE EDGE
SPTx_CLK
(SPORT CLOCK EXTERNAL)
tDDTEN
tDDTTE
SPTx_A/BDx
(DATA CHANNEL A/B)
DRIVE EDGE
DRIVE EDGE
SPTx_CLK
(SPORT CLOCK INTERNAL)
tDDTIN
tDDTTI
SPTx_A/BDx
(DATA CHANNEL A/B)
Figure 16. SPORTs—Enable and Three-State
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The SPTx_TDV output signal becomes active in SPORT multichannel mode. During transmit slots (enabled with active channel selection
registers) the SPTx_TDV is asserted for communication with external devices.
Table 39. SPORTs—Transmit Data Valid (TDV)1
Parameter
Min
2
Max
Unit
Switching Characteristics
tDRDVEN
tDFDVEN
tDRDVIN
tDFDVIN
Data Valid Enable Delay From Drive Edge of External Clock2
ns
ns
ns
ns
Data Valid Disable Delay From Drive Edge of External Clock2
Data Valid Enable Delay From Drive Edge of Internal Clock2
Data Valid Disable Delay From Drive Edge of Internal Clock2
14
–2.5
3.5
1 Specifications apply to all four SPORTs.
2 Referenced to drive edge.
DRIVE EDGE
DRIVE EDGE
SPTx_CLK
(SPORT EXTERNAL CLOCK)
tDRDVEN
tDFDVEN
SPTx_A/BTDV
DRIVE EDGE
DRIVE EDGE
SPTx_CLK
(SPORT INTERNAL CLOCK)
tDRDVIN
tDFDVIN
SPTx_A/BTDV
Figure 17. SPORTs—Transmit Data Valid Internal and External Clock
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Table 40. SPORTs—External Late Frame Sync1
Parameter
Min
Max
Unit
Switching Characteristics
tDDTLFSE
DataDelayFromLateExternalTransmitFrameSyncorExternalReceiveFrame
14
ns
ns
Sync with SPORT_MCTL_A/B bits MCE = 1, MFD = 02
tDDTENFS
Data Enable for SPORT_MCTL_A/B bits MCE = 1, MFD = 02
0.5
1 Specifications apply to all four SPORTs.
2 The tDDTLFSE and tDDTENFS parameters apply to left justified as well as standard serial mode and MCE = 1, MFD = 0.
DRIVE
SAMPLE
DRIVE
SPTx_A/BCLK
(SPORT CLOCK)
tHFSE/I
tSFSE/I
SPTx_A/BFS
(FRAME SYNC)
tDDTE/I
tDDTENFS
tHDTE/I
SPTx_A/BDx
(DATA CHANNEL A/B)
1ST BIT
2ND BIT
tDDTLFSE
Figure 18. External Late Frame Sync
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Asynchronous Sample Rate Converter (ASRC)—Serial Input Port
The ASRC input signals are routed from the DAI0_PINx pins using the SRU. Therefore, the timing specifications provided in Table 41 are
valid at the DAI0_PINx pins.
Table 41. ASRC, Serial Input Port
Parameter
Min
Max
Unit
Timing Requirements
1
tSRCSFS
Frame Sync Setup Before Serial Clock Rising Edge
4
ns
ns
ns
ns
ns
ns
1
tSRCHFS
Frame Sync Hold After Serial Clock Rising Edge
Data Setup Before Serial Clock Rising Edge
Data Hold After Serial Clock Rising Edge
Clock Width
5.5
1
tSRCSD
4
1
tSRCHD
tSRCCLKW
tSRCCLK
5.5
tSCLK0 – 1
2 × tSCLK0
Clock Period
1
The serial clock, data, and frame sync signals can originate from any of the DAI pins. The serial clock and frame sync signals can also originate via PCG or SPORTs. The
input of the PCG can be either CLKIN or any of the DAI pins.
SAMPLE EDGE
tSRCCLK
DAI0_PIN20–1
(SCLK0)
tSRCCLKW
tSRCSFS
tSRCHFS
DAI0_PIN20–1
(FS)
tSRCSD
tSRCHD
DAI0_PIN20–1
(SDATA)
Figure 19. ASRC Serial Input Port Timing
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Asynchronous Sample Rate Converter (ASRC)—Serial Output Port
For the serial output port, the frame sync is an input and it must meet setup and hold times with regard to SCLK0 on the output port. The
serial data output has a hold time and delay specification with regard to the serial clock. The serial clock rising edge is the sampling edge,
and the falling edge is the drive edge.
Table 42. ASRC, Serial Output Port
Parameter
Min
Max
Unit
Timing Requirements
1
tSRCSFS
Frame Sync Setup Before Serial Clock Rising Edge
4
ns
ns
ns
ns
1
tSRCHFS
tSRCCLKW
tSRCCLK
Frame Sync Hold After Serial Clock Rising Edge
5.5
Clock Width
Clock Period
tSCLK0 – 1
2 × tSCLK0
Switching Characteristics
1
tSRCTDD
Transmit Data Delay After Serial Clock Falling Edge
Transmit Data Hold After Serial Clock Falling Edge
13
ns
ns
1
tSRCTDH
1
1 The serial clock, data, and frame sync signals can originate from any of the DAI pins. The serial clock and frame sync signals can also originate via PCG or SPORTs. The input
of the PCG can be either CLKIN, SCLK0, or any of the DAI pins.
SAMPLE EDGE
tSRCCLK
DAI0_PIN20–1
(SCLK0)
tSRCCLKW
tSRCSFS
tSRCHFS
DAI0_PIN20–1
(FS)
tSRCTDD
tSRCTDH
DAI0_PIN20–1
(SDATA)
Figure 20. ASRC Serial Output Port Timing
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SPI Port—Master Timing
SPI0, SPI1, and SPI2
Table 43 and Figure 21 describe the SPI port master operations.
When internally generated, the programmed SPI clock (fSPICLKPROG) frequency in megahertz is set by the following equation:
fCDU_CLKO0
BAUD + 1
fSPICLKPROG
=
---------------------
1
tSPICLKPROG
=
--------------------------
fSPICLKPROG
where BAUD is a field in the SPIx_CLK register that can be set from 0 to 65,535.
Note that
• In dual-mode data transmit, the SPIx_MISO signal is also an output.
• In quad-mode data transmit, the SPIx_MISO, SPIx_D2, and SPIx_D3 signals are also outputs.
• In dual-mode data receive, the SPIx_MOSI signal is also an input.
• In quad-mode data receive, the SPIx_MOSI, SPIx_D2, and SPIx_D3 signals are also inputs.
• Quad mode is supported by SPI1 and SPI2.
• CPHA is a configuration bit in the SPI_CTL register.
Table 43. SPI Port—Master Timing1
Parameter
Timing Requirements
tSSPIDM
Min
Max
Unit
Data Input Valid to SPIx_CLK Edge (Data Input Setup)
SPIx_CLK Sampling Edge to Data Input Invalid
3.5
2
ns
ns
tHSPIDM
Switching Characteristics
tSDSCIM
SPIx_SEL Low to First SPI_CLK Edge for CPHA = 12
SPIx_SEL Low to First SPI_CLK Edge for CPHA = 02
SPIx_CLK High Period3
SPIx_CLK Low Period3
SPIx_CLK Period3
Last SPIx_CLK Edge to SPIx_SEL High for CPHA = 12
Last SPIx_CLK Edge to SPIx_SEL High for CPHA = 02
Sequential Transfer Delay2, 4
tSPICLKPROG – 5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.5 × tSPICLKPROG – 5
0.5 × tSPICLKPROG – 1.5
0.5 × tSPICLKPROG – 1.5
tSPICLKPROG – 1.5
tSPICHM
tSPICLM
tSPICLK
tHDSM
1.5 × tSPICLKPROG – 5
tSPICLKPROG – 5
tSPITDM
tSPICLKPROG – 1.5
tDDSPIDM
tHDSPIDM
SPIx_CLK Edge to Data Out Valid (Data Out Delay)
SPIx_CLK Edge to Data Out Invalid (Data Out Hold)
2.7
–3.75
1 All specifications apply to SPI0, SPI1, and SPI2.
2 Specification assumes the LEADX and LAGX bits in the SPI_DLY register are 1.
3 See Table 19 for details on the minimum period that can be programmed for tSPICLKPROG
4 Applies to sequential mode with STOP ≥ 1.
.
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SPIx_SEL
(OUTPUT)
tSDSCIM
tSPICLM
tSPICHM
tSPICLK
tHDSM
tSPITDM
SPIx_CLK
(OUTPUT)
tHDSPIDM
tDDSPIDM
DATA OUTPUTS
(SPIx_MOSI)
tSSPIDM
CPHA = 1
tHSPIDM
DATA INPUTS
(SPIx_MISO)
tHDSPIDM
tDDSPIDM
DATA OUTPUTS
(SPIx_MOSI)
tSSPIDM
tHSPIDM
CPHA = 0
DATA INPUTS
(SPIx_MISO)
Figure 21. SPI Port—Master Timing
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SPI Port—Slave Timing
SPI0, SPI1, and SPI2
Table 44 and Figure 22 describe SPI port slave operations. Note that
• In dual-mode data transmit, the SPIx_MOSI signal is also an output.
• In quad-mode data transmit, the SPIx_MOSI, SPIx_D2, and SPIx_D3 signals are also outputs.
• In dual-mode data receive, the SPIx_MISO signal is also an input.
• In quad-mode data receive, the SPIx_MISO, SPIx_D2, and SPIx_D3 signals are also inputs.
• In SPI slave mode, the SPI clock is supplied externally and is called fSPICLKEXT
:
1
tSPICLKEXT
=
----------------------
fSPICLKEXT
• Quad mode is supported by SPI1 and SPI2.
• CPHA is a configuration bit in the SPI_CTL register.
Table 44. SPI Port—Slave Timing1
Parameter
Min
Max
Unit
Timing Requirements
tSPICHS
tSPICLS
tSPICLK
tHDS
SPIx_CLK High Period2
SPIx_CLK Low Period2
SPIx_CLK Period2
0.5 × tSPICLKEXT – 1.5
ns
ns
ns
ns
ns
ns
ns
ns
0.5 × tSPICLKEXT – 1.5
tSPICLKEXT – 1.5
Last SPIx_CLK Edge to SPIx_SS Not Asserted
Sequential Transfer Delay
5
tSPITDS
tSDSCI
tSSPID
tHSPID
tSPICLKEXT – 1.5
SPIx_SS Assertion to First SPIx_CLK Edge
Data Input Valid to SPIx_CLK Edge (Data Input Setup)
SPIx_CLK Sampling Edge to Data Input Invalid
11.7
2
1.6
Switching Characteristics
tDSOE
SPIx_SS Assertion to Data Out Active
0
0
14.12
12.6
ns
ns
ns
ns
tDSDHI
tDDSPID
tHDSPID
SPIx_SS Deassertion to Data High Impedance
SPIx_CLK Edge to Data Out Valid (Data Out Delay)
SPIx_CLK Edge to Data Out Invalid (Data Out Hold)
14.16
1.5
1 All specifications apply to SPI0, SPI1, and SPI2.
2 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPIx_CLK. For the external
SPIx_CLK ideal maximum frequency, see the fSPICLKTEXT specification in Table 19.
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SPIx_SS
(INPUT)
tSDSCI
tSPICLS
tSPICHS
tSPICLK
tHDS
tSPITDS
SPIx_CLK
(INPUT)
tDSOE
tDDSPID
tHDSPID
tDDSPID
tDSDHI
DATA OUTPUTS
(SPIx_MISO)
CPHA = 1
tSSPID
tHSPID
DATA INPUTS
(SPIx_MOSI)
tDSOE
tHDSPID
tDDSPID
tDSDHI
DATA OUTPUTS
(SPIx_MISO)
tHSPID
CPHA = 0
tSSPID
DATA INPUTS
(SPIx_MOSI)
Figure 22. SPI Port—Slave Timing
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SPI Port—SPIx_RDY Slave Timing
SPIx_RDY provides flow control. CPOL, CPHA, and FCCH are configuration bits in the SPIx_CTL register.
Table 45. SPI Port—SPIx_RDY Slave Timing1
Parameter
Conditions
Min
Max
Unit
Switching Characteristic
tDSPISCKRDYS SPIx_RDY Deassertion From Last Valid Input SPIx_CLK Edge
FCCH = 0
FCCH = 1
3 × tCDU_CLKO0
4 × tCDU_CLKO0
4 × tCDU_CLKO0 + 10 ns
5 × tCDU_CLKO0 + 10 ns
1 All specifications apply to all three SPIs.
tDSPISCKRDYS
SPIx_CLK
(CPOL = 0)
CPHA = 0
SPIx_CLK
(CPOL = 1)
SPIx_CLK
(CPOL = 0)
CPHA = 1
SPIx_CLK
(CPOL = 1)
SPIx_RDY (O)
Figure 23. SPIx_RDY Deassertion from Valid Input SPIx_CLK Edge in Slave Mode
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SPI Port—Open Drain Mode (ODM) Timing
In Figure 24 and Figure 25, the outputs can be SPIx_MOSI, SPIx_MISO, SPIx_D2, and/or SPIx_D3, depending on the mode of operation.
CPOL and CPHA are configuration bits in the SPI_CTL register.
Table 46. SPI Port—ODM Master Mode Timing1
Parameter
Min
Max
Unit
Switching Characteristics
tHDSPIODMM
tDDSPIODMM
SPIx_CLK Edge to High Impedance From Data Out Valid
SPIx_CLK Edge to Data Out Valid From High Impedance
–1.5
ns
ns
6
1 All specifications apply to all three SPIs.
tHDSPIODMM
tHDSPIODMM
SPIx_CLK
(CPOL = 0)
SPIx_CLK
(CPOL = 1)
OUTPUT
(CPHA = 1)
OUTPUT
(CPHA = 0)
tDDSPIODMM
tDDSPIODMM
Figure 24. ODM Master Mode
Table 47. SPI Port—ODM Slave Mode1
Parameter
Min
Max
Unit
Timing Requirements
tHDSPIODMS
tDDSPIODMS
SPIx_CLK Edge to High Impedance From Data Out Valid
SPIx_CLK Edge to Data Out Valid From High Impedance
0
ns
ns
11
1 All specifications apply to all three SPIs.
tHDSPIODMS
tHDSPIODMS
SPIx_CLK
(CPOL = 0)
SPIx_CLK
(CPOL = 1)
OUTPUT
(CPHA = 1)
OUTPUT
(CPHA = 0)
tDDSPIODMS
tDDSPIODMS
Figure 25. ODM Slave Mode
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SPI Port—SPIx_RDY Master Timing
SPIx_RDY is used to provide flow control. CPOL and CPHA are configuration bits in the SPIx_CTL register, whereas LEADX, LAGX,
and STOP are configuration bits in the SPIx_DLY register.
Table 48. SPI Port—SPIx_RDY Master Timing1
Parameter
Conditions
Min
Max
Unit
Timing Requirement
tSRDYSCKM
Setup Time for SPIx_RDY
(2 + 2 × BAUD2) × tCDU_CLKO0 + 11
ns
Deassertion Before Last Valid
Data SPIx_CLK Edge
Switching Characteristic
3
tDRDYSCKM Assertion of SPIx_RDY to First
BAUD = 0, CPHA = 0 4.5 × tCDU_CLKO0
BAUD = 0, CPHA = 1 4 × tCDU_CLKO0
5.5 × tCDU_CLKO0 + 11
5 × tCDU_CLKO0 + 11
ns
ns
SPIx_CLK Edge of Next Transfer
BAUD > 0, CPHA = 0 (1 + 1.5 × BAUD2) × tCDU_CLKO0 (2+ 2.5×BAUD2)×tCDU_CLKO0 +11 ns
BAUD > 0, CPHA = 1 (1 + 1 × BAUD2) × tCDU_CLKO0 (2 + 2 × BAUD2) × tCDU_CLKO0 + 11 ns
1 All specifications apply to all three SPIs.
2 BAUD value is set using the SPIx_CLK.BAUD bits. BAUD value = SPIx_CLK.BAUD bits + 1.
3 Specification assumes the LEADX, LAGX, and STOP bits in the SPI_DLY register are zero.
tSRDYSCKM
SPIx_RDY
SPIx_CLK
(CPOL = 0)
SPIx_CLK
(CPOL = 1)
Figure 26. SPIx_RDY Setup Before SPIx_CLK
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tDRDYSCKM
SPIx_RDY
SPIx_CLK
(CPOL = 0)
CPHA = 0
SPIx_CLK
(CPOL = 1)
SPIx_CLK
(CPOL = 0)
CPHA = 1
SPIx_CLK
(CPOL = 1)
Figure 27. SPIx_CLK Switching Diagram after SPIx_RDY Assertion
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OSPI Port—Master Timing
OSPI0
Table 49 and Figure 28 describe the OSPI port master operations. Slave mode is not supported for OSPI.
When internally generated, the programmed SPI clock (fSPICLKPROG) frequency in megahertz is set by the following equation:
f
SYSCLK
f
=
----------------------
SPICLKPROG
PRG_MBD
1
t
=
--------------------------------------
f
SPICLKPROG
SPICLKPROG
where PRG_MBD is the master mode baud rate divisor.
Note that
• In dual-mode data transmit, the OSPI0_MISO signal is also an output.
• In quad-mode data transmit, the OSPI0_MISO, OSPI0_D2, and OSPI0_D3 signals are also outputs.
• In octal-mode data transmit, the OSPI0_MISO, OSPI0_D2, OSPI0_D3, OSPI0_D4, OSPI0_D5, OSPI0_D6, and OSPI0_D7 signals
are also outputs.
• In dual-mode data receive, the OSPI0_MOSI signal is also an input.
• In quad-mode data receive, the OSPI0_MOSI, OSPI0_D2, and OSPI0_D3 signals are also inputs.
• In octal-mode data receive, the OSPI0_MISO, OSPI0_D2, OSPI0_D3, OSPI0_D4, OSPI0_D5, OSPI0_D6, and OSPI0_D7 signals are
also outputs.
• CPHA is a configuration bit in the OSPI0_CTL register.
Table 49. OSPI0 Port—Master Timing1
Parameter
Min
Max
Unit
Timing Requirements
tSSPIDM Data Input Valid to OSPI0_CLK Sampling tSYSCLK + 2
Edge (Data Input Setup) 2
ns
ns
tHSPIDM OSPI0_CLK Sampling Edge to Data Input
Invalid (Data Input Hold)2
1
Switching Characteristics
tSDSCIM OSPI0_SEL Low to First OSPI0_CLK Edge3 0.5 × tSPICLKPROG + PRG_CSSOT × tSYSCLK – 1.5
ns
ns
ns
ns
ns
tSPICHM OSPI0_CLK High Period4
0.5 × tSPICLKPROG – 1.5
0.5 × tSPICLKPROG – 1.5
tSPICLKPROG – 1.5
tSPICLM
tSPICLK
tHDSM
OSPI0_CLK Low Period4
OSPI0_CLK Period4
Last OSPI0_CLK Edge to OSPI0_SEL
High for Mode = 05
PRG_CSEOT × tSYSCLK – 1
Last OSPI0_CLK Edge to OSPI0_SEL
High for Mode = 35, 6
PRG_CSEOT × tSYSCLK + 0.5 × tSPICLKPROG – 1
ns
tDDSPIDM OSPI0_CLK Edge to Data Out Valid to
Driving Edge (Data Out Delay)7
(PRG_WRHLD + 1) × tSYSCLK + 2.5 ns
ns
tHDSPIDM OSPI0_CLK Edge to Data Out Invalid to
Driving Edge (Data Out Hold)7
PRG_WRHLD × tSYSCLK – 1
tPD
OSPI0_CLK Internal to OSPI0_CLK Output 2.2
Delay (Propagation Delay)
5.5
ns
1 All specifications apply to OSPI0 only.
2
tSSPIDM and tHSPIDM specifications are characterized for OSPI0_RDC settings of 2 for DDR mode and 4 for SDR mode.
3 PRG_CSSOT = chip select start of transfer (defined in OSPI0_DLY[7:0]).
4 See Table 19 for details on the minimum period that can be programmed for tSPICLKPROG
5 PRG_CSEOT = chip select end of transfer (defined in OSPI0_DLY[15:8]).
6 Mode = clock phase and clock polarity bits (defined inOSPI0_CTL[2:1]).
.
7 PRG_WRHLD = transmit delay to improve output hold (defined in OSPI0_RDC[19:16]).
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OSPI0_SEL
(OUTPUT)
OSPI0_CLK
(INTERNAL)
tPD
tSDSCIM
tSPICLM
tSPICHM
tSPICLK
tHDSM
OSPI0_CLK
(OUTPUT)
tHDSPIDM
tDDSPIDM
DATA OUTPUTS
(OSPI0_MOSI)
tSSPIDM
CPHA = 1
tHSPIDM
DATA INPUTS
(OSPI0_MISO)
tHDSPIDM
tDDSPIDM
DATA OUTPUTS
(OSPI0_MOSI)
tSSPIDM
tHSPIDM
CPHA = 0
DATA INPUTS
(OSPI0_MISO)
Figure 28. OSPI Port—Master Timing
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Precision Clock Generator (PCG) (Direct Pin Routing)
This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes inputs directly from the DAI
pins (via pin buffers) and sends outputs directly to the DAI pins. For the other cases, where the PCG inputs and outputs are not directly
routed to/from DAI pins (via pin buffers), there is no timing data available. All timing parameters and switching characteristics apply to
external DAI pins (DAI0_PINx).
Table 50. PCG (Direct Pin Routing)
Parameter
Min
Max
Unit
Timing Requirements
tPCGIP
tSTRIG
Input Clock Period
tSCLK0 × 2
ns
ns
PCG Trigger Setup Before Falling Edge of PCG Input 4.5
Clock
tHTRIG
PCG Trigger Hold After Falling Edge of PCG Input
Clock
3
ns
Switching Characteristics
tDPCGIO
PCGOutputClockandFrameSyncActiveEdgeDelay 2
After PCG Input Clock
10
ns
ns
tDTRIGCLK
PCG Output Clock Delay After PCG Trigger
PCG Frame Sync Delay After PCG Trigger
Output Clock Period
2 + (2.5 × tPCGIP
)
13.5 + (2.5 × tPCGIP)
1
tDTRIGFS
2.5 + ((2.5 + D – PH) × tPCGIP
2 × tPCGIP – 1
)
13.5 + ((2.5 + D – PH) × tPCGIP) ns
ns
2
tPCGOW
1 D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-2156x SHARC+ Processor Hardware Reference.
2 Normal mode of operation.
tSTRIG
tHTRIG
DAI0_PIN20–1
PCG_TRIGx_I
DAI0_PIN20–1
PCG_EXTx_I
(CLKIN)
tDPCGIO
tPCGIP
DAI0_PIN20–1
PCG_CLKx_O
tDTRIGCLK
tPCGOW
tDPCGIO
DAI0_PIN20–1
PCG_FSx_O
tDTRIGFS
Figure 29. PCG (Direct Pin Routing)
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General-Purpose IO Port Timing
Table 51 and Figure 30 describe I/O timing, related to the general-purpose ports (PORT).
Table 51. General-Purpose Port Timing
Parameter
Min
Max
Unit
Timing Requirement
tWFI
General-Purpose Port Pin Input Pulse Width
2 × tSCLK0 – 1.5
ns
tWFI
GPIO INPUT
Figure 30. General-Purpose Port Timing
General-Purpose I/O Timer Cycle Timing
Table 52, Table 53, and Figure 31 describe timer expired operations related to the general-purpose timer (TIMER0). The width value is the
timer period assigned in the TMx_TMRn_WIDTH register and can range from 1 to 232 – 1. When externally generated, the TMx_CLK
clock is called fTMRCLKEXT
:
1
tTMRCLKEXT
=
------------------------
fTMRCLKEXT
Table 52. Timer Cycle Timing—Internal Mode
Parameter
Min
Max
Unit
Timing Requirements
tWL
Timer Pulse Width Input Low (Measured In SCLK0 Cycles)1 2 × tSCLK0
Timer Pulse Width Input High (Measured In SCLK0 Cycles)1 2 × tSCLK0
ns
ns
tWH
Switching Characteristic
tHTO
Timer Pulse Width Output (Measured In SCLK0 Cycles)2
tSCLK0 × WIDTH – 1.7
tSCLK0 × WIDTH + 1.5
ns
1 The minimum pulse width applies for timer signals in width capture and external clock modes.
2 WIDTH refers to the value in the TMRx_WIDTH register (it can vary from 2 to 232 – 1).
Table 53. Timer Cycle Timing—External Mode
Parameter
Min
Max
Unit
Timing Requirements
tWL
Timer Pulse Width Input Low (Measured In EXT_CLK Cycles)1 2 × tEXT_CLK
Timer Pulse Width Input High (Measured In EXT_CLK Cycles)1 2 × tEXT_CLK
ns
ns
ns
tWH
tEXT_CLK
Timer External Clock Period2
tTMRCLKEXT
Switching Characteristic
tHTO
Timer Pulse Width Output (Measured In EXT_CLK Cycles)3
tEXT_CLK × WIDTH – 1.5
tEXT_CLK × WIDTH + 1.5
ns
1 The minimum pulse width applies for timer signals in width capture and external clock modes.
2 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external TMR_CLK. For the external
TMR_CLK maximum frequency, see the fTMRCLKEXT specification in Table 19.
3 WIDTH refers to the value in the TMRx_WIDTH register (it can vary from 1 to 232 – 1).
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TMR OUTPUT
tHTO
TMR INPUT
tWH, tWL
Figure 31. Timer Cycle Timing
DAIx Pin to DAIx Pin Direct Routing (DAI0 Block and DAI1 Block)
Table 54 and Figure 32 describe I/O timing related to the digital audio interface (DAI) for direct pin connections only (for example,
DAIx_PB01_I to DAIx_PB02_O).
Table 54. DAI Pin to DAI Pin Routing
Parameter
Min
Max
Unit
Switching Characteristic
tDPIO
Delay DAI Pin Input Valid to DAI Output Valid
1.5
12
ns
DAIx_PINn
DAIx_PINm
tDPIO
Figure 32. DAI Pin to DAI Pin Direct Routing
Up/Down Counter/Rotary Encoder Timing
Table 55 and Figure 33 describe timing related to the general-purpose counter (CNT).
Table 55. Up/Down Counter/Rotary Encoder Timing
Parameter
Min
Max
Unit
Timing Requirement
tWCOUNT
Up/Down Counter/Rotary Encoder Input Pulse Width
2 × tSCLK0
ns
CNT0_UD
CNT0_DG
CNT0_ZM
tWCOUNT
Figure 33. Up/Down Counter/Rotary Encoder Timing
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Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
The UART ports receive and transmit operations are described in the ADSP-2156x SHARC+ Processor Hardware Reference.
Sony/Philips Digital Interface (S/PDIF) Transmitter
Serial data input to the S/PDIF transmitter can be formatted as left justified, I2S, or right justified with word widths of 16, 18, 20, or 24 bits.
The following sections provide timing for the transmitter.
S/PDIF Transmitter Serial Input Waveforms
Table 56 and Figure 34 show the right justified mode. Frame sync is high for the left channel and low for the right channel. Data is valid on
the rising edge of the serial clock. The MSB is delayed the minimum in 24-bit output mode or the maximum in 16-bit output mode from a
frame sync transition, so that when there are 64 serial clock periods per frame sync period, the LSB of the data is right justified to the next
frame sync transition.
Table 56. S/PDIF Transmitter Right Justified Mode
Parameter
Timing Requirement
tRJD
Conditions
Nominal
Unit
Frame Sync to MSB Delay in Right Justified Mode
16-bit word mode
18-bit word mode
20-bit word mode
24-bit word mode
16
14
12
8
SCLK0
SCLK0
SCLK0
SCLK0
LEFT/RIGHT CHANNEL
DAI_P20–1
FS
DAI_P20–1
SCLK0
tRJD
DAI_P20–1
SDATA
LSB
MSB
MSB–1 MSB–2
LSB+2 LSB+1
LSB
Figure 34. Right Justified Mode
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Table 57 and Figure 35 show the default I2S justified mode. The frame sync is low for the left channel and high for the right channel. Data
is valid on the rising edge of the serial clock. The MSB is left justified to the frame sync transition but with a delay.
Table 57. S/PDIF Transmitter I2S Mode
Parameter
Timing Requirement
tI2SD
Nominal
Unit
Frame Sync to MSB Delay in I2S Mode
1
SCLK0
LEFT/RIGHT CHANNEL
DAI_P20–1
(FS)
DAI_P20–1
(SCLK0)
tI2SD
DAI_P20–1
(SDATA)
MSB
MSB–1 MSB–2
LSB+2 LSB+1
LSB
Figure 35. I2S Justified Mode
Table 58 and Figure 36 show the left justified mode. The frame sync is high for the left channel and low for the right channel. Data is valid
on the rising edge of the serial clock. The MSB is left justified to the frame sync transition with no delay.
Table 58. S/PDIF Transmitter Left Justified Mode
Parameter
Timing Requirement
tLJD
Nominal
Unit
Frame Sync to MSB Delay in Left Justified Mode
0
SCLK0
DAI_P20–1
(FS)
LEFT/RIGHT CHANNEL
DAI_P20–1
(SCLK0)
tLJD
DAI_P20–1
(SDATA)
MSB
MSB–1 MSB–2
LSB+2 LSB+1
LSB
Figure 36. Left Justified Mode
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S/PDIF Transmitter Input Data Timing
The timing requirements for the S/PDIF transmitter are given in Table 59. Input signals are routed to the DAI0_PINx pins using the SRU.
Therefore, the timing specifications provided below are valid at the DAI0_PINx pins.
Table 59. S/PDIF Transmitter Input Data Timing
Parameter
Min
Max
Unit
Timing Requirements
1
tSISFS
Frame Sync Setup Before Serial Clock Rising Edge
3.4
3
ns
ns
ns
ns
ns
ns
ns
ns
1
tSIHFS
Frame Sync Hold After Serial Clock Rising Edge
Data Setup Before Serial Clock Rising Edge
Data Hold After Serial Clock Rising Edge
Transmit Clock Width
1
tSISD
3
1
tSIHD
3
tSITXCLKW
tSITXCLK
tSISCLKW
tSISCLK
9
Transmit Clock Period
20
36
80
Clock Width
Clock Period
1 The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. The input of the
PCG can be either CLKIN or any of the DAI pins.
SAMPLE EDGE
tSITXCLKW
tSITXCLK
DAI0_PIN20–1
(TxCLK)
tSISCLK
tSISCLKW
DAI0_PIN20–1
(SCLK0)
tSISFS
tSIHFS
DAI0_PIN20–1
(FS)
tSISD
tSIHD
DAI0_PIN20–1
(SDATA)
Figure 37. S/PDIF Transmitter Input Timing
Oversampling Clock (TxCLK) Switching Characteristics
The S/PDIF transmitter requires an oversampling clock input. This high frequency clock (TxCLK) input is divided down to generate the
internal biphase clock.
Table 60. Oversampling Clock (TxCLK) Switching Characteristics
Parameter
Max
Unit
Switching Characteristics
fTXCLK_384
fTXCLK_256
fFS
Frequency for TxCLK = 384 × Frame Sync
Oversampling ratio × frame sync ≤ 1/tSITXCLK
MHz
MHz
kHz
Frequency for TxCLK = 256 × Frame Sync
Frame Rate (FS)
49.2
192.0
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S/PDIF Receiver
The following section describes timing as it relates to the S/PDIF receiver.
Internal Digital PLL Mode
In the internal digital PLL mode, the internal digital PLL generates the 512 × FS clock.
Table 61. S/PDIF Receiver Internal Digital PLL Mode Timing
Parameter
Min
Max
Unit
Switching Characteristics
tDFSI
Frame Sync Delay After Serial Clock
Frame Sync Hold After Serial Clock
Transmit Data Delay After Serial Clock
Transmit Data Hold After Serial Clock
5
5
ns
ns
ns
ns
tHOFSI
tDDTI
tHDTI
–2
–2
DRIVE EDGE
SAMPLE EDGE
DAI0_PIN20–1
(SCLK0)
tDFSI
tHOFSI
DAI0_PIN20–1
(FS)
tDDTI
tHDTI
DAI0_PIN20–1
(DATA CHANNEL A/B)
Figure 38. S/PDIF Receiver Internal Digital PLL Mode Timing
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MediaLB (MLB)
All the numbers shown in Table 62 are applicable for all MLB speed modes (1024 FS, 512 FS, and 256 FS) for the 3-pin protocol, unless
otherwise specified. Refer to the Media Local Bus Specification Version 4.2 for more details.
Table 62. 3-Pin MLB Interface Specifications
Parameter
Min
Typ
Max
Unit
tMLBCLK
MLB Clock Period
1024 FS
20.3
40
81
ns
ns
ns
512 FS
256 FS
tMCKL
MLBCLK Low Time
1024 FS
6.1
14
30
ns
ns
ns
512 FS
256 FS
tMCKH
MLBCLK High Time
1024 FS
9.3
14
30
ns
ns
ns
512 FS
256 FS
tMCKR
MLBCLK Rise Time (VIL to VIH)
1024 FS
1
3
ns
ns
512 FS/256 FS
tMCKF
MLBCLK Fall Time (VIH to VIL)
1024 FS
1
3
ns
ns
512 FS/256 FS
1
tMPWV
MLBCLK Pulse Width Variation
1024 FS
0.7
2.0
nspp
nspp
512 FS/256
tDSMCF
tDHMCF
tMCFDZ
tMCDRV
DAT/SIG Input Setup Time
1
2
0
ns
ns
ns
ns
DAT/SIG Input Hold Time
DAT/SIG Output Time to Three-State
DAT/SIG Output Data Delay From MLBCLK Rising Edge
15
8
2
tMDZH
Bus Hold Time
1024 FS
512 FS/256
2
4
ns
ns
CMLB
DAT/SIG Pin Load
1024 FS
40
60
pf
pf
512 FS/256
1 Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in nanoseconds peak-to-peak.
2 Board designs must ensure the high impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be minimized while
meeting the maximum capacitive load listed.
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MLB_SIG/
MLB_DAT
VALID
(Rx, Input)
tDHMCF
tDSMCF
tMCKH
tMCKL
MLB_CLK
tMCKR
tMCKF
tMLBCLK
tMCFDZ
tMCDRV
tMDZH
MLB_SIG/
MLB_DAT
(Tx, Output)
VALID
Figure 39. MLB Timing (3-Pin Interface)
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Program Trace Macrocell (PTM) Timing
Table 63 and Figure 40 provide I/O timing related to the PTM.
Table 63. TRACE0 Timing
Parameter
Min
Max
Unit
Switching Characteristics
tDTRD
tHTRD
tPTRCK
TRACE0 Data Delay From Trace Clock Maximum
TRACE0 Data Hold From Trace Clock Minimum
TRACE0 Clock Period Minimum
0.5 × tSCLK0 + 3
ns
ns
ns
0.5 × tSCLK0 – 2
2 × tSCLK0 – 1
t
PTRCK
TRACE0_CLK
t
t
HTRD
t
HTRD
TRACE0_DX
D0
D1
t
DTRD
DTRD
Figure 40. Trace Timing
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Debug Interface (JTAG Emulation Port) Timing
Table 64 and Figure 41 provide I/O timing related to the debug interface (JTAG emulator port).
Table 64. JTAG Emulation Port Timing
Parameter
Min
Max
Unit
Timing Requirements
tTCK
JTG_TCK Period
20
4
ns
ns
ns
ns
ns
TCK
tSTAP
JTG_TDI, JTG_TMS Setup Before JTG_TCK High
JTG_TDI, JTG_TMS Hold After JTG_TCK High
System Inputs Setup Before JTG_TCK High1
System Inputs Hold After JTG_TCK High1
JTG_TRST Pulse Width (Measured in JTG_TCK Cycles)2
tHTAP
4
tSSYS
4
tHSYS
4
tTRSTW
4
Switching Characteristics
tDTDO
tDSYS
JTG_TDO Delay From JTG_TCK Low
System Outputs Delay After JTG_TCK Low3
12
17
ns
ns
1 System Inputs = DAI0_PIN20-19, DAI0_PIN12-1, DAI1_PIN20-19, DAI1_PIN12-1, DMC0_A15-0, DMC0_DQ15-0, DMC0_RESET, PA_15-0, PB_15-0, PC_7-0,
SYS_BMODE2-0, SYS_FAULT.
2 50 MHz maximum.
3 System Outputs = DMC0_A15-0, DMC0_BA2-0, DMC0_CAS, DMC0_CK, DMC0_CKE, DMC0_CS0, DMC0_DQ15-0, DMC0_LDM, DMC0_LDQS, DMC0_ODT,
DMC0_RAS, DMC0_RESET, DMC0_UDM, DMC0_UDQS, DMC0_WE, PA_15-0, PB_15-0, PC_7-0, SYS_CLKOUT, SYS_FAULT, SYS_RESOUT.
tTCK
JTG_TCK
tSTAP
tHTAP
JTG_TMS
JTG_TDI
tDTDO
JTG_TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 41. JTAG Port Timing
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OUTPUT DRIVE CURRENTS
20
Figure 42 through Figure 47 show typical current voltage char-
acteristics for the output drivers of the ADSP-2156x processors.
The curves represent the current drive capability of the output
drivers as a function of output voltage.
V
V
V
= 1.575V AT –40°C
= 1.500V AT +25°C
= 1.425V AT +125°C
18
16
14
12
10
8
DD
DD
DD
V
OH
50
V
V
V
= 3.47V AT –40°C
= 3.30V AT +25°C
= 3.13V AT +125°C
DD
DD
DD
40
30
6
V
OH
20
4
10
2
0
0
V
OL
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
–10
–20
–30
–40
–50
SOURCE VOLTAGE (V)
Figure 44. Driver Type B and Driver Type C (DDR3 Drive Strength 100 Ω)
0
V
V
V
= 1.575V AT –40°C
= 1.500V AT +25°C
= 1.425V AT +125°C
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
DD
DD
DD
–2
–4
SOURCE VOLTAGE (V)
Figure 42. Driver Type A Current for All Pins Operating
at Less Than or Equal to 62.5 MHz (3.3 V VDD_EXT
V
OL
)
–6
–8
50
40
V
V
V
= 3.47V AT –40°C
DD
DD
DD
= 3.30V AT +25°C
= 3.13V AT +125°C
–10
–12
–14
–16
V
OH
30
20
10
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
V
SOURCE VOLTAGE (V)
–10
–20
–30
–40
–50
OL
Figure 45. Driver Type B and Driver Type C (DDR3 Drive Strength 100 Ω)
18
16
14
12
10
8
V
V
V
= 1.418V AT –40°C
= 1.350V AT +25°C
= 1.285V AT +125°C
DD
DD
DD
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
V
SOURCE VOLTAGE (V)
OH
Figure 43. Driver Type A Current for All Pins Operating Above
62.5 MHz and Less Than or Equal to125 MHz (3.3 V VDD_EXT
)
6
4
2
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
SOURCE VOLTAGE (V)
Figure 46. Driver Type B and Driver Type C (DDR3L Drive Strength100 Ω)
Rev. B
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ADSP-21562/21563/21565/21566/21567/21569
0
REFERENCE
SIGNAL
V
V
V
= 1.418V AT –40°C
= 1.350V AT +25°C
= 1.285V AT +125°C
DD
DD
DD
–2
–4
tDIS
tENA
V
OL
–6
–8
–10
–12
–14
OUTPUT STOPS DRIVING
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Figure 49. Output Enable/Disable
SOURCE VOLTAGE (V)
Figure 47. Driver Type B and Driver Type C (DDR3L Drive Strength 100 Ω)
Output Disable Time Measurement
Output pins are considered disabled when they stop driving,
enter a high impedance state, and start to decay from the output
high or low voltage. The output disable time, tDIS, is the interval
from when a reference signal reaches a high or low voltage level
to the point when the output stops driving, as shown on the left
side of Figure 49).
TEST CONDITIONS
All timing parameters appearing in this data sheet were mea-
sured under the conditions described in this section. Figure 48
shows the measurement point for ac measurements (except out-
put enable/disable). The measurement point, VMEAS, is
VDD_EXT/2 for VDD_EXT (nominal) = 3.3 V.
Capacitive Loading
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all pins (see Figure 50). VLOAD is equal
to VDD_EXT/2. Figure 51 through Figure 54 show how output
rise time varies with capacitance. The delay and hold specifica-
tions given must be derated by a factor derived from these
figures. The graphs in Figure 51 through Figure 54 cannot be
linear outside the ranges shown.
INPUT
OR
OUTPUT
V
V
MEAS
MEAS
Figure 48. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)
TESTER PIN ELECTRONICS
Output Enable Time Measurement
50:
V
LOAD
T1
Output pins are considered enabled when they make a transi-
tion from a high impedance state to the point when they start
driving.
DUT
OUTPUT
45:
70:
ZO = 50:ꢀ(impedance)
TD = 4.04 r 1.18 ns
The output enable time, tENA, is the interval from the point
when a reference signal reaches a high or low voltage level to the
point when the output starts driving, as shown on the right side
of Figure 49. If multiple pins are enabled, the measurement
value is that of the first pin to start driving.
50:
0.5pF
4pF
2pF
400:
NOTES:
THE WORST-CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED.THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY,THE SYSTEM CAN INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
Figure 50. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Rev. B
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6
5
4
3
2
1
0
1.2
tRISE = 3.3V AT +25°C
tFALL = 3.3V AT +25°C
tRISE = 3.135V AT +125°C
tFALL = 3.135V AT +125°C
tRISE = 3.465V AT –40°C
tFALL = 3.465V AT –40°C
tRISE = 1.35V AT +25°C
tFALL = 1.35V AT +25°C
tRISE = 1.283V AT +125°C
1.0
tFALL = 1.283V AT +125°C
tRISE = 1.418V AT –40°C
tFALL = 1.418V AT –40°C
0.8
0.6
0.4
0.2
0
0
5
10
15
20
25
30
0
1
2
3
4
5
6
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
Figure 51. Driver Type A Rise and Fall Times (10% to 90%) vs. Load
Capacitance for All Pins Operating Above 62.5 MHz and
Less Than or Equal to 125 MHz
Figure 54. Driver Type B and Driver Type C Rise and Fall Times
(10% to 90%) vs. Load Capacitance for DDR3L at 100 Ω
ENVIRONMENTAL CONDITIONS
8
The ADSP-2156x processor is rated for performance over the
temperature range specified in Operating Conditions.
tRISE = 3.3V AT +25°C
tFALL = 3.3V AT +25°C
7
tRISE = 3.135V AT +125°C
tFALL = 3.135V AT +125°C
The JESD51 package thermal characteristics in this section are
provided for package comparison and estimation purposes only.
They are not intended for accurate system temperature calcula-
tion. System thermal simulation is required for accurate
temperature analysis that accounts for all specific 3D system
design features, including, but not limited to other heat sources,
use of heat-sinks, and the system enclosure. Thermal models are
available under the Tools and Simulations tab of the product
page.
6
5
4
3
2
1
0
tRISE = 3.465V AT –40°C
tFALL = 3.465V AT –40°C
In Table 65 and Table 66, airflow measurements comply with
JEDEC standards JESD51-2 and JESD51-6, and the junction-to-
board measurement complies with JESD51-8. Test board design
complies with JEDEC standards JESD51-7 (for leaded surface
mount packages). The junction-to-case measurement complies
with MIL- STD-883 (Method 1012.1). All measurements use a
2S2P JEDEC test board.
0
5
10
15
20
25
30
LOAD CAPACITANCE (pF)
Figure 52. Driver Type A Rise and Fall Times (10% to 90%) vs. Load
Capacitance for All Pins Operating at Less Than or Equal to 62.5 MHz
1.2
To estimate the junction temperature of a single device while on
a JEDEC 2S2P PCB, use:
tRISE = 1.5V AT +25°C
tFALL = 1.5V AT +25°C
tRISE = 1.425V AT +125°C
1.0
tFALL = 1.425V AT +125°C
TJ = TCASE + (JT × PD)
where:
tRISE = 1.575V AT –40°C
tFALL = 1.575V AT –40°C
0.8
TJ is the junction temperature (°C).
0.6
0.4
0.2
0
T
CASE is the case temperature (°C) measured at the top center of
the package.
JT is the typical value (junction-to-top of package characteri-
zation parameter) from Table 65 and Table 66.
PD is the power dissipation (see the Total Internal Power Dissi-
pation section for the method to calculate PD).
0
1
2
3
4
5
6
LOAD CAPACITANCE (pF)
Figure 53. Driver Type B and Driver Type C Typical Rise and Fall Times
(10% to 90%) vs. Load Capacitance for DDR3 at 100 Ω
Rev. B
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ADSP-21562/21563/21565/21566/21567/21569
Values of JA are provided for package comparison and PCB
design considerations. JA can be used for a first-order approxi-
mation of TJ by the equation:
TJ = TA + (JA × PD)
where TA is the ambient temperature (°C).
Values of JC are provided for package comparison and PCB
design considerations when an external heat sink is required.
Note that the thermal characteristics values provided in
Table 65 and Table 66 are modeled values.
Table 65. Thermal Characteristics for 400 CSP_BGA
Parameter Conditions
Typical Unit
JA
JA
JA
JC
JT
JT
JT
0 linear m/s air flow
13.72
12.90
12.54
3.39
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1 linear m/s air flow
2 linear m/s air flow
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
0.06
0.08
0.08
Table 66. Thermal Characteristics for 120 LQFP_EP
Parameter Conditions Typical Unit
JA
JA
JA
JC
JT
JT
JT
0 linear m/s air flow
11.08
10.21
9.86
6.87
0.20
0.30
0.36
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1 linear m/s air flow
2 linear m/s air flow
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
Rev. B
|
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ADSP-21562/21563/21565/21566/21567/21569
ADSP-2156x 400-BALL BGA BALL ASSIGNMENTS
The ADSP-2156x 400-Ball BGA Ball Assignments (Numerical
by Ball Number) table lists the 400-ball BGA package by ball
number.
The ADSP-2156x 400-Ball BGA Ball Assignments (Alphabetical
by Pin Name) table lists the 400-ball BGA package by pin name.
ADSP-2156x 400-BALL BGA BALL ASSIGNMENTS (NUMERICAL BY BALL NUMBER)
Ball No. Pin Name
Ball No. Pin Name
Ball No. Pin Name
Ball No. Pin Name
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
GND
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
DMC0_LDM
DMC0_DQ08
GND
E01
E02
E03
E04
E05
E06
E07
E08
E09
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
F01
F02
F03
F04
F05
F06
F07
F08
F09
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
DMC0_DQ05
DMC0_DQ06
GND
G01
G02
G03
G04
G05
G06
G07
G08
G09
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
H01
H02
H03
H04
H05
H06
H07
H08
H09
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
DMC0_DQ04
DMC0_DQ02
GND
DMC0_DQ11
DMC0_DQ10
DMC0_UDQS
DMC0_DQ15
DMC0_UDM
PB_00
GND
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
GND
VDD_INT
VDD_INT
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_REF
VDD_REF
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_INT
VDD_INT
GND
GND
GND
PB_03
SYS_BMODE2
SYS_HWRST
JTG_TRST
PB_05
PB_01
SYS_RESOUT
JTG_TDO
JTG_TMS
JTG_TDI
GND
SYS_FAULT
DMC0_WE
DMC0_A14
DMC0_A13
DMC0_A10
DMC0_A08
DMC0_BA1
DMC0_A07
DMC0_A04
GND
GND
GND
GND
GND
DMC0_A03
DMC0_A02
DMC0_DQ07
GND
DMC0_BA2
DMC0_CAS
DMC0_LDQS
DMC0_LDQS
GND
DMC0_RZQ
DMC0_VREF
DMC0_DQ03
GND
GND
GND
DMC0_DQ12
DMC0_UDQS
DMC0_DQ14
DMC0_DQ13
PB_04
DMC0_DQ09
GND
GND
VDD_INT
VDD_INT
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_INT
VDD_INT
GND
VDD_INT
VDD_INT
VDD_DMC
VDD_DMC
GND
GND
GND
GND
PB_02
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
GND
SYS_BMODE1
SYS_BMODE0
JTG_TCK
GND
GND
GND
DMC0_RESET
DMC0_A15
DMC0_A12
DMC0_A11
DMC0_A09
DMC0_BA0
DMC0_A06
GND
GND
GND
GND
GND
VDD_DMC
VDD_DMC
VDD_INT
VDD_INT
GND
GND
GND
GND
GND
DMC0_A00
DMC0_A01
DMC0_RAS
DMC0_CS0
DMC0_ODT
DMC0_CKE
DMC0_A05
Rev. B
|
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ADSP-21562/21563/21565/21566/21567/21569
Ball No. Pin Name
Ball No. Pin Name
Ball No. Pin Name
Ball No. Pin Name
J01
J02
J03
J04
J05
J06
J07
J08
J09
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
K01
K02
K03
K04
K05
K06
K07
K08
K09
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
L01
L02
L03
L04
L05
L06
L07
L08
DMC0_DQ01
DMC0_DQ00
GND
L09
GND
N17
N18
N19
N20
P01
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
R01
R02
R03
R04
R05
R06
R07
R08
R09
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
T01
T02
T03
T04
GND
T05
T06
T07
T08
T09
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
U01
U02
U03
U04
U05
U06
U07
U08
U09
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
V01
V02
V03
V04
V05
V06
V07
V08
V09
V10
V11
V12
VDD_EXT
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_EXT
GND
L10
GND
GND
L11
GND
HADC0_VIN0
HADC0_VIN1
GND
DMC0_VREF
VDD_INT
VDD_DMC
VDD_DMC
GND
L12
GND
L13
GND
L14
VDD_INT
VDD_INT
GND
PA_02
L15
PA_01
L16
VDD_EXT
VDD_REF
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_REF
VDD_EXT
GND
GND
L17
GND
GND
L18
HADC0_VREFN
VDD_ANA
HADC0_VREFP
GND
GND
L19
GND
L20
GND
M01
M02
M03
M04
M05
M06
M07
M08
M09
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
N01
N02
N03
N04
N05
N06
N07
N08
N09
N10
N11
N12
N13
N14
N15
N16
VDD_INT
VDD_INT
VDD_INT
VDD_INT
GND
GND
DAI1_PIN09
DAI1_PIN06
DAI1_PIN04
GND
SYS_CLKOUT
VDD_EXT
VDD_INT
VDD_INT
VDD_INT
GND
PA_10
DMC0_CK
DMC0_CK
GND
PA_08
GND
GND
GND
GND
GND
DAI1_PIN02
GND
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
GND
GND
GND
VDD_EXT
VDD_INT
VDD_INT
VDD_DMC
GND
GND
GND
GND
PA_04
VDD_INT
VDD_REF
VDD_EXT
GND
GND
PA_03
VDD_EXT
VDD_REF
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_REF
VDD_EXT
GND
GND
GND
GND
GND
HADC0_VIN2
HADC0_VIN3
SYS_CLKIN0
GND
GND
GND
GND
VDD_INT
VDD_INT
VDD_INT
GND
DAI1_PIN10
DAI1_PIN07
DAI1_PIN05
PA_07
PA_00
VDD_EXT
VDD_REF
VDD_INT
VDD_INT
GND
GND
PA_09
GND
GND
GND
GND
SYS_XTAL0
GND
GND
PB_06
GND
DAI1_PIN03
DAI1_PIN08
DAI1_PIN01
GND
PB_09
GND
GND
PB_12
VDD_EXT
VDD_INT
VDD_INT
VDD_INT
GND
GND
PA_11
GND
DAI0_PIN02
DAI0_PIN06
DAI0_PIN09
DAI0_PIN20
VDD_INT
VDD_REF
VDD_EXT
PA_05
PA_06
GND
Rev. B
|
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ADSP-21562/21563/21565/21566/21567/21569
Ball No. Pin Name
V13
V14
V15
V16
V17
V18
V19
V20
W01
W02
W03
W04
W05
W06
W07
W08
W09
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
Y01
Y02
Y03
Y04
Y05
Y06
Y07
Y08
Y09
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
PC_00
PC_05
GND
GND
DAI1_PIN19
GND
DAI1_PIN11
DAI1_PIN12
GND
GND
PB_08
PB_07
PB_13
PA_12
PA_14
PA_15
DAI0_PIN03
DAI0_PIN05
DAI0_PIN08
DAI0_PIN12
DAI0_PIN19
PB_15
PC_01
PC_03
PC_06
DAI1_PIN20
GND
GND
GND
GND
PB_10
PB_11
GND
PA_13
GND
DAI0_PIN01
DAI0_PIN04
DAI0_PIN07
DAI0_PIN10
DAI0_PIN11
GND
PB_14
PC_02
GND
PC_04
PC_07
GND
GND
Rev. B
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ADSP-21562/21563/21565/21566/21567/21569
ADSP-2156x 400-BALL BGA BALL ASSIGNMENTS (ALPHABETICAL BY PIN NAME)
Pin Name
Ball No. Pin Name
Ball No. Pin Name
Ball No. Pin Name
Ball No.
K13
K17
K18
K19
K20
L02
DAI0_PIN01
DAI0_PIN02
DAI0_PIN03
DAI0_PIN04
DAI0_PIN05
DAI0_PIN06
DAI0_PIN07
DAI0_PIN08
DAI0_PIN09
DAI0_PIN10
DAI0_PIN11
DAI0_PIN12
DAI0_PIN19
DAI0_PIN20
DAI1_PIN01
DAI1_PIN02
DAI1_PIN03
DAI1_PIN04
DAI1_PIN05
DAI1_PIN06
DAI1_PIN07
DAI1_PIN08
DAI1_PIN09
DAI1_PIN10
DAI1_PIN11
DAI1_PIN12
DAI1_PIN19
DAI1_PIN20
DMC0_A00
DMC0_A01
DMC0_A02
DMC0_A03
DMC0_A04
DMC0_A05
DMC0_A06
DMC0_A07
DMC0_A08
DMC0_A09
DMC0_A10
DMC0_A11
DMC0_A12
DMC0_A13
DMC0_A14
DMC0_A15
DMC0_BA0
DMC0_BA1
Y08
V09
W09
Y09
W10
V10
Y10
W11
V11
Y11
Y12
W12
W13
V12
R20
P18
R18
T20
U20
T19
U19
R19
T18
U18
V19
V20
V17
W18
D19
D20
C20
C19
A19
B20
B18
A18
A16
B16
A15
B15
B14
A14
A13
B13
B17
A17
DMC0_BA2
DMC0_CAS
DMC0_CK
DMC0_CK
DMC0_CKE
DMC0_CS0
DMC0_DQ00
DMC0_DQ01
DMC0_DQ02
DMC0_DQ03
DMC0_DQ04
DMC0_DQ05
DMC0_DQ06
DMC0_DQ07
DMC0_DQ08
DMC0_DQ09
DMC0_DQ10
DMC0_DQ11
DMC0_DQ12
DMC0_DQ13
DMC0_DQ14
DMC0_DQ15
DMC0_LDM
DMC0_LDQS
DMC0_LDQS
DMC0_ODT
DMC0_RAS
DMC0_RESET
DMC0_RZQ
DMC0_UDM
DMC0_UDQS
DMC0_UDQS
DMC0_VREF
DMC0_VREF
DMC0_WE
GND
E19
E20
J19
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
C16
C17
C18
D02
D04
D05
D06
D07
D12
D13
D14
D15
D16
D17
D18
E03
E18
F03
F18
G03
G18
H02
H03
H08
H09
H10
H11
H12
H13
H18
J03
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
J20
H20
F20
J02
L03
J01
L08
G02
H01
G01
E01
E02
D01
C02
D03
A03
A02
B03
B06
B05
A05
C01
F01
F02
H19
F19
B12
G19
A06
A04
B04
G20
J04
L09
L10
L11
L12
L13
L16
L17
M01
M02
M08
M09
M10
M11
M12
M13
M17
M18
N02
N08
N09
N10
N11
N12
N13
N17
N18
P01
P17
P19
P20
R02
R17
T01
T04
T17
U01
U04
U05
J08
J09
J10
A12
A01
A20
B01
B02
B19
C03
C04
C05
C06
C14
C15
J11
J12
GND
J13
GND
J18
GND
K01
K02
K03
K08
K09
K10
K11
K12
GND
GND
GND
GND
GND
GND
GND
Rev. B
|
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ADSP-21562/21563/21565/21566/21567/21569
Pin Name
GND
Ball No. Pin Name
Ball No. Pin Name
Ball No. Pin Name
Ball No.
E17
F04
F05
F16
F17
G04
G05
G16
G17
H04
H05
H16
H17
J05
U16
U17
V03
V04
V15
V16
V18
W01
W02
W19
W20
Y01
Y02
Y05
Y07
Y13
Y16
Y19
Y20
N19
N20
M19
M20
L18
L20
B11
C13
C11
C12
A10
N03
P03
P02
R03
R01
T02
T03
V01
U03
V02
U02
V08
W06
Y06
W07
W08
A07
C09
PB_02
B08
C07
B07
C08
V05
W04
W03
V06
Y03
Y04
V07
W05
Y14
W14
V13
W15
Y15
W16
Y17
V14
W17
Y18
B10
B09
A08
N01
M03
A11
A09
C10
L01
L19
F06
F07
F08
F09
F10
F11
F12
F13
F14
F15
G06
G07
G08
G09
G12
G13
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
G14
G15
H06
H07
H14
H15
J06
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
GND
PB_03
GND
PB_04
GND
PB_05
GND
PB_06
GND
PB_07
GND
PB_08
GND
PB_09
J07
GND
PB_10
K07
D08
D09
D10
D11
K04
L04
M04
M16
N04
N16
P04
P16
R04
R16
T05
T16
U06
U07
U08
U09
U10
U11
U12
U13
U14
U15
E04
E05
E06
E07
E08
E09
E10
E11
E12
E13
E14
E15
E16
GND
PB_11
GND
PB_12
GND
PB_13
GND
PB_14
GND
PB_15
GND
PC_00
J14
GND
PC_01
J15
GND
PC_02
J16
GND
PC_03
J17
GND
PC_04
K05
K06
K14
K15
K16
L05
L06
L07
L14
L15
M05
M06
M07
M14
N06
N07
N14
P06
P07
P08
P09
P10
P11
P12
P13
P14
R06
R07
R08
R09
HADC0_VIN0
HADC0_VIN1
HADC0_VIN2
HADC0_VIN3
HADC0_VREFN
HADC0_VREFP
JTG_TCK
JTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
PA_00
PC_05
PC_06
PC_07
SYS_BMODE0
SYS_BMODE1
SYS_BMODE2
SYS_CLKIN0
SYS_CLKOUT
SYS_FAULT
SYS_HWRST
SYS_RESOUT
SYS_XTAL0
VDD_ANA
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
PA_01
PA_02
PA_03
PA_04
PA_05
PA_06
PA_07
PA_08
PA_09
PA_10
PA_11
PA_12
PA_13
PA_14
PA_15
PB_00
PB_01
Rev. B
|
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ADSP-21562/21563/21565/21566/21567/21569
Pin Name
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
Ball No.
R10
R11
R12
R13
R14
G10
G11
M15
N05
N15
P05
P15
R05
R15
T06
T07
T08
T09
T10
T11
T12
T13
T14
T15
Rev. B
|
Page 96 of 104
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ADSP-21562/21563/21565/21566/21567/21569
CONFIGURATION OF THE 400-BALL CSP_BGA
Figure 55 shows an overview of signal placement on the 400-ball CSP_BGA.
TOP VIEW
A1 BALL
CORNER
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
A
B
C
D
E
F
GND
G
H
J
I/O SIGNALS
V
DD_EXT
K
L
V
DD_INT
V
DD_DMC
M
N
P
R
T
V
DD_REF
V
DD_ANA
DMC0_VREF
U
V
W
Y
A1 BALL
CORNER
20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
BOTTOM VIEW
Figure 55. 400-Ball CSP_BGA Configuration
Rev. B
|
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ADSP-21562/21563/21565/21566/21567/21569
ADSP-2156x 120-LEAD LQFP LEAD ASSIGNMENTS
The ADSP-2156x 120-Lead LQFP Lead Assignments (Numeri-
cal by Lead Number) table lists the 120-lead LQFP package by
lead number.
The ADSP-2156x 120-Lead LQFP Lead Assignments (Alphabet-
ical by Pin Name) table lists the 120-lead LQFP package by pin
name.
ADSP-2156x 120-LEAD LQFP LEAD ASSIGNMENTS (NUMERICAL BY LEAD NUMBER)
Lead No. Pin Name
Lead No. Pin Name
Lead No. Pin Name
Lead No. Pin Name
1211
GND
1 Pin121 is the GND supply (see Figure 57)
for the processor; this pad must connect
to GND.
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VDD_INT
GND
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
DAI0_PIN01
DAI0_PIN02
DAI0_PIN03
VDD_INT
81
HADC0_VIN0
HADC0_VIN1
HADC0_VREFP
HADC0_VREFN
VDD_ANA
GND
82
VDD_INT
VDD_INT
SYS_CLKIN0
SYS_XTAL0
VDD_REF
VDD_INT
GND
83
84
VDD_INT
85
DAI0_PIN04
DAI0_PIN05
DAI0_PIN06
DAI0_PIN07
VDD_EXT
86
87
VDD_INT
VDD_INT
VDD_INT
GND
88
89
SYS_CLKOUT
VDD_REF
VDD_EXT
VDD_INT
PA_00
90
VDD_REF
91
VDD_INT
GND
DAI0_PIN08
DAI0_PIN09
DAI0_PIN10
DAI0_PIN19
DAI0_PIN20
VDD_INT
92
93
VDD_INT
VDD_INT
VDD_INT
JTG_TDI
94
PA_01
95
PA_02
96
VDD_INT
PA_03
97
JTG_TCK
JTG_TMS
JTG_TDO
VDD_REF
VDD_EXT
SYS_FAULT
JTG_TRST
SYS_HWRST
SYS_BMODE0
SYS_BMODE1
SYS_RESOUT
PB_00
GND
98
PA_04
VDD_INT
99
PA_05
VDD_INT
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
PA_06
VDD_INT
VDD_INT
VDD_REF
VDD_EXT
PA_07
GND
DAI1_PIN20
DAI1_PIN19
DAI1_PIN10
DAI1_PIN09
VDD_REF
PA_08
PA_09
PA_10
VDD_EXT
VDD_INT
GND
VDD_INT
PB_01
DAI1_PIN08
DAI1_PIN07
DAI1_PIN06
DAI1_PIN05
DAI1_PIN04
DAI1_PIN03
DAI1_PIN02
DAI1_PIN01
VDD_EXT
VDD_INT
VDD_EXT
VDD_REF
PB_02
GND
VDD_INT
VDD_INT
PA_11
PB_03
PA_12
PB_04
PA_13
PB_05
PA_14
VDD_INT
VDD_INT
VDD_INT
GND
VDD_EXT
VDD_REF
PA_15
VDD_REF
VDD_INT
Rev. B
|
Page 98 of 104
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ADSP-21562/21563/21565/21566/21567/21569
ADSP-2156x 120-LEAD LQFP LEAD ASSIGNMENTS (ALPHABETICAL BY PIN NAME)
Pin Name
DAI0_PIN01
DAI0_PIN02
DAI0_PIN03
DAI0_PIN04
DAI0_PIN05
DAI0_PIN06
DAI0_PIN07
DAI0_PIN08
DAI0_PIN09
DAI0_PIN10
DAI0_PIN19
DAI0_PIN20
DAI1_PIN01
DAI1_PIN02
DAI1_PIN03
DAI1_PIN04
DAI1_PIN05
DAI1_PIN06
DAI1_PIN07
DAI1_PIN08
DAI1_PIN09
DAI1_PIN10
DAI1_PIN19
DAI1_PIN20
GND
Lead No.
41
Pin Name
PA_03
Lead No.
18
Pin Name
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
VDD_REF
Lead No.
45
42
PA_04
19
57
43
PA_05
20
59
46
PA_06
21
60
47
PA_07
25
61
48
PA_08
26
69
49
PA_09
27
80
52
PA_10
28
87
53
PA_11
34
88
54
PA_12
35
89
55
PA_13
36
91
56
PA_14
37
93
77
PA_15
40
94
76
PB_00
108
109
113
114
115
116
105
106
05
95
75
PB_01
110
117
118
119
07
74
PB_02
73
PB_03
72
PB_04
71
PB_05
70
SYS_BMODE0
SYS_BMODE1
SYS_CLKIN0
SYS_CLKOUT
SYS_FAULT
SYS_HWRST
SYS_RESOUT
SYS_XTAL0
VDD_ANA
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
11
66
23
65
39
64
10
51
63
102
104
107
06
67
02
79
GND
09
100
112
GND
30
1 Pin121 is the GND supply (see Figure 57)
for the processor; this pad must connect
to GND.
GND
31
85
GND
58
12
GND
62
24
GND
86
38
GND
90
50
GND
92
68
GND
120
1211
81
78
GND
101
111
01
HADC0_VIN0
HADC0_VIN1
82
HADC0_VREFN 84
HADC0_VREFP 83
03
04
JTG_TCK
JTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
PA_00
97
96
99
98
103
14
15
16
08
13
17
22
29
32
PA_01
33
PA_02
44
Rev. B
|
Page 99 of 104
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February 2021
ADSP-21562/21563/21565/21566/21567/21569
CONFIGURATION OF THE 120-LEAD LQFP LEAD CONFIGURATION
Figure 56 shows the top view of the 120-lead LQFP lead configuration and Figure 57 shows the bottom view of the 120-lead LQFP lead
configuration.
LEAD 120
LEAD 91
LEAD 1
LEAD 90
LEAD 1
INDICATOR
120-LEAD LQFP
TOP VIEW
LEAD 30
LEAD 61
LEAD 31
LEAD 60
Figure 56. 120-Lead LQFP Lead Configuration (Top View)
LEAD 91
LEAD 120
LEAD 90
LEAD 1
120-LEAD LQFP
BOTTOM VIEW
GND PAD
(LEAD 121)
LEAD 61
LEAD 30
LEAD 60
LEAD 31
Figure 57. 120-Lead LQFP Lead Configuration (Bottom View)
Rev. B
|
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ADSP-21562/21563/21565/21566/21567/21569
OUTLINE DIMENSIONS
Dimensions in Figure 58 (for the 400-ball BGA) and Figure 59 (for the 120-lead LQFP) are shown in millimeters.
17.10
17.00 SQ
16.90
A1 BALL
CORNER
A1 BALL
CORNER
20 18 16 14 12 10
19 17 15 13 11
8
6
4
2
9
7
5
3
1
A
C
E
G
J
B
D
F
15.20
H
K
M
P
T
BSC SQ
L
N
R
U
W
0.80
BSC
V
Y
TOP VIEW
0.90
REF
BOTTOM VIEW
DETAIL A
SIDE VIEW
1.38
1.28
1.19
0.99
0.94
0.89
DETAIL A
0.70
SEATING
PLANE
0.390
0.343
0.300
0.50
0.45
0.40
COPLANARITY
0.12
BALL DIAMETER
COMPLIANT TO JEDEC STANDARDS MO-275-MMAB-1
Figure 58. 400-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-400-3)
Dimensions shown in millimeters
Rev. B
|
Page 101 of 104
|
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ADSP-21562/21563/21565/21566/21567/21569
16.20
16.00 SQ
15.80
14.10
14.00 SQ
13.90
11.60 REF
SQ
1.60
0.75
0.60
0.45
MAX
PIN 1
INDICATOR
120
91
91
120
90
1
90
1
1.00 REF
SEATING
PLANE
U-GROOVE
PIN 1
INDICATOR
0.10 REF
5.40 REF
SQ
12°
1.45
1.40
1.35
0.20
0.15
0.09
7°
30
61
61
30
0.15
0°
31
60
60
31
0.10
0.05
TOP VIEW
(PINS DOWN)
BOTTOM VIEW
(PINS UP)
0.08
COPLANARITY
0.23
0.18
0.13
VIEW A
0.40
BSC
LEAD PITCH
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
VIEW A
ROTATED 90
°
CCW
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MS-026-BEE-HD
Figure 59. 120-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP]
(SW-120-4)
Dimensions shown in millimeters
SURFACE-MOUNT DESIGN
Table 67 is provided as an aid to PCB design. For industry-stan-
dard design recommendations, refer to IPC-7351, Generic
Requirements for Surface-Mount Design and Land Pattern
Standard.
Table 67. CSP_BGA Data for Use with Surface-Mount Design
Package
Package Ball Attach Type
Package Solder Mask Opening
Package Ball Pad Size
BC-400-3
Solder Mask Defined
0.4 mm Diameter
0.5 mm Diameter
Rev. B
|
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ADSP-21562/21563/21565/21566/21567/21569
AUTOMOTIVE PRODUCTS
The following models are available with controlled manufacturing to support the quality and reliability requirements of automotive appli-
cations. Note that these automotive models may have specifications that differ from the nonautomotive models; therefore designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown in Table 68 are available
for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information
and to obtain the specific Automotive Reliability reports for these models.
Table 68. Automotive Products
Processor Instruction Temperature
External
Memory Port
Package
Option
Model1, 2
Rate (Max)
600 MHz
600 MHz
400 MHz
600 MHz
1000 MHz
Range3
Package Description
ADSP-21563WCSWZ6
ADSP-21563WCSWZ6RL
ADSP-21566WCBCZ4
ADSP-21567WCBCZ6
ADSP-21569WCBCZ10
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
0
0
1
1
1
120-Lead LQFP_EP, Exposed Pad SW-120-4
120-Lead LQFP_EP, Exposed Pad SW-120-4
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
BC-400-3
BC-400-3
BC-400-3
1 Z =RoHS compliant part.
2 RL = Supplied on Tape and Reel.
3 Referenced temperature is junction temperature. See Operating Conditions for junction temperature (TJ) specification.
PLANNED AUTOMOTIVE PRODUCTION PRODUCTS
Processor Instruction Temperature
External
Memory Port
Package
Option
Model1, 2
Rate (Max)
400 MHz
400 MHz
800 MHz
800 MHz
800 MHz
800 MHz
1000 MHz
Range3
Package Description
ADSP-21562WCSWZ4
ADSP-21562WCSWZ4RL
ADSP-21563WCSWZ8
ADSP-21563WCSWZ8RL
ADSP-21565WCSWZ8
ADSP-21565WCSWZ8RL
ADSP-21565WCSWZ10
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
120-Lead LQFP_EP, Exposed Pad SW-120-4
120-Lead LQFP_EP, Exposed Pad SW-120-4
120-Lead LQFP_EP, Exposed Pad SW-120-4
120-Lead LQFP_EP, Exposed Pad SW-120-4
120-Lead LQFP_EP, Exposed Pad SW-120-4
120-Lead LQFP_EP, Exposed Pad SW-120-4
120-Lead LQFP_EP, Exposed Pad SW-120-4
120-Lead LQFP_EP, Exposed Pad SW-120-4
ADSP21565WCSWZ10RL 1000 MHz
ADSP-21566WCBCZ4RL
ADSP-21567WCBCZ6RL
ADSP-21567WCBCZ8
ADSP-21567WCBCZ8RL
ADSP-21569WCBCZ8
ADSP-21569WCBCZ8RL
ADSP21569WCBCZ10RL
400 MHz
600 MHz
800 MHz
800 MHz
800 MHz
800 MHz
1000 MHz
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
BC-400-3
BC-400-3
BC-400-3
BC-400-3
BC-400-3
BC-400-3
BC-400-3
1 Z =RoHS compliant part.
2 RL = Supplied on Tape and Reel.
3 Referenced temperature is junction temperature. See Operating Conditions for junction temperature (TJ) specification.
Rev. B
|
Page 103 of 104
|
February 2021
ADSP-21562/21563/21565/21566/21567/21569
PLANNED PRODUCTION PRODUCTS
Temperature
Range2
External Memory
Port
0
Processor Instruction
Rate (Max)
Package
Option
Model1
Package Description
ADSP-21562BSWZ4
ADSP-21562KSWZ4
ADSP-21563BSWZ8
ADSP-21565BSWZ8
ADSP-21565BSWZ10
ADSP-21565KSWZ10
ADSP-21566BBCZ4
ADSP-21567BBCZ6
ADSP-21567BBCZ8
ADSP-21569BBCZ8
400 MHz
400 MHz
800 MHz
800 MHz
1000 MHz
1000 MHz
400 MHz
600 MHz
800 MHz
800 MHz
–40°C to +125°C
0°C to +110°C
120-Lead LQFP_EP, Exposed Pad SW-120-4
120-Lead LQFP_EP, Exposed Pad SW-120-4
120-Lead LQFP_EP, Exposed Pad SW-120-4
120-Lead LQFP_EP, Exposed Pad SW-120-4
120-Lead LQFP_EP, Exposed Pad SW-120-4
120-Lead LQFP_EP, Exposed Pad SW-120-4
0
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
0°C to +110°C
0
0
0
0
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
1
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
BC-400-3
BC-400-3
BC-400-3
BC-400-3
1
1
1
1 Z =RoHS compliant part.
2 Referenced temperature is junction temperature. See Operating Conditions for junction temperature (TJ) specification.
ORDERING GUIDE
Processor Instruction Temperature
External
Memory Port
Package
Option
Model1
Rate (Max)
800 MHz
800 MHz
400 MHz
600 MHz
800 MHz
800 MHz
1000 MHz
1000 MHz
Range2
Package Description
ADSP-21563KSWZ8
ADSP-21565KSWZ8
ADSP-21566KBCZ4
ADSP-21567KBCZ6
ADSP-21567KBCZ8
ADSP-21569KBCZ8
ADSP-21569BBCZ10
ADSP-21569KBCZ10
0°C to +110°C
0°C to +110°C
0°C to +110°C
0°C to +110°C
0°C to +110°C
0°C to +110°C
–40°C to +125°C
0°C to +110°C
0
0
1
1
1
1
1
1
120-Lead LQFP_EP, Exposed Pad
120-Lead LQFP_EP, Exposed Pad
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
SW-120-4
SW-120-4
BC-400-3
BC-400-3
BC-400-3
BC-400-3
BC-400-3
BC-400-3
1 Z =RoHS compliant part.
2 Referenced temperature is junction temperature. See Operating Conditions for junction temperature (TJ) specification.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2021 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D21778-2/21(B)
Rev. B
| Page 104 of 104 | February 2021
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