ADSP-21367KSZ-ENG_技术文档

SHARC^®Processor

ADSP-21367

processor algorithm combination support will vary

depending upon the chip version and the system configu-

rations. Please visit www.analog.com

Single-Instruction Multiple-Data (SIMD) computational

architecture

On-chip memory—2M bit of on-chip SRAM and a dedicated

6M bit of on-chip mask-programmable ROM

Code compatible with all other members of the SHARC family

The ADSP-21367 is available with a 400 MHz core instruction

rate with unique audio centric peripherals such as the Digi-

tal Audio Interface, S/PDIF transceiver, serial ports, 8-

channel asynchronous sample rate converter, precision

clock generators and more. For complete ordering infor-

mation, see Ordering Guide on page 47

a

Preliminary Technical Data

SUMMARY

High performance 32-bit/40-bit floating point processor

optimized for high performance automotive audio

processing

Audio decoder and post processor-algorithm support with

32-bit floating-point implementations

Non-volatile memory may be configured to support audio

decoders and post processor-algorithms like PCM, Dolby

Digital EX, Dolby Prologic IIx, Dolby Digital Plus, Dolby

headphone, DTS 96/24, Neo:6, DTS ES, DTS Lossless,

MPEG2 AAC, MPEG2 2channel, MP3, WMAPro, and Multi-

channel encoder. Functions like Bass management, Delay,

Speaker equalization, Graphic equalization, Decoder/post-

JTAG TEST & EMULATION

4 BLOCKS OF

CORE PROCESSOR

INSTRUCTION

ON-CHIP MEMORY

EXTERNAL PORT

24

CACHE

32 X 48-BIT

TIMER

2 M BIT RAM, 6 M BI T RO M

8

3

ADDRESS

11

SDRAM

CONTROLLER

ADDR

DATA

DAG2

8X4X32

ASYNCHRONOUS

ME MO RY

INTERFACE

DAG1

8X4X32

PROGRAM

SEQUENCER

CONTROL

32

DATA

32

PM ADDRESS BUS

DMADDRESS BUS

PM DATA BUS

32

64

DM DATA BUS

IOD(32)

IOA(24)

DMA

CONTROLLER

PROCESSING

EL EMENT

(P EX)

PX REGISTER

PROCESSING

ELEMENT

(PEY)

IOP REGIST ER (MEMORY MAPPED)

CONTROL, STATUS, & DATA BUFFERS

34 CHANNELS

ME MORY -T O-

ME MORY DMA (2 )

PWM (16)

PRECISION CLOCK

GENERATORS (4)

SERIAL PORTS (8)

SPI PORT (2)

4

UART (2)

GPIO FLAGS/

IRQ/TIMEXP

INPUT DATA PORT/

PDAP

TWO WIRE

INTERFACE

SRC (8 CHANNELS)

SPDIF (RX/TX)

TIMERS (3)

DAI PINS

DPI PINS

S

DIGITAL PERIP HE RAL INTE RFACE

DIGITAL AUDIO INTERFACE

I/O PROCESSOR

14

20

Figure 1. Functional Block Diagram – Processor Core

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel:781.329.4700

Fax:781.326.8703

www.analog.com

ADSP-21367

Preliminary Technical Data

Up to 16 TDM stream support, each with 128 channels per

frame

Companding selection on a per channel basis in TDM mode

Input data port, configurable as eight channels of serial data

or seven channels of serial data and a single channel of up

to a 20-bit wide parallel data

Signal routing unit provides configurable and flexible con-

nections between all DAI/DPI components

2 Muxed Flag/IRQ lines

1 Muxed Flag/Timer expired line /MS pin

1 Muxed Flag/IRQ /MS pin

KEY FEATURES – PROCESSOR CORE

At 400 MHz (2.5 ns) core instruction rate, the ADSP-21367

performs 2.4 GFLOPS/800 MMACS

2M bit on-chip SRAM (0.75M Bit in blocks 0 and 1, and 250K

Bit in blocks 2 and 3) for simultaneous access by the core

processor and DMA

6M bit on-chip mask-programmable ROM (3M bit in block 0

and 3M bit in block 1)

Dual Data Address Generators (DAGs) with modulo and bit-

reverse addressing

Zero-overhead looping with single-cycle loop setup, provid-

ing efficient program sequencing

Single Instruction Multiple Data (SIMD) architecture

provides:

Two computational processing elements

Concurrent execution

Code compatibility with other SHARC family members at

the assembly level

DEDICATED AUDIO COMPONENTS

S/PDIF Compatible Digital Audio receiver/transmitter sup-

ports EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards

Left-justified, I²S or right-justified serial data input with

16, 18, 20 or 24-bit word widths (transmitter)

Sample Rate Converter (SRC) contains a Serial Input Port, De-

emphasis Filter, Sample Rate Converter (SRC) and Serial

Output Port providing up to -128db SNR performance.

Supports Left Justified, I²S, TDM and Right Justified 24, 20,

18 and 16-bit serial formats (input)

Parallelism in busses and computational units allows: Sin-

gle cycle executions (with or without SIMD) of a multiply

operation, an ALU operation, a dual memory read or

write, and an instruction fetch

Transfers between memory and core at a sustained 6.0G

bytes/s bandwidth at 400 MHz core instruction rate

Pulse Width Modulation provides:

16 PWM outputs configured as four groups of four outputs

supports center-aligned or edge-aligned PWM waveforms

ROM Based Security features include:

INPUT/OUTPUT FEATURES

JTAG access to memory permitted with a 64-bit key

Protected memory regions that can be assigned to limit

access under program control to sensitive code

PLL has a wide variety of software and hardware multi-

plier/divider ratios

Dual voltage: 3.3 V I/O, 1.3 V core

Available in 256-ball BGA and 208-lead LQFP Packages (see

Ordering Guide on page 47)

DMA Controller supports:

34 zero-overhead DMA channels for transfers between

ADSP-21367 internal memory and a variety of

peripherals

32-bit DMA transfers at core clock speed, in parallel with

full-speed processor execution

32-Bit Wide External Port Provides Glueless Connection to

both Synchronous (SDRAM) and Asynchronous Memory

Devices

Programmable wait state options: 2 to 31 SCLK cycles

Delay-line DMA engine maintains circular buffers in exter-

nal memory with tap/offset based reads

SDRAM accesses at 166MHz and Asynchronous accesses at

66MHz

4 Memory Select lines allows multiple external memory

devices

Digital Audio Interface (DAI) includes eight serial ports, four

Precision Clock Generators, an Input Data Port, an S/PDIF

transceiver, an 8-channel asynchronous sample rate con-

verter, and a Signal Routing Unit

Digital Peripheral Interface (DPI) includes, three timers, two

UARTs, two SPI ports, and a two wire interface port

Outputs of PCG's C and D can be driven on to DPI pins

Eight dual data line serial ports that operate at up to 50M

bits/s on each data line — each has a clock, frame sync and

two data lines that can be configured as either a receiver or

transmitter pair

TDM support for telecommunications interfaces including

128 TDM channel support for newer telephony interfaces

such as H.100/H.110

Rev. PrA

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Preliminary Technical Data

ADSP-21367

TABLE OF CONTENTS

Summary ............................................................... 1

Key Features – Processor Core ................................. 2

Input/Output Features ........................................... 2

Dedicated Audio Components ................................. 2

General Description ................................................. 4

ADSP-21367 Family Core Architecture ...................... 4

SIMD Computational Engine ............................... 4

Independent, Parallel Computation Units ................ 4

Data Register File ............................................... 5

Single-Cycle Fetch of Instruction and Four Operands . 5

Instruction Cache .............................................. 5

Pin Function Descriptions ........................................ 12

Address Data Modes ............................................ 14

Boot Modes ....................................................... 14

Core Instruction Rate to CLKIN Ratio Modes ............ 14

ADSP-21367 Specifications ....................................... 15

Recommended Operating Conditions ...................... 15

Electrical Characteristics ....................................... 15

Absolute Maximum Ratings ................................... 16

ESD Sensitivity ................................................... 16

Timing Specifications ........................................... 16

Power-Up Sequencing ....................................... 18

Clock Input .................................................... 19

Clock Signals ................................................... 19

Reset ............................................................. 20

Interrupts ....................................................... 20

Core Timer ..................................................... 21

Timer PWM_OUT Cycle Timing ......................... 21

Timer WDTH_CAP Timing ............................... 22

DAI and DPI Pin to Pin Direct Routing ................. 22

Precision Clock Generator (Direct Pin Routing) ...... 23

Flags ............................................................. 24

SDRAM Interface Timing .................................. 25

External Port Bus Request and Grant Cycle Timing .. 26

Serial Ports ..................................................... 27

Input Data Port ............................................... 30

Parallel Data Acquisition Port (PDAP) .................. 31

Sample Rate Converter—Serial Input Port .............. 32

Sample Rate Converter—Serial Output Port ........... 33

SPDIF Transmitter ........................................... 34

SPDIF Receiver ................................................ 36

SPI Interface—Master ....................................... 38

SPI Interface—Slave .......................................... 39

Data Address Generators With Zero-Overhead Hardware

Circular Buffer Support .................................... 5

Flexible Instruction Set ....................................... 6

ADSP-21367 Memory ............................................ 6

On-Chip Memory .............................................. 6

External Memory .................................................. 6

SDRAM Controller ............................................ 7

Asynchronous Controller .................................... 7

ADSP-21367 Input/Output Features .......................... 7

DMA Controller ................................................ 7

Digital Audio Interface (DAI) ............................... 7

Serial Ports ....................................................... 8

S/PDIF Compatible Digital Audio Receiver/Transmitter

and Synchronous/Asynchronous Sample

Rate Converter ............................................... 8

Digital Peripheral Interface (DPI) .......................... 8

Serial Peripheral (Compatible) Interface .................. 8

UART Port ...................................................... 8

Timers ............................................................ 9

Two Wire Interface Port (TWI) ............................. 9

Pulse Width Modulation ..................................... 9

ROM Based Security ........................................... 9

System Design ...................................................... 9

Program Booting .............................................. 10

Power Supplies ................................................. 10

Target Board JTAG Emulator Connector ................ 10

Development Tools .............................................. 10

Universal Asynchronous Receiver-Transmitter

(UART) Port—Receive and Transmit Timing ...... 40

JTAG Test Access Port and Emulation .................. 41

Output Drive Currents ......................................... 42

Test Conditions .................................................. 42

Capacitive Loading .............................................. 42

Thermal Characteristics ........................................ 43

Ordering Guide ..................................................... 45

Designing an Emulator-Compatible DSP

Board (Target) .............................................. 11

Evaluation Kit .................................................. 11

Additional Information ......................................... 11

Rev. PrA

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ADSP-21367

Preliminary Technical Data

GENERAL DESCRIPTION

The ADSP-21367 SHARC processor is a members of the SIMD

SHARC family of DSPs that feature Analog Devices' Super Har-

vard Architecture. The ADSP-21367 is source code compatible

with the ADSP-2126x, and ADSP-2116x, DSPs as well as with

first generation ADSP-2106x SHARC processors in SISD (Sin-

gle-Instruction, Single-Data) mode. The ADSP-21367 is a 32-

bit/40-bit floating point processors optimized for high perfor-

mance automotive audio applications with its large on-chip

SRAM and mask-programmable ROM, multiple internal buses

to eliminate I/O bottlenecks, and an innovative Digital Audio

Interface (DAI).

• On-Chip mask-programmable ROM (6M bit)

• JTAG test access port

The block diagram of the ADSP-21367 on page 1 also illustrates

the following architectural features:

• DMA controller

• Eight full duplex serial ports

• Two SPI-compatible interface ports

• Digital Audio Interface that includes four precision clock

generators (PCG), an input data port (IDP), an S/PDIF

receiver/transmitter, eight channels asynchronous sample

rate converters, eight serial ports, eight serial interfaces, a

20-bit parallel input port, a flexible signal routing unit

(SRU), and a Digital Peripheral Interface (DPI)

As shown in the functional block diagram on page 1, the

ADSP-21367 uses two computational units to deliver a signifi-

cant performance increase over the previous SHARC processors

on a range of DSP algorithms. Fabricated in a state-of-the-art,

high speed, CMOS process, the ADSP-21367 processor achieves

an instruction cycle time of 2.5 ns at 400 MHz. With its SIMD

computational hardware, the ADSP-21367 can perform 2.4

GFLOPS running at 400 MHz.

ADSP-21367 FAMILY CORE ARCHITECTURE

The ADSP-21367 is code compatible at the assembly level with

the ADSP-2126x, ADSP-21160 and ADSP-21161, and with the

first generation ADSP-2106x SHARC processors. The ADSP-

21367 shares architectural features with the ADSP-2126x and

ADSP-2116x SIMD SHARC processors, as detailed in the fol-

lowing sections.

Table 1 shows performance benchmarks for the ADSP-21367.

Table 1. ADSP-21367 Benchmarks (at 400 MHz)

Benchmark Algorithm

Speed

(at 400 MHz)

SIMD Computational Engine

The ADSP-21367 contains two computational processing ele-

ments that operate as a Single-Instruction Multiple-Data

(SIMD) engine. The processing elements are referred to as PEX

and PEY and each contains an ALU, multiplier, shifter and reg-

ister file. PEX is always active, and PEY may be enabled by

setting the PEYEN mode bit in the MODE1 register. When this

mode is enabled, the same instruction is executed in both pro-

cessing elements, but each processing element operates on

different data. This architecture is efficient at executing math

intensive DSP algorithms.

1024 Point Complex FFT (Radix 4, with reversal) 23.25 µs

FIR Filter (per tap)¹

1.25 ns

5.0 ns

IIR Filter (per biquad)¹

Matrix Multiply (pipelined)

[3x3] × [3x1]

[4x4] × [4x1]

11.25 ns

20.0 ns

Divide (y/×)

8.75 ns

13.5 ns

Inverse Square Root

¹Assumes two files in multichannel SIMD mode

Entering SIMD mode also has an effect on the way data is trans-

ferred between memory and the processing elements. When in

SIMD mode, twice the data bandwidth is required to sustain

computational operation in the processing elements. Because of

this requirement, entering SIMD mode also doubles the band-

width between memory and the processing elements. When

using the DAGs to transfer data in SIMD mode, two data values

are transferred with each access of memory or the register file.

The ADSP-21367 continues SHARC’s industry leading stan-

dards of integration for DSPs, combining a high performance

32-bit DSP core with integrated, on-chip system features.

The block diagram of the ADSP-21367 on page 1, illustrates the

following architectural features:

• Two processing elements, each of which comprises an

ALU, Multiplier, Shifter and Data Register File

Independent, Parallel Computation Units

• Data Address Generators (DAG1, DAG2)

• Program sequencer with instruction cache

Within each processing element is a set of computational units.

The computational units consist of an arithmetic/logic unit

(ALU), multiplier, and shifter. These units perform all opera-

tions in a single cycle. The three units within each processing

element are arranged in parallel, maximizing computational

throughput. Single multifunction instructions execute parallel

ALU and multiplier operations. In SIMD mode, the parallel

ALU and multiplier operations occur in both processing ele-

• PM and DM buses capable of supporting four 32-bit data

transfers between memory and the core at every core pro-

cessor cycle

• Three Programmable Interval Timers with PWM Genera-

tion, PWM Capture/Pulse width Measurement, and

External Event Counter Capabilities

• On-Chip SRAM (2M bit)

Rev. PrA

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Preliminary Technical Data

ADSP-21367

ments. These computation units support IEEE 32-bit single-

precision floating-point, 40-bit extended precision floating-

point, and 32-bit fixed-point data formats.

sufficient registers to allow the creation of up to 32 circular buff-

ers (16 primary register sets, 16 secondary). The DAGs

automatically handle address pointer wraparound, reduce over-

head, increase performance, and simplify implementation.

Circular buffers can start and end at any memory location.

Data Register File

A general-purpose data register file is contained in each pro-

cessing element. The register files transfer data between the

computation units and the data buses, and store intermediate

results. These 10-port, 32-register (16 primary, 16 secondary)

register files, combined with the ADSP-2136x enhanced Har-

vard architecture, allow unconstrained data flow between

computation units and internal memory. The registers in PEX

are referred to as R0-R15 and in PEY as S0-S15.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel

operations, for concise programming. For example, the

ADSP-21367 can conditionally execute a multiply, an add, and a

subtract in both processing elements while branching and fetch-

ing up to four 32-bit values from memory—all in a single

instruction.

Single-Cycle Fetch of Instruction and Four Operands

ADSP-21367 MEMORY

The ADSP-21367 features an enhanced Harvard architecture in

which the data memory (DM) bus transfers data and the pro-

gram memory (PM) bus transfers both instructions and data

(see Figure 1 on page 1). With the ADSP-21367’s separate pro-

gram and data memory buses and on-chip instruction cache,

the processor can simultaneously fetch four operands (two over

each data bus) and one instruction (from the cache), all in a sin-

gle cycle.

The ADSP-21367 adds the following architectural features to

the SIMD SHARC family core.

On-Chip Memory

The ADSP-21367 contains two megabits of internal RAM and

six megabits of internal mask-programmable ROM. Each block

can be configured for different combinations of code and data

storage (see Table 2). Each memory block supports single-cycle,

independent accesses by the core processor and I/O processor.

The ADSP-21367 memory architecture, in combination with its

separate on-chip buses, allow two data transfers from the core

and one from the I/O processor, in a single cycle.

Instruction Cache

The ADSP-21367 includes an on-chip instruction cache that

enables three-bus operation for fetching an instruction and four

data values. The cache is selective—only the instructions whose

fetches conflict with PM bus data accesses are cached. This

cache allows full-speed execution of core, looped operations

such as digital filter multiply-accumulates, and FFT butterfly

processing.

The ADSP-21367’s, SRAM can be configured as a maximum of

64K words of 32-bit data, 128K words of 16-bit data, 42K words

of 48-bit instructions (or 40-bit data), or combinations of differ-

ent word sizes up to three megabits. All of the memory can be

accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float-

ing-point storage format is supported that effectively doubles

the amount of data that may be stored on-chip. Conversion

between the 32-bit floating-point and 16-bit floating-point for-

mats is performed in a single instruction. While each memory

block can store combinations of code and data, accesses are

most efficient when one block stores data using the DM bus for

transfers, and the other block stores instructions and data using

the PM bus for transfers.

Data Address Generators With Zero-Overhead Hardware

Circular Buffer Support

The ADSP-21367’s two data address generators (DAGs) are

used for indirect addressing and implementing circular data

buffers in hardware. Circular buffers allow efficient program-

ming of delay lines and other data structures required in digital

signal processing, and are commonly used in digital filters and

Fourier transforms. The two DAGs of the ADSP-21367 contain

Table 2. ADSP-21367 Internal Memory Space

IOP Registers 0x0000 0000 - 0003 FFFF

Long Word (64 bits)

ExtendedPrecisionNormalor Normal Word (32 bits)

Short Word (16 bits)

Instruction Word (48 bits)

BLOCK 0 ROM

0x0004 0000–0x0004 BFFF

0x0008 0000–0x0008 FFFF

0x0008 0000–0x0009 7FFF

0x0010 0000–0x0012 FFFF

Reserved

0x0004 F000–0x0004 FFFF

0x0009 4000–0x0009 FFFF

0x0009 E0000–0x0009 FFFF

0x0013 C000–0x0013 FFFF

BLOCK 0 RAM

0x0004 C000–0x0004 EFFF

0x0009 0000–0x0009 3FFF

0x0009 8000–0x0009 DFFF

0x0013 0000–0x0013 BFFF

BLOCK 1 ROM

0x0005 0000–0x0005 BFFF

0x000A 0000–0x000A FFFF

0x000A 0000– 0x000B 7FFF

0x0014 0000–0x0016 FFFF

Rev. PrA

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ADSP-21367

Preliminary Technical Data

Table 2. ADSP-21367 Internal Memory Space (Continued)

IOP Registers 0x0000 0000 - 0003 FFFF

Long Word (64 bits)

ExtendedPrecisionNormalor Normal Word (32 bits)

Short Word (16 bits)

Instruction Word (48 bits)

Reserved

0x0005 F000–0x0005 FFFF

0x000B 4000–0x000B FFFF

0x000B E000– 0x000B FFFF

0x0017 C000–0x0017 FFFF

BLOCK 1 RAM

0x0005 C000–0x0005 EFFF

0x000B 0000–0x000B 3FFF

0x000B 8000–0x000B DFFF

0x0017 0000–0x0017 BFFF

BLOCK 2 RAM

0x0006 0000–0x0006 0FFF

0x000C 0000–0x000C 1554

0x000C 0000–0x000C 1FFF

0x0018 0000–0x0018 3FFF

Reserved

0x0006 1000– 0x0006 FFFF

0x000C 1555–0x000C 3FFF

0x000C 2000–0x000D FFFF

0x0018 4000–0x001B FFFF

BLOCK 3 RAM

0x0007 0000–0x0007 0FFF

0x000E 0000–0x000E 1554

0x000E 0000–0x000E 1FFF

0x001C 0000–0x001C 3FFF

Reserved

0x0007 1000– 0x0007 FFFF

0x000E 1555–0x000F FFFF

0x000E 2000–0x000F FFFF

0x001C 4000–0x001F FFFF

Using the DM bus and PM buses, with one bus dedicated to

each memory block, assures single-cycle execution with two

data transfers. In this case, the instruction must be available in

the cache.

The SDRAM controller address, data, clock, and command pins

can drive loads up to 30 pF. For larger memory systems, the

SDRAM controller external buffer timing should be selected

and external buffering should be provided so that the load on

the SDRAM controller pins does not exceed 30 pF.

EXTERNAL MEMORY

Asynchronous Controller

The External Port on the ADSP-21367 SHARC provides a high

performance, glueless interface to a wide variety of industry-

standard memory devices. The 32-bit wide bus may be used to

interface to synchronous and/or asynchronous memory devices

through the use of it's separate internal memory controllers: the

first is an SDRAM controller for connection of industry-stan-

dard synchronous DRAM devices and DIMMs (Dual Inline

Memory Module), while the second is an asynchronous mem-

ory controller intended to interface to a variety of memory

devices. Four memory select pins enable up to four separate

devices to coexist, supporting any desired combination of syn-

chronous and asynchronous device types.

The asynchronous memory controller provides a configurable

interface for up to four separate banks of memory or I/O

devices. Each bank can be independently programmed with dif-

ferent timing parameters, enabling connection to a wide variety

of memory devices including SRAM, ROM, and flash EPROM,

as well as I/O devices that interface with standard memory con-

trol lines. Bank0 occupies a 14.7M word window and banks 1, 2,

and 3 occupy a 16M word window in the processor’s address

space but, if not fully populated, these windows are not made

contiguous by the memory controller logic. The banks can also

be configured as 8-bit, 16-bit, or 32-bit wide buses for ease of

interfacing to a range of memories and I/O devices tailored

either to high performance or to low cost and power.

SDRAM Controller

The SDRAM controller provides an interface to up to four sepa-

rate banks of industry-standard SDRAM devices or DIMMs, at

speeds up to f_SCLK. Fully compliant with the SDRAM standard,

each bank can has it's own memory select line (MS0–MS3), and

can be configured to contain between 16M bytes and

128M bytes of memory.

The asynchronous memory controller is capable of a maximum

throughput of 267M bytes/sec using a 66MHz external bus

speed. Other features include 8 to 32-bit and 16 to 32-bit pack-

ing and unpacking, booting from Bank Select 1, and support for

delay line DMA.

ADSP-21367 INPUT/OUTPUT FEATURES

The controller maintains all of the banks as a contiguous

address space so that the processor sees this as a single address

space, even if different size devices are used in the different

banks.

The ADSP-21367 I/O processor provides 34 channels of DMA,

as well as an extensive set of peripherals. These include a 20 pin

Digital Audio Interface which controls:

A set of programmable timing parameters is available to config-

ure the SDRAM banks to support slower memory devices. The

memory banks can be configured as either 32 bits wide for max-

imum performance and bandwidth or 16 bits wide for

minimum device count and lower system cost.

• Eight Serial ports

• S/PDIF Receiver/Transmitter

• Four Precision Clock generators

Rev. PrA

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Preliminary Technical Data

ADSP-21367

• Four Sample Rate Converters

For complete information on using the DAI, see the ADSP-

2136x SHARC Processor Hardware Reference.

• Internal Data port/Parallel Data Acquisition port

Serial Ports

The ADSP-21367 processor also contains a 14 pin Digital

Peripheral Interface which controls:

The ADSP-21367 features eight synchronous serial ports that

provide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices such as Analog devices AD183x

family of audio codecs, ADCs, and DACs. The serial ports are

made up of two data lines, a clock and frame sync. The data

lines can be programmed to either transmit or receive and each

data line has a dedicated DMA channel.

• Three general-purpose timers

• Two Serial Peripheral Interfaces

• Two Universal Asynchronous Receiver/Transmitters

(UARTs)

• A Two Wire Interface/I²C

Serial ports are enabled via 16 programmable and simultaneous

receive or transmit pins that support up to 32 transmit or 32

receive channels of audio data when all eight SPORTS are

enabled, or eight full duplex TDM streams of 128 channels per

frame.

DMA Controller

The ADSP-21367’s on-chip DMA controller allows data trans-

fers without processor intervention. The DMA controller

operates independently and invisibly to the processor core,

allowing DMA operations to occur while the core is simulta-

neously executing its program instructions. DMA transfers can

occur between the ADSP-21367’s internal memory and its serial

ports, the SPI-compatible (Serial Peripheral Interface) ports, the

IDP (Input Data Port), the Parallel Data Acquisition Port

(PDAP) or the UART. Thirty-four channels of DMA are avail-

able on the ADSP-21367—sixteen via the serial ports, eight via

the Input Data Port, four for the UARTs, two for the SPI inter-

face, two for the external port, and two for memory-to-memory

transfers. Programs can be downloaded to the ADSP-21367

using DMA transfers. Other DMA features include interrupt

generation upon completion of DMA transfers, and DMA

chaining for automatic linked DMA transfers.

The serial ports operate at a maximum data rate of 50M bits/s.

Serial port data can be automatically transferred to and from

on-chip memory via dedicated DMA channels. Each of the

serial ports can work in conjunction with another serial port to

provide TDM support. One SPORT provides two transmit sig-

nals while the other SPORT provides the two receive signals.

The frame sync and clock are shared.

Serial ports operate in five modes:

• Standard DSP serial mode

• Multichannel (TDM) mode with support for Packed I²S

mode

• I²S mode

• Packed I²S mode

Delay Line DMA

The ADSP-21367 processor provides Delay Line DMA func-

tionality. This allows processor reads and writes to external

Delay Line Buffers (and hence to external memory) with limited

core interaction.

• Left-justified sample pair mode

Left-justified sample pair mode is a mode where in each frame

sync cycle two samples of data are transmitted/received—one

sample on the high segment of the frame sync, the other on the

low segment of the frame sync. Programs have control over var-

ious attributes of this mode.

Digital Audio Interface (DAI)

The Digital Audio Interface (DAI) provides the ability to con-

nect various peripherals to any of the DSPs DAI pins

(DAI_P20–1).

Each of the serial ports supports the left-justified sample pair

and I²S protocols (I²S is an industry standard interface com-

monly used by audio codecs, ADCs and DACs such as the

Analog Devices AD183x family), with two data pins, allowing

four left-justified sample pair or I²S channels (using two stereo

devices) per serial port, with a maximum of up to 32 I²S chan-

nels. The serial ports permit little-endian or big-endian

transmission formats and word lengths selectable from 3 bits to

32 bits. For the left-justified sample pair and I²S modes, data-

word lengths are selectable between 8 bits and 32 bits. Serial

ports offer selectable synchronization and transmit modes as

well as optional µ-law or A-law companding selection on a per

channel basis. Serial port clocks and frame syncs can be inter-

nally or externally generated.

Programs make these connections using the Signal Routing

Unit (SRU, shown in Figure 1.

The SRU is a matrix routing unit (or group of multiplexers) that

enables the peripherals provided by the DAI to be intercon-

nected under software control. This allows easy use of the DAI

associated peripherals for a much wider variety of applications

by using a larger set of algorithms than is possible with non con-

figurable signal paths.

The DAI also includes eight serial ports, an S/PDIF

receiver/transmitter, four precision clock generators (PCG),

eight channels of synchronous sample rate converters, and an

input data port (IDP). The IDP provides an additional input

path to the ADSP-21367 core, configurable as either eight chan-

nels of I²S serial data or as seven channels plus a single 20-bit

wide synchronous parallel data acquisition port. Each data

channel has its own DMA channel that is independent from the

ADSP-21367's serial ports.

The serial ports also contain frame sync error detection logic

where the serial ports detect frame syncs that arrive early (for

example frame syncs that arrive while the transmission/recep-

tion of the previous word is occurring). All the serial ports also

share one dedicated error interrupt.

Rev. PrA

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Page 7 of 48

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November 2004

ADSP-21367

Preliminary Technical Data

interface standard. The UART port also includes support for 5

to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. The

UART port supports two modes of operation:

S/PDIF Compatible Digital Audio Receiver/Transmitter

and Synchronous/Asynchronous Sample Rate Converter

The S/PDIF transmitter has no separate DMA channels. It

receives audio data in serial format and converts it into a

biphase encoded signal. The serial data input to the transmitter

can be formatted as left justified, I²S or right justified with word

widths of 16, 18, 20, or 24 bits.

• PIO (Programmed I/O) – The processor sends or receives

data by writing or reading I/O-mapped UART registers.

The data is double-buffered on both transmit and receive.

• DMA (Direct Memory Access) – The DMA controller

transfers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. The UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

The serial data, clock, and frame sync inputs to the S/PDIF

transmitter are routed through the Signal Routing Unit (SRU).

They can come from a variety of sources such as the SPORTs,

external pins, the precision clock generators (PCGs), or the

sample rate converters (SRC) and are controlled by the SRU

control registers.

The UART port's baud rate, serial data format, error code gen-

eration and status, and interrupts are programmable:

The sample rate converter (SRC) contains four SRC blocks and

is the same core as that used in the AD1896 192 kHz Stereo

Asynchronous Sample Rate Converter and provides up to

128dB SNR. The SRC block is used to perform synchronous or

asynchronous sample rate conversion across independent stereo

channels, without using internal processor resources. The four

SRC blocks can also be configured to operate together to con-

vert multichannel audio data without phase mismatches.

Finally, the SRC is used to clean up audio data from jittery clock

sources such as the S/PDIF receiver.

• Supporting bit rates ranging from (f_SCLK/ 1,048,576) to

(f_SCLK/16) bits per second.

• Supporting data formats from 7 to12 bits per frame.

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

The UART port’s clock rate is calculated as:

f_SCLK

UART Clock Rate = ------------------------------------------------

16 × UART_Divisor

Digital Peripheral Interface (DPI)

The Digital Peripheral Interface provides connections to two

serial peripheral interface ports, two universal asynchronous

receiver-transmitters (UARTs), a Two Wire Interface (TWI), 12

Flags, and three general-purpose timers.

Where the 16-bit UART_Divisor comes from the DLH register

(most significant 8 bits) and DLL register (least significant

8 bits).

In conjunction with the general-purpose timer functions, auto-

baud detection is supported.

Serial Peripheral (Compatible) Interface

The ADSP-21367 SHARC processor contains two Serial Periph-

eral Interface ports (SPIs). The SPI is an industry standard

synchronous serial link, enabling the ADSP-21367 SPI compati-

ble port to communicate with other SPI compatible devices. The

SPI consists of two data pins, one device select pin, and one

clock pin. It is a full-duplex synchronous serial interface, sup-

porting both master and slave modes. The SPI port can operate

in a multimaster environment by interfacing with up to four

other SPI compatible devices, either acting as a master or slave

device. The ADSP-21367 SPI compatible peripheral implemen-

tation also features programmable baud rate and clock phase

and polarities. The ADSP-21367 SPI compatible port uses open

drain drivers to support a multimaster configuration and to

avoid data contention.

Timers

The ADSP-21367 has a total of four timers: a core timer that can

generate periodic software interrupts and three general purpose

timers that can generate periodic interrupts and be indepen-

dently set to operate in one of three modes:

• Pulse Waveform Generation mode

• Pulse Width Count /Capture mode

• External Event Watchdog mode

The core timer can be configured to use FLAG3 as a Timer

Expired signal, and each general purpose timer has one bidirec-

tional pin and four registers that implement its mode of

operation: a 6-bit configuration register, a 32-bit count register,

a 32-bit period register, and a 32-bit pulse width register. A sin-

gle control and status register enables or disables all three

general purpose timers independently.

UART Port

The ADSP-21367 processor provides a full-duplex Universal

Asynchronous Receiver/Transmitter (UART) port, which is

fully compatible with PC-standard UARTs. The UART port

provides a simplified UART interface to other peripherals or

hosts, supporting full-duplex, DMA-supported, asynchronous

transfers of serial data. The UART also has multiprocessor com-

munication capability using 9-bit address detection. This allows

it to be used in multidrop networks through the RS-485 data

Rev. PrA

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November 2004

Preliminary Technical Data

ADSP-21367

Two Wire Interface Port (TWI)

SYSTEM DESIGN

The TWI is a bi-directional 2-wire, serial bus used to move 8-bit

data while maintaining compliance with the I2C bus protocol.

The TWI Master incorporates the following features:

The following sections provide an introduction to system design

options and power supply issues.

Program Booting

• Simultaneous Master and Slave operation on multiple

device systems with support for multi master data

arbitration

The internal memory of the ADSP-21367 boots at system

power-up from an 8-bit EPROM via the external port, an SPI

master, an SPI slave or an internal boot. Booting is determined

by the Boot Configuration (BOOTCFG1–0) pins (see Table 4 on

page 14). Selection of the boot source is controlled via the SPI as

either a master or slave device, or it can immediately begin exe-

cuting from ROM.

• Digital filtering and timed event processing

• 7 and 10 bit addressing

• 100K bits/s and 400K bits/s data rates

• Low interrupt rate

Power Supplies

Pulse Width Modulation

The ADSP-21367 has separate power supply connections for the

The PWM module is a flexible, programmable, PWM waveform

generator that can be programmed to generate the required

switching patterns for various applications related to motor and

engine control or audio power control. The PWM generator can

generate either center-aligned or edge-aligned PWM wave-

forms. In addition, it can generate complementary signals on

two outputs in paired mode or independent signals in non

paired mode (applicable to a single group of four PWM

waveforms).

internal (V_DDINT), external (V_DDEXT), and analog (A_VDD/A_VSS

)

power supplies. The internal and analog supplies must meet the

1.3V requirement. The external supply must meet the 3.3V

requirement. All external supply pins must be connected to the

same power supply.

Note that the analog supply (A_VDD) powers the ADSP-21367’s

clock generator PLL. To produce a stable clock, programs

should provide an external circuit to filter the power input to

the A_VDDpin. Place the filter as close as possible to the pin. For

an example circuit, see Figure 2. To prevent noise coupling, use

a wide trace for the analog ground (A_VSS) signal and install a

decoupling capacitor as close as possible to the pin. Note that

the A_VSSand A_VDDpins specified in Figure 2 are inputs to the

processor and not the analog ground plane on the board. For

more information, see Electrical Characteristics on page 15.

The entire PWM module has four groups of four PWM outputs

each. Therefore, this module generates 16 PWM outputs in

total. Each PWM group produces two pairs of PWM signals on

the four PWM outputs.

The PWM generator is capable of operating in two distinct

modes while generating center-aligned PWM waveforms: single

update mode or double update mode. In single update mode the

duty cycle values are programmable only once per PWM period.

This results in PWM patterns that are symmetrical about the

mid-point of the PWM period. In double update mode, a sec-

ond updating of the PWM registers is implemented at the mid-

point of the PWM period. In this mode, it is possible to produce

asymmetrical PWM patterns that produce lower harmonic dis-

tortion in three-phase PWM inverters.

10⍀

V_DDINT

A_VDD

0.1␮F

0.01␮F

A_VSS

Figure 2. Analog Power (A_VDD) Filter Circuit

ROM Based Security

The ADSP-21367 has a ROM security feature that provides

hardware support for securing user software code by preventing

unauthorized reading from the internal code when enabled.

When using this feature, the processor does not boot-load any

external code, executing exclusively from internal SRAM/ROM.

Additionally, the processor is not freely accessible via the JTAG

port. Instead, a unique 64-bit key, which must be scanned in

through the JTAG or Test Access Port will be assigned to each

customer. The device will ignore a wrong key. Emulation fea-

tures and external boot modes are only available after the

correct key is scanned.

Target Board JTAG Emulator Connector

Analog Devices DSP Tools product line of JTAG emulators uses

the IEEE 1149.1 JTAG test access port of the ADSP-21367 pro-

cessor to monitor and control the target board processor during

emulation. Analog Devices DSP Tools product line of JTAG

emulators provides emulation at full processor speed, allowing

inspection and modification of memory, registers, and proces-

sor stacks. The processor's JTAG interface ensures that the

emulator will not affect target system loading or timing.

For complete information on Analog Devices’ SHARC DSP

Tools product line of JTAG emulator operation, see the appro-

priate “Emulator Hardware User's Guide”.

Rev. PrA

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Page 9 of 48

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November 2004

ADSP-21367

Preliminary Technical Data

The VisualDSP++ IDDE lets programmers define and manage

DSP software development. Its dialog boxes and property pages

let programmers configure and manage all of the SHARC devel-

opment tools, including the color syntax highlighting in the

VisualDSP++ editor. This capability permits programmers to:

DEVELOPMENT TOOLS

The ADSP-21367 is supported with a complete set of

CROSSCORE® software and hardware development tools,

including Analog Devices emulators and VisualDSP++® devel-

opment environment. The same emulator hardware that

supports other SHARC processors also fully emulates the

ADSP-21367.

• Control how the development tools process inputs and

generate outputs

• Maintain a one-to-one correspondence with the tool’s

command line switches

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy to use assembler (which is based on an alge-

braic syntax), an archiver (librarian/library builder), a linker, a

loader, a cycle-accurate instruction-level simulator, a C/C++

compiler, and a C/C++ runtime library that includes DSP and

mathematical functions. A key point for these tools is C/C++

code efficiency. The compiler has been developed for efficient

translation of C/C++ code to DSP assembly. The SHARC has

architectural features that improve the efficiency of compiled

C/C++ code.

The VisualDSP++ Kernel (VDK) incorporates scheduling and

resource management tailored specifically to address the mem-

ory and timing constraints of DSP programming. These

capabilities enable engineers to develop code more effectively,

eliminating the need to start from the very beginning, when

developing new application code. The VDK features include

Threads, Critical and Unscheduled regions, Semaphores,

Events, and Device flags. The VDK also supports Priority-based,

Preemptive, Cooperative, and Time-Sliced scheduling

approaches. In addition, the VDK was designed to be scalable. If

the application does not use a specific feature, the support code

for that feature is excluded from the target system.

The VisualDSP++ debugger has a number of important fea-

tures. Data visualization is enhanced by a plotting package that

offers a significant level of flexibility. This graphical representa-

tion of user data enables the programmer to quickly determine

the performance of an algorithm. As algorithms grow in com-

plexity, this capability can have increasing significance on the

designer’s development schedule, increasing productivity. Sta-

tistical profiling enables the programmer to non intrusively poll

the processor as it is running the program. This feature, unique

to VisualDSP++, enables the software developer to passively

gather important code execution metrics without interrupting

the real-time characteristics of the program. Essentially, the

developer can identify bottlenecks in software quickly and effi-

ciently. By using the profiler, the programmer can focus on

those areas in the program that impact performance and take

corrective action.

Because the VDK is a library, a developer can decide whether to

use it or not. The VDK is integrated into the VisualDSP++

development environment, but can also be used via standard

command line tools. When the VDK is used, the development

environment assists the developer with many error-prone tasks

and assists in managing system resources, automating the gen-

eration of various VDK based objects, and visualizing the

system state, when debugging an application that uses the VDK.

VisualDSP++ Component Software Engineering (VCSE) is

Analog Devices’ technology for creating, using, and reusing

software components (independent modules of substantial

functionality) to quickly and reliably assemble software applica-

tions. Download components from the Web and drop them into

the application. Publish component archives from within

VisualDSP++. VCSE supports component implementation in

C/C++ or assembly language.

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source

and object information)

Use the Expert Linker to visually manipulate the placement of

code and data on the embedded system. View memory utiliza-

tion in a color-coded graphical form, easily move code and data

to different areas of the processor or external memory with the

drag of the mouse, examine run time stack and heap usage. The

Expert Linker is fully compatible with the existing Linker Defi-

nition File (LDF), allowing the developer to move between the

graphical and textual environments.

• Insert breakpoints

• Set conditional breakpoints on registers, memory,

and stacks

• Trace instruction execution

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

In addition to the software and hardware development tools

available from Analog Devices, third parties provide a wide

range of tools supporting the SHARC processor family. Hard-

ware tools include SHARC processor PC plug-in cards. Third

party software tools include DSP libraries, real-time operating

systems, and block diagram design tools.

• Create custom debugger windows

Rev. PrA

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Page 10 of 48 | November 2004

Preliminary Technical Data

ADSP-21367

The USB controller on the EZ-KIT Lite board connects the

board to the USB port of the user’s PC, enabling the

Designing an Emulator-Compatible DSP Board (Target)

The Analog Devices family of emulators are tools that every

DSP developer needs to test and debug hardware and software

systems. Analog Devices has supplied an IEEE 1149.1 JTAG

Test Access Port (TAP) on each JTAG DSP. Nonintrusive in-

circuit emulation is assured by the use of the processor’s JTAG

interface—the emulator does not affect target system loading or

timing. The emulator uses the TAP to access the internal fea-

tures of the processor, allowing the developer to load code, set

breakpoints, observe variables, observe memory, and examine

registers. The processor must be halted to send data and com-

mands, but once an operation has been completed by the

emulator, the DSP system is set running at full speed with no

impact on system timing.

VisualDSP++ evaluation suite to emulate the on-board proces-

sor in-circuit. This permits the customer to download, execute,

and debug programs for the EZ-KIT Lite system. It also allows

in-circuit programming of the on-board Flash device to store

user-specific boot code, enabling the board to run as a standal-

one unit without being connected to the PC.

With a full version of VisualDSP++ installed (sold separately),

engineers can develop software for the EZ-KIT Lite or any cus-

tom defined system. Connecting one of Analog Devices JTAG

emulators to the EZ-KIT Lite board enables high-speed, non-

intrusive emulation.

ADDITIONAL INFORMATION

To use these emulators, the target board must include a header

that connects the DSP’s JTAG port to the emulator.

This data sheet provides a general overview of the ADSP-21367

architecture and functionality. For detailed information on the

ADSP-2136x Family core architecture and instruction set, refer

to the ADSP-2136x SHARC Processor Hardware Reference and

the ADSP-2136x SHARC Processor Programming Reference.

For details on target board design issues including mechanical

layout, single processor connections, signal buffering, signal ter-

mination, and emulator pod logic, see the EE-68: Analog Devices

JTAG Emulation Technical Reference on the Analog Devices

website (www.analog.com)—use site search on “EE-68.” This

document is updated regularly to keep pace with improvements

to emulator support.

Evaluation Kit

Analog Devices offers a range of EZ-KIT Lite evaluation plat-

forms to use as a cost effective method to learn more about

developing or prototyping applications with Analog Devices

processors, platforms, and software tools. Each EZ-KIT Lite

includes an evaluation board along with an evaluation suite of

the VisualDSP++ development and debugging environment

with the C/C++ compiler, assembler, and linker. Also included

are sample application programs, power supply, and a USB

cable. All evaluation versions of the software tools are limited

for use only with the EZ-KIT Lite product.

Rev. PrA

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Page 11 of 48 | November 2004

ADSP-21367

Preliminary Technical Data

PIN FUNCTION DESCRIPTIONS

The following symbols appear in the Type column of TBD:

A = Asynchronous, G = Ground, I = Input, O = Output,

P = Power Supply, S = Synchronous, (A/D) = Active Drive,

(O/D) = Open Drain, and T = Three-State, (pd) = pull-down

resistor, (pu) = pull-up resistor.

Table 3. Pin List

Name

Type

State During

and After

Reset

Description

ADDR_23–0

DATA_31–0

DAI _P_20–1

I/Owithprogrammable

PUP¹

Three-state

External Address Bus.

External Data Bus.

I/Owithprogrammable

PUP

I/O with programma-

ble²PUP

Digital Audio Interface Pins. These pins provide the physical interface to the SRU.

The SRU configuration registers define the combination of on-chip peripheral inputs

or outputs connected to the pin and to the pin’s output enable. The configuration

registers of these peripherals then determines the exact behavior of the pin. Any

input or output signal present in the SRU may be routed to any of these pins. The SRU

provides the connection from the Serial ports, Input data port, precision clock gen-

erators and timers, sample rate converters and SPI to the DAI_P20–1 pins These pins

have internal 22.5 kΩpull-up resistors which are enabled on reset. These pull-ups can

be disabled in the DAI_PIN_PULLUP register.

DPI _P_14–1

ACK

I/O with programma-

ble³PUP

Three-state

Digital Peripheral Interface.

Input with programma-

ble PUP¹

Memory Acknowledge. External devices can deassert ACK (low) to add wait states

to an external memory access. ACK is used by I/O devices, memory controllers, or

other peripherals to hold off completion of an external memory access.

RD

I/Owithprogrammable

PUP¹

External Port Read Enable. RD is asserted low whenever the processor reads 8-bit

or 16-bit data from an external memory device. When AD15–0 are flags, this pin

remains deasserted. RD has a 22.5 kΩ internal pull-up resistor.

WR

Output with program-

mable PUP¹

External Port Write Enable. WR is asserted low whenever the processor writes 8-bit

or 16-bit data to an external memory device. When AD15–0 are flags, this pin remains

deasserted. WR has a 22.5 kΩ internal pull-up resistor.

SDRAS

SDCAS

SDWE

Output with program-

mable PUP¹

SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin.

SDRAM column address select. Connect to SDRAM’s CAS pin.

SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin.

SDRAM Clock Enable. Connect to SDRAM’s CKE pin.

SDRAM A10.

Output with program-

mable PUP¹

Output with program-

mable PUP¹

SDCKE

SDA10

SDCLK0

Output with program-

mable PUP¹

Output with program-

mable PUP¹

I/O

SDRAM Clock Configure.

Rev. PrA

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Page 12 of 48 | November 2004

Preliminary Technical Data

ADSP-21367

Table 3. Pin List

Name

Type

State During

and After

Reset

Description

MS_0–1

I/Owithprogrammable

PUP¹

Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the cor-

responding banks of external memory. Memory bank size must be defined in the

ADSP-21062’ssystemcontrolregister(SYSCON).TheMS_3-0linesaredecodedmemory

address lines that change at the same time as the other address lines. When no

external memory access is occurring the MS3-0 lines are inactive; they are active

however when a conditional memory access instruction is executed, whether or not

the condition is true. In a multiprocessing system the MS_3-0lines are output by the

bus master.

FLAG[0]/IRQ0

FLAG[1]/IRQ1

I/O

FLAG0/Interrupt Request0.

FLAG1/Interrupt Request1.

FLAG[2]/IRQ2/

MS2

I/O with

FLAG2/Interrupt Request/Memory Select2.

programmable¹pull-

up (for MS mode)

FLAG[3]/TIMEX

P/MS3

I/O with

FLAG3/Timer Expired/Memory Select3.

programmable¹pull-

up (for MS mode)

TDI

Input with pull-up

Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a

22.5 kΩ internal pull-up resistor.

TDO

TMS

Output

Test Data Output (JTAG). Serial scan output of the boundary scan path.

Input with pull-up

Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 kΩ

internal pull-up resistor.

TCK

Input

Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted

(pulsed low) after power-up or held low for proper operation of the ADSP-21367.

TRST

Input with pull-up

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)

after power-up or held low for proper operation of the ADSP-21367. TRST has a 22.5

kΩ

internal pull-up resistor.

EMU

Output with pull-up

Input

Emulation Status. Must be connected to the ADSP-21367 Analog Devices DSP Tools

product line of JTAG emulators target board connector only. EMU has a 22.5 k

Ω

internal pull-up resistor.

CLK_CFG_1–0

Core/CLKIN Ratio Control. These pins set the start up clock frequency. See Table 5

for a description of the clock configuration modes.

Note that the operating frequency can be changed by programming the PLL multi-

plier and divider in the PMCTL register at any time after the core comes out of reset.

BOOT_CFG_1–0

RESET

Input

Boot Configuration Select. These pins select the boot mode for the processor. The

BOOTCFG pins must be valid before reset is asserted. See Table 4 for a description of

the boot modes.

Processor Reset. Resets the ADSP-21367 to a known state. Upon deassertion, there

is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins

program execution from the hardware reset vector address. The RESET input must be

asserted (low) at power-up.

Rev. PrA

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Page 13 of 48 | November 2004

ADSP-21367

Preliminary Technical Data

Table 3. Pin List

Name

Type

State During

and After

Reset

Description

XTAL

Output

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external

crystal.

CLKIN

Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21367 clock input.

It configures the ADSP-21367 to use either its internal clock generator or an external

clock source. Connecting the necessary components to CLKIN and XTAL enables the

internal clock generator. Connecting the external clock to CLKIN while leaving XTAL

unconnected configures the ADSP-21367 to use the external clock source such as an

externalclockoscillator.Thecoreisclocked eitherbythePLLoutputorthisclockinput

depending on the CLKCFG1–0 pin settings. CLKIN may not be halted, changed, or

operated below the specified frequency.

CLKOUT

Output

Local Clock Out. CLKOUT can also be configured as a reset out pin.The functionality

can be switched between the PLL output clock and reset out by setting bit 12 of the

PMCTREG register. The default is reset out.

¹Pull-up is always enabled for ID - 000 in uniprocessor mode and ID- 001 in Multiprocessing mode.

²Pull-up can be enabled/disabled, value of pull-up cannot be programmed.

³OP is three-statable

ADDRESS/DATA MODES

TBD

BOOT MODES

Table 4. Boot Mode Selection

BOOTCFG1–0

Booting Mode

SPI Slave Boot

00

01

10

SPI Master Boot

AMI boot via EPROM

CORE INSTRUCTION RATE TO CLKIN RATIO MODES

For details on processor timing, see Timing Specifications and

Figure 3 on page 17.

Table 5. Core Instruction Rate/ CLKIN Ratio Selection

CLKCFG1–0

Core to CLKIN Ratio

00

01

10

6:1

32:1

16:1

Rev. PrA

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Page 14 of 48 | November 2004

Preliminary Technical Data

ADSP-21367

ADSP-21367 SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

K Grade

Min

Parameter¹

Max

Unit

V_DDINT

A_VDD

Internal (Core) Supply Voltage

1.235

3.13

2.0

1.365

3.47

V

Analog (PLL) Supply Voltage

V_DDEXT

External (I/O) Supply Voltage

2

V_IH

High Level Input Voltage @ V_DDEXT= max

Low Level Input Voltage @ V_DDEXT= min

High Level Input Voltage @ V_DDEXT= max

Low Level Input Voltage @ V_DDEXT= min

Ambient Operating Temperature

V_DDEXT+ 0.5

+0.8

V

2

V_IL

–0.5

1.74

–0.5

0

V

3

V_{IH_CLKIN}

V_{IL_CLKIN}

V_DDEXT+ 0.5

+1.19

V

4, 5

T_AMB

+70

°C

1

Specifications subject to change without notice.

²Applies to input and bidirectional pins: AD15–0, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKCFGx, RESET, TCK, TMS, TDI, TRST.

³Applies to input pin CLKIN.

⁴See Thermal Characteristics on page 41 for information on thermal specifications.

⁵See Engineer-to-Engineer Note (No. TBD) for further information.

ELECTRICAL CHARACTERISTICS

Parameter¹

Test Conditions

Min

Max

Unit

2

V_OH

High Level Output Voltage

Low Level Output Voltage

High Level Input Current

Low Level Input Current

@ V_DDEXT= min, I_OH= –1.0 mA³

@ V_DDEXT= min, I_OL= 1.0 mA³

@ V_DDEXT= max, V_IN= V_DDEXTmax

@ V_DDEXT= max, V_IN= 0 V

@ V_DDEXT= max, V_IN= V_DDEXTmax

@ V_DDEXT= max, V_IN= 0 V

t_CCLK= 5.0 ns, V_DDINT= 1.3

A_VDD= max

2.4

V

2

V_OL

0.4

10

V

4, 5

I_IH

µA

mA

pF

4

I_IL

10

5

I_ILPU

Low Level Input Current Pull-up

Three-State Leakage Current

Three-State Leakage Current Pull-up

Supply Current (Internal)

Supply Current (Analog)

200

10

6, 7

I_OZH

6

I_OZL

10

7

I_OZLPU

200

500

10

8, 9

I_DD-INTYP

10

AI_DD

11, 12

C_IN

Input Capacitance

f_IN=1 MHz, T_CASE=25°C, V_IN=1.3V

4.7

1

Specifications subject to change without notice.

²Applies to output and bidirectional pins: AD15–0, RD, WR, ALE, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, XTAL.

³See Output Drive Currents on page 41 for typical drive current capabilities.

⁴Applies to input pins: SPIDS, BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN.

⁵Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, TDI.

⁶Applies to three-statable pins: FLAG3–0.

⁷Applies to three-statable pins with 22.5 kΩ pull-ups: AD15–0, DAI_Px, SPICLK, EMU, MISO, MOSI.

⁸Typical internal current data reflects nominal operating conditions.

⁹See Engineer-to-Engineer Note (No. TBD) for further information.

¹⁰Characterized, but not tested.

¹¹Applies to all signal pins.

¹²Guaranteed, but not tested.

Rev. PrA

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Page 15 of 48 | November 2004

ADSP-21367

Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

Parameter

Rating

1

Internal (Core) Supply Voltage (V_DDINT

)

–0.3 V to +1.5 V

–0.3 V to +4.6 V

+ 0.5 V

1

Analog (PLL) Supply Voltage (A_VDD

)

1

External (I/O) Supply Voltage (V_DDEXT

)

1

Input Voltage–0.5 V to V_DDEXT

1

Output Voltage Swing–0.5 V to V_DDEXT

Load Capacitance¹

+ 0.5 V

200 pF

Storage Temperature Range¹

–65°C to +150°C

125°C

Junction Temperature under Bias

¹Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only;

functional operation of the device at these or any other conditions greater than those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods

may affect device reliability.

ESD SENSITIVITY

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily

accumulate on the human body and test equipment and can discharge without detection.

AlthoughtheADSP-21367featuresproprietaryESDprotectioncircuitry,permanentdamagemay

occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

Table 7. Clock Periods

TIMING SPECIFICATIONS

The ADSP-21367’s internal clock (a multiple of CLKIN) pro-

vides the clock signal for timing internal memory, processor

core, serial ports, and parallel port (as required for read/write

strobes in asynchronous access mode). During reset, program

the ratio between the processor’s internal clock frequency and

external (CLKIN) clock frequency with the CLKCFG1–0 pins

(see Table 5 on page 14). To determine switching frequencies

for the serial ports, divide down the internal clock, using the

programmable divider control of each port (DIVx for the serial

ports).

Timing

Requirements

Description¹

t_CK

CLKIN Clock Period

t_CCLK

t_PCLK

t_SCLK

(Processor) Core Clock Period

(Peripheral) Clock Period = 2 × t_CCLK

Serial Port Clock Period = (t_PCLK) × SR

SDRAM Clock Period = (TBD)

SPI Clock Period = (t_PCLK) × SPIR

t_SDCLK

t_SPICLK

¹where:

The ADSP-21367’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the processor uses an internal phase-locked loop (PLL).

This PLL-based clocking minimizes the skew between the sys-

tem clock (CLKIN) signal and the processor’s internal clock (the

clock source for the parallel port logic and I/O pads).

SR = serial port-to-core clock ratio (wide range, determined by SPORT

CLKDIV)

SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPIBAUD register)

DAI_Px = Serial Port Clock

SPICLK = SPI Clock

Figure 3 shows Core to CLKIN ratios of 6:1, 16:1 and 32:1 with

external oscillator or crystal. Note that more ratios are possible

and can be set through software using the power management

control register (PMCTL). For more information, see the ADSP-

2136x SHARC Processor Programming Reference.

Note the definitions of various clock periods that are a function

of CLKIN and the appropriate ratio control (Table 6).

Table 6. ADSP-21367 CLKOUT and CCLK Clock

Generation Operation

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times. See

Figure 34 on page 41 under Test Conditions for voltage refer-

ence levels.

Timing

Description

Calculation

Requirements

CLKIN

CCLK

Input Clock

Core Clock

1/t_CK

1/t_CCLK

Rev. PrA

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Page 16 of 48 | November 2004

Preliminary Technical Data

ADSP-21367

Switching Characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching char-

acteristics describe what the processor will do in a given

circumstance. Use switching characteristics to ensure that any

timing requirement of a device connected to the processor (such

as memory) is satisfied.

CLKOUT

CLKIN

XTAL

PLL

CCLK

(CORE CLOCK)

PLLILCLK

XTAL

OSC

6:1, 16:1,

32:1

SDCLK

(SDRAM CLOCK)

Timing Requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

CLK-CFG [1:0]

Figure 3. Core Clock and System Clock Relationship to CLKIN

Rev. PrA

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Page 17 of 48 | November 2004

ADSP-21367

Preliminary Technical Data

Power-Up Sequencing

The timing requirements for processor startup are given in

Table 8.

Table 8. Power Up Sequencing Timing Requirements (Processor Startup)

Parameter

Min

Max

Unit

Timing Requirements

t_RSTVDD

RESET Low Before V_DDINT/V_DDEXTon

V_DDINTon Before V_DDEXT

0

ns

t_IVDDEVDD

–50

0

10²

20³

200

ms

µs

1

t_CLKVDD

CLKIN Valid After V_DDINT/V_DDEXTValid

CLKIN Valid Before RESET Deasserted

PLL Control Setup Before RESET Deasserted

t_CLKRST

t_PLLRST

µs

Switching Characteristic

4 5

t_CORERST

Core Reset Deasserted After RESET Deasserted

4096t_CK+ 2 t_CCLK,

¹Valid V_DDINT/V_DDEXTassumes that the supplies are fully ramped to their 1.3 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds

depending on the design of the power supply subsystem.

²Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's datasheet for startup time.

Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

³Based on CLKIN cycles

⁴Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and

propagate default states at all I/O pins.

⁵The 4096 cycle count depends on t_SRSTspecification in Table 10. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097

cycles maximum.

RESET

t_RSTVDD

V

DDINT

t_IVDDEVDD

V

t_CLKVDD

DDEXT

CLKIN

t_CLKRST

CLK_CFG1-0

t_CORERST

t_PLLRST

RSTOUT

Figure 4. Power-Up Sequencing

Rev. PrA

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Page 18 of 48 | November 2004

Preliminary Technical Data

ADSP-21367

Clock Input

Table 9. Clock Input

Parameter

400 MHz

Min

Unit

Max

Timing Requirements

t_CK

CLKIN Period

15¹

6¹

320²

150²

TBD

10

ns

t_CKL

t_CKH

t_CKRF

t_CCLK

CLKIN Width Low

CLKIN Width High

CLKIN Rise/Fall (0.4V–2.0V)

CCLK Period

3

2.5¹

¹Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.

²Applies only for CLKCFG1–0 = 01 and default values for PLL control bits in PMCTL.

³Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t_CCLK

.

t_CK

CLKIN

t_CKH

t_CKL

Figure 5. Clock Input

Clock Signals

The ADSP-21367 can use an external clock or a crystal. See the

CLKIN pin description in TBD. The programmer can configure

the ADSP-21367 to use its internal clock generator by connect-

ing the necessary components to CLKIN and XTAL. Figure 6

shows the component connections used for a crystal operating

in fundamental mode. Note that the clock rate is achieved using

a 16.67 MHz crystal and a PLL multiplier ratio 16:1

(CCLK:CLKIN achieves a clock speed of 266 MHz). To achieve

the full core clock rate, programs need to configure the multi-

plier bits in the PMCTL register.

CLKIN

XTAL

1M⍀

C1

C2

X1

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL

SELECTION MUST COMPLY WITH CLKCFG1-0 = 10 OR = 01.

Figure 6. 400 MHz Operation (Fundamental Mode Crystal)

Rev. PrA

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Page 19 of 48

|

November 2004

ADSP-21367

Preliminary Technical Data

Reset

Table 10. Reset

Parameter

Min

Max

Unit

Timing Requirements

1

t_WRST

t_SRST

RESET Pulse Width Low

RESET Setup Before CLKIN Low

4t_CK

8

ns

¹Applies after the power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 100 µs while RESET is low, assuming

stable VDD and CLKIN (not including start-up time of external clock oscillator).

CLKIN

t_SRST

t_WRST

RESET

Figure 7. Reset

Interrupts

The following timing specification applies to the FLAG0,

FLAG1, and FLAG2 pins when they are configured as IRQ0,

IRQ1, and IRQ2 interrupts.

Table 11. Interrupts

Parameter

Min

2 × t_PCLK+2

Max

Unit

Timing Requirement

t_IPW

IRQx Pulse Width

ns

DPI14-1

FLAG2-0

(IRQ2-0)

t_IPW

Figure 8. Interrupts

Rev. PrA

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Page 20 of 48 | November 2004

Preliminary Technical Data

ADSP-21367

Core Timer

The following timing specification applies to FLAG3 when it is

configured as the core timer (CTIMER).

Table 12. Core Timer

Parameter

Min

Max

Unit

Switching Characteristic

t_WCTIM

CTIMER Pulse width

4 × t_PCLK– 1

ns

t_WCTIM

FLAG3

(CTIMER)

Figure 9. Core Timer

Timer PWM_OUT Cycle Timing

The following timing specification applies to Timer0, Timer1,

and Timer2 in PWM_OUT (pulse width modulation) mode.

Timer signals are routed to the DAI_P20–1 pins through the

SRU. Therefore, the timing specifications provided below are

valid at the DAI_P20–1 pins.

Table 13. Timer PWM_OUT Timing

Parameter

Min

2 t_PCLK– 1

Max

2(2³¹– 1) t_PCLK

Unit

Switching Characteristic

t_PWMO

Timer Pulse Width Output

ns

t_PWMO

DPI14-0

(TIMER2-0)

Figure 10. Timer PWM_OUT Timing

Rev. PrA

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Page 21 of 48 | November 2004

ADSP-21367

Preliminary Technical Data

Timer WDTH_CAP Timing

The following timing specification applies to Timer0, Timer1,

and Timer2 in WDTH_CAP (pulse width count and capture)

mode. Timer signals are routed to the DAI_P20–1 pins through

the SRU. Therefore, the timing specification provided below are

valid at the DAI_P20–1 pins.

Table 14. Timer Width Capture Timing

Parameter

Min

2 t_PCLK

Max

2(2³¹– 1) t_PCLK

Unit

Timing Requirement

t_PWI

Timer Pulse Width

ns

t_PWI

DPI14-0

(TIMER2-0)

Figure 11. Timer Width Capture Timing

Pin to Pin Direct Routing (DAI and DPI)

For direct pin connections only (for example DAI_PB01_I to

DAI_PB02_O).

Table 15. DAI Pin to Pin Routing

Parameter

Min

Max

Unit

Timing Requirement

t_DPIO

Delay DAI Pin Input Valid to DAI Output Valid

1.5

10

ns

DAI_Pn

DPI_Pn

DAI_pm

DPI_Pm

t_DPIO

Figure 12. DAI Pin to Pin Direct Routing

Rev. PrA

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Page 22 of 48 | November 2004

Preliminary Technical Data

ADSP-21367

inputs and outputs are not directly routed to/from DAI pins (via

pin buffers) there is no timing data available. All Timing Param-

eters and Switching Characteristics apply to external DAI pins

(DAI_P07 – DAI_P20).

Precision Clock Generator (Direct Pin Routing)

This timing is only valid when the SRU is configured such that

the Precision Clock Generator (PCG) takes its inputs directly

from the DAI pins (via pin buffers) and sends its outputs

directly to the DAI pins. For the other cases, where the PCG’s

Table 16. Precision Clock Generator (Direct Pin Routing)

Parameter

Min

Max

Unit

Timing Requirements

t_PCGIW

t_STRIG

t_HTRIG

Input Clock Period

24

2

PCG Trigger Setup Before Falling Edge of PCG Input Clock

PCG Trigger Hold After Falling Edge of PCG Input Clock

ns

2

Switching Characteristics

t_DPCGIO

PCG Output Clock and Frame Sync Active Edge Delay After

PCG Input Clock

2.5

10

ns

t_DTRIG

PCG Output Clock and Frame Sync Delay After PCG Trigger

Output Clock Period

2.5 + 2.5 × t_PCGOW10 + 2.5 × t_PCGOWns

48

t_PCGOW

t_STRIG

DAI_Pn

DPI_Pn

PCG_TRIGx_I

t_PCGIW

t_HTRIG

DAI_Pm

DPI_Pm

PCG_EXTx_I

(CLKIN)

t_DPCGIO

DAI_Py

DPI_Py

PCG_CLKx_O

t_PCGOW

DAI_Pz

DPI_Pz

PCG_FSx_O

t_DTRIG

Figure 13. Precision Clock Generator (Direct Pin Routing)

Rev. PrA

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Page 23 of 48 | November 2004

ADSP-21367

Preliminary Technical Data

Flags

The timing specifications provided below apply to the FLAG3–0

and DPI_P14–1 pins, the parallel port, and the serial peripheral

interface (SPI). See TBD for more information on flag use.

Table 17. Flags

Parameter

Min

Max

Unit

Timing Requirement

t_FIPW

FLAG3–0 IN Pulse Width

2 × t_PCLK+ 3

ns

Switching Characteristic

t_FOPWFLAG3–0 OUT Pulse Width

2 × t_PCLK– 1

ns

DPI_P140-1

(FLAG3-0

)

IN

(DATA31-0)

t_FIPW

DPI_P14-1

(FLAG3-0

)

OUT

(DATA31-0)

t_FOPW

Figure 14. Flags

Rev. PrA

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Page 24 of 48 | November 2004

Preliminary Technical Data

ADSP-21367

SDRAM Interface Timing

Table 18. SDRAM Interface Timing¹

Parameter

Minimum

Maximum

Unit

Timing Requirement

t_SSDAT

t_HSDAT

DATA Setup Before CLKOUT

DATA Hold After CLKOUT

TBD

ns

Switching Characteristic

t_SCLK

CLKOUT Period

TBD

ns

t_SCLKH

CLKOUT Width High

t_SCLKL

CLKOUT Width Low

t_DCAD

Command, ADDR, Data Delay After CLKOUT²

Command, ADDR, Data Hold After CLKOUT¹

Data Disable After CLKOUT

TBD

t_HCAD

TBD

t_DSDAT

t_ENSDAT

¹For V_DDINT= 1.3 V.

Data Enable After CLKOUT

²Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.

t_SCLK

t_SCLKH

SDCLK

t_SSDAT

t_SCLKL

t_HSDAT

DATA (IN)

t_DCAD

t_DSDAT

t_ENSDAT

t_HCAD

DATA(OUT)

t_DCAD

CMND ADDR

(OUT)

t_HCAD

NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.

Figure 15. SDRAM Interface Timing

Rev. PrA

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Page 25 of 48 | November 2004

ADSP-21367

Preliminary Technical Data

Serial Ports

To determine whether communication is possible between two

devices at clock speed n, the following specifications must be

confirmed: 1) frame sync delay and frame sync setup and hold,

2) data delay and data setup and hold, and 3) SCLK width.

Serial port signals (SCLK, FS, data channel A,/data channel B)

are routed to the DAI_P20–1 pins using the SRU. Therefore, the

timing specifications provided below are valid at the

DAI_P20–1 pins.

Table 19. Serial Ports—External Clock

Parameter

Min

Max

Unit

Timing Requirements

1

t_SFSE

FS Setup Before SCLK

(Externally Generated FS in either Transmit or Receive Mode)

2.5

ns

1

t_HFSE

FS Hold After SCLK

(Externally Generated FS in either Transmit or Receive Mode)

2.5

24

ns

1

t_SDRE

Receive Data Setup Before Receive SCLK

Receive Data Hold After SCLK

SCLK Width

1

t_HDRE

t_SCLKW

t_SCLK

SCLK Period

48

Switching Characteristics

2

t_DFSE

FS Delay After SCLK

(Internally Generated FS in either Transmit or Receive Mode)

7

ns

2

t_HOFSE

FS Hold After SCLK

(Internally Generated FS in either Transmit or Receive Mode)

2

ns

2

t_DDTE

Transmit Data Delay After Transmit SCLK

2

t_HDTE

Transmit Data Hold After Transmit SCLK

¹Referenced to sample edge.

²Referenced to drive edge.

Table 20. Serial Ports—Internal Clock

Parameter

Min

Max

Unit

Timing Requirements

1

t_SFSI

FS Setup Before SCLK

(Externally Generated FS in either Transmit or Receive Mode)

7

ns

1

t_HFSI

FS Hold After SCLK

(Externally Generated FS in either Transmit or Receive Mode)

2.5

7

ns

1

t_SDRI

Receive Data Setup Before SCLK

Receive Data Hold After SCLK

1

t_HDRI

2.5

Switching Characteristics

2

t_DFSI

FS Delay After SCLK (Internally Generated FS in Transmit Mode)

3

ns

2

t_HOFSI

FS Hold After SCLK (Internally Generated FS in Transmit Mode)

FS Delay After SCLK (Internally Generated FS in Receive or Mode)

FS Hold After SCLK (Internally Generated FS in Receive Mode)

Transmit Data Delay After SCLK

–1.0

2

t_DFSI

3

t_HOFSI

2

t_DDTI

3

2

t_HDTI

Transmit Data Hold After SCLK

–1.0

t_SCLKIW

Transmit or Receive SCLK Width

0.5t_SCLK– 2

0.5t_SCLK+ 2

¹Referenced to the sample edge.

²Referenced to drive edge.

Rev. PrA

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Page 26 of 48 | November 2004

Preliminary Technical Data

ADSP-21367

Table 21. Serial Ports—Enable and Three-State

Parameter

Min

2

Max

Unit

Switching Characteristics

1

t_DDTEN

Data Enable from External Transmit SCLK

Data Disable from External Transmit SCLK

Data Enable from Internal Transmit SCLK

ns

1

t_DDTTE

7

1

t_DDTIN

–1

¹Referenced to drive edge.

Table 22. Serial Ports—External Late Frame Sync

Parameter

Min

Max

Unit

Switching Characteristics

1

t_DDTLFSE

Data Delay from Late External Transmit FS or External Receive FS

with MCE = 1, MFD = 0

7

ns

1

t_DDTENFS

Data Enable for MCE = 1, MFD = 0

0.5

¹The t_DDTLFSEand t_DDTENFSparameters apply to Left-justified Sample Pair as well as DSP serial mode, and MCE = 1, MFD = 0.

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

DRIVE

SAMPLE

DRIVE

DAI_P20-1

(SCLK)

t_SFSE/I

t_HFSE/I

DAI_P20-1

(FS)

t_DDTE/I

t_DDTENFS

t_HDTE/I

1ST BIT

DAI_P20-1

(DATA CHANNEL A/B)

2ND BIT

t_DDTLFSE

LATE EXTERNAL TRANSMIT FS

DRIVE

SAMPLE

DRIVE

t_HFSE/I

DAI_P20-1

(SCLK)

t_SFSE/I

DAI_P20-1

(FS)

t_DDTE/I

t_DDTENFS

t_HDTE/I

1ST BIT

DAI_P20-1

(DATA CHANNEL A/B)

2ND BIT

t_DDTLFSE

NOTE

SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20-1 PINS

USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20-1 PINS.

Figure 16. External Late Frame Sync¹

¹This figure reflects changes made to support Left-justified Sample Pair mode.

Rev. PrA

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Page 27 of 48 | November 2004

ADSP-21367

Preliminary Technical Data

DATA RECEIVE— INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DATA RECEIVE— EXTERNAL CLOCK

DRIVE EDGE

SAMPLE EDGE

t_SCLKIW

t_SCLKW

DAI_P20-1

(SCLK)

DAI_P20-1

(SCLK)

t_DFSI

t_DFSE

t_HFSE

t_HFSI

t_SFSI

t_SFSE

t_HOFSI

t_HOFSE

DAI_P20-1

(FS)

DAI_P20-1

(FS)

t_HDRE

t_SDRI

t_HDRI

t_SDRE

DAI_P20-1

(DATA CHANNEL A/B)

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DATA TRANSMIT — INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DATA TRANSMIT — EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

t_SCLKIW

t_SCLKW

DAI_P20-1

(SCLK)

DAI_P20-1

(SCLK)

t_DFSI

t_DFSE

t_HFSI

t_HOFSI

t_SFSI

t_HOFSE

t_SFSE

t_HFSE

DAI_P20-1

(FS)

DAI_P20-1

(FS)

t_DDTE

t_DDTI

t_HDTE

t_HDTI

DAI_P20-1

(DATA CHANNEL A/B)

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE EDGE

DAI_P20-1

SCLK

SCLK (EXT)

t_DDTEN

t_DDTTE

DAI_P20-1

(DATA CHANNEL A/B)

DRIVE EDGE

DAI_P20-1

SCLK (INT)

t_DDTIN

DAI_P20-1

(DATA CHANNEL A/B)

Figure 17. Serial Ports

Rev. PrA

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Page 28 of 48

|

November 2004

Preliminary Technical Data

ADSP-21367

Input Data Port

The timing requirements for the IDP are given in Table 23.IDP

Signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins

using the SRU. Therefore, the timing specifications provided

below are valid at the DAI_P20–1 pins.

Table 23. IDP

Parameter

Min

Max

Unit

Timing Requirements

1

t_SISFS

FS Setup Before SCLK Rising Edge

FS Hold After SCLK Rising Edge

SData Setup Before SCLK Rising Edge

SData Hold After SCLK Rising Edge

Clock Width

2.5

9

ns

1

t_SIHFS

1

t_SISD

1

t_SIHD

t_IDPCLKW

t_IDPCLK

Clock Period

24

1

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_IPDCLK

t_IPDCLKW

DAI_P20-1

(SCLK)

t_SISFS

t_SIHFS

DAI_P20-1

(FS)

t_SISD

t_SIHD

DAI_P20-1

(SDATA)

Figure 18. IDP Master Timing

Rev. PrA

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Page 29 of 48 | November 2004

ADSP-21367

Preliminary Technical Data

ence. Note that the most significant 16 bits of external PDAP

data can be provided through either the parallel port AD15–0 or

the DAI_P20–5 pins. The remaining 4 bits can only be sourced

through DAI_P4–1. The timing below is valid at the

DAI_P20–1 pins or at the AD15–0 pins.

Parallel Data Acquisition Port (PDAP)

The timing requirements for the PDAP are provided in

Table 24. PDAP is the parallel mode operation of channel 0 of

the IDP. For details on the operation of the IDP, see the IDP

chapter of the ADSP-2136x SHARC Processor Hardware Refer-

Table 24. Parallel Data Acquisition Port (PDAP)

Parameter

Min

Max

Unit

Timing Requirements

1

t_SPCLKEN

PDAP_CLKEN Setup Before PDAP_CLK Sample Edge

PDAP_CLKEN Hold After PDAP_CLK Sample Edge

PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge

PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge

Clock Width

2.5

7

ns

1

t_HPCLKEN

1

t_PDSD

1

t_PDHD

t_PDCLKW

t_PDCLK

Clock Period

24

Switching Characteristics

t_PDHLDDDelay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word

t_PDSTRBPDAP Strobe Pulse Width

2 × t_CCLK

ns

1 × t_CCLK– 1

1

Source pins of DATA are ADDR7–0, DATA7–0, or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.

SAMPLE EDGE

t_PDCLK

t_PDCLKW

DAI_P20-1

(PDAP_CLK)

t_SPCLKEN

t_HPCLKEN

DAI_P20-1

(PDAP_CLKEN)

t_PDSD

t_PDHD

DATA

DAI_P20-1

(PDAP_STROBE)

t_PDSTRB

t_PDHLDD

Figure 19. PDAP Timing

Rev. PrA

|

Page 30 of 48 | November 2004

Preliminary Technical Data

ADSP-21367

Sample Rate Converter—Serial Input Port

The SRC input signals (SCLK, FS, and SDATA) are routed from

the DAI_P20–1 pins using the SRU. Therefore, the timing spec-

ifications provided in Table 25 are valid at the DAI_P20–1 pins.

Table 25. SRC, Serial Input Port

Parameter

Min

Max

Unit

Timing Requirements

1

t_SRCSFS

FS Setup Before SCLK Rising Edge

FS Hold After SCLK Rising Edge

SData Setup Before SCLK Rising Edge

SData Hold After SCLK Rising Edge

Clock Width

4

ns

1

t_SRCHFS

5.5

4

1

t_SRCSD

1

t_SRCHD

t_SRCCLKW

t_SRCCLK

5.5

9

Clock Period

20

1

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_SRCCLK

t_SRCCLKW

DAI_P20-1

(SCLK)

t_SRCSFS

t_SRCHFS

DAI_P20-1

(FS)

t_SRCSD

t_SRCHD

DAI_P20-1

(SDATA)

Figure 20. SRC Serial Input Port Timing

Rev. PrA

|

Page 31 of 48 | November 2004

ADSP-21367

Preliminary Technical Data

and delay specification with regard to SCLK. Note that SCLK

rising edge is the sampling edge and the falling edge is the drive

edge.

Sample Rate Converter—Serial Output Port

For the serial output port, the frame-sync is an input and it

should meet setup and hold times with regard to SCLK on the

output port. The serial data output, SDATA, has a hold time

Table 26. SRC, Serial Output Port

Parameter

Min

Max

Unit

Timing Requirements

1

t_SRCSFS

FS Setup Before SCLK Rising Edge

FS Hold Before SCLK Rising Edge

4

ns

1

t_SRCHFS

5.5

Switching Characteristics

1

t_SRCTDD

Transmit Data Delay After SCLK Falling Edge

Transmit Data Hold After SCLK Falling Edge

7

ns

1

t_SRCTDH

2

1

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_SRCCLK

t_SRCCLKW

DAI_P20-1

(SCLK)

t_SRCSFS

t_SRCHFS

DAI_P20-1

(FS)

t_SRCTDH

t_SRCTDD

DAI_P20-1

(SDATA)

Figure 21. SRC Serial Output Port Timing

Rev. PrA

|

Page 32 of 48 | November 2004

Preliminary Technical Data

ADSP-21367

SPDIF Transmitter

Serial data input to the SPDIF transmitter can be formatted as

left justified, I²S or right justified with word widths of 16, 18, 20,

or 24 bits. The following sections provide timing for the

transmitter.

SPDIF Transmitter—Serial Input Waveforms

Figure 22 shows the right-justified mode. LRCLK is HI for the

left channel and LO for the right channel. Data is valid on the

rising edge of SCLK. The MSB is delayed 12-bit clock periods

(in 20-bit output mode) or 16-bit clock periods (in 16-bit output

mode) from an LRCLK transition, so that when there are 64

SCLK periods per LRCLK period, the LSB of the data will be

right-justified to the next LRCLK transition.

LRCLK

RIGHT CHANNEL

LEFT CHANNEL

SCLK

SDATA

LSB

MSB MSB-1 MSB-2

LSB+2 LSB+1

LSB

MSB MSB-1 MSB-2

LSB+2 LSB+1

LSB

Figure 22. Right-Justified Mode

Figure 23 shows the default I2S-justified mode. LRCLK is LO

for the left channel and HI for the right channel. Data is valid on

the rising edge of SCLK. The MSB is left-justified to an LRCLK

transition but with a single SCLK period delay.

RIGHT CHANNEL

LRCLK

LEFT CHANNEL

SCLK

MSB MSB-1 MSB-2

LSB+2 LSB+1 LSB

MSB

MSB-1 MSB-2

LSB+2 LSB+1 LSB

MSB

SDATA

Figure 23. I²S-Justified Mode

Figure 24 shows the left-justified mode. LRCLK is HI for the left

channel and LO for the right channel. Data is valid on the rising

edge of SCLK. The MSB is left-justified to an LRCLK transition

with no MSB delay.

LRCLK

RIGHT CHANNEL

LEFT CHANNEL

SCLK

SDATA

LSB+2 LSB+1 LSB

MSB

MSB-1 MSB-2

LSB+2 LSB+1

LSB

MSB

MSB-1 MSB-2

MSB MSB+1

Figure 24. Left-Justified Mode

Rev. PrA

|

Page 33 of 48 | November 2004

ADSP-21367

Preliminary Technical Data

SPDIF Transmitter Input Data Timing

The timing requirements for the Input port are given in

Table 27. Input Signals (SCLK, FS, SDATA) are routed to the

DAI_P20–1 pins using the SRU. Therefore, the timing specifica-

tions provided below are valid at the DAI_P20–1 pins.

Table 27. SPDIF Transmitter Input Data Timing

Parameter

Min

Max

Unit

Timing Requirements

1

t_SIFS

FS Setup Before SCLK Rising Edge

FS Hold After SCLK Rising Edge

SData Setup Before SCLK Rising Edge

SData Hold After SCLK Rising Edge

Clock Width

4

ns

1

t_SIHFS

5.5

4

1

t_SISD

1

t_SIHD

t_SISCLKW

t_SISCLK

5.5

9

Clock Period

20

1

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_SISCLKW

DAI_P20-1

(SCLK)

t_SIHFS

t_SISFS

DAI_P20-1

(FS)

t_SISD

t_SIHD

DAI_P20-1

(SDATA)

Figure 25. SPDIF Transmitter Input Timing

Over Sampling Clock (TXCLK) Switching Characteristics

SPDIF Transmitter has an over sampling clock. This TXCLK

input is divided down to generate the Biphase Clock.

Table 28. Over Sampling Clock (TXCLK) Switching Characteristics

Parameter

Min

Max

147.5

98.4

Unit

MHz

TXCLK Frequency for TXCLK = 768 × FS

TXCLK Frequency for TXCLK = 512 × FS

TXCLK Frequency for TXCLK = 384 × FS

TXCLK Frequency for TXCLK = 256 × FS

Frame Rate

73.8

49.2

192.0

Rev. PrA

|

Page 34 of 48

|

November 2004

Preliminary Technical Data

ADSP-21367

SPDIF Receiver

The following sections describe timing as it relates to the SPDIF

receiver.

Internal Digital PLL Mode

In internal Digital Phase-locked Loop mode the internal PLL

(Digital PLL) generates the 512 × Fs clock.

Table 29. SPDIF Receiver Internal Digital PLL Mode Timing

Parameter

Min

Max

Unit

Switching Characteristics

t_DFSI

LRCLK Delay After SCLK

LRCLK Hold After SCLK

Transmit Data Delay After SCLK

Transmit Data Hold After SCLK

Transmit SCLK Width

5

ns

t_HOFSI

t_DDTI

–2

t_HDTI

–2

40

1

t_SCLKIW

t_CCLK

Core Clock Period

5

¹SCLK frequency is 64 x FS where FS = the frequency of LRCLK.

DRIVE EDGE

SAMPLE EDGE

t_SCLKIW

DAI_P20-1

(SCLK)

t_DFSI

t_HFSI

t_SFSI

t_HOFSI

DAI_P20-1

(FS)

t_DDTI

t_HDTI

DAI_P20-1

(DATA CHANNEL A/B)

Figure 26. SPDIF Receiver Internal Digital PLL Mode Timing

Rev. PrA

|

Page 35 of 48 | November 2004

ADSP-21367

Preliminary Technical Data

External PLL Mode

In External PLL Mode internal Digital PLL is disabled and the

receiver runs on the PLL that is connected to the processor

externally. This external PLL generates the 512 x Fs clock

(MCLK) from the reference clock (LRCLK) and gives it to

SPDIF receiver.

Table 30. SPDIF Receiver External PLL Mode Timing

Parameter

Min

Max

Unit

Timing Requirements

t_MCP

FMCLK

t_BDM

t_LDM

t_DDP

MCLK Period

10

ns

MCLK Frequency (1/t_MCP

)

100

30

MHz

ns

SCLK Propagation Delay from MCLK to the Falling Edge

LRCLK Propagation Delay From MCLK

Data Propagation Delay From MCLK

Data Output Setup To SCLK

30

ns

30

ns

t_DDS

1/2 SCLK Period

ns

t_DDH

Data Output Hold From SCLK

ns

MCLK INPUT

(NOT TO SCALE)

BCLK OUTPUT

t_BDM

LRCLK

OUTPUT

t_LDM

t_DDS

MSB

t_DDH

SDATA OUTPUT

2

I S-JUSTIFIED

MODE

t_DDP

t_DDS

SDATA OUTPUT

RIGHT-JUSTIFIED

MODE

MSB

LSB

t_DDH

t_DDP

Figure 27. SPDIF Receiver External PLL Mode Timing

Rev. PrA

|

Page 36 of 48 | November 2004

Preliminary Technical Data

ADSP-21367

SPI Interface—Master

The ADSP-21367 contains two SPI ports. The primary has dedi-

cated pins and the secondary is available through the DPI. The

timing provided in Table 31 and Table 32 on page 38 applies to

both.

Table 31. SPI Interface Protocol — Master Switching and Timing Specifications

Parameter

Min

Max

Unit

Timing Requirements

t_SSPIDM

t_HSPIDM

Data Input Valid To SPICLK Edge (Data Input Set-up Time)

SPICLK Last Sampling Edge To Data Input Not Valid

8

2

ns

Switching Characteristics

t_SPICLKM

t_SPICHM

t_SPICLM

t_DDSPIDM

t_HDSPIDM

t_SDSCIM

t_HDSM

Serial Clock Cycle

8 × t_PCLK

ns

SErial Clock High Period

4 × t_PCLK

Serial Clock Low Period

4 × t_PCLK– 2

SPICLK Edge to Data Out Valid (Data Out Delay Time)

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

FLAG3–0IN (SPI device select) Low to First SPICLK Edge

Last SPICLK Edge to FLAG3–0IN High

Sequential Transfer Delay

0

2

ns

4 × t_PCLK– 2

4 × t_PCLK– 1

t_SPITDM

FLAG3-0

(OUTPUT)

t_SDSCIM

t_SPICHM

t_SPICLM

t_SPICHM

t_DDSPIDM

t_SPICLKM

t_HDSM

t_SPITDM

SPICLK

(CP = 0)

(OUTPUT)

t_SPICLM

SPICLK

(CP = 1)

(OUTPUT)

t_HDSPIDM

MOSI

(OUTPUT)

MSB

LSB

t_SSPIDM

CPHASE=1

t_HSPIDM

t_HSSPIDM

MISO

MSB

LSB

(INPUT)

VALID

t_HDSPIDM

t_DDSPIDM

MOSI

(OUTPUT)

MSB

LSB

t_SSPIDM

t_HSPIDM

CPHASE=0

MSB

VALID

LSB

VALID

MISO

(INPUT)

Figure 28. SPI Master Timing

Rev. PrA

|

Page 37 of 48 | November 2004

ADSP-21367

Preliminary Technical Data

SPI Interface—Slave

Table 32. SPI Interface Protocol —Slave Switching and Timing Specifications

Parameter

Min

Max

Unit

Timing Requirements

t_SPICLKS

t_SPICHS

t_SPICLS

t_SDSCO

Serial Clock Cycle

4 × t_PCLK

ns

Serial Clock High Period

Serial Clock Low Period

2 × t_PCLK

2 × t_PCLK– 2

SPIDS Assertion to First SPICLK Edge

CPHASE = 0

CPHASE = 1

2 × t_PCLK

t_HDS

Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0

Data Input Valid to SPICLK edge (Data Input Set-up Time)

SPICLK Last Sampling Edge to Data Input Not Valid

SPIDS Deassertion Pulse Width (CPHASE=0)

2 × t_PCLK

ns

t_SSPIDS

t_HSPIDS

t_SDPPW

2

2 × t_PCLK

Switching Characteristics

t_DSOE

SPIDS Assertion to Data Out Active

0

4

ns

t_DSDHI

t_DDSPIDS

t_HDSPIDS

t_DSOV

SPIDS Deassertion to Data High Impedance

4

SPICLK Edge to Data Out Valid (Data Out Delay Time)

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

SPIDS Assertion to Data Out Valid (CPHASE=0)

9.4

2 × t_PCLK

5 × t_PCLK

SPIDS

(INPUT)

t_SPICHS

t_SPICLS

t_SPICLKS

t_HDS

t_SDPPW

SPICLK

(CP = 0)

(INPUT)

t_SPICLS

t_SDSCO

t_{SPIC HS}

SPICLK

(CP = 1)

(INPUT)

t_DSDHI

t_HDLSBS

t_DDSPIDS

t_DSOE

t_DDSPIDS

MISO

(OUTPUT)

MSB

LSB

t_HSPIDS

CPHASE=1

t_{SSPID S}

t_SSPIDS

MOSI

LSB

MSB

(INPUT)

VALID

t_DSOV

t_DSOE

t_HDLSBS

t_{D DSPIDS}

t_{D SDHI}

MISO

(OUTPUT)

LSB

MSB

t_HSPIDS

CPHASE=0

t_{SSPID S}

LSB

MSB

MOSI

VALID

(INPUT)

Figure 29. SPI Slave Timing

Rev. PrA

|

Page 38 of 48 | November 2004

Preliminary Technical Data

ADSP-21367

Universal Asynchronous Receiver-Transmitter

(UART) Port—Receive and Transmit Timing

Figure 30 describes UART port receive and transmit operations.

The maximum baud rate is SCLK/16. As shown in Figure 30

there is some latency between the generation internal UART

interrupts and the external data operations. These latencies are

negligible at the data transmission rates for the UART.

CLKOUT

(SAMPLE CLOCK)

RXD

DATA(5–8)

STOP

RECEIVE

INTERNAL

UART RECEIVE

INTERRUPT

UART RECEIVE BIT SET BY DATA STOP;

CLEARED BY FIFO READ

START

TXD

DATA(5–8)

STOP (1–2)

TRANSMIT

INTERNAL

UART TRANSMIT

INTERRUPT

UART TRANSMIT BIT SET BY PROGRAM;

CLEARED BY WRITE TO TRANSMIT

Figure 30. UART Port—Receive and Transmit Timing

Rev. PrA

|

Page 39 of 48 | November 2004

ADSP-21367

Preliminary Technical Data

JTAG Test Access Port and Emulation

Table 33. JTAG Test Access Port and Emulation

Parameter

Min

Max

Unit

Timing Requirements

t_TCK

TCK Period

t_CK

5

ns

t_STAP

t_HTAP

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK Low

System Inputs Hold After TCK Low

TRST Pulse Width

6

1

t_SSYS

7

1

t_HSYS

t_TRSTW

18

4t_CK

Switching Characteristics

t_DTDOTDO Delay from TCK Low

System Outputs Delay After TCK Low

7

ns

2

t_DSYS

10

¹System Inputs = AD15–0, SPIDS, CLKCFG1–0, RESET, BOOTCFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0.

²System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU, ALE.

t

TCK

t

STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t

SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 31. IEEE 1149.1 JTAG Test Access Port

Rev. PrA

|

Page 40 of 48 | November 2004

Preliminary Technical Data

ADSP-21367

OUTPUT DRIVE CURRENTS

CAPACITIVE LOADING

Figure 32 shows typical I-V characteristics for the output driv-

ers of the ADSP-21367. The curves represent the current drive

capability of the output drivers as a function of output voltage.

Output delays and holds are based on standard capacitive loads:

30 pF on all pins (see Figure 33). Figure 37 shows graphically

how output delays and holds vary with load capacitance. The

graphs of Figure 35, Figure 36, and Figure 37 may not be linear

outside the ranges shown for Typical Output Delay vs. Load

Capacitance and Typical Output Rise Time (20%-80%, V=Min)

vs. Load Capacitance.

TBD

Figure 32. ADSP-21367 Typical Drive

TEST CONDITIONS

The ac signal specifications (timing parameters) appear

Table 10 on page 20 through Table 33 on page 40. These include

output disable time, output enable time, and capacitive loading.

The timing specifications for the SHARC apply for the voltage

reference levels in Figure 33.

Figure 35. Typical Output Rise/Fall Time (20%-80%,

V_DDEXT= Max)

Timing is measured on signals when they cross the 1.5 V level as

described in Figure 34. All delays (in nanoseconds) are mea-

sured between the point that the first signal reaches 1.5 V and

the point that the second signal reaches 1.5 V.

TBD

50⍀

TO

OUTPUT

1.5V

30pF

Figure 36. Typical Output Rise/Fall Time (20%-80%,

V

_DDEXT=Min)

Figure 33. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

TBD

INPUT

OR

OUTPUT

1.5V

Figure 37. Typical Output Delay or Hold vs. Load Capacitance

(at Ambient Temperature)

Figure 34. Voltage Reference Levels for AC Measurements

commercial temperature range, T_AMB= –40°C to 85°C.

THERMAL CHARACTERISTICS

The ADSP-21367 processor is rated for performance over the

Rev. PrA

|

Page 41 of 48 | November 2004

ADSP-21367

Preliminary Technical Data

Table 34 through Table 36 airflow measurements comply with

JEDEC standards JESD51-2 and JESD51-6 and the junction-to-

board measurement complies with JESD51-8. Test board and

thermal via design comply with JEDEC standards JESD51-9

(BGA). The junction-to-case measurement complies with MIL-

STD-883. All measurements use a 2S2P JEDEC test board.

Table 35. Thermal Characteristics for 256 Ball SBGA (Ther-

mal vias in PCB)

Parameter

Ψ_JT

Ψ_JMT

Condition

Typical

TBD

Unit

°C/W

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

TBD

To determine the Junction Temperature of the device while on

the application PCB, use:

Ψ_JMT

TBD

Table 36. Thermal Characteristics for 208-Lead MQFP

T = T

+ (Ψ × P )

JT

D

J

CASE

Parameter

θ_JA

θ_JMA

θ_JC

Ψ_JT

Ψ_JMT

Condition

Typical

TBD

Unit

°C/W

where:

T_J= Junction temperature °C

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

TBD

T_CASE= Case temperature (°C) measured at the top center of

the package

TBD

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

TBD

Ψ_JT= Junction-to-Top (of package) characterization parameter

is the Typical value from Table 34 and Table 36.

TBD

P

_D= Power dissipation (see EE Note #TBD)

Values of θ_JAare provided for package comparison and PCB

design considerations. θ_JAcan be used for a first order approxi-

mation of T_Jby the equation:

T = T + (θ × P )

J

A

JA

D

where:

T_A= Ambient Temperature °C

Values of θ_JCare provided for package comparison and PCB

design considerations when an external heatsink is required.

Values of θ_JBare provided for package comparison and PCB

design considerations. Note that the thermal characteristics val-

ues provided in Table 34 through Table 36 are modeled values.

Table 34. Thermal Characteristics for 256 Ball SBGA (No

thermal vias in PCB)

Parameter

θ_JA

θ_JMA

θ_JC

Ψ_JT

Ψ_JMT

Condition

Typical

TBD

Unit

°C/W

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

TBD

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

TBD

Table 35. Thermal Characteristics for 256 Ball SBGA (Ther-

mal vias in PCB)

Parameter

θ_JA

θ_JMA

θ_JC

Condition

Typical

TBD

Unit

°C/W

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

TBD

Rev. PrA

|

Page 42 of 48

|

November 2004

Preliminary Technical Data

ADSP-21367

256-BALL SBGA PINOUT

Table 37. 256-Ball SBGA Pin Assignment (Numerically by Ball Number)

Ball No. Signal

DAI10

A01

A02

A03

A04

A05

A06

A07

A08

A09

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

E01

E02

E03

E04

E17

E18

E19

E20

J01

NC

B01

B02

B03

B04

B05

B06

B07

B08

B09

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

F01

F02

F03

F04

F17

F18

F19

F20

K01

K02

K03

K04

DAI5

C01

C02

C03

C04

C05

C06

C07

C08

C09

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

G01

G02

G03

G04

G17

G18

G19

G20

L01

L02

L03

L04

DAI9

DAI7

GND

D01

D02

D03

D04

D05

D06

D07

D08

D09

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

H01

H02

H03

H04

H17

H18

H19

H20

M01

M02

M03

M04

TDI

SDCLK1

TRST

DAI6

TMS

GND

CLK_CFG0

CLK_CFG1

EMU

TCK

IOVDD

GND

IOVDD

GND

BOOTCFG_0

BOOTCFG_1

TDO

GND

IOVDD

VDD

DAI4

VDD

DAI1

DAI3

GND

DPI14

DPI12

DPI10

DPI9

DAI2

GND

IOVDD

VDD

DPI13

DPI11

DPI8

VDD

GND

IOVDD

VDD

DPI7

DPI5

VDD

DPI6

DPI4

GND

DPI3

DPI1

GND

IOVDD

GND

DPI2

RESET

DATA30

DATA29

DATA28

NC

VDD

CLKOUT

DATA31

NC

VDD

IOVDD

GND

VDD

DATA27

RPBA

DAI15

DAI13

GND

DATA26

DATA24

DAI17

DAI16

VDD

NC

DAI11

DAI8

DAI14

DAI12

GND

VDD

GND

IOVDD

VDD

GND

IOVDD

GND

IOVDD

GND

VDD

DATA25

DATA23

DAI19

DAI18

GND

ID2

DATA22

DATA20

FLAG2

FLAG1

VDD

DATA19

DATA18

ACK

DATA21

FLAG0

DAI20

GND

J02

FLAG3

GND

J03

J04

GND

IOVDD

VDD

GND

Rev. PrA

|

Page 43 of 48

|

November 2004

ADSP-21367

Preliminary Technical Data

Table 37. 256-Ball SBGA Pin Assignment (Numerically by Ball Number) (Continued)

Ball No. Signal

J17

GND

K17

K18

K19

K20

P01

P02

P03

P04

P17

P18

P19

P20

V01

V02

V03

V04

V05

V06

V07

V08

V09

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

VDD

L17

VDD

M17

M18

M19

M20

T01

T02

T03

T04

T17

T18

T19

T20

Y01

Y02

Y03

Y04

Y05

Y06

Y07

Y08

Y09

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

IOVDD

GND

J18

GND

VDD

L18

VDD

J19

ID1

ID0

L19

DATA15

DATA14

SDWE

DATA12

DATA13

SDCKE

SDCAS

GND

J20

DATA17

RD

DATA16

SDA10

WR

L20

N01

N02

N03

N04

N17

N18

N19

N20

U01

U02

U03

U04

U05

U06

U07

U08

U09

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

R01

SDCLK0

GND

R02

SDRAS

GND

VDD

R03

IOVDD

GND

VDD

R04

GND

IOVDD

GND

VDD

R17

IOVDD

GND

VDD

R18

GND

DATA11

DATA10

MS0

DATA8

DATA9

ADDR22

ADDR23

VDD

R19

DATA6

DATA7

GND

DATA5

DATA4

GND

R20

W01

W02

W03

W04

W05

W06

W07

W08

W09

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

MS1

ADDR21

ADDR19

ADDR20

ADDR17

ADDR16

ADDR15

ADDR14

AVDD

NC

VDD

NC

GND

ADDR18

BR1

IOVDD

GND

BR2

IOVDD

VDD

GND

XTAL2

CLKIN

NC

VDD

IOVDD

GND

AVSS

NC

IOVDD

VDD

GND

ADDR13

ADDR12

ADDR10

ADDR8

ADDR5

ADDR4

ADDR1

ADDR2

ADDR0

NC

BR3

VDD

BR4

IOVDD

VDD

GND

ADDR11

ADDR9

ADDR7

ADDR6

ADDR3

GND

IOVDD

VDD

IOVDD

VDD

GND

VDD

GND

DATA0

DATA2

DATA1

DATA3

GND

NC

Rev. PrA

|

Page 44 of 48

|

November 2004

Preliminary Technical Data

ADSP-21367

208-LEAD MQFP PINOUT

Table 38. 208-Lead MQFP Pin Assignment (Numerically by Lead Number)

Pin No.

1

Signal

VDD

Pin No.

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

Signal

VDD

Pin No.

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

Signal

VDD

Pin No.

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

Signal

VDD

GND

VDD

TDI

2

DATA28

DATA27

GND

3

IOVDD

ADDR0

ADDR2

ADDR1

ADDR4

ADDR3

ADDR5

GND

IOVDD

SDCAS

SDRAS

SDCKE

SDWE

WR

4

5

IOVDD

DATA26

DATA25

DATA24

DATA23

GND

6

7

8

TRST

TCK

9

SDA10

GND

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

GND

VDD

TMS

VDD

IOVDD

SDCLK0

GND

DATA22

DATA21

DATA20

IOVDD

GND

IOVDD

ADDR6

ADDR7

ADDR8

ADDR9

ADDR10

GND

CLK_CFG0

BOOTCFG0

CLK_CFG1

EMU

VDD

RD

ACK

DATA19

DATA18

VDD

FLAG3

FLAG2

FLAG1

FLAG0

DAI20

GND

BOOTCFG1

TDO

DAI4

GND

VDD

DAI2

DATA17

VDD

GND

DAI3

IOVDD

ADDR11

ADDR12

ADDR13

GND

DAI1

GND

VDD

IOVDD

GND

VDD

GND

IOVDD

DAI19

DAI18

DAI17

DAI16

DAI15

DAI14

DAI13

DAI12

VDD

DATA16

DATA15

DATA14

DATA13

DATA12

IOVDD

GND

VDD

DPI14

DPI13

DPI12

DPI11

DPI10

DPI9

AVSS

AVDD

GND

CLKIN

XTAL2

IOVDD

GND

VDD

DPI8

GND

DPI7

DATA11

DATA10

DATA9

DATA8

DATA7

DATA6

IOVDD

GND

VDD

IOVDD

GND

IOVDD

GND

ADDR14

GND

VDD

IOVDD

ADDR15

ADDR16

ADDR17

ADDR18

GND

DAI11

DAI10

DAI8

DPI6

DPI5

DPI4

DAI9

DPI3

VDD

DAI6

DPI1

DATA4

IOVDD

DAI7

DPI2

Rev. PrA

|

Page 45 of 48

|

November 2004

ADSP-21367

Preliminary Technical Data

Table 38. 208-Lead MQFP Pin Assignment (Numerically by Lead Number) (Continued)

Pin No.

45

Signal

DATA5

DATA2

DATA3

DATA0

DATA1

IOVDD

GND

Pin No.

97

Signal

ADDR19

ADDR20

ADDR21

ADDR23

ADDR22

MS1

Pin No.

149

Signal

DAI5

IOVDD

GND

VDD

Pin No.

201

Signal

CLKOUT

RESET

46

98

150

202

47

99

151

203

IOVDD

GND

48

100

101

102

103

104

152

204

49

153

GND

VDD

205

DATA30

DATA31

DATA29

VDD

50

154

206

51

MS0

155

GND

VDD

207

52

VDD

156

208

PACKAGE DIMENSIONS

The ADSP-21367 is available in a 208-lead-free MQFP package

and 256-ball lead-free and leaded SBGA packages

A1 CORNER

INDEX AREA

20 18 16 14 12 10

19 17 15 13 11

8

6

4

2

9

7

5

3

1

A

B

C

D

E

F

A1 BALL

INDICATOR

G

H

J

K

L

BOTTOM

VIEW

27.00

TOP VIEW

BSC SQ

M

N

P

R

T

U

V

W

Y

24.13

REF SQ

1.00

0.80

0.60

1.70 MAX

0.70

1.27

0.60

NOM

0.10

MIN

0.50

0.20

COPLANARITY

SEATING

PLANE

0.90

0.75

0.60

BALL

DIAMETER

0.25 MIN 4X

DIMENSIONS ARE IN MILLIMETERS AND COMPLY

WITH JEDEC STANDARDS MO-192-BAL-2.

Figure 38. 256-Lead SBGA, Thermally Enhanced (BP-256)

Rev. PrA

|

Page 46 of 48 | November 2004

Preliminary Technical Data

ADSP-21367

30.85

30.60 SQ

30.35

0.75

0.60

0.45

4.10

MAX

208

1

157

156

SEATING

PLANE

PIN 1 INDICATOR

28.20

28.00 SQ

27.80

TOP VIEW

(PINS DOWN)

3.60

3.40

3.20

VIEW A

105

104

52

0.20

0.09

53

0.50

BSC

0.27

0.17

0.50

0.25

0.08 MAX

(LEAD COPLANARITY)

(LEAD PITCH)

(LEAD WIDTH)

VIEW A

ROTATED 90° CCW

NOTES:

1. THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 FROM ITS IDEAL

POSITION WHEN MEASURED IN THE LATERAL DIRECTION.

2. CENTER DIMENSIONS ARE TYPICAL UNLESS OTHERWISE NOTED.

3. DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH

JEDEC STANDARD MS-029, FA-1.

Figure 39. 208-Lead MQFP (S-208-2)

ORDERING GUIDE

Analog Devices offers a wide variety of audio algorithms and

combinations to run on the ADSP-21367 processor. These

products are sold as part of a chip set, bundled with necessary

application software under special part numbers. For a complete

list, visit our web site at www.analog.com/SHARC.

These product also may contain 3rd party IPs that may require

users to have authorization from the respective IP holders to

receive them. Royalty for use of the 3rd party IPs may also be

payable by users.

Part Number^{1, 2}

Ambient Temperature Instruction

On-Chip ROM

SRAM

Operating Voltage Packages

Range

Rate

ADSP-21367SKSZ-ENG

ADSP-21367SKBP-ENG

ADSP-21367SKBPZENG

¹B indicates Ball Grid Array package.

0°C to + 70°C

266 MHz

2M bit

6M bit

1.2 INT/3.3 EXT V

1.3 INT/3.3 EXT V

208-Lead MQFP,

Pb-Free

0°C to +70°C

400 MHz

256-Ball SBGA, Pb-

Bearing

256-Ball SBGA, Pb-

Free

²Z indicates Lead Free package. For more information about lead free package offerings, please visit www.analog.com.

Rev. PrA

|

Page 47 of 48 | November 2004

ADSP-21367

Preliminary Technical Data

©

registered trademarks are the property of their respective owners.

PR05267-0-11/04(PrA)

Rev. PrA

|

Page 48 of 48 | November 2004


型号：	ADSP-21367KSZ-ENG
厂家：	ADI
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ADSP-21367KSZ-ENG [ADI]

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ADSP-21367SKBP-ENG

ADSP-21367SKBPZENG

ADSP-21367SKSZ-ENG

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ADSP-21368BBP-2A

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