ADSP-21062KB-160 [ADI]
ADSP-2106x SHARC DSP Microcomputer Family; ADSP- 2106x SHARC DSP单片机系列型号: | ADSP-21062KB-160 |
厂家: | ADI |
描述: | ADSP-2106x SHARC DSP Microcomputer Family |
文件: | 总48页 (文件大小:368K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
®
ADSP-2106x SHARC
a
DSP Microcomputer Family
ADSP-21062/ADSP-21062L
SUMMARY
IEEE JTAG Standard 1149.1 Test Access Port and
On-Chip Emulation
High Performance Signal Processor for Communica-
tions, Graphics and Imaging Applications
Super Harvard Architecture
Four Independent Buses for Dual Data Fetch,
Instruction Fetch and Nonintrusive I/O
32-Bit IEEE Floating-Point Computation Units—
Multiplier, ALU, and Shifter
Dual-Ported On-Chip SRAM and Integrated I/O
Peripherals—A Complete System-On-A-Chip
Integrated Multiprocessing Features
240-Lead Thermally Enhanced MQFP Package
225-Ball Plastic Ball Grid Array (PBGA)
32-Bit Single-Precision and 40-Bit Extended-Precision
IEEE Floating-Point Data Formats or 32-Bit Fixed-
Point Data Format
Parallel Computations
Single-Cycle Multiply and ALU Operations in Parallel with
Dual Memory Read/Writes and Instruction Fetch
Multiply with Add and Subtract for Accelerated FFT
Butterfly Computation
KEY FEATURES
40 MIPS, 25 ns Instruction Rate, Single-Cycle Instruction
Execution
120 MFLOPS Peak, 80 MFLOPS Sustained Performance
Dual Data Address Generators with Modulo and Bit-
Reverse Addressing
2 Mbit On-Chip SRAM
Dual-Ported for Independent Access by Core Processor
and DMA
Off-Chip Memory Interfacing
4 Gigawords Addressable
Programmable Wait State Generation, Page-Mode
DRAM Support
Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup
DUAL-PORTED SRAM
CORE PROCESSOR
INSTRUCTION
TIMER
JTAG
TWO INDEPENDENT
7
CACHE
DUAL-PORTED BLOCKS
32 x 48-BIT
TEST &
EMULATION
PROCESSOR PORT
I/O PORT
DATA
ADDR
DATA
ADDR
DATA
ADDR
ADDR
DATA
DAG2
DAG1
PROGRAM
SEQUENCER
8 x 4 x 24
8 x 4 x 32
EXTERNAL
PORT
IOD
48
IOA
17
PM ADDRESS BUS
24
32
32
48
ADDR BUS
MUX
DM ADDRESS BUS
MULTIPROCESSOR
INTERFACE
PM DATA BUS
DM DATA BUS
48
BUS
CONNECT
(PX)
DATA BUS
MUX
40/32
HOST PORT
4
6
DMA
DATA
REGISTER
FILE
IOP
REGISTERS
MEMORY MAPPED)
CONTROLLER
(
SERIAL PORTS
(2)
16 x 40-BIT
BARREL
SHIFTER
6
ALU
MULTIPLIER
CONTROL,
STATUS &
DATA BUFFERS
36
LINK PORTS
(6)
I/O PROCESSOR
Figure 1. ADSP-21062/ADSP-21062L Block Diagram
SHARC is a registered trademark of Analog Devices, Inc.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
ADSP-21062/ADSP-21062L
DMA Controller
Multiprocessing
10 DMA Channels for Transfers Between ADSP-21062
Internal Memory and External Memory, External
Peripherals, Host Processor, Serial Ports, or Link
Ports
Background DMA Transfers at 40 MHz, in Parallel with
Full-Speed Processor Execution
Glueless Connection for Scalable DSP Multiprocessing
Architecture
Distributed On-Chip Bus Arbitration for Parallel Bus
Connect of Up to Six ADSP-21062s Plus Host
Six Link Ports for Point-to-Point Connectivity and Array
Multiprocessing
240 Mbytes/s Transfer Rate Over Parallel Bus
240 Mbytes/s Transfer Rate Over Link Ports
Host Processor Interface to 16- and 32-Bit Microprocessors
Host Can Directly Read/Write ADSP-21062 Internal
Memory
Serial Ports
Two 40 Mbit/s Synchronous Serial Ports with Com-
panding Hardware
Independent Transmit and Receive Functions
Figure 7. JTAG Clocktree for Multiple ADSP-2106x
TABLE OF CONTENTS
Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. Memory Read—Bus Master . . . . . . . . . . . . . . . . 20
Figure 14. Memory Write—Bus Master . . . . . . . . . . . . . . . 21
Figure 15. Synchronous Read/Write—Bus Master . . . . . . . 23
Figure 16. Synchronous Read/Write—Bus Slave . . . . . . . . . 25
Figure 17. Multiprocessor Bus Request and Host Bus
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 3
ADSP-21000 FAMILY CORE ARCHITECTURE . . . . . . . 4
ADSP-21062/ADSP-21062L FEATURES . . . . . . . . . . . . . . 4
DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 8
TARGET BOARD CONNECTOR FOR EZ-ICE®
PROBE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
RECOMMENDED OPERATING CONDITIONS . . . . . . 13
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . 13
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 17
Memory Read—Bus Master . . . . . . . . . . . . . . . . . . . . . . . 20
Memory Write—Bus Master . . . . . . . . . . . . . . . . . . . . . . 21
Synchronous Read/Write—Bus Master . . . . . . . . . . . . . . 22
Synchronous Read/Write—Bus Slave . . . . . . . . . . . . . . . . 24
Multiprocessor Bus Request and Host Bus Request . . . . . 26
Asynchronous Read/Write—Host to ADSP-21062 . . . . . . 28
Three-State Timing—Bus Master, Bus Slave,
HBR, SBTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DMA Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Link Ports: 1 × CLK Speed Operation . . . . . . . . . . . . . . 33
Link Ports: 2 × CLK Speed Operation . . . . . . . . . . . . . . 34
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
JTAG Test Access Port and Emulation . . . . . . . . . . . . . . . 39
OUTPUT DRIVE CURRENTS . . . . . . . . . . . . . . . . . . . . . 40
POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . . 43
225 Ball Plastic Ball Grid Array (PBGA)
Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 18a. Synchronous REDY Timing . . . . . . . . . . . . . . 28
Figure 18b. Asynchronous Read/Write—Host to
ADSP-21062 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 19a. Three-State Timing (Bus Transition Cycle,
SBTS Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 19b. Three-State Timing (Host Transition Cycle) . . 30
Figure 20. DMA Handshake Timing . . . . . . . . . . . . . . . . . 32
Figure 21. Link Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 22. Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 23. External Late Frame Sync . . . . . . . . . . . . . . . . . 38
Figure 24. IEEE 11499.1 JTAG Test Access Port . . . . . . . 39
Figure 25. Output Enable/Disable . . . . . . . . . . . . . . . . . . . 41
Figure 26. Equivalent Device Loading for AC Measurements
(Includes All Fixtures) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 27. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable) . . . . . . . . . . . . . . . . . . . 41
Figure 28. ADSP-21062 Typical Drive Currents
Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 44
225 Ball Plastic Ball Grid Array (PBGA)
(VDD = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 29. Typical Output Rise Time (10%–90% VDD
)
Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PACKAGE DIMENSIONS, 225-Ball PBGA . . . . . . . . . . . 46
240-LEAD METRIC MQFP PIN CONFIGURATIONS . . 47
PACKAGE DIMENSIONS, 240-Lead Metric MQFP . . . 48
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
vs. Load Capacitance (VDD = 5 V) . . . . . . . . . . . . . . . . . . 42
Figure 30. Typical Output Rise Time (0.8 V–2.0 V) vs. Load
Capacitance (VDD = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 31. Typical Output Delay or Hold vs. Load Capacitance
(at Maximum Case Temperature) (VDD = 5 V) . . . . . . . . 42
Figure 32. ADSP-21062 Typical Drive Currents
Figures
Figure 1. ADSP-21062/ADSP-21062L Block Diagram . . . . 1
Figure 2. ADSP-21062 System . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Shared Memory Multiprocessing System . . . . . . . . 6
Figure 4. ADSP-21062/ADSP-21062L Memory Map . . . . . 7
Figure 5. Target Board Connector For ADSP-2106x
EZ-ICE Emulator (Jumpers in Place) . . . . . . . . . . . . . . . 11
Figure 6. JTAG Scan Path Connections for Multiple
ADSP-2106x Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
(VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 33. Typical Output Rise Time (10%–90% VDD
)
vs. Load Capacitance (VDD = 3.3 V) . . . . . . . . . . . . . . . . 42
Figure 34. Typical Output Rise Time (0.8 V–2.0 V) vs. Load
Capacitance (VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 35. Typical Output Delay or Hold vs. Load Capacitance
(at Maximum Case Temperature) (VDD = 3.3 V) . . . . . . . 43
EZ-ICE is a registered trademark of Analog Devices, Inc.
REV. C
–2–
ADSP-21062/ADSP-21062L
including a 2 Mbit SRAM memory (4 Mbit on the ADSP-21060),
host processor interface, DMA controller, serial ports and
link port and parallel bus connectivity for glueless DSP
multiprocessing.
Figure 1 shows a block diagram of the ADSP-21062, illustrating
the following architectural features:
S
GENERAL NOTE
This data sheet represents production released specifications for
the ADSP-21062 (5 V) and ADSP-21062L (3.3 V) processors,
for both 33 MHz and 40 MHz speed grades. The product name
“ADSP-21062” is used throughout this data sheet to represent
all devices, except where expressly noted.
Computation Units (ALU, Multiplier and Shifter) with a
Shared Data Register File
Data Address Generators (DAG1, DAG2)
Program Sequencer with Instruction Cache
Interval Timer
On-Chip SRAM
External Port for Interfacing to Off-Chip Memory and
Peripherals
Host Port and Multiprocessor Interface
DMA Controller
Serial Ports and Link Ports
JTAG Test Access Port
Figure 2 shows a typical single-processor system. A multi-
processing system is shown in Figure 3.
GENERAL DESCRIPTION
The ADSP-21062 SHARC—Super Harvard Architecture
Computer—is a signal processing microcomputer that offers new
capabilities and levels of performance. The ADSP-21062
SHARCs are 32-bit processors optimized for high performance
DSP applications. The ADSP-21062 builds on the ADSP-21000
DSP core to form a complete system-on-a-chip, adding a dual-
ported on-chip SRAM and integrated I/O peripherals supported
by a dedicated I/O bus.
Table I. ADSP-21062/ADSP-21062L Benchmarks (@ 40 MHz)
1024-Pt. Complex FFT
0.46 ms
18,221 cycles
(Radix 4, with Digit Reverse)
FIR Filter (per Tap)
IIR Filter (per Biquad)
Divide (y/x)
25 ns
1 cycle
4 cycles
6 cycles
9 cycles
100 ns
150 ns
Fabricated in a high speed, low power CMOS process, the
ADSP-21062 has a 25 ns instruction cycle time and operates
at 40 MIPS. With its on-chip instruction cache, the processor
can execute every instruction in a single cycle. Table I shows
performance benchmarks for the ADSP-21062.
Inverse Square Root (1/√x)
DMA Transfer Rate
225 ns
240 Mbytes/s
The ADSP-21062 SHARC represents a new standard of inte-
gration for signal computers, combining a high performance
floating-point DSP core with integrated, on-chip system features
REV. C
–3–
ADSP-21062/ADSP-21062L
ADSP-21000 FAMILY CORE ARCHITECTURE
Instruction Cache
The ADSP-21062 includes the following architectural features
of the ADSP-21000 family core. The ADSP-21062 processors
are code- and function-compatible with the ADSP-21020.
The ADSP-21062 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and two
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
allows full-speed execution of core, looped operations such as
digital filter multiply-accumulates and FFT butterfly processing.
Independent, Parallel Computation Units
The arithmetic/logic unit (ALU), multiplier and shifter all per-
form single-cycle instructions. The three units are arranged in
parallel, maximizing computational throughput. Single multi-
function instructions execute parallel ALU and multiplier opera-
tions. These computation units support IEEE 32-bit single-
precision floating-point, extended precision 40-bit floating-
point, and 32-bit fixed-point data formats.
Data Address Generators with Hardware Circular Buffers
The ADSP-21062’s two data address generators (DAGs) imple-
ment circular data buffers in hardware. Circular buffers allow
efficient programming of delay lines and other data structures
required in digital signal processing, and are commonly used in
digital filters and Fourier transforms. The two DAGs of the
ADSP-21062 contain sufficient registers to allow the creation of
up to 32 circular buffers (16 primary register sets, 16 secondary).
The DAGs automatically handle address pointer wraparound,
reducing overhead, increasing performance and simplifying
implementation. Circular buffers can start and end at any
memory location.
ADSP-2106x
BMS
1x CLOCK
3
CLKIN
EBOOT
LBOOT
CS
BOOT
EPROM
(OPTIONAL)
ADDR
DATA
IRQ
2-0
FLAG
3-0
TIMEXP
4
ADDR
ADDR
DATA
31-0
MEMORY
AND
PERIPHERALS
(OPTIONAL)
DATA
47-0
Flexible Instruction Set
LINK
DEVICES
(6 MAXIMUM)
(OPTIONAL)
LxCLK
LxACK
LxDAT
3-0
RD
WR
OE
WE
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the ADSP-
21062 can conditionally execute a multiply, an add, a subtract
and a branch, all in a single instruction.
ACK
ACK
CS
MS
3-0
TCLK0
RCLK0
TFS0
RSF0
DT0
PAGE
SBTS
SW
SERIAL
DEVICE
(OPTIONAL)
DMA DEVICE
(OPTIONAL)
DATA
ADSP-21062/ADSP-21062L FEATURES
Augmenting the ADSP-21000 family core, the ADSP-21062
adds the following architectural features:
ADRCLK
DMAR1-2
DMAG1-2
DR0
TCLK1
RCLK1
TFS1
RFS1
DT1
CS
HBR
Dual-Ported On-Chip Memory
SERIAL
DEVICE
(OPTIONAL)
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
The ADSP-21062 contains two megabits of on-chip SRAM,
organized as two blocks of 1 Mbits each, which can be config-
ured for different combinations of code and data storage. Each
memory block is dual-ported for single-cycle, independent ac-
cesses by the core processor and I/O processor or DMA control-
ler. The dual-ported memory and separate on-chip buses allow
two data transfers from the core and one from I/O, all in a single
cycle.
HBG
REDY
DR1
BR
1-6
ADDR
DATA
RPBA
CPA
JTAG
ID
2-0
RESET
7
Figure 2. ADSP-21062 System
Data Register File
On the ADSP-21062, the memory can be configured as a maxi-
mum of 64K words of 32-bit data, 128K words of 16-bit data,
40K words of 48-bit instructions (or 40-bit data), or combina-
tions of different word sizes up to two megabits. All of the
memory can be accessed as 16-bit, 32-bit or 48-bit words.
A general purpose data register file is used for transferring data
between the computation units and the data buses, and for
storing intermediate results. This 10-port, 32-register (16 pri-
mary, 16 secondary) register file, combined with the ADSP-
21000 Harvard architecture, allows unconstrained data flow
between computation units and internal memory.
A 16-bit floating-point storage format is supported, which effec-
tively doubles the amount of data that may be stored on-chip.
Conversion between the 32-bit floating-point and 16-bit floating-
point formats is done in a single instruction.
Single-Cycle Fetch of Instruction and Two Operands
The ADSP-21062 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see Figure 1). With its separate program and data memory
buses and on-chip instruction cache, the processor can simulta-
neously fetch two operands and an instruction (from the cache),
all in a single cycle.
While each memory block can store combinations of code and
data, accesses are most efficient when one block stores data,
using the DM bus for transfers, and the other block stores
instructions and data, using the PM bus for transfers. Using the
DM bus and PM bus in this way, with one dedicated to each
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache. Single-cycle execution is also maintained when one of the
data operands is transferred to or from off-chip, via the ADSP-
21062’s external port.
REV. C
–4–
ADSP-21062/ADSP-21062L
include interrupt generation upon completion of DMA trans-
fers and DMA chaining for automatic linked DMA transfers.
Off-Chip Memory and Peripherals Interface
The ADSP-21062’s external port provides the processor’s inter-
face to off-chip memory and peripherals. The 4-gigaword off-
chip address space is included in the ADSP-21062’s unified
address space. The separate on-chip buses—for PM addresses,
PM data, DM addresses, DM data, I/O addresses and I/O
data—are multiplexed at the external port to create an external
system bus with a single 32-bit address bus and a single 48-bit
(or 32-bit) data bus.
Serial Ports
The ADSP-21062 features two synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices. The serial ports can operate at
the full clock rate of the processor, providing each with a maxi-
mum data rate of 40 Mbit/s. Independent transmit and receive
functions provide greater flexibility for serial communications.
Serial port data can be automatically transferred to and from
on-chip memory via DMA. Each of the serial ports offers TDM
multichannel mode.
Addressing of external memory devices is facilitated by on-chip
decoding of high-order address lines to generate memory bank
select signals. Separate control lines are also generated for sim-
plified addressing of page-mode DRAM. The ADSP-21062
provides programmable memory wait states and external
memory acknowledge controls to allow interfacing to DRAM
and peripherals with variable access, hold and disable time
requirements.
The serial ports can operate with little-endian or big-endian
transmission formats, with word lengths selectable from 3 bits to
32 bits. They offer selectable synchronization and transmit
modes as well as optional µ-law or A-law companding. Serial
port clocks and frame syncs can be internally or externally
generated.
Host Processor Interface
The ADSP-21062’s host interface allows easy connection to
standard microprocessor buses, both 16-bit and 32-bit, with
little additional hardware required. Asynchronous transfers at
speeds up to the full clock rate of the processor are supported.
The host interface is accessed through the ADSP-21062’s exter-
nal port and is memory-mapped into the unified address space.
Four channels of DMA are available for the host interface; code
and data transfers are accomplished with low software overhead.
Multiprocessing
The ADSP-21062 offers powerful features tailored to multi-
processor DSP systems. The unified address space (see
Figure 4) allows direct interprocessor accesses of each ADSP-
21062’s internal memory. Distributed bus arbitration logic is
included on-chip for simple, glueless connection of systems
containing up to six ADSP-21062s and a host processor. Master
processor changeover incurs only one cycle of overhead. Bus
arbitration is selectable as either fixed or rotating priority. Bus lock
allows indivisible read-modify-write sequences for semaphores. A
vector interrupt is provided for interprocessor commands. Maxi-
mum throughput for interprocessor data transfer is 240 Mbytes/s
over the link ports or external port. Broadcast writes allow simulta-
neous transmission of data to all ADSP-21062s and can be used
to implement reflective semaphores.
The host processor requests the ADSP-21062’s external bus
with the host bus request (HBR), host bus grant (HBG), and
ready (REDY) signals. The host can directly read and write the
internal memory of the ADSP-21062, and can access the DMA
channel setup and mailbox registers. Vector interrupt support is
provided for efficient execution of host commands.
DMA Controller
Link Ports
The ADSP-21062’s on-chip DMA controller allows zero-
overhead data transfers without processor intervention. The
DMA controller operates independently and invisibly to the
processor core, allowing DMA operations to occur while the
core is simultaneously executing its program instructions.
The ADSP-21062 features six 4-bit link ports that provide addi-
tional I/O capabilities. The link ports can be clocked twice per
cycle, allowing each to transfer eight bits of data per cycle. Link
port I/O is especially useful for point-to-point interprocessor
communication in multiprocessing systems.
DMA transfers can occur between the ADSP-21062’s internal
memory and either external memory, external peripherals or a
host processor. DMA transfers can also occur between the
ADSP-21062’s internal memory and its serial ports or link
ports. DMA transfers between external memory and external
peripheral devices are another option. External bus packing to
16-, 32-, or 48-bit words is performed during DMA transfers.
The link ports can operate independently and simultaneously,
with a maximum data throughput of 240 Mbytes/s. Link port
data is packed into 32- or 48-bit words, and can be directly read
by the core processor or DMA-transferred to on-chip memory.
Each link port has its own double-buffered input and output
registers. Clock/acknowledge handshaking controls link port
transfers. Transfers are programmable as either transmit or
receive.
Ten channels of DMA are available on the ADSP-21062—two
via the link ports, four via the serial ports, and four via the
processor’s external port (for either host processor, other
ADSP-21062s, memory or I/O transfers). Four additional
link port DMA channels are shared with serial port 1 and the
external port. Programs can be downloaded to the ADSP-
21062 using DMA transfers. Asynchronous off-chip peripher-
als can control two DMA channels using DMA Request/
Grant lines (DMAR1-2, DMAG1-2). Other DMA features
Program Booting
The internal memory of the ADSP-21062 can be booted at
system power-up from either an 8-bit EPROM, a host proces-
sor, or through one of the link ports. Selection of the boot
source is controlled by the BMS (Boot Memory Select),
EBOOT (EPROM Boot), and LBOOT (Link/Host Boot) pins.
32-bit and 16-bit host processors can be used for booting.
REV. C
–5–
ADSP-21062/ADSP-21062L
ADSP-2106x #6
ADSP-2106x #5
ADSP-2106x #4
ADSP-2106x #3
ADDR
CLKIN
31-0
DATA
47-0
RESET
RPBA
3
011
ID
2-0
CONTROL
CPA
BR , BR
5
1-2
4-6
BR
3
ADSP-2106x #2
ADDR
CLKIN
RESET
RPBA
31-0
47-0
DATA
3
010
ID
2-0
CONTROL
CPA
BR , BR
5
1
3-6
BR
2
ADSP-2106x #1
1x
CLOCK
CLKIN
ADDR
DATA
ADDR
DATA
31-0
GLOBAL
MEMORY
RESET
RESET
47-0
AND
PERIPHERALS
(OPTIONAL)
OE
RD
WR
ACK
RPBA
WE
ACK
CS
3
001
ID
2-0
MS
3-0
CS
BMS
PAGE
SBTS
SW
BOOT
EPROM
(OPTIONAL)
ADDR
CONTROL
DATA
ADRCLK
CS
HBR
HBG
REDY
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
ADDR
DATA
CPA
5
BR
2-6
BR
1
Figure 3. Shared Memory Multiprocessing System
REV. C
–6–
ADSP-21062/ADSP-21062L
0x0040 0000
0x0000 0000
0x0002 0000
IOP REGISTERS
BANK 0
INTERNAL
MEMORY
SPACE
MS
MS
MS
0
1
2
NORMAL WORD ADDRESSING
SHORT WORD ADDRESSING
DRAM
(OPTIONAL)
0x0004 0000
0x0008 0000
INTERNAL MEMORY SPACE
OF ADSP-2106x
BANK 1
BANK 2
WITH ID=001
0x0010 0000
0x0018 0000
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=010
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=011
EXTERNAL
MEMORY
SPACE
0x0020 0000
0x0028 0000
MULTIPROCESSOR
MEMORY SPACE
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=100
MS
BANK 3
3
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=101
BANK SIZE IS
0x0030 0000
0x0038 0000
SELECTED BY
MSIZE BIT FIELD OF
SYSCON
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=110
REGISTER.
BROADCAST WRITE
TO ALL
NONBANKED
ADSP-2106xs
0x003F FFFF
NORMAL WORD ADDRESSING: 32-BIT DATA WORDS
48-BIT INSTRUCTION WORDS
SHORT WORD ADDRESSING: 16-BIT DATA WORDS
0xFFFF FFFF
Figure 4. ADSP-21062/ADSP-21062L Memory Map
DEVELOPMENT TOOLS
dimensioned arrays. The ADSP-21000 Family Development
Software is available for both the PC and Sun platforms.
The ADSP-21062 is supported with a complete set of software
and hardware development tools, including an EZ-ICE In-
Circuit Emulator, EZ-LAB® development board, EZ-KIT, and
development software. The EZ-LAB contains an evaluation board
with an ADSP-21062 (5 V) processor and provides a serial connec-
tion to your PC. The SHARC EZ-KIT combines the ADSP-
21000 Family Development Software for the PC and the
EZ-LAB ADSP-21062’s Development Board in one package.
The EZ-KIT contains in addition to the EZ-LAB development
board, an optimizing compiler, assembler, instruction level simu-
lator, run-time libraries, diagnostic utilities and a complete set
of example programs.
The ADSP-21062 EZ-ICE Emulator uses the IEEE 1149.1
JTAG test access port of the ADSP-21062 processor to monitor
and control the target board processor during emulation. The
EZ-ICE provides full-speed emulation, allowing inspection and
modification of memory, registers, and processor stacks. Nonintru-
sive in-circuit emulation is assured by the use of the processor’s
JTAG interface—the emulator does not affect target system
loading or timing.
Further details and ordering information are available in the
ADSP-21000 Family Hardware & Software Development Tools
data sheet (ADDS-210xx-TOOLS). This data sheet can be
requested from any Analog Devices sales office, distributor or
the Literature Center.
The same EZ-ICE hardware can be used for the ADSP-21060/
ADSP-21061, to fully emulate the ADSP-21062, with the excep-
tion of displaying and modifying the two new SPORTS registers.
The emulator will not display these two registers, but your
code can use them.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family. Hard-
ware tools include SHARC PC plug-in cards, multiprocessor
SHARC VME boards, and daughter card modules with multiple
SHARCs and additional memory. These modules are based on
the SHARCPAC™ module specification. Third party software
tools include an Ada compiler, DSP libraries, operating systems,
and block diagram design tools.
Analog Devices’ ADSP-21000 Family Development Software
includes an easy to use Assembler based on an algebraic syntax,
an Assembly Library/Librarian, a Linker, an Instruction-level
Simulator, an ANSI C optimizing Compiler, the CBug™ C
Source-Level Debugger, and a C Runtime Library including
DSP and mathematical functions. The Optimizing Compiler
includes Numerical C extensions based on the work of the
ANSI Numerical C Extensions Group. Numerical C provides
extensions to the C language for array selection, vector math
operations, complex data types, circular pointers, and variably
ADDITIONAL INFORMATION
This data sheet provides a general overview of the ADSP-21062
architecture and functionality. For detailed information on the
ADSP-21000 Family core architecture and instruction set, refer
to the ADSP-21062 SHARC User’s Manual, Second Edition.
CBug and SHARCPAC are trademarks of Analog Devices, Inc.
EZ-LAB is a registered trademark of Analog Devices, Inc.
REV. C
–7–
ADSP-21062/ADSP-21062L
PIN FUNCTION DESCRIPTIONS
DRx, TCLKx, RCLKx, LxDAT3-0, LxCLK, LxACK, TMS
and TDI)—these pins can be left floating. These pins have a
logic-level hold circuit that prevents the input from floating
internally.
ADSP-21062 pin definitions are listed below. All pins are iden-
tical on the ADSP-21062 and ADSP-21062L. Inputs identified
as synchronous (S) must meet timing requirements with respect
to CLKIN (or with respect to TCK for TMS, TDI). Inputs
identified as asynchronous (A) can be asserted asynchronously
to CLKIN (or to TCK for TRST).
A = Asynchronous
O = Output
G = Ground
P = Power Supply
(O/D) = Open Drain
I = Input
S = Synchronous
(A/D) = Active Drive
Unused inputs should be tied or pulled to VDD or GND,
except for ADDR31-0, DATA47-0, FLAG3-0, SW, and inputs that
have internal pull-up or pull-down resistors (CPA, ACK, DTx,
T = Three-State (when SBTS is asserted, or when the
ADSP-21062 is a bus slave)
Pin
Type
Function
ADDR31-0
I/O/T
External Bus Address. The ADSP-21062 outputs addresses for external memory and peripherals on
these pins. In a multiprocessor system the bus master outputs addresses for read/writes of the internal
memory or IOP registers of other ADSP-21062s. The ADSP-21062 inputs addresses when a host
processor or multiprocessing bus master is reading or writing its internal memory or IOP registers.
DATA47-0
I/O/T
O/T
External Bus Data. The ADSP-21062 inputs and outputs data and instructions on these pins. 32-bit
single-precision floating-point data and 32-bit fixed-point data is transferred over bits 47–16 of the
bus. 40-bit extended-precision floating-point data is transferred over bits 47–8 of the bus. 16-bit short
word data is transferred over bits 31–16 of the bus. In PROM boot mode, 8-bit data is transferred over
bits 23–16. Pull-up resistors on unused DATA pins are not necessary.
MS3-0
Memory Select Lines. These lines are asserted (low) as chip selects for the corresponding banks of
external memory. Memory bank size must be defined in the ADSP-21062’s system control register
(SYSCON). The MS3-0 lines are decoded memory address lines that change at the same time as the
other address lines. When no external memory access is occurring the MS3-0 lines are inactive; they are
active however when a conditional memory access instruction is executed, whether or not the condi-
tion is true. MS0 can be used with the PAGE signal to implement a bank of DRAM memory (Bank 0).
In a multiprocessing system the MS3-0 lines are output by the bus master.
RD
I/O/T
I/O/T
O/T
Memory Read Strobe. This pin is asserted (low) when the ADSP-21062 reads from external
memory devices or from the internal memory of other ADSP-21062s. External devices (including
other ADSP-21062s) must assert RD to read from the ADSP-21062’s internal memory. In a multipro-
cessing system RD is output by the bus master and is input by all other ADSP-21062s.
WR
Memory Write Strobe. This pin is asserted (low) when the ADSP-21062 writes to external memory
devices or to the internal memory of other ADSP-21062s. External devices must assert WR to write to
the ADSP-21062’s internal memory. In a multiprocessing system WR is output by the bus master and
is input by all other ADSP-21062s.
PAGE
DRAM Page Boundary. The ADSP-21062 asserts this pin to signal that an external DRAM page
boundary has been crossed. DRAM page size must be defined in the ADSP-21062’s memory control
register (WAIT). DRAM can only be implemented in external memory Bank 0; the PAGE signal can
only be activated for Bank 0 accesses. In a multiprocessing system PAGE is output by the bus master.
ADRCLK
O/T
Clock Output Reference. In a multiprocessing system ADRCLK is output by the bus master.
SW
I/O/T
Synchronous Write Select. This signal is used to interface the ADSP-21062 to synchronous
memory devices (including other ADSP-21062s). The ADSP-21062 asserts SW (low) to provide an
early indication of an impending write cycle, which can be aborted if WR is not later asserted (e.g., in
a conditional write instruction). In a multiprocessing system, SW is output by the bus master and is
input by all other ADSP-21062s to determine if the multiprocessor memory access is a read or write.
SW is asserted at the same time as the address output. A host processor using synchronous writes
must assert this pin when writing to the ADSP-21062(s).
ACK
I/O/S
Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external
memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off
completion of an external memory access. The ADSP-21062 deasserts ACK as an output to add wait
states to a synchronous access of its internal memory. In a multiprocessing system, a slave ADSP-
21062 deasserts the bus master’s ACK input to add wait state(s) to an access of its internal memory.
The bus master has a keeper latch on its ACK pin that maintains the input at the level to which it
was last driven.
REV. C
–8–
ADSP-21062/ADSP-21062L
Pin
Type
Function
SBTS
I/S
Suspend Bus Three-State. External devices can assert SBTS (low) to place the external bus address,
data, selects and strobes in a high impedance state for the following cycle. If the ADSP-21062
attempts to access external memory while SBTS is asserted, the processor will halt and the memory
access will not be completed until SBTS is deasserted. SBTS should only be used to recover from host
processor/ADSP-21062 deadlock, or used with a DRAM controller.
IRQ2-0
I/A
Interrupt Request Lines. May be either edge-triggered or level-sensitive.
FLAG3-0
I/O/A
Flag Pins. Each is configured via control bits as either an input or output. As an input, they can be
tested as a condition. As an output, they can be used to signal external peripherals.
TIMEXP
O
Timer Expired. Asserted for four cycles when the timer is enabled and TCOUNT decrements to
zero.
HBR
I/A
Host Bus Request. This pin must be asserted by a host processor to request control of the
ADSP-21062’s external bus. When HBR is asserted in a multiprocessing system, the ADSP-21062
that is bus master will relinquish the bus and assert HBG. To relinquish the bus, the ADSP-21062
places the address, data, select and strobe lines in a high impedance state. HBR has priority over all
ADSP-21062 bus requests (BR6-1) in a multiprocessing system.
HBG
CS
I/O
I/A
Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may take
control of the external bus. HBG is asserted (held low) by the ADSP-21062 until HBR is released. In
a multiprocessing system, HBG is output by the ADSP-21062 bus master and is monitored by all others.
Chip Select. Asserted by host processor to select the ADSP-21062.
REDY (O/D) O
Host Bus Acknowledge. The ADSP-21062 deasserts REDY (low) to add wait states to an asynchro-
nous access of its internal memory or IOP registers by a host. This pin is an open drain output (O/D)
by default; it can be programmed in the ADREDY bit of the SYSCON register to be active drive
(A/D). REDY will only be output if the CS and HBR inputs are asserted.
DMAR1
DMAR2
DMAG1
DMAG2
BR6-1
I/A
DMA Request 1 (DMA Channel 7).
DMA Request 2 (DMA Channel 8).
DMA Grant 1 (DMA Channel 7).
DMA Grant 2 (DMA Channel 8).
I/A
O/T
O/T
I/O/S
Multiprocessing Bus Requests. Used by multiprocessing ADSP-21062s to arbitrate for bus master-
ship. An ADSP-21062 only drives its own BRx line (corresponding to the value of its ID2-0 inputs) and
monitors all others. In a multiprocessor system with less than six ADSP-21062s, the unused BRx pins
should be pulled high; the processor’s own BRx line must not be pulled high or low because it is an
output.
ID2-0
I
Multiprocessing ID. Determines which multiprocessing bus request (BR1 – BR6) is used by ADSP-
21062. ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, etc. ID = 000 in single-processor
systems. These lines are a system configuration selection which should be hardwired or changed at
reset only.
RPBA
I/S
I/O
Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor
bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system con-
figuration selection which must be set to the same value on every ADSP-21062. If the value of RPBA is
changed during system operation, it must be changed in the same CLKIN cycle on every ADSP-21062.
CPA (O/D)
Core Priority Access. Asserting its CPA pin allows the core processor of an ADSP-21062 bus slave
to interrupt background DMA transfers and gain access to the external bus. CPA is an open drain
output that is connected to all ADSP-21062s in the system. The CPA pin has an internal 5 kΩ pull-up
resistor. If core access priority is not required in a system, the CPA pin should be left unconnected.
DTx
O
Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 kΩ internal pull-up resistor.
Data Receive (Serial Ports 0, 1). Each DR pin has a 50 kΩ internal pull-up resistor.
Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 kΩ internal pull-up resistor.
Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 kΩ internal pull-up resistor.
DRx
I
TCLKx
RCLKx
I/O
I/O
REV. C
–9–
ADSP-21062/ADSP-21062L
Pin
Type
I/O
Function
TFSx
Transmit Frame Sync (Serial Ports 0, 1).
Receive Frame Sync (Serial Ports 0, 1).
RFSx
I/O
LxDAT3-0
I/O
Link Port Data (Link Ports 0–5). Each LxDAT pin has a 50 kΩ internal pull-down resistor that is
enabled or disabled by the LPDRD bit of the LCOM register.
LxCLK
LxACK
EBOOT
I/O
I/O
I
Link Port Clock (Link Ports 0–5). Each LxCLK pin has a 50 kΩ internal pull-down resistor that is
enabled or disabled by the LPDRD bit of the LCOM register.
Link Port Acknowledge (Link Ports 0–5). Each LxACK pin has a 50 kΩ internal pull-down resistor
that is enabled or disabled by the LPDRD bit of the LCOM register.
EPROM Boot Select. When EBOOT is high, the ADSP-21062 is configured for booting from an 8-
bit EPROM. When EBOOT is low, the LBOOT and BMS inputs determine booting mode. See table
below. This signal is a system configuration selection that should be hardwired.
LBOOT
I
Link Boot. When LBOOT is high, the ADSP-21062 is configured for link port booting. When
LBOOT is low, the ADSP-21062 is configured for host processor booting or no booting. See table
below. This signal is a system configuration selection that should be hardwired.
BMS
I/O/T*
Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOT = 1,
LBOOT = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low, indi-
cates that no booting will occur and that ADSP-21062 will begin executing instructions from external
memory. See table below. This input is a system configuration selection that should be hardwired.
*Three-statable only in EPROM boot mode (when BMS is an output).
EBOOT
LBOOT
BMS
Booting Mode
1
0
0
0
0
1
0
0
1
0
1
1
Output
EPROM (Connect BMS to EPROM chip select.)
Host Processor
Link Port
No Booting. Processor executes from external memory.
Reserved
Reserved
1 (Input)
1 (Input)
0 (Input)
0 (Input)
x (Input)
CLKIN
I
Clock In. External clock input to the ADSP-21062. The instruction cycle rate is equal to CLKIN.
CLKIN may not be halted, changed, or operated below the minimum specified frequency.
RESET
I/A
Processor Reset. Resets the ADSP-21062 to a known state and begins program execution at the
program memory location specified by the hardware reset vector address. This input must be asserted
(low) at power-up.
TCK
TMS
I
Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan.
I/S
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ internal pull-up
resistor.
TDI
I/S
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kΩ internal
pull-up resistor.
TDO
O
Test Data Output (JTAG). Serial scan output of the boundary scan path.
TRST
I/A
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-
up or held low for proper operation of the ADSP-21062. TRST has a 20 kΩ internal pull-up resistor.
EMU
ICSA
VDD
GND
NC
O
O
P
Emulation Status. Must be connected to the ADSP-21062 EZ-ICE target board connector only.
Reserved, leave unconnected.
Power Supply; nominally +5.0 V dc for 5 V devices or +3.3 V dc for 3.3 V devices. (30 pins)
Power Supply Return. (30 pins)
G
Do Not Connect. Reserved pins which must be left open and unconnected.
REV. C
–10–
ADSP-21062/ADSP-21062L
The 14-pin, 2-row pin strip header is keyed at the Pin 3 location —
Pin 3 must be removed from the header. The pins must be
0.025 inch square and at least 0.20 inch in length. Pin spacing
should be 0.1 × 0.1 inches. Pin strip headers are available from
vendors such as 3M, McKenzie, and Samtec.
TARGET BOARD CONNECTOR FOR EZ-ICE PROBE
The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1
JTAG test access port of the ADSP-2106x to monitor and
control the target board processor during emulation. The EZ-
ICE probe requires the ADSP-2106x’s CLKIN, TMS, TCK,
TRST, TDI, TDO, EMU, and GND signals be made acces-
sible on the target system via a 14-pin connector (a 2 row × 7
pin strip header) such as that shown in Figure 5. The EZ-ICE
probe plugs directly onto this connector for chip-on-board
emulation. You must add this connector to your target board
design if you intend to use the ADSP-2106x EZ-ICE. The total
trace length between the EZ-ICE connector and the furthest
device sharing the EZ-ICE JTAG pin should be limited to 15
inches maximum for guaranteed operation. This length restric-
tion must include EZ-ICE JTAG signals that are routed to one
or more ADSP-2106x devices, or a combination of ADSP-
2106x devices and other JTAG devices on the chain.
The BTMS, BTCK, BTRST, and BTDI signals are provided so
that the test access port can also be used for board-level testing.
When the connector is not being used for emulation, place
jumpers between the BXXX pins and the XXX pins as shown in
Figure 5. If you are not going to use the test access port for
board testing, tie BTRST to GND and tie or pull up BTCK to
VDD. The TRST pin must be asserted after power-up (through
BTRST on the connector) or held low for proper operation of
the ADSP-2106x. None of the BXXX pins (Pins 5, 7, 9, 11) are
connected on the EZ-ICE probe.
The JTAG signals are terminated on the EZ-ICE probe as follows:
Signal Termination
1
3
5
2
4
6
TMS
TCK
Driven through 22 Ω Resistor (16 mA Driver)
Driven at 10 MHz through 22 Ω Resistor (16 mA
Driver)
EMU
GND
KEY (NO PIN)
CLKIN (OPTIONAL)
TMS
TRST* Active Low Driven through 22 Ω Resistor (16 mA
Driver) (Pulled Up by On-Chip 20 kΩ Resistor)
BTMS
TDI
TDO
Driven by 22 Ω Resistor (16 mA Driver)
7
9
8
One TTL Load, Split Termination (160/220)
TCK
BTCK
CLKIN One TTL Load, Split Termination (160/220)
EMU
10
12
Active Low 4.7 kΩ Pull-Up Resistor, One TTL Load
(Open-Drain Output from the DSP)
BTRST
TRST
11
*TRST is driven low until the EZ-ICE probe is turned on by the emulator at
software start-up. After software start-up, TRST is driven high.
BTDI
GND
TDI
13
14
TDO
TOP VIEW
Figure 5. Target Board Connector For ADSP-2106x
EZ-ICE Emulator (Jumpers in Place)
JTAG
ADSP-2106x
ADSP-2106x
#1
DEVICE
n
(OPTIONAL)
TDI
TDO
TDO
TDO
TDI
TDI
TDI
EZ-ICE
JTAG
CONNECTOR
OTHER
JTAG
CONTROLLER
TCK
TMS
EMU
TRST
TDO
CLKIN
OPTIONAL
Figure 6. JTAG Scan Path Connections for Multiple ADSP-2106x Systems
REV. C
–11–
ADSP-21062/ADSP-21062L
Figure 6 shows JTAG scan path connections for systems that
contain multiple ADSP-2106x processors.
EMU should be treated as critical signals in terms of skew,
and should be laid out as short as possible on your board. If
TCK, TMS, and CLKIN are driving a large number of ADSP-
21062s (more than eight) in your system, then treat them as a
“clock tree” using multiple drivers to minimize skew. (See
Figure 7 “JTAG Clock Tree” and “Clock Distribution” in the
“High Frequency Design Considerations” section of the ADSP-
2106x User’s Manual, Second Edition.)
Connecting CLKIN to Pin 4 of the EZ-ICE header is optional.
The emulator only uses CLKIN when directed to perform
operations such as starting, stopping, and single-stepping mul-
tiple ADSP-2106xs in a synchronous manner. If you do not need
these operations to occur synchronously on the multiple proces-
sors, simply tie Pin 4 of the EZ-ICE header to ground.
If synchronous multiprocessor operations are not needed (i.e.,
CLKIN is not connected), just use appropriate parallel termi-
nation on TCK and TMS. TDI, TDO, EMU and TRST are
not critical signals in terms of skew.
If synchronous multiprocessor operations are needed and
CLKIN is connected, clock skew between the multiple ADSP-
21062 processors and the CLKIN pin on the EZ-ICE header
must be minimal. If the skew is too large, synchronous operations
may be off by one or more cycles between processors. For syn-
chronous multiprocessor operation TCK, TMS, CLKIN and
For complete information on the SHARC EZ-ICE, see the
ADSP-21000 Family JTAG EZ-ICE User's Guide and Reference.
TDI
TDO
TDI
TDO
TDI
TDO
5k⍀
*
TDI
TDO
TDI
TDO
TDI
TDO
TDI
5k⍀
*
EMU
TCK
TMS
TRST
TDO
SYSTEM
CLKIN
CLKIN
EMU
*OPEN DRAIN DRIVER OR EQUIVALENT, i.e.,
Figure 7. JTAG Clocktree for Multiple ADSP-2106x Systems
REV. C
–12–
ADSP-21062/ADSP-21062L
ADSP-21062–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS (5 V)
A Grade
C Grade
K Grade
Parameter
Test Conditions Min Max
Min Max
Min Max
Units
VDD
Supply Voltage
4.75 5.25
4.75 5.25
4.75 5.25
V
TCASE Case Operating Temperature
–40
2.0
2.2
+85
–40
+100
VDD + 0.5
VDD + 0.5
0
2.0
2.2
+85
VDD + 0.5
VDD + 0.5
°C
VIH1
VIH2
VIL
High Level Input Voltage1
High Level Input Voltage2
Low Level Input Voltage1, 2
@ VDD = max
@ VDD = max
@ VDD = min
VDD + 0.5 2.0
VDD + 0.5 2.2
V
V
V
–0.5 0.8
–0.5 0.8
–0.5 0.8
NOTES
1Applies to input and bidirectional pins: DATA47-0, ADDR31-0, RD, WR, SW, ACK, SBTS, IRQ2-0, FLAG3-0, HBG, CS, DMAR1, DMAR2, BR6-1, ID2-0, RPBA,
CPA, TFS0, TFS1, RFS0, RFS1, LxDAT3-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1.
2Applies to input pins: CLKIN, RESET, TRST.
ELECTRICAL CHARACTERISTICS (5 V)
Parameter
Test Conditions
Min
Max
Units
VOH
VOL
IIH
IIL
IILP
IOZH
IOZL
IOZHP
IOZLC
IOZLA
IOZLAR
IOZLS
CIN
High Level Output Voltage1
Low Level Output Voltage1
High Level Input Current3, 4
Low Level Input Current3
@ VDD = min, IOH = –2.0 mA2
@ VDD = min, IOL = 4.0 mA2
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 1.5 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
4.1
V
V
0.4
10
10
150
10
10
350
1.5
350
4.2
150
4.7
µA
µA
µA
µA
µA
µA
mA
µA
mA
µA
pF
Low Level Input Current4
Three-State Leakage Current5, 6, 7, 8
Three-State Leakage Current5, 9
Three-State Leakage Current9
Three-State Leakage Current7
Three-State Leakage Current10
Three-State Leakage Current8
Three-State Leakage Current6
Input Capacitance11, 12
fIN = 1 MHz, TCASE = 25°C, VIN = 2.5 V
NOTES
11Applies to output and bidirectional pins: DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, TIMEXP, HBG, REDY, DMAG1,
DMAG2, BR6-1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3-0, LxCLK, LxACK, BMS, TDO, EMU, ICSA.
12See “Output Drive Currents” for typical drive current capabilities.
13Applies to input pins: ACK SBTS, IRQ2-0, HBR, CS, DMAR1, DMAR2, ID2-0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.
14Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI.
15Applies to three-statable pins: DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, REDY, HBG, DMAG1, DMAG2, BMS, BR6–1
,
TFSX, RFSX, TDO, EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID2-0 = 001 and another ADSP-21062 is
not requesting bus mastership.)
16Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.
17Applies to CPA pin.
18Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID2-0 = 001 and another
ADSP-21062L is not requesting bus mastership).
19Applies to three-statable pins with internal pull-downs: LxDAT3-0, LxCLK, LxACK.
10Applies to ACK pin when keeper latch enabled.
11Applies to all signal pins.
12Guaranteed but not tested.
Specifications subject to change without notice.
–13–
REV. C
ADSP-21062/ADSP-21062L
POWER DISSIPATION ADSP-21062 (5 V)
These specifications apply to the internal power portion of VDD only. See the Power Dissipation section of this data sheet for calcula-
tion of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation, see
the technical note “SHARC Power Dissipation Measurements.”
Specifications are based on the following operating scenarios:
Operation
Peak Activity (IDDINPEAK
)
High Activity (IDDINHIGH
)
Low Activity (IDDINLOW)
Instruction Type
Multifunction
Multifunction
Single Function
Instruction Fetch
Cache
Internal Memory
1 per Cycle (DM)
1 per 2 Cycles
Internal Memory
None
Core Memory Access
Internal Memory DMA
2 per Cycle (DM and PM)
1 per Cycle
1 per 2 Cycles
To estimate power consumption for a specific application, use the following equation where % is the amount of time your program
spends in that state:
%PEAK × IDDINPEAK + %HIGH × IDDINHIGH + %LOW × IDDINLOW + %IDLE × IDDIDLE = power consumption
Parameter
Test Conditions
Max
Units
IDDINPEAK
Supply Current (Internal)1
Supply Current (Internal)2
Supply Current (Internal)2
Supply Current (Idle)3
tCK = 30 ns, VDD = max
745
850
575
670
340
390
200
mA
mA
mA
mA
mA
mA
mA
t
CK = 25 ns, VDD = max
IDDINHIGH
IDDINLOW
tCK = 30 ns, VDD = max
tCK = 25 ns, VDD = max
tCK = 30 ns, VDD = max
t
CK = 25 ns, VDD = max
IDDIDLE
VDD = max
NOTES
1The test program used to measure IDDINPEAK represents worst case processor operation and is not sustainable under normal application conditions. Actual internal
power measurements made using typical applications are less than specified.
2IDDINHIGH is a composite average based on a range of high activity code. IDDINLOW is a composite average based on a range of low activity code.
3Idle denotes ADSP-21062L state during execution of IDLE instruction.
REV. C
–14–
ADSP-21062/ADSP-21062L
ADSP-21062L–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS (3.3 V)
A Grade
C Grade
K Grade
Parameter
Test Conditions Min Max
Min Max
Min Max
Units
VDD
Supply Voltage
3.15 3.45
3.15 3.45
3.15 3.45
V
TCASE Case Operating Temperature
–40
2.0
2.2
+85
–40
+100
VDD + 0.5
VDD + 0.5
0
2.0
2.2
–0.5 0.8
+85
VDD + 0.5
VDD + 0.5
°C
VIH1
VIH2
VIL
High Level Input Voltage1
High Level Input Voltage2
Low Level Input Voltage1, 2
@ VDD = max
@ VDD = max
@ VDD = min
VDD + 0.5 2.0
VDD + 0.5 2.2
V
V
V
–0.5 0.8
–0.5 0.8
NOTES
1Applies to input and bidirectional pins: DATA47-0, ADDR31-0, RD, WR, SW, ACK, SBTS, IRQ2-0, FLAG3-0, HBG, CS, DMAR1, DMAR2, BR6-1, ID2-0, RPBA,
CPA, TFS0, TFS1, RFS0, RFS1, LxDAT3-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1.
2Applies to input pins: CLKIN, RESET, TRST.
ELECTRICAL CHARACTERISTICS (3.3 V)
Parameter
Test Conditions
Min
Max
Units
VOH
VOL
IIH
IIL
IILP
IOZH
IOZL
IOZHP
IOZLC
IOZLA
IOZLAR
IOZLS
CIN
High Level Output Voltage1
Low Level Output Voltage1
High Level Input Current3, 4
Low Level Input Current3
@ VDD = min, IOH = –2.0 mA2
@ VDD = min, IOL = 4.0 mA2
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 1.5 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
2.4
V
V
0.4
10
10
150
10
µA
µA
µA
µA
µA
µA
mA
µA
mA
µA
pF
Low Level Input Current4
Three-State Leakage Current5, 6, 7, 8
Three-State Leakage Current5, 9
Three-State Leakage Current9
Three-State Leakage Current7
Three-State Leakage Current10
Three-State Leakage Current8
Three-State Leakage Current6
Input Capacitance11, 12
10
350
1.5
350
4.2
150
4.7
fIN = 1 MHz, TCASE = 25°C, VIN = 2.5 V
NOTES
11Applies to output and bidirectional pins: DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, TIMEXP, HBG, REDY, DMAG1,
DMAG2, BR6-1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3-0, LxCLK, LxACK, BMS, TDO, EMU, ICSA.
12See “Output Drive Currents” for typical drive current capabilities.
13Applies to input pins: ACK SBTS, IRQ2-0, HBR, CS, DMAR1, DMAR2, ID2-0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.
14Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI.
15Applies to three-statable pins: DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, REDY, HBG, DMAG1, DMAG2, BMS, BR6–1
,
TFSX, RFSX, TDO, EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID2-0 = 001 and another ADSP-21062 is
not requesting bus mastership.)
16Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.
17Applies to CPA pin.
18Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID2-0 = 001 and another
ADSP-21062L is not requesting bus mastership).
19Applies to three-statable pins with internal pull-downs: LxDAT3-0, LxCLK, LxACK.
10Applies to ACK pin when keeper latch enabled.
11Applies to all signal pins.
12Guaranteed but not tested.
Specifications subject to change without notice.
REV. C
–15–
ADSP-21062/ADSP-21062L
POWER DISSIPATION ADSP-21062L (3.3 V)
These specifications apply to the internal power portion of VDD only. See the Power Dissipation section of this data sheet for calcula-
tion of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation,
see the technical note “SHARC Power Dissipation Measurements.”
Specifications are based on the following operating scenarios:
Operation
Peak Activity (IDDINPEAK
)
High Activity (IDDINHIGH
)
Low Activity (IDDINLOW)
Instruction Type
Multifunction
Multifunction
Single Function
Instruction Fetch
Cache
Internal Memory
1 per Cycle (DM)
1 per 2 Cycles
Internal Memory
None
Core Memory Access
Internal Memory DMA
2 per Cycle (DM and PM)
1 per Cycle
1 per 2 Cycles
To estimate power consumption for a specific application, use the following equation where % is the amount of time your program
spends in that state:
%PEAK × IDDINPEAK + %HIGH × IDDINHIGH + %LOW × IDDINLOW + %IDLE × IDDIDLE = power consumption
Parameter
Test Conditions
Max
Units
IDDINPEAK
Supply Current (Internal)1
Supply Current (Internal)2
Supply Current (Internal)2
Supply Current (Idle)3
tCK = 30 ns, VDD = max
540
600
425
475
250
275
180
mA
mA
mA
mA
mA
mA
mA
t
CK = 25 ns, VDD = max
IDDINHIGH
IDDINLOW
tCK = 30 ns, VDD = max
tCK = 25 ns, VDD = max
tCK = 30 ns, VDD = max
t
CK = 25 ns, VDD = max
IDDIDLE
VDD = max
NOTES
1The test program used to measure IDDINPEAK represents worst case processor operation and is not sustainable under normal application conditions. Actual internal
power measurements made using typical applications are less than specified.
2IDDINHIGH is a composite average based on a range of high activity code. IDDINLOW is a composite average based on a range of low activity code.
3Idle denotes ADSP-21062L state during execution of IDLE instruction.
REV. C
–16–
ADSP-21062/ADSP-21062L
ABSOLUTE MAXIMUM RATINGS (5 V DEVICE)*
ABSOLUTE MAXIMUM RATINGS (3.3 V DEVICE)*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . 130°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . +280°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . 130°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . +280°C
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only; functional operation of the device at these or
any other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only; functional operation of the device at these or
any other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-21062 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
TIMING SPECIFICATIONS
GENERAL NOTES
Switching Characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Two speed grades of the ADSP-21062 will be offered, 40 MHz
and 33.3 MHz. The specifications shown are based on a
CLKIN frequency of 40 MHz (tCK = 25 ns). The DT derating
allows specifications at other CLKIN frequencies (within the
min–max range of the tCK specification; see Clock Input below).
DT is the difference between the actual CLKIN period and a
CLKIN period of 25 ns:
DT = tCK – 25 ns
Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the proces-
sor operates correctly with other devices.
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add parameters to derive longer times.
(O/D) = Open Drain
(A/D) = Active Drive
For voltage reference levels, see Figure 27 under Test Conditions.
REV. C
–17–
ADSP-21062/ADSP-21062L
ADSP-21062
40 MHz 33 MHz
ADSP-21062L
40 MHz 33 MHz
Min Max Units
Parameter
Min
Max
Min
Max
Min
Max
Clock Input
Timing Requirements:
tCK
CLKIN Period
25
7
5
100
3
30
7
5
100
3
25
8.75
5
100
3
30
8.75
5
100
3
ns
ns
ns
ns
tCKL
tCKH
tCKRF
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V–2.0 V)
tCK
CLKIN
tCKH
tCKL
Figure 8. Clock Input
ADSP-21062
ADSP-21062L
Min Max
Parameter
Reset
Min
Max
Units
Timing Requirements:
tWRST
RESET Pulsewidth Low1
tSRST
RESET Setup Before CLKIN High2
4tCK
14 + DT/2
4tCK
14 + DT/2 tCK
ns
ns
tCK
NOTES
1Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET
is low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).
2Only required if multiple ADSP-21062s must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required
for multiple ADSP-21062s communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically after reset.
CLKIN
tSRST
tWRST
RESET
Figure 9. Reset
ADSP-21062
ADSP-21062L
Parameter
Min
Max
Min
Max
Units
Interrupts
Timing Requirements:
tSIR
tHIR
tIPW
IRQ2-0 Setup Before CLKIN High1
18 + 3DT/4
2 + tCK
18 + 3DT/4
2 + tCK
ns
ns
ns
IRQ2-0 Hold Before CLKIN High1
IRQ2-0 Pulsewidth2
12 + 3DT/4
12 + 3DT/4
NOTES
1Only required for IRQx recognition in the following cycle.
2Applies only if tSIR and tHIR requirements are not met.
CLKIN
IRQ2-0
tSIR
tHIR
tIPW
Figure 10. Interrupts
REV. C
–18–
ADSP-21062/ADSP-21062L
ADSP-21062
ADSP-21062L
Parameter
Min
Max
Min
Max
Units
Timer
Switching Characteristic:
tDTEX
CLKIN High to TIMEXP
15
15
ns
CLKIN
tDTEX
tDTEX
TIMEXP
Figure 11. Timer
ADSP-21062
Parameter
Flags
Min
Max
Units
Timing Requirements:
tSFI
tHFI
tDWRFI
FLAG3-0IN Setup Before CLKIN High1
FLAG3-0IN Hold After CLKIN High1
FLAG3-0IN Delay After RD/WR Low1
FLAG3-0IN Hold After RD/WR Deasserted1
8 + 5DT/16
0 – 5DT/16
8 + 5DT/16
0 – 5DT/16
ns
ns
ns
ns
5 + 7DT/16
5 + 7DT/16
tHFIWR
0
0
Switching Characteristics:
tDFO
FLAG3-0OUT Delay After CLKIN High
16
14
16
14
ns
ns
ns
ns
tHFO
tDFOE
tDFOD
FLAG3-0OUT Hold After CLKIN High
CLKIN High to FLAG3-0OUT Enable
CLKIN High to FLAG3-0OUT Disable
4
3
4
3
NOTE
1Flag inputs meeting these setup and hold times will affect conditional instructions in the following instruction cycle.
CLKIN
tDFOE
tDFO
tDFO
tDFOD
tHFO
FLAG3-0
OUT
FLAG OUTPUT
CLKIN
tHFI
tSFI
FLAG3-0
IN
tHFIWR
tDWRFI
RD, WR
FLAG INPUT
Figure 12. Flags
REV. C
–19–
ADSP-21062/ADSP-21062L
Memory Read—Bus Master
characteristics also apply for bus master synchronous read/write
timing (see Synchronous Read/Write – Bus Master below). If
these timing requirements are met, the synchronous read/write
timing can be ignored (and vice versa).
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21062 is
the bus master accessing external memory space. These switching
ADSP-21062
ADSP-21062L
Max
Parameter
Min
Max
Min
Units
Timing Requirements:
tDAD
tDRLD
tHDA
Address, Selects Delay to Data Valid1, 4
18 + DT + W
12 + 5DT/8 + W
18 + DT + W
12 + 5DT/8 + W ns
ns
RD Low to Data Valid1
Data Hold from Address, Selects2
Data Hold from RD High2
0.5
2.0
0.5
2.0
ns
ns
tHDRH
tDAAK
tDSAK
ACK Delay from Address, Selects3, 4
ACK Delay from RD Low3
14 + 7DT/8 + W
8 + DT/2 + W
14 + 7DT/8 + W ns
8 + DT/2 + W
ns
Switching Characteristics:
tDRHA
tDARL
tRW
Address, Selects Hold After RD High
0 + H
2 + 3DT/8
12.5 + 5DT/8 + W
8 + 3DT/8 + HI
0 + H
2 + 3DT/8
12.5 + 5DT/8 + W
8 + 3DT/8 + HI
ns
ns
ns
ns
Address, Selects to RD Low4
RD Pulsewidth
tRWR
RD High to WR, RD, DMAGx Low
tSADADC Address, Selects Setup Before
ADRCLK High4
0 + DT/4
0 + DT/4
ns
W = (number of wait states specified in WAIT register) × tCK.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
NOTES
1Data Delay/Setup: User must meet tDAD or tDRLD or synchronous spec tSSDATI
.
2Data Hold: User must meet tHDA or tHDRH or synchronous spec tHSDATI. See System Hold Time Calculation under Test Conditions for the calculation of hold times
given capacitive and dc loads.
3ACK Delay/Setup: User must meet tDAAK or tDSAK or synchronous specification tSACKC for deassertion of ACK (Low), all three specifications must be met for asser-
tion of ACK (High).
4The falling edge of MSx, SW, BMS is referenced.
ADDRESS
MSx, SW
BMS
tDRHA
tDARL
tRW
RD
tHDA
tHDRH
tDRLD
tDAD
DATA
tDSAK
tRWR
tDAAK
ACK
WR, DMAG
tSADADC
ADRCLK
(OUT)
Figure 13. Memory Read—Bus Master
REV. C
–20–
ADSP-21062/ADSP-21062L
Memory Write—Bus Master
characteristics also apply for bus master synchronous read/write
timing (see Synchronous Read/Write–Bus Master). If these
timing requirements are met, the synchronous read/write timing
can be ignored (and vice versa).
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21062 is
the bus master accessing external memory space. These switching
ADSP-21062
ADSP-21062L
Max
Parameter
Min
Max
Min
Units
Timing Requirements:
tDAAK
tDSAK
ACK Delay from Address, Selects1, 2
14 + 7DT/8 + W
8 + DT/2 + W
14 + 7DT/8 + W ns
ACK Delay from WR Low1
8 + DT/2 + W
ns
Switching Characteristics:
tDAWH
tDAWL
tWW
tDDWH
tDWHA
Address, Selects to WR Deasserted2
17 + 15DT/16 + W
3 + 3DT/8
17 + 15DT/16 + W
3 + 3DT/8
ns
ns
ns
ns
ns
Address, Selects to WR Low2
WR Pulsewidth
12 + 9DT/16 + W
7 + DT/2 + W
0.5 + DT/16 + H
1 + DT/16 + H
8 + 7DT/16 + H
5 + 3DT/8 + I
–1 + DT/16
12 + 9DT/16 + W
7 + DT/2 + W
0.5 + DT/16 + H
1 + DT/16 + H
8 + 7DT/16 + H
5 + 3DT/8 + I
–1 + DT/16
Data Setup Before WR High
Address Hold After WR Deasserted
tDATRWH Data Disable After WR Deasserted3
6 + DT/16 + H
6 + DT/16 + H ns
tWWR
tDDWR
tWDE
WR High to WR, RD, DMAGx Low
Data Disable Before WR or RD Low
WR Low to Data Enabled
ns
ns
ns
ns
tSADADC Address, Selects to ADRCLK High2
0 + DT/4
0 + DT/4
W = (number of wait states specified in WAIT register) × tCK
.
H = tCK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
I = tCK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
NOTES
1ACK Delay/Setup: User must meet tDAAK or tDSAK or synchronous specification tSACKC for deassertion of ACK (Low), all three specifications must be met for asser-
tion of ACK (High).
2The falling edge of MSx, SW, BMS is referenced.
3See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
ADDRESS
MSx , SW
BMS
tDWHA
tDAWH
tWW
tDAWL
WR
tWWR
tDDWR
tDDWH
tWDE
tDATRWH
DATA
tDSAK
tDAAK
ACK
RD , DMAG
tSADADC
ADRCLK
(OUT)
Figure 14. Memory Write—Bus Master
REV. C
–21–
ADSP-21062/ADSP-21062L
Synchronous Read/Write—Bus Master
When accessing a slave ADSP-21062, these switching character-
istics must meet the slave’s timing requirements for synchronous
read/writes (see Synchronous Read/Write—Bus Slave). The
slave ADSP-21062 must also meet these (bus master) timing
requirements for data and acknowledge setup and hold times.
Use these specifications for interfacing to external memory
systems that require CLKIN—relative timing or for accessing a
slave ADSP-21062 (in multiprocessor memory space). These
synchronous switching characteristics are also valid during asyn-
chronous memory reads and writes (see Memory Read—Bus
Master and Memory Write—Bus Master).
ADSP-21062
ADSP-21062L
Parameter
Min
Max
Min
Max
Units
Timing Requirements:
tSSDATI Data Setup Before CLKIN
tHSDATI Data Hold After CLKIN
3 + DT/8
3.5 – DT/8
3 + DT/8
3.5 – DT/8
ns
ns
tDAAK
ACK Delay After Address, MSx,
SW, BMS1, 2
14 + 7 DT/8 + W
14 + 7 DT/8 + W
ns
ns
ns
tSACKC ACK Setup Before CLKIN2
tHACK
6.5 + DT/4
–1 – DT/4
6.5 + DT/4
–1 – DT/4
ACK Hold After CLKIN
Switching Characteristics:
tDADRO Address, MSx, BMS, SW Delay
After CLKIN1
7 – DT/8
7 – DT/8
ns
tHADRO Address, MSx, BMS, SW Hold
After CLKIN
–1 – DT/8
9 + DT/8
–2 – DT/8
–3 – 3DT/16 4 – 3DT/16
8 + DT/4
–1 – DT/8
9 + DT/8
–2 – DT/8
–3 – 3DT/16 4 – 3DT/16
8 + DT/4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDPGC
tDRDO
PAGE Delay After CLKIN
RD High Delay After CLKIN
16 + DT/8
4 – DT/8
16 + DT/8
4 – DT/8
tDWRO WR High Delay After CLKIN
tDRWL RD/WR Low Delay After CLKIN
tSDDATO Data Delay After CLKIN
tDATTR Data Disable After CLKIN3
tDADCCK ADRCLK Delay After CLKIN
tADRCK ADRCLK Period
12.5 + DT/4
19 + 5DT/16
7 – DT/8
12.5 + DT/4
19 + 5DT/16
7 – DT/8
0 – DT/8
4 + DT/8
tCK
(tCK/2 – 2)
(tCK/2 – 2)
0 – DT/8
4 + DT/8
tCK
(tCK/2 – 2)
(tCK/2 – 2)
10 + DT/8
10 + DT/8
tADRCKH ADRCLK Width High
tADRCKL ADRCLK Width Low
W = (number of Wait states specified in WAIT register) × tCK
.
NOTES
1The falling edge of MSx, SW, BMS is referenced.
2ACK Delay/Setup: User must meet tDAAK or tDSAK or synchronous specification tSACKC for deassertion of ACK (Low), all three specifications must be met for assertion
of ACK (High).
3See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
REV. C
–22–
ADSP-21062/ADSP-21062L
CLKIN
tADRCK
tADRCKL
tADRCKH
tDADCCK
ADRCLK
tHADRO
tDAAK
tDADRO
ADDRESS
MSx, SW
tDPGC
PAGE
tHACK
tSACKC
ACK
(IN)
READ CYCLE
tDRWL
tDRDO
RD
tHSDATI
tSSDATI
DATA
(IN)
WRITE CYCLE
tDWRO
tDRWL
WR
tDATTR
tSDDATO
DATA
(OUT)
Figure 15. Synchronous Read/Write—Bus Master
REV. C
–23–
ADSP-21062/ADSP-21062L
Synchronous Read/Write—Bus Slave
memory space). The bus master must meet these (bus slave)
timing requirements.
Use these specifications for ADSP-21062 bus master accesses of
a slave’s IOP registers or internal memory (in multiprocessor
ADSP-21062
ADSP-21062L
Parameter
Min
Max
Min
Max
Units
Timing Requirements:
tSADRI
tHADRI
tSRWLI
tHRWLI
tRWHPI
tSDATWH
tHDATWH
Address, SW Setup Before CLKIN
15 + DT/2
15 + DT/2
ns
ns
ns
ns
ns
ns
ns
Address, SW Hold Before CLKIN
RD/WR Low Setup Before CLKIN1
RD/WR Low Hold After CLKIN
RD/WR Pulse High
5 + DT/2
5 + DT/2
9.5 + 5DT/16
–4 – 5DT/16
3
5
1
9.5 + 5DT/16
–4 – 5DT/16
3
5
1
8 + 7DT/16
8 + 7DT/16
Data Setup Before WR High
Data Hold After WR High
Switching Characteristics:
tSDDATO
tDATTR
tDACKAD
tACKTR
Data Delay After CLKIN
19 + 5DT/16
7 – DT/8
9
19 + 5DT/16 ns
Data Disable After CLKIN2
ACK Delay After Address, SW3
ACK Disable After CLKIN3
0 – DT/8
0 – DT/8
7 – DT/8
9
ns
ns
ns
–1 – DT/8
6 – DT/8
–1 – DT/8
6 – DT/8
NOTES
1tSRWLI (min) = 9.5 + 5DT/16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, t SRWLI (min)
= 4 + DT/8.
2See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
3tDACKAD is true only if the address and SW inputs have setup times (before CLKIN) greater than 10 + DT/8 and less than 19 + 3DT/4. If the address and SW inputs have
setup times greater than 19 + 3DT/4, then ACK is valid 14 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK
regardless of the state of MMSWS or strobes. A slave will three-state ACK every cycle with tACKTR
.
REV. C
–24–
ADSP-21062/ADSP-21062L
CLKIN
tSADRI
tHADRI
ADDRESS
SW
tDACKAD
tACKTR
ACK
READ ACCESS
tSRWLI
tHRWLI
tRWHPI
RD
tSDDATO
tDATTR
DATA
(OUT)
WRITE ACCESS
tRWHPI
tSRWLI
tHRWLI
WR
tHDATWH
tSDATWH
DATA
(IN)
Figure 16. Synchronous Read/Write—Bus Slave
REV. C
–25–
ADSP-21062/ADSP-21062L
Multiprocessor Bus Request and Host Bus Request
Use these specifications for passing of bus mastership between
multiprocessing ADSP-21062s (BRx) or a host processor
(HBR, HBG).
ADSP-21062
Max
ADSP-21062L
Max
Parameter
Min
Min
Units
Timing Requirements:
tHBGRCSV
tSHBRI
tHHBRI
tSHBGI
tHHBGI
tSBRI
HBG Low to RD/WR/CS Valid1
20 + 5DT/4
14 + 3DT/4
6 + DT/2
20 + 5DT/4
14 + 3DT/4
6 + DT/2
ns
ns
ns
ns
ns
ns
ns
ns
ns
HBR Setup Before CLKIN2
20 + 3DT/4
13 + DT/2
13 + DT/2
21 + 3DT/4
20 + 3DT/4
13 + DT/2
13 + DT/2
21 + 3DT/4
HBR Hold Before CLKIN2
HBG Setup Before CLKIN
HBG Hold Before CLKIN High
BRx, CPA Setup Before CLKIN3
BRx, CPA Hold Before CLKIN High
RPBA Setup Before CLKIN
RPBA Hold Before CLKIN
tHBRI
tSRPBAI
tHRPBAI
6 + DT/2
6 + DT/2
12 + 3DT/4
12 + 3DT/4
Switching Characteristics:
tDHBGO
tHHBGO
tDBRO
HBG Delay After CLKIN
7 – DT/8
7 – DT/8
7 – DT/8
7 – DT/8
ns
ns
ns
ns
ns
ns
HBG Hold After CLKIN
BRx Delay After CLKIN
BRx Hold After CLKIN
CPA Low Delay After CLKIN
CPA Disable After CLKIN
REDY (O/D) or (A/D) Low from CS
and HBR Low4
–2 – DT/8
–2 – DT/8
–2 – DT/8
–2 – DT/8
–2 – DT/8
–2 – DT/8
tHBRO
tDCPAO
tTRCPA
tDRDYCS
8 – DT/8
4.5 – DT/8
8 – DT/8
4.5 – DT/8
8.5
10
8.75
10
ns
ns
ns
tTRDYHG
tARDYTR
REDY (O/D) Disable or REDY (A/D)
High from HBG4
44 + 23DT/16
44 + 23DT/16
REDY (A/D) Disable from CS or
HBR High4
NOTES
1For first asynchronous access after HBR and CS asserted, ADDR31-0 must be a non-MMS value 1/2 tCK before RD or WR goes low or by tHBGRCSV after HBG goes
low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the ADSP-21062” section in the
ADSP-21062 SHARC User’s Manual, Second Edition.
2Only required for recognition in the current cycle.
3CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.
4(O/D) = open drain, (A/D) = active drive.
REV. C
–26–
ADSP-21062/ADSP-21062L
CLKIN
tSHBRI
tHHBRI
HBR
tDHBGO
tHHBGO
HBG
(OUT)
tDBRO
tHBRO
BRx
(OUT)
tTRCPA
tDCPAO
CPA (OUT)
(O/D)
tSHBGI
tHHBGI
HBG (IN)
tSBRI
tHBRI
BRx (IN)
CPA (IN) (O/D)
tSRPBAI
tHRPBAI
RPBA
HBR AND CS
tTRDYHG
tDRDYCS
REDY (O/D)
tARDYTR
REDY (A/D)
tHBGRCSV
HBG (OUT)
RD
WR
CS
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 17. Multiprocessor Bus Request and Host Bus Request
REV. C
–27–
ADSP-21062/ADSP-21062L
Asynchronous Read/Write—Host to ADSP-21062
drive the RD and WR pins to access the ADSP-21062’s internal
memory or IOP registers. HBR and HBG are assumed low for
this timing.
Use these specifications for asynchronous host processor accesses
of an ADSP-21062, after the host has asserted CS and HBR
(low). After HBG is returned by the ADSP-21062, the host can
ADSP-21062
Max
ADSP-21062L
Max
Parameter
Min
Min
Units
Read Cycle
Timing Requirements:
tSADRDL
tHADRDH
tWRWH
tDRDHRDY
tDRDHRDY
Address Setup/CS Low Before RD Low1
Address Hold/CS Hold Low After RD
RD/WR High Width
RD High Delay After REDY (O/D) Disable
RD High Delay After REDY (A/D) Disable
0
0
6
0
0
0
0
6
0
0
ns
ns
ns
ns
ns
Switching Characteristics:
tSDATRDY
tDRDYRDL
tRDYPRD
Data Valid Before REDY Disable from Low
2
2
ns
ns
REDY (O/D) or (A/D) Low Delay After RD Low
REDY (O/D) or (A/D) Low Pulse
Width for Read
10
8
10
8
45 + 21DT/16
2
45 + 21DT/16
2
ns
ns
tHDARWH
Data Disable After RD High
Write Cycle
Timing Requirements:
tSCSWRL
tHCSWRH
tSADWRH
tHADWRH
tWWRL
CS Low Setup Before WR low
0
0
5
2
7
6
0
0
5
2
7
6
ns
ns
ns
ns
ns
ns
CS Low Hold After WR high
Address Setup Before WR High
Address Hold After WR High
WR Low Width
tWRWH
RD/WR High Width
tDWRHRDY
WR High Delay After REDY
(O/D) or (A/D) Disable
0
5
1
0
5
1
ns
ns
ns
tSDATWH
tHDATWH
Data Setup Before WR High
Data Hold After WR High
Switching Characteristics:
tDRDYWRL REDY (O/D) or (A/D) Low Delay
After WR/CS Low
REDY (O/D) or (A/D) Low Pulse
Width for Write
10
10
ns
ns
tRDYPWR
15 + 7DT/16
1 + 7DT/16
15 + 7DT/16
tSRDYCK
REDY (O/D) or (A/D) Disable to CLKIN
8 + 7DT/16 1 + 7DT/16
8 + 7DT/16 ns
NOTE
1Not required if RD and address are valid tHBGRCSV after HBG goes low. For first access after HBR asserted, ADDR31-0 must be a non-MMS value 1/2 tCLK before RD
or WR goes low or by tHBGRCSV after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Proces-
sor Control of the ADSP-21062” section in the ADSP-21062 SHARC User’s Manual, Second Edition.
CLKIN
tSRDYCK
REDY (O/D)
REDY (A/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 18a. Synchronous REDY Timing
REV. C
–28–
ADSP-21062/ADSP-21062L
READ CYCLE
ADDRESS/CS
tHADRDH
tSADRDL
tWRWH
RD
tHDARWH
DATA (OUT)
tDRDHRDY
tSDATRDY
tRDYPRD
tDRDYRDL
REDY (O/D)
REDY (A/D)
WRITE CYCLE
ADDRESS
tHADWRH
tSADWRH
tHCSWRH
tSCSWRL
CS
tWWRL
tWRWH
WR
tHDATWH
tSDATWH
DATA (IN)
tDWRHRDY
tDRDYWRL
tRDYPWR
REDY (O/D)
REDY (A/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 18b. Asynchronous Read/Write—Host to ADSP-21062
REV. C
–29–
ADSP-21062/ADSP-21062L
Three-State Timing—Bus Master, Bus Slave, HBR, SBTS
These specifications show how the memory interface is disabled
(stops driving) or enabled (resumes driving) relative to CLKIN
and the SBTS pin. This timing is applicable to bus master tran-
sition cycles (BTC) and host transition cycles (HTC) as well as
the SBTS pin.
ADSP-21062
ADSP-21062L
Parameter
Min
Max
Min
Max
Units
Timing Requirements:
tSTSCK
tHTSCK
SBTS Setup Before CLKIN
SBTS Hold Before CLKIN
12 + DT/2
12 + DT/2
ns
ns
6 + DT/2
6 + DT/2
Switching Characteristics:
tMIENA Address/Select Enable After CLKIN
tMIENS
Strobes Enable After CLKIN1
tMIENHG HBG Enable After CLKIN
tMITRA Address/Select Disable After CLKIN
tMITRS
Strobes Disable After CLKIN1
tMITRHG HBG Disable After CLKIN
tDATEN
tDATTR
tACKEN
tACKTR
tADCEN
tADCTR
–1 – DT/8
–1.5 – DT/8
–1.5 – DT/8
–1.25 – DT/8
–1.5 – DT/8
–1.5 – DT/8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0 – DT/4
1.5 – DT/4
2.0 – DT/4
0 – DT/4
1.5 – DT/4
2.0 – DT/4
Data Enable After CLKIN2
Data Disable After CLKIN2
ACK Enable After CLKIN2
ACK Disable After CLKIN2
ADRCLK Enable After CLKIN
ADRCLK Disable After CLKIN
9 + 5DT/16
0 – DT/8
7.5 + DT/4
–1 – DT/8
–2 – DT/8
9 + 5DT/16
–0.5 – DT/8
7.5 + DT/4
–1 – DT/8
–2 – DT/8
7 – DT/8
6 – DT/8
8 – DT/4
7 – DT/8
6 – DT/8
8 – DT/4
tMTRHBG Memory Interface Disable Before
HBG Low3
tMENHBG Memory Interface Enable After
HBG High3
0 + DT/8
19 + DT
0 + DT/8
19 + DT
ns
ns
NOTES
1Strobes = RD, WR, SW, PAGE, DMAG.
2In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
3Memory Interface = Address, RD, WR, MSx, SW, PAGE, DMAGx, BMS (in EPROM boot mode).
CLKIN
tSTSCK
tHTSCK
SBTS
tMITRA, tMITRS, tMITRHG
tMIENA, tMIENS, tMIENHG
MEMORY
INTERFACE
tDATTR
tDATEN
DATA
tACKTR
tACKEN
ACK
tADCEN
tADCTR
ADRCLK
Figure 19a. Three-State Timing (Bus Transition Cycle, SBTS Assertion)
HBG
tMTRHBG
tMENHBG
MEMORY
INTERFACE
MEMORY INTERFACE = ADDRESS, RD, WR, MSx, SW, PAGE, DMAGx. BMS (IN EPROM BOOT MODE)
Figure 19b. Three-State Timing (Host Transition Cycle)
REV. C
–30–
ADSP-21062/ADSP-21062L
DMA Handshake
transfer is controlled by ADDR31-0, RD, WR, MS3-0, and ACK
(not DMAG). For Paced Master mode, the Memory Read–Bus
Master, Memory Write–Bus Master, and Synchronous Read/
Write–Bus Master timing specifications for ADDR31-0, RD, WR,
MS3-0, SW, PAGE, DATA47-0, and ACK also apply.
These specifications describe the three DMA handshake modes.
In all three modes DMAR is used to initiate transfers. For hand-
shake mode, DMAG controls the latching or enabling of data
externally. For external handshake mode, the data transfer is
controlled by the ADDR31-0, RD, WR, SW, PAGE, MS3-0
,
ACK, and DMAG signals. For Paced Master mode, the data
ADSP-21062
ADSP-21062L
Max
Parameter
Min
Max
Min
Units
Timing Requirements:
tSDRLC
tSDRHC
tWDR
DMARx Low Setup Before CLKIN1
5
5
5
5
ns
ns
DMARx High Setup Before CLKIN1
DMARx Width Low
(Nonsynchronous)
6
2
6
2
ns
ns
ns
ns
ns
ns
tSDATDGL Data Setup After DMAGx Low2
tHDATIDG Data Hold After DMAGx High
tDATDRH Data Valid After DMARx High2
tDMARLL DMARx Low Edge to Low Edge
10 + 5DT/8
16 + 7DT/8
10 + 5DT/8
16 + 7DT/8
23 + 7DT/8
6
23 + 7DT/8
6
tDMARH
DMARx Width High
Switching Characteristics:
tDDGL
tWDGH
tWDGL
tHDGC
DMAGx Low Delay After CLKIN
DMAGx High Width
DMAGx Low Width
9 + DT/4
6 + 3DT/8
12 + 5DT/8
–2 – DT/8
8 + 9DT/16
0
15 + DT/4
6 – DT/8
9 + DT/4
6 + 3DT/8
12 + 5DT/8
–2 – DT/8
8 + 9DT/16
0
15 + DT/4
6 – DT/8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DMAGx High Delay After CLKIN
tVDATDGH Data Valid Before DMAGx High3
tDATRDGH Data Disable After DMAGx High4
7
2
7
2
tDGWRL
tDGWRH
tDGWRR
tDGRDL
tDRDGH
tDGRDR
tDGWR
WR Low Before DMAGx Low
DMAGx Low Before WR High
WR High Before DMAGx High
RD Low Before DMAGx Low
RD Low Before DMAGx High
RD High Before DMAGx High
DMAGx High to WR, RD, DMAGx
Low
–0.25
–0.25
10 + 5DT/8 + W
1 + DT/16
0
11 + 9DT/16 + W
0
10 + 5DT/8 + W
1 + DT/16
0
11 + 9DT/16 + W
0
3 + DT/16
2
3 + DT/16
2
3
3
5 + 3DT/8 + HI
5 + 3DT/8 + HI
17 + DT
ns
ns
tDADGH
tDDGHA
Address/Select Valid to DMAGx High 17 + DT
Address/Select Hold after DMAGx
High
–0.5
–1
ns
W = (number of wait states specified in WAIT register) × tCK
.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
NOTES
1Only required for recognition in the current cycle.
2tSDATDGL is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the
data can be driven tDATDRH after DMARx is brought high.
3tVDATDGH is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then tVDATDGH = 8 + 9DT/16 + (n × tCK) where
n equals the number of extra cycles that the access is prolonged.
4See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
REV. C
–31–
ADSP-21062/ADSP-21062L
CLKIN
tSDRLC
tDMARLL
tSDRHC
tWDR
tDMARH
DMARx
DMAGx
tHDGC
tDDGL
tWDGL
tWDGH
TRANSFERS BETWEEN ADSP-2106x INTERNAL MEMORY AND EXTERNAL DEVICE
tDATRDGH
tVDATDGH
DATA (FROM
ADSP-2106x TO
EXTERNAL DRIVE)
tDATDRH
tHDATIDG
tSDATDGL
DATA (FROM
EXTERNAL DRIVE
TO ADSP-2106x)
TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE)
tDGWRL
WR
tDGWRH
tDGWRR
(EXTERNAL DEVICE
TO EXTERNAL
MEMORY)
tDGRDR
tDGRDL
RD
(EXTERNAL
MEMORY TO
EXTERNAL DEVICE)
tDRDGH
tDADGH
tDDGHA
ADDRESS
MSx, SW
*
MEMORY READ – BUS MASTER, MEMORY WRITE – BUS MASTER, AND SYNCHRONOUS READ/WRITE – BUS MASTER
TIMING SPECIFICATIONS FOR ADDR
, RD, WR, SW, MS AND ACK ALSO APPLY HERE.
31-0
3-0
Figure 20. DMA Handshake Timing
REV. C
–32–
ADSP-21062/ADSP-21062L
Link Ports: 1
؋
CLK Speed Operation ADSP-21062
Max
ADSP-21062L
Parameter
Min
Min
Max
Units
Receive
Timing Requirements:
tSLDCL
tHLDCL
tLCLKIW
Data Setup Before LCLK Low
Data Hold After LCLK Low
LCLK Period (1 × Operation)
3
3
tCK
6
5
3
3
tCK
6
5
ns
ns
ns
ns
ns
tLCLKRWL LCLK Width Low
tLCLKRWH LCLK Width High
Switching Characteristics:
tDLAHC
tDLALC
tENDLK
tTDLK
LACK High Delay After CLKIN High
18 + DT/2
–3
5 + DT/2
28.5 + DT/2
13
18 + DT/2
–3
5 + DT/2
28.5 + DT/2
13
ns
ns
ns
ns
LACK Low Delay After LCLK High1
LACK Enable from CLKIN
LACK Disable from CLKIN
20 + DT/2
20 + DT/2
Transmit
Timing Requirements:
tSLACH LACK Setup Before LCLK High
tHLACH LACK Hold After LCLK High
18
–7
18
–7
ns
ns
Switching Characteristics:
tDLCLK
tDLDCH
tHLDCH
LCLK Delay After CLKIN (1 × operation)
Data Delay After LCLK High
Data Hold After LCLK High
15.5
2.5
15.5
2.5
ns
ns
ns
ns
ns
–3
–3
tLCLKTWL LCLK Width Low
tLCLKTWH LCLK Width High
(tCK/2) – 1
(tCK/2) + 1.25 (tCK/2) – 1
(tCK/2) – 1.5
(tCK/2) + 1.5
(tCK/2) + 1
(tCK/2) – 1.25 (tCK/2) + 1
tDLACLK
tENDLK
tTDLK
LCLK Low Delay After LACK High
LDAT, LCLK Enable After CLKIN
LDAT, LCLK Disable After CLKIN
(tCK/2) + 8.75 (3 × tCK/2) + 17 (tCK/2) + 8
(3 × tCK/2) + 17 ns
5 + DT/2
5 + DT/2
ns
20 + DT/2
20 + DT/2
ns
Link Port Service Request Interrupts: 1 × and
2 × Speed Operations
Timing Requirements:
tSLCK
tHLCK
LACK/LCLK Setup Before CLKIN Low2 10
10
2
ns
ns
LACK/LCLK Hold After CLKIN Low2
2
NOTES
1LACK will go low with tDLALC relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.
2Only required for interrupt recognition in the current cycle.
REV. C
–33–
ADSP-21062/ADSP-21062L
Link Ports: 2
؋
CLK Speed Operation from 2 × speed specifications will result in unrealistically small
skew times because they include multiple tester guardbands. The
setup and hold skew times shown below are calculated to include
only one tester guardband.
Calculation of link receiver data setup and hold relative to link
clock is required to determine the maximum allowable skew that
can be introduced in the transmission path between LDATA
and LCLK. Setup skew is the maximum delay that can be intro-
duced in LDATA relative to LCLK, (setup skew = tLCLKTWH
min – tDLDCH – tSLDCL). Hold skew is the maximum delay that
can be introduced in LCLK relative to LDATA, (hold skew =
tLCLKTWL min – tHLDCH – tHLDCL). Calculations made directly
ADSP-21062 Setup Skew = 1.84 ns max
ADSP-21062 Hold Skew
= 2.78 ns max
ADSP-21062L Setup Skew = 2.10 ns max
ADSP-21062L Hold Skew = 1.87 ns max
ADSP-21062
ADSP-21062L
Max
Parameter
Min
Max
Min
Units
Receive
Timing Requirements:
tSLDCL
tHLDCL
tLCLKIW
Data Setup Before LCLK Low
Data Hold After LCLK Low
LCLK Period (2 × Operation)
2.5
2.25
tCK/2
4.5
4
2.25
2.25
tCK/2
5.25
4
ns
ns
ns
ns
ns
tLCLKRWL LCLK Width Low
tLCLKRWH LCLK Width High
Switching Characteristics:
tDLAHC
tDLALC
LACK High Delay After CLKIN High
18 + DT/2
6
28.5 + DT/2
16
18 + DT/2
6
29.5 + DT/2
16
ns
ns
LACK Low Delay After LCLK High1
Transmit
Timing Requirements:
tSLACH LACK Setup Before LCLK High
tHLACH LACK Hold After LCLK High
19
–6.75
19
–6.5
ns
ns
Switching Characteristics:
tDLCLK
tDLDCH
tHLDCH
LCLK Delay After CLKIN
Data Delay After LCLK High
Data Hold After LCLK High
8
2.25
8
2.25
ns
ns
ns
ns
ns
–2.0
(tCK/4) – 1
–2.25
(tCK/4) – 1
tLCLKTWL LCLK Width Low
tLCLKTWH LCLK Width High
(tCK/4) + 1.25
(tCK/4) – 1.25 (tCK/4) + 1
(tCK/4) + 1.5
(tCK/4) – 1.5 (tCK/4) + 1
tDLACLK
LCLK Low Delay After LACK High
(tCK/4) + 9 (3 × tCK/4) + 16.5 (tCK/4) + 9
(3 × tCK/4) + 16.5 ns
NOTE
1LACK will go low with tDLALC relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.
REV. C
–34–
ADSP-21062/ADSP-21062L
TRANSMIT
CLKIN
tDLCLK
tLCLKTWH
tLCLKTWL
LAST NIBBLE
TRANSMITTED
FIRST NIBBLE
TRANSMITTED
LCLK INACTIVE
(HIGH)
LCLK 1x
OR
LCLK 2x
tDLDCH
tHLDCH
LDAT(3:0)
LACK (IN)
OUT
tDLACLK
tSLACH
tHLACH
THE tSLACH REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.
RECEIVE
CLKIN
tLCLKIW
tLCLKRWH
tLCLKRWL
LCLK 1x
OR
LCLK 2x
tHLDCL
tSLDCL
LDAT(3:0)
IN
tDLALC
tDLAHC
LACK (OUT)
LINK PORT ENABLE/THREE-STATE DELAY FROM INSTRUCTION
CLKIN
tENDLK
tTDLK
LCLK
LDAT(3:0)
LACK
LINK PORT ENABLE OR THREE-STATE TAKES EFFECT TWO CYCLES AFTER A WRITE TO A LINK PORT CONTROL REGISTER.
LINK PORT INTERRUPT SETUP TIME
CLKIN
tHLCK
tSLCK
LCLK
LACK
Figure 21. Link Ports
REV. C
–35–
ADSP-21062/ADSP-21062L
Serial Ports
ADSP-21062
Max
ADSP-21062L
Max
Parameter
Min
Min
Units
External Clock
Timing Requirements:
tSFSE
TFS/RFS Setup Before TCLK/RCLK1
TFS/RFS Hold After TCLK/RCLK1, 2
Receive Data Setup Before RCLK1
Receive Data Hold After RCLK1
TCLK/RCLK Width
3.5
4
1.5
4
9
tCK
3.5
4
1.5
4
9
tCK
ns
ns
ns
ns
ns
ns
tHFSE
tSDRE
tHDRE
tSCLKW
tSCLK
TCLK/RCLK Period
Internal Clock
Timing Requirements:
tSFSI
TFS Setup Before TCLK1; RFS Setup
Before RCLK1
8
1
3
3
8
1
3
3
ns
ns
ns
ns
tHFSI
tSDRI
tHDRI
TFS/RFS Hold After TCLK/RCLK1, 2
Receive Data Setup Before RCLK1
Receive Data Hold After RCLK1
External or Internal Clock
Switching Characteristics:
tDFSE
RFS Delay After RCLK (Internally
Generated RFS)3
13
13
ns
ns
tHOFSE
RFS Hold After RCLK (Internally
Generated RFS)3
3
3
External Clock
Switching Characteristics:
tDFSE
TFS Delay After TCLK (Internally
Generated TFS)3
13
16
13
16
ns
tHOFSE
TFS Hold After TCLK (Internally
Generated TFS)3
3
5
3
5
ns
ns
ns
tDDTE
tHDTE
Transmit Data Delay After TCLK3
Transmit Data Hold After TCLK3
Internal Clock
Switching Characteristics:
tDFSI
TFS Delay After TCLK (Internally
Generated TFS)3
4.5
4.5
7.5
ns
tHOFSI
TFS Hold After TCLK (Internally
Generated TFS)3
–1.5
–1.5
0
ns
ns
ns
ns
tDDTI
tHDTI
tSCLKIW
Transmit Data Delay After TCLK3
Transmit Data Hold After TCLK3
TCLK/RCLK Width
7.5
0
(tSCLK/2) – 2.5
(tSCLK/2) + 2.5
(tSCLK/2) – 2.5 (tSCLK/2) + 2.5
Enable and Three-State
Switching Characteristics:
tDDTEN
tDDTTE
tDDTIN
tDDTTI
tDCLK
Data Enable from External TCLK3
4.25
0
4
ns
ns
ns
ns
ns
ns
Data Disable from External TCLK3
Data Enable from Internal TCLK3
Data Disable from Internal TCLK3
TCLK/RCLK Delay from CLKIN
SPORT Disable After CLKIN
10.5
16
0
3
7.5
22 + 3DT/8
17
22 + 3DT/8
17
tDPTR
Gated SCLK with External TFS
(Mesh Multiprocessing)4
Timing Requirements:
tSTFSCK
tHTFSCK
TFS Setup Before CLKIN
TFS Hold After CLKIN
5
5
ns
ns
tCK/2
tCK/2
External Late Frame Sync
Switching Characteristics:
tDDTLFSE Data Delay from Late External TFS or
External RFS with MCE = 1, MFD = 05
tDDTENFS Data Enable from late FS or MCE = 1,
MFD = 05
12.75
12.75
ns
ns
3.5
3.5
To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup
and hold, 2) data delay and data setup and hold, and 3) SCLK width.
REV. C
–36–
ADSP-21062/ADSP-21062L
NOTES
1Referenced to sample edge.
2RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
3Referenced to drive edge.
4Applies only to gated serial clock mode used for serial port system I/O in mesh multiprocessing systems.
5MCE = 1, TFS enable and TFS valid follow tDDTLFSE and tDDTENFS
.
DATA RECEIVE– INTERNAL CLOCK
DATA RECEIVE– EXTERNAL CLOCK
SAMPLE
EDGE
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKW
RCLK
RCLK
tDFSE
tHOFSE
tDFSE
tHOFSE
tHFSE
tSFSI
tHFSI
tSFSE
RFS
DR
RFS
DR
tSDRE
tHDRE
tSDRI
tHDRI
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT– INTERNAL CLOCK
DATA TRANSMIT– EXTERNAL CLOCK
SAMPLE
EDGE
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKW
TCLK
TCLK
tDFSI
tHOFSI
tDFSE
tHOFSE
tSFSI
tHFSI
tHFSE
tSFSE
TFS
TFS
tDDTI
tDDTE
tHDTI
tHDTE
DT
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE
EDGE
DRIVE
EDGE
TCLK / RCLK
TCLK (EXT)
DT
tDDTEN
tDDTTE
DRIVE
EDGE
DRIVE
EDGE
TCLK / RCLK
TCLK (INT)
tDDTIN
tDDTTI
DT
CLKIN
CLKIN
tHTFSCK
tDPTR
tSTFSCK
SPORT ENABLE AND
THREE-STATE
LATENCY
TCLK, RCLK
SPORT DISABLE DELAY
FROM INSTRUCTION
TFS (EXT)
TFS, RFS, DT
IS TWO CYCLES
tDCLK
NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH
EXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O FOR
MESH MULTIPROCESSING.
TCLK (INT)
RCLK (INT)
LOW TO HIGH ONLY
Figure 22. Serial Ports
–37–
REV. C
ADSP-21062/ADSP-21062L
EXTERNAL RFS with MCE = 1, MFD = 0
DRIVE
SAMPLE
DRIVE
tHOFSE/I
RCLK
RFS
(SEE NOTE 2
ON PREVIOUS PAGE)
tSFSE/I
tDDTE/I
tDDTENFS
tHDTE/I
1ST BIT
DT
2ND BIT
tDDTLFSE
LATE EXTERNAL TFS
DRIVE
DRIVE
SAMPLE
TCLK
TFS
tHOFSE/I
(SEE NOTE 2
ON PREVIOUS PAGE)
tSFSE/I
tDDTE/I
tDDTENFS
tHDTE/I
1ST BIT
DT
2ND BIT
tDDTLFSE
Figure 23. External Late Frame Sync
REV. C
–38–
ADSP-21062/ADSP-21062L
JTAG Test Access Port and Emulation
ADSP-21062
ADSP-21062L
Parameter
Min
Max
Min
Max
Units
Timing Requirements:
tTCK
TCK Period
tCK
5
6
7
18
tCK
5
6
7
18.5
ns
ns
ns
ns
ns
ns
tSTAP
tHTAP
tSSYS
tHSYS
tTRSTW
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK Low1
System Inputs Hold After TCK Low1
TRST Pulsewidth
4tCK
4tCK
Switching Characteristics:
tDTDO TDO Delay from TCK Low
tDSYS
System Outputs Delay After TCK Low2
13
18.5
13
18.5
ns
ns
NOTES
1System Inputs = DATA47-0, ADDR31-0, RD, WR, ACK, SBTS, SW, HBR, HBG, CS, DMAR1, DMAR2, BR6-1, ID2-0, RPBA, IRQ2-0, FLAG3-0, DR0, DR1,
TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN, RESET.
2System Outputs = DATA47-0, ADDR31-0, MS3-0, RD, WR, ACK, PAGE, ADRCLK, SW, HBG, REDY, DMAG1, DMAG2, BR6-1, CPA, FLAG3-0, TIMEXP, DT0,
DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3-0, LxCLK, LxACK, BMS.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 24. IEEE 11499.1 JTAG Test Access Port
REV. C
–39–
ADSP-21062/ADSP-21062L
OUTPUT DRIVE CURRENTS
Table III. External Power Calculations (3.3 V Device)
Figure 28 shows typical I-V characteristics for the output drivers
of the ADSP-21062. The curves represent the current drive
capability of the output drivers as a function of output voltage.
Pin
Type
# of
%
2
Pins Switching
؋
C ؋
f ؋
VDD = PEXT Address
MS0
WR
Data
ADDRCLK
15
1
1
32
1
50
0
–
50
–
× 44.7 pF × 10 MHz × 10.9 V = 0.037 W
× 44.7 pF × 10 MHz × 10.9 V = 0.000 W
× 44.7 pF × 20 MHz × 10.9 V = 0.010 W
× 14.7 pF × 10 MHz × 10.9 V = 0.026 W
× 4.7 pF × 20 MHz × 10.9 V = 0.001 W
POWER DISSIPATION
Total power dissipation has two components, one due to inter-
nal circuitry and one due to the switching of external output
drivers. Internal power dissipation is dependent on the instruc-
tion execution sequence and the data operands involved. Inter-
nal power dissipation is calculated in the following way:
P
EXT = 0.074 W
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
P
INT = IDDIN × VDD
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
P
TOTAL = PEXT + (IDDIN2 × 5.0 V )
Note that the conditions causing a worst-case PEXT are different
from those causing a worst-case PINT. Maximum PINT cannot
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching simultaneously.
– the number of output pins that switch during each cycle (O)
– the maximum frequency at which they can switch (f)
– their load capacitance (C)
– their voltage swing (VDD
)
and is calculated by:
TEST CONDITIONS
Output Disable Time
P
EXT = O × C × VDD2 × f
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from
their output high or low voltage. The time for the voltage on the
bus to decay by ∆V is dependent on the capacitive load, CL and
the load current, IL. This decay time can be approximated by
the following equation:
The load capacitance should include the processor’s package
capacitance (CIN). The switching frequency includes driving the
load high and then back low. Address and data pins can drive
high and low at a maximum rate of 1/(2tCK). The write strobe
can switch every cycle at a frequency of 1/tCK. Select pins switch
at 1/(2tCK), but selects can switch on each cycle.
C
∆V
Example:
L
t
=
DECAY
I
L
Estimate PEXT with the following assumptions:
The output disable time tDIS is the difference between tMEASURED
and tDECAY as shown in Figure 25. The time tMEASURED is the
interval from when the reference signal switches to when the
output voltage decays ∆V from the measured output high or
output low voltage. tDECAY is calculated with test loads CL and
IL, and with ∆V equal to 0.5 V.
–A system with one bank of external data memory RAM (32-bit)
–Four 128K × 8 RAM chips are used, each with a load of 10 pF
–External data memory writes occur every other cycle, a rate
of 1/(4tCK), with 50% of the pins switching
–The instruction cycle rate is 40 MHz (tCK = 25 ns).
The PEXT equation is calculated for each class of pins that can
drive:
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The output enable time tENA is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram (Figure 25). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
Table II. External Power Calculations (5 V Device)
Pin
Type
# of
%
2
Pins Switching
؋
C ؋
f ؋
VDD = PEXT Address
MS0
15
1
1
32
1
50
0
–
50
–
× 44.7 pF × 10 MHz × 25 V = 0.084 W
× 44.7 pF × 10 MHz × 25 V = 0.000 W
× 44.7 pF × 20 MHz × 25 V = 0.022 W
× 14.7 pF × 10 MHz × 25 V = 0.059 W
× 4.7 pF × 20 MHz × 25 V = 0.002 W
WR
Data
ADDRCLK
PEXT = 0.167 W
REV. C
–40–
ADSP-21062/ADSP-21062L
Example System Hold Time Calculation
I
OL
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose ∆V
to be the difference between the ADSP-21062’s output voltage
and the input threshold for the device requiring the hold time. A
typical ∆V will be 0.4 V. CL is the total bus capacitance (per
data line), and IL is the total leakage or three-state current (per
data line). The hold time will be tDECAY plus the minimum
disable time (i.e., tDATRWH for the write cycle).
TO
OUTPUT
PIN
+1.5V
50pF
I
OH
REFERENCE
SIGNAL
Figure 26. Equivalent Device Loading for AC Measure-
ments (Includes All Fixtures)
tMEASURED
tENA
tDIS
Capacitive Loading
V
V
OH (MEASURED)
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see Figure 26). The delay and hold specifica-
tions given should be derated by a factor of 1.5 ns/50 pF for
loads other than the nominal value of 50 pF. Figures 29–30,
33–34 show how output rise time varies with capacitance. Fig-
ures 31, 35 show graphically how output delays and holds vary
with load capacitance. (Note that this graph or derating does
not apply to output disable delays; see the previous section
Output Disable Time under Test Conditions.) The graphs of
Figures 29, 30 and 31 may not be linear outside the ranges
shown.
V
V
OH (MEASURED)
OL (MEASURED)
V
V
– ⌬V
+ ⌬V
2.0V
1.0V
OH (MEASURED)
OL (MEASURED)
OL (MEASURED)
tDECAY
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE TO BE
APPROXIMATELY 1.5V
Figure 25. Output Enable/Disable
INPUT OR
OUTPUT
1.5V
1.5V
Figure 27. Voltage Reference Levels for AC Measure-
ments (Except Output Enable/Disable)
REV. C
–41–
ADSP-21062/ADSP-21062L
5
4
3
2
1
100
75
50
25
5.25V, –40؇C
0
5.0V, +25°C
Y = 0.03X –1.45
4.75V, +85°C
–25
–50
4.75V, +85
°C
–75
–100
–125
5.0V, +25
°
C
5.25V, –40°C
–150
–175
–200
NOMINAL
–1
25
50
75
100
125
150
175
200
0
0.75
1.50
2.25
3.00
3.75
4.50
5.25
LOAD CAPACITANCE – pF
SOURCE VOLTAGE – V
Figure 31. Typical Output Delay or Hold vs. Load Capaci-
tance (at Maximum Case Temperature) (VDD = 5 V)
Figure 28. ADSP-21062 Typical Drive Currents (VDD = 5 V)
120
100
16.0
14.0
12.0
3.3V, +25°C
80
60
40
3.6V, –40°C
RISE TIME
3.0V, +85؇C
10.0
V
20
0
OH
Y = 0.005X + 3.7
8.0
6.0
4.0
–20
–40
–60
FALL TIME
3.0V, +85°C
3.3V, +25°C
3.6V, –40°C
–80
–100
–120
2.0
0
Y = 0.0031X + 1.1
V
OL
0
0.5
1
1.5
2
2.5
3
3.5
0
20
40
60
80
100 120 140 160 180 200
SOURCE VOLTAGE – V
LOAD CAPACITANCE – pF
Figure 32. ADSP-21062 Typical Drive Currents (VDD = 3.3 V)
Figure 29. Typical Output Rise Time (10%–90% VDD) vs.
Load Capacitance (VDD = 5 V)
18
16
3.5
3.0
2.5
14
Y = 0.0796X + 1.17
12
RISE TIME
10
2.0
Y = 0.009X + 1.1
RISE TIME
8
1.5
6
4
2
0
Y = 0.0467X + 0.55
FALL TIME
1.0
FALL TIME
Y = 0.005X + 0.6
0.5
0
0
20
40
60
80 100 120 140 160 180 200
0
20
40
60
80
100 120 140 160 180 200
LOAD CAPACITANCE – pF
LOAD CAPACITANCE – pF
Figure 33. Typical Output Rise Time (10%–90% VDD) vs.
Load Capacitance (VDD = 3.3 V)
Figure 30. Typical Output Rise Time (0.8 V–2.0 V) vs.
Load Capacitance (VDD = 5 V)
REV. C
–42–
ADSP-21062/ADSP-21062L
ENVIRONMENTAL CONDITIONS
9
8
Thermal Characteristics
The ADSP-21062 is available in 240-lead thermally enhanced
MQFP and 225-lead plastic ball grid array packages. The top
surface of the thermally enhanced MQFP contains a copper slug
from which most of the die heat is dissipated. The slug is flush
with the top surface of the package. Note that the copper slug is
internally connected to GND through the device substrate.
7
6
Y = 0.0391X + 0.36
5
4
RISE TIME
Y = 0.0305X + 0.24
Both packages are specified for a case temperature (TCASE). To
ensure that the TCASE is not exceeded, a heatsink and/or an air
flow source may be used. A heatsink should be attached with a
thermal adhesive.
3
2
1
0
FALL TIME
T
CASE = TAMB + ( PD × θCA
)
0
20
40
60
80 100 120 140 160 180 200
T
PD =
CASE = Case temperature (measured on top surface of package)
LOAD CAPACITANCE – pF
Power dissipation in W (this value depends upon the
specific application; a method for calculating PD is
shown under Power Dissipation).
Figure 34. Typical Output Rise Time (0.8 V–2.0 V) vs.
Load Capacitance (VDD = 3.3 V)
θCA
=
Value from table below.
5
240 MQFP
4
3
2
1
Y = 0.0329X –1.65
JC = 0.3؇C/W
Airflow
(Linear Ft./Min.)
0
100
200
400
600
θ
CA (°C/W)
10
9
8
7
6
NOTES
This represents thermal resistance at total power of 5 W.
With air flow, no variance is seen in θCA with power.
θ
CA at 0 LFM varies with power: at 2W, θCA = 14°C/W, at 3W θCA = 11°C/W.
NOMINAL
225 PBGA
–1
25
50
75
100
125
150
175
200
LOAD CAPACITANCE – pF
JC = 1.7؇C/W
Airflow
(Linear Ft./Min.)
Figure 35. Typical Output Delay or Hold vs. Load Capaci-
tance (at Maximum Case Temperature) (VDD = 3.3 V)
0
200
400
θ
CA (°C/W)
20.7
15.3
12.9
NOTE
No variance is seen in θCA with power.
REV. C
–43–
ADSP-21062/ADSP-21062L
225-Ball Plastic Ball Grid Array (PBGA) Package Descriptions
Ball #
Name
Ball #
Name
Ball #
Name
Ball #
Name
Ball #
Name
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
BMS
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
ADDR25
ADDR26
MS2
ADDR29
DMAR1
TFS1
CPA
HBG
DMAG2
BR5
BR1
G01
G02
G03
G04
G05
G06
G07
G08
G09
G10
G11
G12
G13
G14
G15
ADDR14
ADDR15
ADDR16
ADDR19
GND
VDD
VDD
VDD
VDD
VDD
GND
K01
K02
K03
K04
K05
K06
K07
K08
K09
K10
K11
K12
K13
K14
K15
ADDR6
ADDR5
ADDR3
ADDR0
ICSA
GND
VDD
VDD
VDD
GND
GND
N01
N02
N03
N04
N05
N06
N07
N08
N09
N10
N11
N12
N13
N14
N15
EMU
TDO
IRQ0
IRQ1
ADDR30
DMAR2
DT1
RCLK1
TCLK0
RCLK0
ADRCLK
CS
CLKIN
PAGE
BR3
DATA47
DATA44
DATA42
ID2
L5DAT1
L4CLK
L3CLK
L3DAT3
L2DAT0
L1ACK
L1DAT3
L0DAT3
DATA1
DATA3
DATA40
DATA37
DATA35
DATA34
DATA22
DATA25
DATA24
DATA23
DATA8
DATA11
DATA13
DATA14
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
MS0
SW
ADDR31
HBR
DR1
DT0
DR0
REDY
RD
ACK
BR6
BR2
DATA45
DATA43
DATA39
E01
E02
E03
E04
E05
E06
E07
E08
E09
E10
E11
E12
E13
E14
E15
ADDR21
ADDR22
ADDR24
ADDR27
GND
GND
GND
GND
GND
GND
NC
DATA33
DATA30
DATA32
DATA31
H01
H02
H03
H04
H05
H06
H07
H08
H09
H10
H11
H12
H13
H14
H15
ADDR12
ADDR11
ADDR13
ADDR10
GND
VDD
VDD
VDD
VDD
VDD
GND
DATA18
DATA19
DATA21
DATA20
L01
L02
LA03
L04
L05
L06
L07
L08
L09
L10
L11
L12
L13
L14
L15
ADDR2
ADDR1
FLAG0
FLAG3
RPBA
GND
GND
GND
GND
GND
NC
DATA4
DATA7
DATA9
DATA10
P01
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
P13
P14
P15
TRST
TMS
EBOOT
ID0
L5CLK
L5DAT3
L4DAT0
L4DAT3
L3DAT2
L2CLK
L2DAT2
L1DAT0
L0ACK
L0DAT1
DATA0
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
MS3
MS1
ADDR28
SBTS
TCLK1
RFS1
TFS0
RFS0
WR
DMAG1
BR4
F01
F02
F03
F04
F05
F06
F07
F08
F09
F10
F11
F12
F13
F14
F15
ADDR17
ADDR18
ADDR20
ADDR23
GND
GND
VDD
VDD
VDD
GND
GND
J01
J02
J03
J04
J05
J06
J07
J08
J09
J10
J11
J12
J13
J14
J15
ADDR9
ADDR8
ADDR7
ADDR4
GND
VDD
VDD
VDD
VDD
VDD
GND
M01
M02
M03
M04
M05
M06
M07
M08
M09
M10
M11
M12
M13
M14
M15
FLAG1
FLAG2
TIMEXP
TDI
R01
R02
R03
R04
R05
R06
R07
R08
R09
R10
R11
R12
R13
R14
R15
TCK
IRQ2
RESET
ID1
LBOOT
L5ACK
L5DAT2
L4DAT2
L3DAT0
L2DAT3
L1DAT1
L0DAT0
DATA2
DATA5
DATA6
L5DAT0
L4ACK
L4DAT1
L3ACK
L3DAT1
L2ACK
L2DAT1
L1CLK
L1DAT2
L0CLK
L0DAT2
DATA46
DATA41
DATA38
DATA36
DATA29
DATA26
DATA28
DATA27
DATA12
DATA15
DATA16
DATA17
REV. C
–44–
ADSP-21062/ADSP-21062L
225-Ball Plastic Ball Grid Array (PBGA) Package Pinout
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
DMAR2
BMS
DT1
DATA42 DATA44 DATA47
PAGE
CLKIN
ADRCLK RCLK0
TCLK0
RCLK1
ADDR30
BR3
CS
A
B
C
D
E
F
HBR
MS0
DATA39 DATA43 DATA45
ACK
REDY
DR0
DT0
DR1
ADDR31
BR2
BR6
RD
SW
SBTS
MS3
DATA36 DATA38 DATA41 DATA46
DATA34 DATA35 DATA37 DATA40
RFS0
TFS0
RFS1
TFS1
TCLK1
ADDR28
BR4
BR1
DMAG1
BR5
WR
MS1
CPA
DMAR1
MS2
ADDR29
ADDR26 ADDR25
DMAG2
HBG
DATA31 DATA32 DATA30 DATA33
NC
GND
GND
GND
GND
GND
GND
ADDR27 ADDR24 ADDR22 ADDR21
DATA27 DATA28 DATA26 DATA29
DATA23 DATA24 DATA25 DATA22
GND
GND
GND
VDD
VDD
VDD
VDD
VDD
VDD
VDD
GND
VDD
GND
GND
ADDR23 ADDR20 ADDR18 ADDR17
ADDR19 ADDR16 ADDR15 ADDR14
G
H
J
DATA20 DATA21 DATA19 DATA18
DATA17 DATA16 DATA15 DATA12
GND
GND
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
GND
GND
ADDR10 ADDR13 ADDR11 ADDR12
ADDR4 ADDR7 ADDR8 ADDR9
DATA14 DATA13 DATA11 DATA8
GND
NC
GND
GND
VDD
GND
VDD
GND
VDD
GND
GND
GND
ICSA
ADDR0 ADDR3 ADDR5 ADDR6
K
L
DATA10 DATA9
DATA7 DATA4
RPBA
FLAG3
FLAG0 ADDR1 ADDR2
DATA6
DATA5
DATA2 L0DAT0 L1DAT1 L2DAT3 L3DAT0 L4DAT2 L5DAT2 L5ACK LBOOT
TDI
TIMEXP FLAG2
FLAG1
M
N
P
R
IRQ1
IRQ0
EMU
DATA3 DATA1 L0DAT3 L1DAT3 L1ACK L2DAT0 L3DAT3 L3CLK
L4CLK L5DAT1
ID2
TDO
TMS
IRQ2
TRST
DATA0 L0DAT1 L0ACK L1DAT0 L2DAT2 L2CLK L3DAT2 L4DAT3 L4DAT0 L5DAT3 L5CLK
L0DAT2 L0CLK L1DAT2 L1CLK L2DAT1 L2ACK L3DAT1 L3ACK L4DAT1 L4ACK L5DAT0
ID0
ID1
EBOOT
RESET
TCK
REV. C
–45–
ADSP-21062/ADSP-21062L
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
225-Ball PBGA
0.913 (23.20)
0.906 (23.00)
0.898 (22.80)
15141312 1110 9
8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
0.700
(17.78)
0.791 (20.10)
0.787 (20.00)
0.783 (19.90)
0.913 (23.20)
0.906 (23.00)
0.898 (22.80)
BSC
TOP VIEW
0.050
(1.27)
BSC
0.791 (20.10)
0.787 (20.00)
0.783 (19.90)
0.050 (1.27) BSC
0.700 (17.78) BSC
DETAIL A
DETAIL A
0.051 (1.30)
0.047 (1.20)
0.043 (1.10)
0.101 (2.57)
0.091 (2.32)
0.081 (2.06)
0.026 (0.65)
0.024 (0.61)
0.022 (0.57)
0.006 (0.15) MAX
NOTES
SEATING
PLANE
0.035 (0.90)
0.030 (0.75)
0.024 (0.60)
1.THE ACTUAL POSITION OF THE BALL ARRAY IS WITHIN 0.12 (0.30)
OF ITS IDEAL POSITION RELATIVE TO THE EDGE OF THE PACKAGE.
2.THE ACTUAL POSITION OF ANY BALL IS WITHIN 0.004 (0.10)
OF ITS IDEAL POSITION RELATIVE TO THE ARRAY OF BALLS.
BALL DIAMETER
REV. C
–46–
ADSP-21062/ADSP-21062L
240-LEAD METRIC MQFP PIN CONFIGURATIONS
240
181
1
180
TOP VIEW
HEAT
SLUG
GND
60
121
61
120
THE 240-LEAD PACKAGE CONTAINS A COPPER HEAT SLUG FLUSH WITH ITS
TOP SURFACE. THE SLUG IS EITHER CONNECTED TO GROUND OR FLOATING.
Pin Pin
No. Name
Pin Pin
No. Name
Pin Pin
No. Name
Pin Pin
No. Name
Pin Pin
No. Name
Pin Pin
No. Name
1
2
3
4
5
6
7
8
TDI
TRST
VDD
TDO
TIMEXP
EMU
ICSA
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
ADDR20
ADDR21
GND
ADDR22
ADDR23
ADDR24
VDD
GND
VDD
ADDR25
ADDR26
ADDR27
GND
MS3
MS2
MS1
MS0
SW
BMS
ADDR28
GND
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
TCLK0
TFS0
DR0
201 L2DAT0
202 L2CLK
203 L2ACK
204 NC
161 DATA14
162 DATA13
163 DATA12
164 GND
165 DATA11
166 DATA10
167 DATA9
168 VDD
169 DATA8
170 DATA7
171 DATA6
172 GND
173 DATA5
174 DATA4
175 DATA3
176 VDD
121 DATA41
122 DATA40
123 DATA39
124 VDD
125 DATA38
126 DATA37
127 DATA36
128 GND
RCLK0
RFS0
VDD
VDD
GND
ADRCLK
REDY
HBG
CS
RD
WR
GND
VDD
GND
CLKIN
ACK
205 VDD
206 L3DAT3
207 L3DAT2
208 L3DAT1
209 L3DAT0
210 L3CLK
211 L3ACK
212 GND
213 L4DAT3
214 L4DAT2
215 L4DAT1
216 L4DAT0
217 L4CLK
218 L4ACK
219 VDD
FLAG3
FLAG2
FLAG1
FLAG0
GND
ADDR0
ADDR1
VDD
ADDR2
ADDR3
ADDR4
GND
ADDR5
ADDR6
ADDR7
VDD
ADDR8
ADDR9
ADDR10
GND
ADDR11
ADDR12
ADDR13
VDD
ADDR14
ADDR15
GND
ADDR16
ADDR17
ADDR18
VDD
9
129 NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
130 DATA35
131 DATA34
132 DATA33
133 VDD
134 VDD
135 GND
136 DATA32
137 DATA31
138 DATA30
139 GND
140 DATA29
141 DATA28
142 DATA27
143 VDD
177 DATA2
178 DATA1
179 DATA0
180 GND
100 DMAG2
101 DMAG1
102 PAGE
103 VDD
104 BR6
105 BR5
106 BR4
107 BR3
108 BR2
109 BR1
110 GND
111 VDD
112 GND
113 DATA47
114 DATA46
115 DATA45
116 VDD
117 DATA44
118 DATA43
119 DATA42
120 GND
220 GND
221 VDD
181 GND
VDD
VDD
ADDR29
ADDR30
ADDR31
GND
222 L5DAT3
223 L5DAT2
224 L5DAT1
225 L5DAT0
226 L5CLK
227 L5ACK
228 GND
229 ID2
230 ID1
231 ID0
232 LBOOT
233 RPBA
234 RESET
235 EBOOT
236 IRQ2
237 IRQ1
238 IRQ0
182 L0DAT3
183 L0DAT2
184 L0DAT1
185 L0DAT0
186 L0CLK
187 L0ACK
188 VDD
189 L1DAT3
190 L1DAT2
191 L1DAT1
192 L1DAT0
193 L1CLK
194 L1ACK
195 GND
144 VDD
145 DATA26
146 DATA25
147 DATA24
148 GND
149 DATA23
150 DATA22
151 DATA21
152 VDD
153 DATA20
154 DATA19
155 DATA18
156 GND
157 DATA17
158 DATA16
159 DATA15
160 VDD
SBTS
DMAR2
DMAR1
HBR
DT1
TCLK1
TFS1
DR1
RCLK1
RFS1
GND
CPA
196 GND
197 VDD
198 L2DAT3
199 L2DAT2
200 L2DAT1
VDD
ADDR19
239 TCK
240 TMS
DT0
REV. C
–47–
ADSP-21062/ADSP-21062L
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
240-Lead Metric MQFP
1.372 (34.85)
1.362 (34.60) TYP SQ
1.352 (34.35)
1.264 (32.10)
1.260 (32.00) TYP SQ
1.256 (31.90)
0.161 (4.10)
MAX
1.161 (29.50) BSC SQ
0.030 (0.75)
0.024 (0.60) TYP
0.020 (0.50)
240
181
180
1
240 LEAD METRIC MQFP
TOP VIEW (PINS DOWN)
SEATING
PLANE
LEAD PITCH
0.01969 (0.50)
TYP
HEAT
SLUG
LEAD WIDTH
0.011 (0.27)
0.009 (0.22) TYP
0.007 (0.17)
GND
INCHES (MILLIMETERS)
60
121
120
0.003 (0.08)
MAX
61
0.010 (0.25)
MIN
THE THERMALLY ENHANCED MQFP PACKAGE CONTAINS A
COPPER HEAT SLUG FLUSH WITH ITS TOP SURFACE; THE
SLUG IS EITHER CONNECTED TO GROUND OR FLOATING.
0.138 (3.50)
0.134 (3.40) TYP THE HEAT SLUG DIAMETER IS 24.1 (0.949) mm.
0.130 (3.30)
NOTE:
THE ACTUAL POSITION OF EACH LEAD IS WITHIN (0.08)
0.0032 FROM ITS IDEAL POSITION WHEN MEASURED IN THE
LATERAL DIRECTION.
CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.
ORDERING GUIDE
Case
Instruction
Rate
On-Chip
SRAM
Operating
Voltage
Package
Options
Part Number
Temperature Range
ADSP-21062KS-133
ADSP-21062KS-160
ADSP-21062KB-160
ADSP-21062CS-160
ADSP-21062LKS-133
ADSP-21062LKS-160
ADSP-21062LKB-160
ADSP-21062LAB-160
ADSP-21062LCS-160
0°C to +85°C
0°C to +85°C
0°C to +85°C
–40°C to +100°C
0°C to +85°C
0°C to +85°C
0°C to +85°C
–40°C to +85°C
–40°C to +100°C
33 MHz
40 MHz
40 MHz
40 MHz
33 MHz
40 MHz
40 MHz
40 MHz
40 MHz
2 Mbit
2 Mbit
2 Mbit
2 Mbit
2 Mbit
2 Mbit
2 Mbit
2 Mbit
2 Mbit
5 V
5 V
5 V
5 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
MQFP
MQFP
PBGA
MQFP
MQFP
MQFP
PBGA
PBGA
MQFP
REV. C
–48–
相关型号:
ADSP-21062KBZ-160
48-BIT, 40 MHz, OTHER DSP, PBGA225, ROHS COMPLIANT, PLASTIC, MS-034AAJ-2, BGA-225
ROCHESTER
ADSP-21062LABZ-160
48-BIT, 40 MHz, OTHER DSP, PBGA225, ROHS COMPLIANT, PLASTIC, MS-034AAJ-2, BGA-225
ROCHESTER
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