ADRF6821ACPZ-RL7 [ADI]
450 MHz to 2800 MHz, DPD RFIC with Integrated Fractional-N PLL and VCO;
| 型号： | ADRF6821ACPZ-RL7 |
| 厂家： | 
ADI |
| 描述： | 450 MHz to 2800 MHz, DPD RFIC with Integrated Fractional-N PLL and VCO 光电二极管 |
| 文件： | 总61页 (文件大小：1057K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
450 MHz to 2800 MHz, DPD RFIC with
Integrated Fractional-N PLL and VCO
ADRF6821
Data Sheet
The high isolation 2:1 RF switch and on-chip wideband RF
balun enable the ADRF6821 to support two single-ended, 50 Ω
terminated RF inputs. A programmable attenuator ensures an
optimal differential RF input level to the high linearity demodulator
core. The integrated attenuator offers an attenuation range of
15 dB with a step size of 1 dB. High linearity IF amplifiers follow
the demodulator and provide an interface to the next component
in the chain, typically an analog-to-digital converter (ADC).
FEATURES
DPD receiver with integrated fractional-N PLL
RF input frequency range: 450 MHz to 2800 MHz
Internal LO input frequency range: 450 MHz to 2800 MHz
Dual RF inputs with SPDT absorptive RF switches
Integrated RF balun for single-ended 50 Ω input
Integrated VCO to cover complete RF input range
Digital programmable LO phase offset and dc nulling
Programmable via 4-wire SPI
The ADRF6821 offers two alternatives for generating the
differential local oscillator (LO) input signal: internally via
the on-chip fractional-N synthesizer with low phase noise
VCOs or externally via a low phase noise LO signal. The
integrated synthesizer enables continuous LO coverage from
450 MHz to 2800 MHz. The PLL reference input supports a
wide frequency range and includes integrated reference dividers
before the phase frequency detector (PFD).
56-lead, 8 mm × 8 mm LFCSP
APPLICATIONS
Cellular W-CDMA/GSM/LTE
DPD receivers
Microwave, point to point radios
GENERAL DESCRIPTION
When selected, the output of the internal fractional-N synthesizer
is applied to a divide by 2, quadrature phase splitter. From the
external LO path, a 2× LO signal can be used with the divide by 2,
quadrature phase splitter to generate the quadrature LO inputs
to the mixers.
The ADRF6821 is a highly integrated, dual radio frequency (RF)
input, zero intermediate frequency (IF)/low IF RFIC receiver
with a quadrature demodulator, digital step attenuator (DSA),
IF linear amplifiers, an integrated, fractional-N phase-locked loop
(PLL), and a low phase noise, multicore, voltage controlled
oscillator (VCO). The RFIC is ideally suited for communication
digital predistortion (DPD) systems.
The ADRF6821 is fabricated using an advanced silicon germanium
(SiGe), bipolar complementary metal oxide semiconductor
(BiCMOS) process. It is available in a 56-lead, RoHS compliant,
8 mm × 8 mm LFCSP package with an exposed pad. Performance
is specified over the −40°C to +105°C case temperature range.
FUNCTIONAL BLOCK DIAGRAM
IF_QOUT+ IF_QOUT–
54 53
DC DAC
/R
PFD
/N
RFIN_FB0
RF_SEL0
4
9
41 CPOUT
CP
Σ-Δ
0
30
VTUNE
RF_SEL1 10
÷2
÷
90
32 EX_LO_IN–
31
EX_LO_IN+
39 LO_OUT–
38 LO_OUT+
11
RFIN_FB1
SPI
DC DAC
24
25
26
27
17
18
IF_IOUT+ IF_IOUT–
SCLK SDIO SDO CS
Figure 1.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2017–2018 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADRF6821
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
RF Attenuator ............................................................................. 21
Active Mixer................................................................................ 21
I and Q Polarity .......................................................................... 21
Low-Pass Filters (LPF) and IF Amplifiers............................... 21
LO Generation Block................................................................. 21
Register Write Sequence............................................................ 24
Serial Peripheral Interface (SPI)............................................... 24
Applications Information .............................................................. 25
Basic Connections...................................................................... 25
Low-Pass Filter Bandwidth Selection ...................................... 28
I/Q Output Loading ................................................................... 29
Analog-to-Digital Converter (ADC) Interfacing................... 29
Image Rejection.......................................................................... 31
Power Supply Configuration..................................................... 32
Layout .......................................................................................... 34
Register Map and Register Descriptions ..................................... 35
Register Descriptions................................................................. 38
Outline Dimensions....................................................................... 61
Ordering Guide .......................................................................... 61
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
System Specifications ................................................................... 4
DSA and RF Input Switch Specifications .................................. 5
PLL/VCO Specifications.............................................................. 6
Digital Logic Specifications......................................................... 7
Serial Peripheral Interface (SPI) Timing Specifications.......... 8
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 12
Phase-Locked Loop (PLL) Performance ................................. 17
Theory of Operation ...................................................................... 20
RF Input Switch .......................................................................... 20
Balun ............................................................................................ 21
REVISION HISTORY
8/2018—Rev. 0 to Rev. A
Changed VCC_AMP_I Pin and VCC_MIX_I Pin to
VCC_IFMIX_I Pin ........................................................ Throughout
Changed VCC_MIX_Q Pin and VCC_AMP_Q Pin to
VCC_IFMIX_Q Pin ..................................................... Throughout
Changes to Figure 3........................................................................ 10
Changes to Figure 62...................................................................... 32
Updated Outline Dimensions....................................................... 62
5/2017—Revision 0: Initial Version
Rev. A | Page 2 of 61
Data Sheet
ADRF6821
SPECIFICATIONS
All supply pins = 3.3 V, TA = 25°C, low-side LO injection, internal LO, minimum attenuation setting (DSA setting of 0 dB),
MIXER_GAIN_PEAK = 0, common-mode voltage (VCM) = 1.6 V, 25 Ω matching resistors on I/Q differential outputs, unless
otherwise noted. All losses from input and output traces and baluns are de-embedded from results.
Table 1.
Parameter
Test Conditions/Comments
Min Typ Max
Unit
RF INPUT INTERFACE
Input Impedance
RF Frequency Range
I/Q OUTPUT INTERFACE
Return Loss
50
Ω
MHz
450
2800
IF_IOUT and IF_QOUT terminated with 100 Ω differential loads (25 Ω
external resistors are required on each differential output pin)
−10
dB
Output Impedance
Output DC Offset
10
40
2
55
1.6
Ω
No correction
Correction applied
mV
mV
mV
V
DC Offset Correction Range
Output VCM
VCM Ripple
1.2
−5
1.8
+5
mV
LO INPUT
External LO operation, differential
Required Power
Input Impedance
Return Loss
−6
+6
dBm
Ω
dB
100
−10
Frequency Range
Low-side or high-side LO
450
2800
MHz
LO OUTPUT
Power1, 2
2× LO output, differential, observation purposes only
TRM_XLODRV_DRV_POUT = 1
2× fLO = 1800 MHz
2× fLO = 3600 MHz
2× fLO = 5400 MHz
Output Impedance
Return Loss
Frequency Range
POWER SUPPLY
PLL/VCO Supplies3
RF/IF Supplies
0
−1
0
50
−10
dBm
dBm
dBm
Ω
dB
MHz
Differential
2× fLO
900
5600
3.2
3.1
3.3
3.3
3.4
3.5
V
V
POWER CONSUMPTION
RF/IF Supplies
0.9
W
PLL/VCO Supplies
fLO = 1000 MHz
fLO = 2000 MHz
fLO = 2800 MHz
Internal LO
Internal LO
Internal LO
1.0
0.9
0.8
W
W
W
1 For LO output power setting, see the LO Generation Block section.
2 fLO means LO frequency.
3 See the Applications Information section for the supply circuit design.
Rev. A | Page 3 of 61
ADRF6821
Data Sheet
SYSTEM SPECIFICATIONS
All supply pins = 3.3 V, TA = 25°C, internal LO, minimum attenuation setting (DSA setting of 0 dB), MIXER_GAIN_PEAK = 0, VCM = 1.6 V,
25 Ω matching resistors on I/Q differential outputs, unless otherwise noted. All losses from input and output traces and baluns are
de-embedded from results.
Table 2.
Parameter
Test Conditions/Comments
Min Typ Max Unit
DEMODULATION BANDWIDTH
GROUP DELAY RIPPLE
500
0.1
0.2
MHz
ns
ns
Fixed LO frequency, any 75 MHz bandwidth (BW)
Fixed LO frequency, any 280 MHz BW
DYNAMIC PERFORMANCE AT fLO = 1000 MHz
High-side LO, IF frequency (fIF) = 100 MHz, RF frequency (fRF) =
900 MHz, low-pass filter (LPF) set to lowest BW
Power Gain
12
dB
Gain Flatness
Over any 75 MHz bandwidth, LPF set to maximum BW
Over any 280 MHz bandwidth, LPF set to maximum BW
Over all DSA settings, VCM = 1.6 V
Over all DSA settings, output power (POUT) = −10 dBm/tone,
fIF = 1 MHz to 75 MHz separation
0.12
0.35
12
dB
dB
dBm
dBm
Output 1 dB Power Compression (OP1dB)
Output Third-Order Intercept (OIP3)
33
Over all DSA settings, POUT = −10 dBm/tone, fIF = 175 MHz to
200 MHz separation
Over all DSA settings, POUT = −10 dBm/tone, fIF = 1 MHz to
75 MHz separation
35
75
dBm
dBm
Output Second-Order Intercept (OIP2)
Second-Order Harmonic Distortion (HD2)
Third-Order Harmonic Distortion (HD3)
Noise Figure
POUT = −7 dBm continuous wave (CW) signal
POUT = −7 dBm CW signal
Double-side band (DSB)
−85
−85
14
dBc
dBc
dB
Image Rejection
LO to IF Leakage
LO to RF Leakage
RF to IF Leakage
−41
−40
−62
−47
−58
dB
See Figure 26
See Figure 27
See Figure 25
Channel to channel
Low-side LO, fIF = 100 MHz, fRF = 2100 MHz
dBm
dBm
dBc
dBc
Isolation
DYNAMIC PERFORMANCE AT fLO = 2000 MHz
Power Gain
11
dB
Gain Flatness
Over any 75 MHz bandwidth
Over any 280 MHz bandwidth
Over all DSA settings, VCM = 1.6 V
Over all DSA settings, POUT = −10 dBm/tone, fIF =1 MHz to
75 MHz separation
0.16
0.55
12
dB
dB
dBm
dBm
OP1dB
OIP3
32
Over all DSA settings, POUT = −10 dBm/tone, fIF = 175 MHz to
200 MHz separation
Over all DSA settings, POUT = −10 dBm/tone, fIF = 1 MHz to
75 MHz separation
33
74
dBm
dBm
OIP2
HD2
HD3
POUT = −7 dBm CW signal
POUT = −7 dBm CW signal
DSB
−81
−86
15
−41
−48
−61
−52
−43
dBc
dBc
dB
Noise Figure
Image Rejection
LO to IF Leakage
LO to RF Leakage
RF to IF Leakage
Isolation
dB
See Figure 26
See Figure 27
See Figure 25
Channel to channel
dBm
dBm
dBc
dBc
Rev. A | Page 4 of 61
Data Sheet
ADRF6821
Parameter
Test Conditions/Comments
Min Typ Max Unit
DYNAMIC PERFORMANCE AT fLO = 2800 MHz
High-side LO, fIF = 100 MHz, fRF = 2700 MHz
Power Gain
10
dB
Gain Flatness
Over any 75 MHz bandwidth
Over any 280 MHz bandwidth
Over all DSA settings, VCM = 1.6 V
Over all DSA settings, POUT = −10 dBm/tone, fIF =1 MHz to
75 MHz separation
0.08
0.25
12
dB
dB
dBm
dBm
OP1dB
OIP3
33
Over all DSA settings, POUT = −10 dBm/tone, fIF = 175 MHz to
200 MHz separation
Over all DSA settings, POUT = −10 dBm/tone, fIF = 1 MHz to
75 MHz separation
34
70
dBm
dBm
OIP2
HD2
HD3
POUT = −7 dBm CW signal
POUT = −7 dBm CW signal
DSB
−80
−82
17
−32
−54
−59
−61
−46
dBc
dBc
dB
Noise Figure
Image Rejection
LO to IF Leakage
LO to RF Leakage
RF to IF Leakage
Isolation
dB
See Figure 26
See Figure 27
See Figure 25
Channel to channel
dBm
dBm
dBc
dBc
DSA AND RF INPUT SWITCH SPECIFICATIONS
All supply pins = 3.3 V, TA = 25°C, internal LO, minimum attenuation setting (DSA setting of 0 dB), MIXER_GAIN_PEAK = 0, VCM = 1.6 V,
25 Ω matching resistors on I/Q differential outputs, unless otherwise noted. All losses from input and output traces and baluns are
de-embedded from results.
Table 3.
Parameter
Test Conditions/Comments
Min Typ
Max Unit
DIGITAL STEP ATTENUATOR
Attenuation Range
Step Size
Step Error
Settling Time
DSA Phase Shift
RF INPUT SWITCH
Switch Settling Time
15
1
dB
dB
dB
ns
(0.3 + attenuation × 5%)
100
5
Between any two different attenuation settings
Between any two different attenuation settings
Degrees
50% control signal to 99% or1% RF signal final value
2
µs
Rev. A | Page 5 of 61
ADRF6821
Data Sheet
PLL/VCO SPECIFICATIONS
All supply pins = 3.3 V, TA = 25°C, reference frequency (fREF) = 122.88 MHz, fREF power = 10 dBm, PFD frequency (fPFD) = 30.72 MHz, and
loop filter BW = 20 kHz, unless otherwise noted.
Table 4.
Parameter
PLL REFERENCE
Frequency
Level
Test Conditions/Comments
Min
Typ
Max
Unit
10
0.7
30.72 250
3.3
MHz
V p-p
For PLL lock condition, 50 Ω to ground required
close to REF_IN pin
Step Size
Lock Time
240
0.4
kHz
ms
For PLL lock condition
PFD FREQUENCY, fPFD
INTERNAL VCO RANGE
OPEN-LOOP VCO PHASE NOISE
VCO Frequency (fVCO) = 5440 MHz
30.72 61.44 MHz
4000
8000
MHz
10 kHz offset
100 kHz offset
1 MHz offset
10 MHz offset
−83
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−110
−132
−152
fVCO = 7060 MHz
10 kHz offset
100 kHz offset
1 MHz offset
10 MHz offset
−80
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−106
−127
−147
SYNTHESIZER SPECIFICATIONS
Fractional Figure of Merit (FOM)
Flicker FOM
−227
−262
dBc/Hz
dBc/Hz
fPFD Spurs1
Output to internal mixer and daisy-chain of
another ADRF6821
fPFD × 1
fPFD × 2
fPFD × 3 and Higher
−90
−95
−95
−70
dBc
dBc
dBc
dBc
Unwanted Spurs (Other Than PFD and Harmonics)1
Output to internal mixer and daisy-chain of
another ADRF6821
fLO = 1765 MHz, fVCO = 7060 MHz
Closed-Loop Phase Noise
1 kHz offset
10 kHz offset
100 kHz offset
950 kHz offset
2.1 MHz offset
3.5 MHz offset
7.5 MHz offset
10 MHz offset
85 MHz offset
100 Hz to 10 MHz integration BW
−102
−97
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
−117
−138
−145
−149
−153
−156
−158
0.2
Integrated Phase Noise
Rev. A | Page 6 of 61
Data Sheet
ADRF6821
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
fLO = 2720 MHz, fVCO = 5440 MHz
Closed-Loop Phase Noise
1 kHz offset
10 kHz offset
100 kHz offset
950 kHz offset
2.1 MHz offset
3.5 MHz offset
7.5 MHz offset
10 MHz offset
85 MHz offset
100 Hz to 10 MHz integration BW
−102
−99
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
−114
−137
−144
−148
−153
−155
−156
0.2
Integrated Phase Noise
1 Auxiliary LO output measurements are performed under a daisy-chain configuration with another ADRF6821 device. Measurements are taken from the auxiliary LO
output of the daisy chained ADRF6821.
DIGITAL LOGIC SPECIFICATIONS
The following specifications are for all digital inputs.
Table 5.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
LOGIC INPUT VOLTAGE
Low
High
VIL
VIH
0
1.2
0.5
3.6
V
V
LOGIC INPUT CURRENT
High
Low
IIH
IIL
−100
−100
+100
+100
µA
µA
LOGIC OUTPUT VOLTAGE
Low
High
VOL
VOH
0
1.4
0.4
1.8
V
V
When driving loads with complementary metal oxide
semiconductor (CMOS) 1.8 V interface
When driving loads with CMOS 3.3 V interface
2.4
3.3
V
LOGIC OUTPUT CURRENT
High Driving
Low Driving
IOH
IOL
1
1
2
2
mA
mA
Rev. A | Page 7 of 61
ADRF6821
Data Sheet
SERIAL PERIPHERAL INTERFACE (SPI) TIMING SPECIFICATIONS
Table 6.
Parameter
Symbol
Min
Typ
Max
Unit
TIMING REQUIREMENTS
SDI to SCLK Rising Edge Setup
SCLK Rising Edge to SDI Hold
Period of SCLK
CS Falling Edge to SCLK Rising Edge, Setup Time
SCLK Rising Edge to CS Rising Edge, Hold Time
SCLK Falling Edge to Valid Readback Data, SDIO or SDO (Not Shown in Figure 2)
SCLK
tDS
tDH
tCLK
tS
8
8
50
10
30
18
ns
ns
ns
ns
ns
ns
tC
tDV
Period of SCLK for a Logic High State
Period of SCLK for a Logic Low State
tHIGH
tLOW
25
25
ns
ns
SPI Timing Diagram
tDS
tHIGH
tS
tC
tCLK
tDH
tLOW
CS
DON’T CARE
DON’T CARE
SCLK DON’T CARE
SDIO DON’T CARE R/W A14 A13 A12 A11 A10
A9
A8
A7
A6
A5
D4
D3
D2
D1
D0
Figure 2. SPI Write (MSB First), 16-Bit Instruction, Timing Measurements
Rev. A | Page 8 of 61
Data Sheet
ADRF6821
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 7.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
Rating
VCC_LO1, VCC_LO2, VCC_3V3_I,
VCC_3V3_Q, VCC_IFMIX_I,
VCC_IFMIX_Q, VCCVCO_3V3,
VCCDIV_3V3, VCCFBDIV_3V3,
VCCLO_MIX_3V3,
VCCLO_AUX_3V3, VCCCP_3V3,
VCCPFD_3V3, VCCREF_3V3,
VBAT_DIG_3V3
−0.3 V to +3.6 V
Typical θJA and θJC are specified vs. the number of PCB layers.
The use of appropriate thermal management techniques is
recommended to ensure the maximum junction temperature
does not exceed the limits shown in Table 8.
VCM_I, VCM_Q
CS, SCLK, SDIO, SDO
−0.3 V to +3.3 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
2.5 V peak, ac-coupled
−0.3 V to +3.6 V
−0.3 V to +3.6 V
20 dBm
10 dBm, differential
125°C
−40°C to +105°C
Table 8. Thermal Resistance
Package Type
θJA
θJC
Unit
CP-56-161
RF_SEL0, RF_SEL1, RFBT_FB
RFIN_FB0, RFIN_FB1
RST, SLEEP
JEDEC 1s0p Board2
Not applicable 3.3
°C/W
°C/W
Cold Plate Only, No PCB3 Not applicable 2.8
JEDEC 2s2p Board2
29.3
Not applicable °C/W
VTUNE, CPOUT, REF_IN, DCL_BIAS
RF Input Power RFIN
EXT_LO_IN−, EXT_LO_IN+
Maximum Junction Temperature
Operating Temperature Range
(Measured at Paddle)
1 The maximum junction temperature of 125°C cannot be exceeded.
2 Per JEDEC JESD51-12.
3 For nonstandardized testing where the paddle of the device is directly
connected to a cold plate. This approach can be useful to estimate junction
temperature when the exact paddle temperature is known in the application.
Storage Temperature Range
−65°C to +150°C
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 9 of 61
ADRF6821
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VCM_Q
VDD_DIG
GND
1
2
3
4
5
6
7
8
9
42 VCCCP_3V3
41 CPOUT
40 GND
RFIN_FB0
GND
39 LO_OUT–
38 LO_OUT+
VCC_LO1
RFBT_FB
VCC_LO2
RF_SEL0
37 VCCLO_AUX_3V3
36 VCCLO_MIX_3V3
35 VCCFBDIV_3V3
34 VCCDIV_3V3
33 VCCVCO_3V3
32 EXT_LO_IN–
31 EXT_LO_IN+
30 VTUNE
ADRF6821
TOP VIEW
(Not to Scale)
RF_SEL1 10
RFIN_FB1 11
GND 12
SLEEP 13
VCM_I 14
29 DCL_BIAS
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO A GROUND
PLANE WITH LOW THERMAL IMPEDANCE.
Figure 3. Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
Mnemonic
VCM_Q
VDD_DIG
GND
Description
1
2
Q Channel VCM Input.
Digital VDD (1.8 V) Pin from On-Chip LDO.
Ground.
3, 5, 12, 16,
19, 52, 55
4
6
7
8
RFIN_FB0
VCC_LO1
RFBT_FB
VCC_LO2
RF_SEL0
RF_SEL1
RFIN_FB1
SLEEP
RF Input 0 Single-Pole, Double-Throw (SPDT), 50 Ω Single-Ended.
LO Path VCC.
RF Input Low Frequency Balun Connection. This pin requires a dc block to an external inductor.
LO Path VCC.
RF Input 0 Select.
9
10
11
13
14
15
17
18
20
21
22
23
24
25
26
RF Input 1 Select.
RF Input 1 SPDT, 50 Ω Single-Ended.
Pin Controllable Fast Turn On/Off (1.8 V and 3.3 V Compatible).
I Channel VCM Input.
VCM_I
VCC_3V3_I
IF_IOUT+
IF_IOUT−
VCC_IFMIX_I
VDCPL_I
VCC_IFMIX_I
LO_LCKDT
SCLK
I Channel 3.3 V Supply.
I Channel IF Positive Output.
I Channel IF Negative Output.
I Channel IF Amplifier VCC Supply.
I Channel Mixer Decoupling.
I Channel Mixer VCC Supply.
LO Lock Detect.
SPI Clock.
SDIO
SDO
SPI Data Input/Output in 3-Wire Mode. SPI data input in 4-wire mode.
SPI Data Output. SDO used in 4-wire mode only.
Rev. A | Page 10 of 61
Data Sheet
ADRF6821
Pin No.
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
53
54
56
Mnemonic
Description
CS
SPI Chip Select (N).
RST
Reset (Active Low).
DCL_BIAS
VTUNE
VCO Core Bias Decouple.
VTUNE Input.
Positive External LO Input.
Negative External LO Input.
VCC 3.3 V Supply.
LO Chain and Divider 3.3 V Supply.
PLL Feedback Divider 3.3 V Supply.
LO Mixer Output Buffer 3.3 V Supply.
LO External Output Buffer 3.3 V Supply.
Positive External LO Output.
Negative External LO Output.
Charge Pump Ground.
Charge Pump Output.
Charge Pump 3.3 V Supply.
PFD 3.3 V Supply.
Reference Input Buffer 3.3 V Supply.
Reference Input Buffer.
SPI 1.8 V LDO External Decouple Output.
EXT_LO_IN+
EXT_LO_IN−
VCCVCO_3V3
VCCDIV_3V3
VCCFBDIV_3V3
VCCLO_MIX_3V3
VCCLO_AUX_3V3
LO_OUT+
LO_OUT−
GND
CPOUT
VCCCP_3V3
VCCPFD_3V3
VCCREF_3V3
REF_IN
SPILDO_OUT_1V8
SDMLDO_OUT_1V8 Sigma-Delta Modulator (SDM) 1.8 V LDO External Decouple Output.
VBAT_DIG_3V3
VCC_IFMIX_Q
VDCPL_Q
VCC_IFMIX_Q
IF_QOUT−
IF_QOUT+
VCC_3V3_Q
EPAD
SPI and SDM LDO 3.3 V Input.
Q Channel Mixer VCC Supply.
Q Channel Mixer Decoupling.
Q Channel IF Amplifier VCC Supply.
Q Channel IF Negative Output.
Q Channel IF Positive Output.
Q Channel 3.3 V Supply.
Exposed Pad. The exposed pad must be connected to a ground plane with low thermal impedance.
Rev. A | Page 11 of 61
ADRF6821
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
All supply pins = 3.3 V, TA = 25°C, high-side LO injection for LO frequencies less than or equal to 1 GHz and equal to 2.8 GHz, low-side
LO injection for frequencies between 1 GHz and 2.8 GHz, internal LO, minimum attenuation setting (DSA setting of 0 dB), MIXER_GAIN_
PEAK = 0, VCM = 1.6 V, and 25 Ω matching resistors on I/Q differential outputs, unless otherwise noted. For linearity measurements, a tone
spacing of 75 MHz is used, unless otherwise noted. All losses from input and output traces and baluns are de-embedded from results.
14
12
10
8
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
+105°C
+27°C
–40°C
6
MIXER_GAIN_PEAK = 0
MIXER_GAIN_PEAK = 3
4
2
0
450
920
1390
1860
2330
2800
75
160
245
330
415
500
RF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 7. Gain Flatness vs. IF Frequency, Fixed LO Frequency of 2000 MHz,
75 MHz IF Frequency Window
Figure 4. Gain vs. RF Frequency for Various MIXER_GAIN_PEAK
(Register 0x003A, Bits[1:0]) Settings
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.0
0.8
14
12
10
8
0.6
LO = 1000MHz
LO = 2000MHz
LO = 2800MHz
0.4
0.2
0
6
–0.2
–0.4
–0.6
–0.8
–1.0
LO = 1000MHz
4
2
0
LO = 2000MHz
LO = 2800MHz
75
160
245
330
415
500
0
100
200
300
400
500
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 5. Gain vs. IF Frequency, RF Sweep with Fixed LO, RF to IF Roll-Off
Figure 8. Gain Flatness vs. IF Frequency for Various LOs, 75 MHz (Left Axis)
and 280 MHz (Right Axis) IF Frequency Window
1.0
0.9
0.8
0.7
0.6
0.5
0.4
14
13
12
11
+105°C
10
+27°C
0.3
+105°C
–40°C
+27°C
0.2
0.1
0
–40°C
9
8
280
324
368
412
456
500
500
940
1380
1820
2260
2700
IF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 6. Gain Flatness vs. IF Frequency, Fixed LO Frequency of 2000 MHz,
280 MHz IF Frequency Window
Figure 9. Output P1dB vs. RF Frequency
Rev. A | Page 12 of 61
Data Sheet
ADRF6821
45
40
35
30
25
20
15
10
5
14
13
12
11
10
9
MIXER_GAIN_PEAK = 0
MIXER_GAIN_PEAK = 3
LO = 1000MHz
LO = 2000MHz
LO = 2800MHz
8
0
600
0
100
200
300
400
500
1040
1480
1920
2360
2800
LO FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 10. Output P1dB vs. IF Frequency, RF Sweep with Fixed LO,
Various LO Frequency
Figure 13. Output IP3 vs. LO Frequency, Measured on −10 dBm for
Each Tone at the IF Output for Various MIXER_GAIN_PEAK
(Register 0x003A, Bits[1:0]) Settings
14
12
10
8
45
40
35
30
25
20
6
15
LO = 1000MHz
DSA = 0dB
4
2
0
LO = 2000MHz
LO = 2800MHz
DSA = 8dB
DSA = 15dB
10
5
0
1.2
1.4
1.6
(V)
1.8
2.0
600
1040
1480
1920
2360
2800
V
CM
LO FREQUENCY (MHz)
Figure 11. Output P1dB vs. Common-Mode Voltage (VCM), IF = 100 MHz
Figure 14. Output IP3 vs. LO Frequency for Various DSA Settings,
Measured on −10 dBm for Each Tone at the IF Output
45
40
35
30
25
20
45
40
35
30
25
20
+105°C
15
15
LO = 1000MHz
+27°C
LO = 2000MHz
–40°C
LO = 2800MHz
10
10
5
0
5
0
0
100
200
300
400
500
600
1040
1480
1920
2360
2800
IF FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 12. Output IP3 vs. LO Frequency, Measured on −10 dBm for Each
Tone at the IF Output for Various Temperature
Figure 15. Output IP3 vs. IF Frequency for Various LO Frequencies,
Measured on −10 dBm for Each Tone at the IF Output, Low Side LO for 1 GHz
Rev. A | Page 13 of 61
ADRF6821
Data Sheet
110
100
90
80
70
60
50
40
30
20
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
DIFFERENCE
PRODUCT
SUM
+105°C
+27°C
–40°C
PRODUCT
MIXER_GAIN_PEAK = 0
MIXER_GAIN_PEAK = 3
600
1040
1480
1920
2360
2800
0
100
200
300
400
500
LO FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 16. Output IP2 vs. LO Frequency for Various MIXER_GAIN_PEAK
(Register 0x003A, Bits[1:0]) Settings
Figure 19. HD2 vs IF Frequency, LO at 2000 MHz and POUT = −7 dBm
110
–10
DIFFERENCE
PRODUCT
–20
100
+105°C
+27°C
–40°C
–30
–40
90
80
70
60
–50
–60
–70
SUM
PRODUCT
50
40
30
20
DSA = 0dB
–80
DSA = 15dB
–90
–100
–110
600
1040
1480
1920
2360
2800
0
50
100
150
200
250
300
350
LO FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 17. Output IP2 vs. LO Frequency, Measured on −10 dBm for Each
Tone at the IF Output for Various DSA Settings
Figure 20. HD3 vs. IF Frequency, LO at 2000 MHz and POUT = −7 dBm
90
–10
DIFFERENCE
PRODUCT
–20
80
70
60
50
40
30
20
10
0
LO = 1000MHz
LO = 2000MHz
–30
–40
LO = 2800MHz
–50
SUM
PRODUCT
–60
–70
HD2
LO = 1000MHz
LO = 2000MHz
LO = 2800MHz
–80
–90
–100
–110
HD3
0
100
200
300
400
500
0
100
200
300
400
500
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 21. HD2 and HD3 vs. IF Frequency for Various LO Frequencies
Figure 18. Output IP2 vs. IF Frequency, RF Sweep with Fixed LO, Measured
on −10 dBm for Each Tone at the IF Output
Rev. A | Page 14 of 61
Data Sheet
ADRF6821
60
50
40
30
20
10
0
0
–10
–20
–30
–40
–50
–60
–70
–80
DSA = 0dB
DSA = 15dB
CHANNEL 1
LO = 1000MHz
LO = 2000MHz
LO = 2800MHz
CHANNEL 0
0
100
200
300
400
500
550
1000
1450
1900
2350
2800
IF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 22. Image Rejection vs. IF Frequency for Various LO Frequencies
Figure 25. RF to IF Leakage at IF Output
0
–10
–20
–30
–40
–50
–60
–70
–80
30
28
LO = 1000MHz
DSA = 0dB
DSA = 15dB
LO = 2000MHz
26
24
22
20
18
16
14
12
10
LO = 2800MHz
Q OUTPUT
I OUTPUT
1000
0
100
200
300
400
500
550
1450
1900
2350
2800
LO FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 23. Noise Figure vs. IF Frequency for Various LO Frequencies,
Double Side Band
Figure 26. LO to IF Leakage at IF Output
0
–30
–40
–50
–60
–70
–80
–90
DSA = 0dB
DSA = 15dB
–10
Q OUTPUT
I OUTPUT
–20
–30
–40
–50
–60
–70
DSA = 0dB
DSA = 15dB
450
920
1390
1860
2330
2800
550
1000
1450
1900
2350
2800
RF FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 24. Channel to Channel Isolation vs. RF Frequency
Figure 27. LO to RF Leakage vs. LO Frequency
Rev. A | Page 15 of 61
ADRF6821
Data Sheet
500
450
400
350
300
250
200
150
100
0
–2
PLL/VCO = 3.3V
RF/IF = 3.3V
–4
–6
–8
–10
–12
–14
–16
–18
–20
I OUTPUT
Q OUTPUT
450
920
1390
1860
2330
2800
0
100
200
300
400
500
LO FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 28. Supply Current vs. LO Frequency
Figure 30. Return Loss vs. IF Frequency, Differential with 25 Ω Series
Resistor on Each Leg, Measured with 100 Ω Differential
0
–5
–10
–15
–20
–25
–30
–35
–40
CHANNEL 0
CHANNEL 1
450
920
1390
1860
2330
2800
RF FREQUENCY (MHz)
Figure 29. Return Loss vs. RF Frequency for Channel 0 and Channel 1
Rev. A | Page 16 of 61
Data Sheet
ADRF6821
PHASE-LOCKED LOOP (PLL) PERFORMANCE
All supply pins = 3.3 V, TA = 25°C, fPFD = 30.72 MHz, fREF = 122.88 MHz, 20 kHz loop filter, measured at LO output, unless otherwise noted.
0
–10
–60
–70
+105°C
+27°C
–40°C
–20
–30
–90
–40
–80
–50
–60
–100
–110
–120
–130
–140
–150
–160
–170
–70
–90
–80
–100
–110
–120
–130
–140
–150
–160
–170
0.001
0.01
0.1
1
10
100
0.001
0.01
0.1
1
10
100
OFFSET FREQUENCY (MHz)
OFFSET FREQUENCY (MHz)
Figure 31. Open-Loop VCO Phase Noise vs. Offset Frequency for Various
Temperatures
Figure 34. Closed-Loop Phase Noise vs. Offset Frequency for fLO = 2350 MHz
0
–60
–70
–10
VCO = 4GHz
–20
–30
VCO = 4.7GHz
VCO = 5.6GHz
VCO = 6.8GHz
–90
–40
–80
–50
–60
–100
–110
–120
–130
–140
–150
–160
–170
–70
–90
–80
–100
–110
–120
–130
–140
–150
–160
–170
0.001
0.01
0.1
1
10
100
0.001
0.01
0.1
1
10
100
OFFSET FREQUENCY (MHz)
OFFSET FREQUENCY (MHz)
Figure 32. Open-Loop VCO Phase Noise vs. Offset Frequency for Various
VCO Frequencies
Figure 35. Closed-Loop Phase Noise vs. Offset Frequency for fLO = 2720 MHz
–60
–70
–170
–180
–190
–200
–210
–220
–230
–240
–250
–260
–270
+105°C
+27°C
–40°C
–90
–80
–100
–110
–120
–130
–140
–150
–160
–170
FRACTIONAL
FLICKER
1390
0.001
0.01
0.1
1
10
100
450
920
1860
2330
2800
OFFSET FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 33. Closed-Loop Phase Noise vs. Offset Frequency for fLO = 1765 MHz
Figure 36. PLL Figure of Merit (FOM) vs. LO Frequency
Rev. A | Page 17 of 61
ADRF6821
Data Sheet
–50
–60
–50
–60
+105°C
+27°C
–40°C
+105°C
+27°C
–40°C
–70
–80
10kHz
–90
–70
–100
–110
–120
–130
–140
–150
–160
–170
–80
100kHz
–90
1MHz
–100
–110
10MHz
450
920
1390
1860
2330
2800
450
920
1390
1860
2330
2800
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 37. Closed-Loop LO Phase Noise vs. LO Frequency for Various
Offset Frequencies and for Various Temperatures
Figure 40. Reference Spurs, 2 × fPFD Offset vs. LO Frequency
1.0
–50
3 × fPFD
4 × fPFD
5 × fPFD
6 × fPFD
7 × fPFD
0.9
+105°C
+27°C
–60
–70
–40°C
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–80
–90
–100
–110
450
920
1390
1860
2330
2800
450
920
1390
1860
2330
2800
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 38. 100 Hz to 10 MHz Integrated Phase Noise with Spurs vs.
LO Frequency
Figure 41. Reference Spurs, 3 × fPFD and Higher Offset vs. LO Frequency
0
–10
–20
–50
+105°C
+27°C
–60
–40°C
–70
HD2
HD3
–80
–90
–30
–40
–50
–60
–100
–110
450
920
1390
1860
2330
2800
1000
1360
1720
2080
2440
2800
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 39. Reference Spurs, 1 × fPFD Offset vs. LO Frequency
Figure 42. LO HD2 and HD3 vs. LO Frequency
Rev. A | Page 18 of 61
Data Sheet
ADRF6821
2101.5
2101.0
2100.5
2100.0
2099.5
2099.0
2098.5
0
–5
–10
–15
–20
–25
–30
–35
–40
EXTERNAL LO INPUTS
AUXILIARY LO OUTPUTS
0
100
200
300
400
500
600
900
1840
2180
3720
4660
5600
TIME (µs)
LO FREQUENCY (MHz)
Figure 43. LO Frequency Settling Time, LO = 2.1 GHz
Figure 44. Return Loss vs. LO Frequency for Auxiliary LO Outputs and
External LO Inputs
Rev. A | Page 19 of 61
ADRF6821
Data Sheet
THEORY OF OPERATION
RF INPUT SWITCH
The ADRF6821 integrates many of the essential building blocks
for a high bandwidth quadrature demodulator and receiver,
especially for the feedback downconverter path for the digital
predistortion in cellular base stations. The main features include
two single-pole, double-throw (SPDT) RF input switches, a
balun, a variable RF attenuator, a pair of active mixers, and two
baseband buffers. Additionally, the local oscillator (LO) signals
for the mixers are generated by a fractional-N synthesizer and a
multicore voltage controlled oscillator (VCO), covering an octave
frequency range with low phase noise. A pair of flip-flops then
divides the LO frequency by two and generates the in phase and
quadrature phase LO signals to drive the mixers. The synthesizer
uses a fractional-N phase-locked loop (PLL) with additional
frequency dividers to enable continuous LO coverage from
450 MHz to 2800 MHz.
The ADRF6821 incorporates two SPDT switches, which allow
one RF input to be selected while the other RF input can be
correctly terminated to 50 Ω. Selection of the desired RF input
is achieved externally via two control pins or serially via register
writes to the SPI. When compared to the serial write approach,
pin control allows faster switching between the RF inputs. Using
the RF_SEL0 and RF_SEL1 pins (Pin 9 and Pin 10, respectively),
the RF input can be switched from one channel to the other
quickly and settle the IF output within 2 µs. When the input is
controlled via the SPI serial port, the time for the serial data
transfer must also be considered and is dependent on the serial
interface clock rate.
The SEL_RFSW_SPI_CONTROL bit (Register 0x0030, Bit 6)
selects whether the RF input switch is controlled via the external
pins or via the SPI (see Table 10). By default at power-up, the
device is configured for pin control. In serial mode control,
writing to the RFSW_SEL0 bit (Register 0x0030, Bit 4) allows
selection of RF Input 0 and writing to the RFSW_SEL1 bit
(Register 0x0030, Bit 5) allows selection of RF Input 1. If only
one RFINx port is used, the unused RF input must be properly
terminated to improve isolation. It is recommended to use a dc
blocking capacitor to GND as termination. Figure 45 shows the
recommended configuration when only RFIN_FB0 is employed.
The signal path through the device begins at one of two RF
inputs, RFIN_FB0 and RFIN_FB1, selected by the RF switches.
The selected single-ended input converts to a differential signal
via the integrated balun. The differential RF signal attenuates to
an optimal input level via the digital step attenuator with 15 dB
of attenuation range in 1 dB steps. The RF signal then mixes
with the LO signal in the Gilbert cell mixers down to an
intermediate frequency (IF) or baseband. From the mixer, the
signal passes through a wideband low-pass filter to remove the
higher order mixing terms, followed by a fixed gain linear IF
amplifier.
ADRF6821
RFIN_FB0
4
The different sections of the ADRF6821 are controlled through
registers programmable via a serial peripheral interface (SPI).
50Ω
The EN_ANALOG_MASTER bit (Register 0x0020, Bit 1) is the
master enable for all enables related to the RF switch, attenuator,
mixer, IF amplifiers, divider, and LO drivers. This bit does not
control any of the enables related to LO generation blocks.
RFIN_FB1
100pF
11
50Ω
Figure 45. Terminating the Unused Port of the ADRF6821
Table 10. RF Input Selection1
SEL_RFSW_SPI_CONTROL Bit,
(Register 0x0030, Bit 6)
RFSW_SEL0 Bit,
(Register 0x0030, Bit 4)
RFSW_SEL1 Bit,
(Register 0x0030, Bit 5)
RF_SEL0 and RF_SEL1 Pins
RF Input Pin
RFIN_FB0
RFIN_FB1
RFIN_FB0
RFIN_FB1
0
0
1
1
X
X
1
0
X
X
0
1
RF_SEL0
RF_SEL1
X
X
1 X means don’t care.
Rev. A | Page 20 of 61
Data Sheet
ADRF6821
At power-up, depending on the whether high-side or low-side
injection of the LO frequency is applied, the I channel can
either lead or lag the Q channel by 90°. When the RF frequency
is greater than the LO frequency (low-side LO injection), the
Q channel leads the I channel. On the contrary, if the RF
frequency is less than the LO frequency (high-side LO
injection), the I channel leads the Q channel by 90°.
BALUN
The ADRF6821 integrates a balun operating over a 450 MHz to
2800 MHz frequency range. The wideband balun offers the
benefit of ease of drivability with single-ended, 50 Ω RF inputs,
and the single-ended to differential conversion of the integrated
balun provides additional common-mode noise rejection.
RF ATTENUATOR
LOW-PASS FILTERS (LPF) AND IF AMPLIFIERS
The RF digital step attenuator follows the balun, and the
attenuation range is 0 dB to 15 dB with a step size of 1 dB.
The ATTEN_DSA bits (Register 0x0031, Bits[5:2]) in the
DSA_CONTROL register determine the setting of the RF
digital step attenuator. The EN_DSA (Register 0x0031, Bit [0])
bit enables the RF attenuator.
From the mixer, the IF or baseband outputs pass through an
integrated adjustable LPF to remove the unwanted mixing
product. The LPF bandwidth is adjustable over four steps, as
listed in Table 12.
Table 12. LPF Bandwidth Selection
EN_LPF_LB_I
(Register 0x0060, Bit 0) (Register 0x0060, Bit 1) Bandwidth
EN_LPF_LB_Q
LPF
ACTIVE MIXER
After the RF digital step attenuator, the RF signal is split and
provided to a pair of double balanced, Gilbert cell active mixers.
The RF signal is then downconverted by the on-chip LO at the
mixer, resulting in a baseband output. Enable the mixer and the
common-mode controls as listed in Table 11.
0
0
1
1
0
1
0
1
1 GHz
750 MHz
500 MHz
250 MHz
From the LPF, the IF or baseband signal passes to a linear
output amplifier to drive the baseband output pins (IF_IOUT+,
IF_IOUT−, IF_QOUT−, and IF_QOUT+). The IF amplifier
provides the overall gain for the ADRF6821 and, with the
required 25 Ω series resistors, allows the ADRF6821 to drive
a 100 Ω load directly. The ADRF6821 can be interfaced to a
variety of analog-to-digital converters (ADCs), and the
common-mode output can be adjusted with the external VCM
pin. The IF amplifiers are enabled through the EN_IFAMP_I
bit (Register 0x0070, Bit 0) and the EN_IFAMP_Q bit
(Register 0x0070, Bit 1).
Table 11. Demodulator Enable Registers
Register Address
Value Description
0x0032
0x0040
0x0033
0x0034
0x3E
0x0F
0x2D
0x2D
Demodulator enables
Common-mode control enables
Mixer LO common-mode control
Mixer output stage common-
mode control
The ADRF6821 provides a gain peaking circuit to increase the
gain for high RF. The amount of gain peaking is controlled by
the MIXER_GAIN_PEAK bits (Register 0x003A, Bits[1:0]).
Note that increased gain leads to slight degradation of the
linearity performance.
LO GENERATION BLOCK
The ADRF6821 supports the use of both internal and external
LO signals for the mixers. The internally generated or externally
supplied 2× LO signal is fed to the quadrature divider. The
quadrature divider block divides the 2× LO frequency by 2 and
then generates two LO signals with a 90° phase difference.
The ADRF6821 uses dc compensation digital-to-analog converters
(DACs) for both I and Q outputs. DC compensation covers a
range of 40 mV. Control the dc compensation value via the
CODE_DC_IDAC_RF0 bits (Register 0x0051) for the I output
and the CODE_DC_QDAC_RF0 bits (Register 0x0052) via the
Q output for Channel 0. For Channel 1, use the CODE_DC_
IDAC_RF1 bits (Register 0x0053) for the I output and the
CODE_DC_QDAC_RF1 bits (Register 0x0054) for the Q output.
The control words are in signed magnitude format and eight bits
wide. The effective least significant bit (LSB) is approximately
0.5 mV.
The internal 2× LO is generated by an on-chip VCO, which is
tunable over a frequency range of 4000 MHz to 8000 MHz. The
output of the VCO is phase locked to an external reference clock
through a fractional-N PLL that is programmable through the SPI
control registers. To produce 2× LO signals over the 900 MHz to
5600 MHz frequency range to drive the LO divider, steer the
VCO outputs through an output divider. Alternatively, an
external signal can be used with the dividers to generate the
2× LO signals to the quadrature divider and the demodulators.
I AND Q POLARITY
The ADRF6821 offers the flexibility of specifying the polarity of
the I and Q outputs, where I can lead Q or vice versa. By addressing
SEL_LODRV_PREDRVI_POL (Register 0x0080, Bit 1) or
SEL_LODRV_PREDRVQ_POL (Register 0x0080, Bit 2), both
the I and Q outputs can be inverted from their default configuration.
The flexibility of specifying the polarity becomes important
when the I and Q outputs are processed simultaneously in the
complex domain, I + jQ.
Rev. A | Page 21 of 61
ADRF6821
Data Sheet
Internal LO Mode
PLL Frequency Programming
For internal LO mode, the ADRF6821 uses the on-chip PLL and
VCO to synthesize the frequency of the LO signal. The PLL,
shown in Figure 46, consists of a reference path, phase and
frequency detector (PFD), charge pump, and a programmable
integer divider with prescaler. The reference path takes in a
reference clock and it is divided down by a value calculated with
a reference (R) divider together with a doubler bit and a
prescaler bit. Then the divided down reference signal passes to
the PFD. The PFD compares this signal to the divided down
signal from the VCO. The PFD sends an up or down signal to
the charge pump if the VCO signal is slow or fast compared to the
reference frequency. The charge pump sends a current pulse to
the off-chip loop filter to increase or decrease the tuning voltage
(VTUNE).
The INT, FRAC1, FRAC2, and MOD values, in conjunction
with the R counter, make it possible to generate output frequencies
that are spaced by fractions of the PFD frequency (fPFD).
Calculate the VCO frequency (VCOOUT) by
VCOOUT = fPFD × N
where:
(1)
VCOOUT is the output frequency of the VCO (without using
the output divider).
f
f
PFD is the frequency of the phase frequency detector. Calculate
PFD by
PFD = REFIN × ((1 + D)/(R × (1 + T)))
f
(2)
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit (Register 0x120E, Bit 3).
R is the preset divide ratio of the binary 7-bit programmable
reference counter, 1 to 255, (Register 0x120C, Bits[6:0]).
T is the REFIN divide by 2 bit, set to 0 or 1, (Register 0x120E, Bit 0).
N is the desired value of the feedback counter. N compromises
The ADRF6821 integrates multiple VCO cores covering an
octave range of 4 GHz to 8 GHz. The suitable VCO is selected
with the autotune functionality built into the chip. After the
user determines the necessary register values, a write to the
INT_L register (Address 0x1200) initiates the autotune process.
FRAC2
FRAC1+
LO Frequency and Dividers
MOD
(3)
N = INT +
where:
16,777,216
The signal coming from the VCO or the external LO inputs
passes through a series of dividers before it is buffered to drive
the demodulator. The programmable, divide by 2 stages divide
the frequency of the incoming signal by 1, 2, 4, and 8 before
reaching the quadrature divider that further divides the signal
frequency by 2 to generate the in phase and quadrature phase
LO signals for the mixers. The LO control bits (OUT_DIVRATIO,
Register 0x1414, Bits[4:0]) needed to select the different LO
frequency ranges are listed in Table 13.
INT is the 16-bit integer value (23 to 32,767 for the prescaler in
4/5 mode, 75 to 65,535 for the prescaler in 8/9 mode) referenced
with Register 0x1201 and Register 0x1200. The recommended
setting for the prescaler is 8/9 mode, and it is set by enabling
PRE_SEL (Register 0x120B, Bit 1).
FRAC1 is the 24-bit numerator of the primary modulus (0 to
16,777,215) referenced with Register 0x1204, Register 0x1203,
and Register 0x1202.
Table 13. Output Divide Ratio for Frequency Ranges
FRAC2 is the numerator of the 14-bit auxiliary modulus (0 to
16,383) referenced with Register 0x1234, Bits[5:0] and
Register 0x1233.
2× LO Frequency OUT_DIVRATIO
VCO
(Register 0x1414, Bits[4:0]) Frequency
(MHz)
900 to 1000
1000 to 2000
2000 to 4000
4000 to 5600
01000
00100
00010
00001
(2× LO) × 8
(2× LO) × 4
(2× LO) × 2
(2× LO) × 1
MOD is the programmable, 14-bit auxiliary fractional modulus
(2 to 16,383), referenced with Register 0x1209, Bits[5:0] and
Register 0x1208.
EXT_LO_IN+ 31
32
SEE PLL FREQUENCY
PROGRAMMING SECTION
EXT_LO_IN–
REGISTER 0x1414
[4:0]
OUT
DIVIDER
DIVIDE
BY 2
REF_IN
EXTERNAL
LOOP FILTER
R
CPOUT
VTUNE
30
TO DEMODULATOR
45
PFD
CHARGE
PUMP
DIVIDER
41
SEE PLL FREQUENCY
PROGRAMMING SECTION
SEE EXTERNAL
LO MODE
SECTION
FRAC2
FRAC1 +
PRESCALER
MOD
16,777,216
N = INT +
REGISTER 0x120B
Figure 46. PLL/VCO Block Diagram
Rev. A | Page 22 of 61
Data Sheet
ADRF6821
Equation 3 results in a very fine frequency resolution with no
residual frequency error. To apply this formula, take the
following steps:
PLL Lock Time
The time it takes to lock the PLL after the last register is written
into two parts: VCO band calibration and loop settling.
1. Calculate N by VCOOUT/fPFD
.
After writing to the last register, the PLL automatically performs
a VCO band calibration to choose the correct VCO band. This
calibration requires approximately 200 µs. After calibration
completes, the feedback action of the PLL causes the VCO to
eventually lock to the correct frequency. The speed with which
this lock occurs depends on the small signal settling of the loop.
Settling time, after calibration, depends on the PLL loop filter
bandwidth. With a 20 kHz loop filter bandwidth, settling time is
approximately 200 µs.
2. The integer value of this number forms INT.
3. Subtract the INT value from the full N value.
4. Multiply the remainder by 224.
5. The integer value of this number forms FRAC1.
6. Calculate MOD based on the channel spacing (fCHSP) by
MOD = fPFD/GCD(fPFD, fCHSP
)
(4)
where:
GCD(fPFD, fCHSP) is the greatest common divider of the PFD
frequency and the desired channel spacing frequency.
Lock Detect Control
The ADRF6821 provides two ways of observing lock detection.
Lock detection can be monitored from a dedicated register,
LOCK_DETECT (Register 0x124D, Bit 0). Lock detection can
also be monitored through the dedicated LO_LCKDT pin (Pin 23).
7. Calculate FRAC2 by the following equation:
FRAC2 = ((N − INT) × 224 − FRAC1)) × MOD
(5)
The FRAC2 and MOD fraction result in outputs with zero
frequency error for channel spacings when
Required PLL/VCO Settings and Register Write Sequence
f
PFD/GCD(fPFD/fCHSP) < 16,383
where:
PFD is the frequency of the phase frequency detector.
GCD is a greatest common denominator function.
CHSP is the desired channel spacing frequency.
(6)
Configure the PLL registers as described in the PLL Frequency
Programming section to achieve the desired frequency, and
the last write must be to Register 0x1200 (INT_L). When
Register 0x1200 is programmed, an internal VCO calibration
initiates, which is the last step to locking the PLL.
f
f
External LO Mode
After determining the necessary register values for PLL, set the
SD_EN_FRAC0 bit (Register 0x122A, Bit 5) to 1. In the integer
mode (when FRAC = 0), set the SD_EN_OUT_OFF bit
(Register 0x122A, Bit 4) to 1. In the same manner, set the
SD_EN_OUT_OFF bit to 0 for fractional mode (that is, when
FRAC ≠ 0).
The external LO frequency range is 900 MHz to 5600 MHz and
2× LO signal is used with the internal quadrature divider. To
configure for external LO mode, write the following register
sequence and apply the differential LO signals to Pin 31
(EXT_LO_IN+) and Pin 32 (EXT_LO_IN−).
It is recommended to set the charge pump current to be 2.4 mA,
by setting the CP_CURRENT bit (Register 0x122E, Bits[3:0]) to
8. With a 20 kHz loop filter, the charge pump current setting
results in an optimized performance.
Table 14. Register Settings for External LO Mode
Register Required Value Description
0x120B
0x122D
0x1240
0x1217
0x121F
0x1021
0x1414
0x00
0x00
0x03
0x00
0x40
0xD8
0xA1
Disable feedback divider
Disable PFD and charge pump (CP)
Disable VCO adjust
Set VCO select to a low value
Disable calibration
Bleed Setting
The PFD circuitry compares the PFD and divided down VCO
signals. The ADRF6821 employs a bleed circuit to put the PFD
circuit in the linear operation region. The bleed circuit introduces a
delay to the incoming PFD signal, indicated as PFD_OFFSET in
Equation 7. Calculate the bleed current, BICP, (Register 0x122F,
Bits[7:0]), from the desired PFD_OFFSET, as shown in
Equation 7.
Disable PLL blocks
Use external LO
The EXT_LO_IN+ and EXT_LO_IN− input pins must be
ac-coupled. When not in use, leave the EXT_LO_IN+ and
EXT_LO_IN− pins unconnected.
BICP = Integer(round(float(ICP × PFD_OFFSET ×
f
PFD)/960)/255))
where:
CP is the charge pump current.
The recommended PFD_OFFSET for the 20 kHz loop filter is 2 ns.
(7)
I
Rev. A | Page 23 of 61
ADRF6821
Data Sheet
Quadrature Divider
SERIAL PERIPHERAL INTERFACE (SPI)
The quadrature divider block divides the 2× LO frequency
generated by either the internal PLL and VCO or the external
input by 2. Next, the quadrature divide block generates two
LO signals with a 90° phase difference. To enable the divider,
disable the bits, EN_IBIASGEN (Register 0x0090, Bit 0),
EN_DIVPATH_BUF (Register 0x0090, Bit 1), and
EN_DIVPATH_QUADDIV (Register 0x0090, Bit 2). Two
separate LO drivers take these LO signals and feed them to the
mixers. LO driver paths are enabled via the following registers:
The SPI of the ADRF6821 allows the user to configure the
device for specific functions or operations through a structured
register space provided inside the chip. This interface provides
users with added flexibility and customization. Addresses are
accessed via the SPI and can be written to or read from the SPI.
The serial peripheral interface consists of four control lines:
CS
SCLK, SDIO, SDO, and . The serial clock (SCLK) is the serial
shift clock, and it synchronizes the serial interface reads and
writes. SDIO is the serial data input or the serial data output
depending on the instruction sent and the relative position in
•
•
•
•
EN_LODRV_DRVI (Register 0x0090, Bit 3)
EN_LODRV_DRVQ (Register 0x0090, Bit 4)
EN_LODRV_PREDRVI (Register 0x0090, Bit 5)
EN_LODRV_PREDRVQ (Register 0x0090, Bit 6)
CS
the timing frame. Chip select bar ( ) is an active low control
CS
that gates the read and write cycles. The falling edge of
conjunction with the rising edge of SCLK determines the start
CS
in
of the frame. When
is high, all SCLK and SDIO activity is
REGISTER WRITE SEQUENCE
ignored. See Table 6 for the serial timing and its definitions.
The proper register write sequence starts with locking the LO
frequency or enabling the external LO inputs. After ensuring that
the local oscillator is locked in either the internal PLL/VCO or
the external LO source, enable the LO_OE bit (Register 0x1414,
Bit 6). After enabling the LO_OE bit, the RF and IF blocks can
be enabled as defined in the Theory of Operation section.
The ADRF6821 protocol consists of a read/write followed by
16 register address bits and 8 data bits. Both the address and
data fields are organized with the most significant bit (MSB)
first and end with the least significant bit (LSB).
The SPI and general-purpose input/output (GPIO) interfaces of
the ADRF6821 provides two options for the logic voltage levels,
1.8 V and 3.3 V. The interfaces use 1.8 V logic levels as the
default. Enable SPI_18_33_SEL (Register 0x0020, Bit 0) and
SPI_1P8_3P3_CTRL (Register 0x1401, Bit 4) for 3.3 V compatible
logic levels. See Table 6 for the SPI specifications.
Rev. A | Page 24 of 61
Data Sheet
ADRF6821
APPLICATIONS INFORMATION
BASIC CONNECTIONS
39Ω
39Ω
0.1µF
0.1µF
25Ω
25Ω
35.7Ω
35.7Ω
Q OUTPUT
TC 1-1-13MX+
54 53
45
220Ω
CPOUT
4300pF
VTUNE
4300pF
DC DAC
220Ω
100pF
0.12µF
/R
PFD
/N
4
RF INPUT 0
RFIN_FB0
41 CPOUT
CP
Δ-Σ
9
RF_SEL0
30
VTUNE
0
RF_SEL1 10
100pF
÷2
EX LO INPUT
÷
90
EX_LO_IN–
32
31
TCM 1-8 3X+
EX_LO_IN+
100pF
100pF
RFIN_FB1
11
RF INPUT 0
SPI
DC DAC
17 18
24 25 26 27
39Ω
0.1µF
0.1µF
25Ω
25Ω
35.7Ω
I OUTPUT
TC 1-1-13MX+
35.7Ω
39Ω
Figure 47. Typical Application Circuit
Table 15. Typical Connections
Pin No.
RF Inputs
4, 11
Mnemonic
Description
Basic Connection
RFIN_FB0, RFIN_FB1
RF inputs
The single-ended RF inputs have a 50 Ω impedance.
These pins must be ac-coupled. Terminate unused
RF inputs with a dc blocking capacitor to ground
to improve isolation. Refer to the Layout section
for the recommended PCB layout.
RF Balun Optimization
7
RFBT_FB
RF balun tuning inductor
RF select control pins
Connect the balun tuning inductor (LTUNE) to ground.
GPIOs
9, 10
RF_SEL0, RF_SEL1
Active high. 1.8 V and 3.3 V logic level compatible.
See the Theory of Operation section for RF select
pin use.
13
SLEEP
Sleep mode enable pin
Active high. 1.8 V and 3.3 V logic level compatible.
Rev. A | Page 25 of 61
ADRF6821
Data Sheet
Pin No.
Mnemonic
Description
Basic Connection
3.3 V RF/IF Power
15, 56
VCC_3V3_I, VCC_3V3_Q
Supply for DSA and RF
switches
Decouple these power supply pins to ground
using 100 pF, 0.1 µF, and 10 µF capacitors. Place
the decoupling capacitors close to these pins.
6, 8
VCC_LO1, VCC_LO2
LO path to mixer supply
Mixer supply
Decouple these power supply pins to ground
using 100 pF and 0.1 µF capacitors. Place the
decoupling capacitors close to these pins.
22, 49
VCC_IFMIX_I,
VCC_IFMIX_Q
20, 51
VCC_IFMIX_I,
VCC_IFMIX_Q
IF amplifier supply
VCM adjust pins
VCM Input
1, 14
VCM_Q, VCM_I
Decouple the VCM input pins to ground using
100 pF and 0.1 µF capacitors and connect these
pins to the same supply domain as the
VCC_IFMIX_Q and VCC_IFMIX_I pins. Place the
decoupling capacitors close to the pins. Place a
resistive divider to divide the supply voltage into
two. Use 5.1 kΩ (or similar) for resistive divider
component values.
Decoupling
2
VDD_DIG
Decoupling pin for the
internal LDO to supply the
internal digital circuits
Decouple these pins to ground using 100 pF and
0.1 µF capacitors. Place the decoupling capacitors
close to these pins.
21, 50
VDCPL_I, VDCPL_Q
Decoupling pins for I and Q
channels
IF Outputs
17, 18, 53, 54
IF_IOUT+, IF_IOUT−,
IF_QOUT−, IF_QOUT+
I and Q outputs
Place 25 Ω resistors in series for each differential
leg. The differential I/Q output impedance
together with the series 25 Ω resistors becomes
60 Ω. For optimized performance, the 60 Ω output
impedance must be terminated with a 100 Ω load.
3.3 V PLL/VCO Power
33
34
VCCVCO_3V3
VCCDIV_3V3
VCO 3.3 V supply
Decouple these power supply pins to ground using
100 pF and 0.1 µF capacitors. Place the decoupling
capacitors close to the pins. Employ ferrite beads
to provide isolation between the PLL/VCO supply
pins. Beware of the series resistance of the ferrite
beads and try to minimize the voltage drop.
LO chain and divider 3.3 V
supply
35
36
37
VCCFBDIV_3V3
VCCLO_MIX_3V3
VCCLO_AUX_3V3
PLL feedback divider 3.3 V
supply
LO mixer output buffer 3.3 V
supply
LO external output buffer
3.3 V supply
42
43
44
VCCCP_3V3
VCCPFD_3V3
VCCREF_3V3
Charge pump 3.3 V supply
PFD 3.3 V supply
Reference input buffer 3.3 V
supply
48
VBAT_DIG_3V3
SPI and SDM LDO 3.3 V
supply
PLL/VCO
23
29
30
LO_LCKDT
DCL_BIAS
VTUNE
LO lock detect
VCO core bias decouple
VTUNE input
Decouple this pin to ground using a 0.1 µF capacitor.
This pin is driven by the output of the loop filter;
its nominal input voltage range is 1.5 V to 2.5 V.
41
45
CPOUT
REF_IN
Charge pump output
Reference input buffer
Connect this pin to the VTUNE pin through the
loop filter.
The nominal input level of this pin is 1 V p-p. The
input range is 10 MHz to 250 MHz. This pin is
internally biased and must be ac-coupled and
terminated externally with a 50 Ω resistor. Place
the ac coupling capacitor between the pin and
Rev. A | Page 26 of 61
Data Sheet
ADRF6821
Pin No.
Mnemonic
Description
Basic Connection
the resistor.
46
47
SPILDO_OUT_1V8
SDMLDO_OUT_1V8
SPI 1.8 V LDO external
decouple output
Decouple these pins to ground using 100 pF and
0.1 µF capacitors. Place the decoupling capacitors
close to the pins.
SDM 1.8 V LDO external
decouple output
Auxiliary LO Output
38, 39
LO_OUT+, LO_OUT−
LO outputs
The differential output impedance of the buffer of
the LO outputs is 50 Ω.
External LO Inputs
31, 32
EXT_LO_IN+,
EXT_LO_IN−
External LO inputs
The differential input impedance of the buffer of
the external LO inputs is 100 Ω.
Serial Peripheral Interface
24
25
SCLK
SDIO
SPI clock
1.8 V and 3.3 V compatible logic levels.
SPI data input/output in 3-wire 1.8 V and 3.3 V compatible logic levels.
mode and SPI data input in
for 4-wire mode
26
SDO
SPI data output for 4-wire
mode and this pin is not used
for 3-wire mode
1.8 V and 3.3 V compatible logic levels.
27
CS
SPI chip select
Active low; 1.8 V and 3.3 V compatible logic levels
Active low; 1.8 V and 3.3 V compatible logic levels
Connect these pins to the ground of the PCB.
Reset
28
RST
Reset
Ground
3, 5, 12, 16, 19, 52, 55
40
GND
GND
Ground
Charge pump ground
Do not connect this pin to the paddle ground,
connect this pin to the PCB ground.
Exposed Pad
EPAD
Exposed Pad
The exposed pad is on the bottom of the package.
The exposed pad must be soldered to ground.
Rev. A | Page 27 of 61
ADRF6821
Data Sheet
Figure 49 and Figure 50 illustrate the effect of the LPF on the RF
to IF leakage and LO to IF leakage.
LOW-PASS FILTER BANDWIDTH SELECTION
The ADRF6821 incorporates an on-chip, third-order, low-pass
filter (LPF) between the demodulator and the output buffer. The
filter has four different bandwidth settings. The EN_LPF_LB_I
(Register 0x0060, Bit 0) and the EN_LPF_LB_Q (Register 0x0060,
Bit 1) bits enable various LPF bandwidth modes, as detailed in
Table 12.
0
1000MHz BANDWIDTH
750MHz BANDWIDTH
500MHz BANDWIDTH
250MHz BANDWIDTH
–10
–20
–30
–40
–50
–60
–70
The ADRF6821 incorporates a wideband buffer at the I and Q
outputs that poses a challenge for the linearity of the overall
RFIC. For RF and LO frequencies lower than 1000 MHz, the
mixing product, RF + LO, is amplified by the wideband buffer
and, in turn, deteriorates the overall linearity. The on-chip LPF
can improve the leakage rejection of the high frequency mixing
product. Depending on the I/Q bandwidth requirement of the
system, the LPF can be set to lower bandwidths to provide
rejection at RF and LO frequencies. Table 16 can determine the
LPF bandwidth according to RF and LO frequency of operation.
450
920
1390
1860
2330
2800
RF FREQUENCY (MHz)
Figure 49. RF to IF Rejection for RF Frequency at 100 MHz and a Low-Pass
Filter Setting of 250 MHz
0
Table 16. LPF Bandwidth Selection for Various RF and LO
Frequencies
1000MHz BANDWIDTH
750MHz BANDWIDTH
500MHz BANDWIDTH
–10
250MHz BANDWIDTH
LO Frequency
(MHz)
LPF Bandwidth
Setting (MHz)
EN_LPF_LB_I,
EN_LPF_LB_Q
–20
–30
–40
–50
–60
–70
–80
450 to 1000
1000 to 1200
1200 to 2000
2000 to 2800
250
500
750
1000
1, 1
1, 0
0, 1
0, 0
Moreover, the on-chip LPF can improve the RF to IF and LO to
IF leakage performance for RF and LO frequencies higher than
1 GHz. However, note the gain flatness degradation with the use
of various LPF settings (see Figure 48).
450
920
1390
1860
2330
2800
14
LO FREQUENCY (MHz)
Figure 50. LO to IF Rejection for LO Frequency at 100 MHz and a Low-Pass
Filter Setting of 250 MHz
12
10
8
6
4
1000MHz BANDWIDTH
750MHz BANDWIDTH
2
500MHz BANDWIDTH
250MHz BANDWIDTH
300 400
IF FREQUENCY (MHz)
0
0
100
200
500
Figure 48. Gain vs. IF Frequency for Various Low-Pass Filter Settings,
LO = 2000 MHz
Rev. A | Page 28 of 61
Data Sheet
ADRF6821
90
80
70
60
50
40
30
20
10
I/Q OUTPUT LOADING
By design, the ADRF6821 has an I/Q output impedance of 10 Ω
and it is optimized to perform with an external 25 Ω in each
differential leg. External resistors increase the output impedance
and with the external 25 Ω, the total differential output
impedance equals 60 Ω. When terminated with a 100 Ω differential
load, the return loss is less than −10 dB for a wide range of IF
frequencies.
ADRF6821
I/Q OUTPUTS
25Ω
100ꢀ
200ꢀ
10Ω
25Ω
500
960
1420
1880
2340
2800
LO FREQUENCY (MHz)
Figure 54. Output IP2 (OIP2) vs. LO Frequency for Different Loads
Z
LOAD
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–60
Figure 51. IF Output Schematic
–70
Different application circuits can require various loading
conditions for the I and Q outputs. Therefore, it is important
to understand the effect of I and Q output loading on the
performance characteristics, such as output IF gain, output IP3,
output IP2, HD2 and HD3. Figure 53 to Figure 55 illustrates the
effect of output loading on these characteristics.
–80
–90
–100
–110
–120
–130
–140
14
100ꢀ
200ꢀ
13
12
11
10
9
100ꢀ
200ꢀ
0
50
100
150
200
250
IF FREQUENCY (MHz)
Figure 55. HD2 and HD3 vs. IF Frequency for Different Loads
8
7
6
5
4
0
100
200
300
400
500
IF FREQUENCY (MHz)
Figure 52. Gain vs. IF Frequency for Different Loads
45
40
35
30
25
20
15
10
5
100ꢀ
200ꢀ
0
500
960
1420
1880
2340
2800
LO FREQUENCY (MHz)
Figure 53. Output IP3 (OIP3) vs. LO Frequency for Different Loads
Rev. A | Page 29 of 61
ADRF6821
Data Sheet
I/Q OUTPUTS
ANALOG-TO-DIGITAL CONVERTER (ADC)
INTERFACING
56nH 68nH 56nH
25ꢀ
8.2pF 15pF
15pF
6.8pF
The ADRF6821 perfectly suits in a zero IF receiver chain. The
integrated IF amplifier of the ADRF6821 provides variable and
sufficient drive capabilities for both buffered and unbuffered
ADCs. It also provides isolation between the sampling edges of
the ADC and the mixer core. As a result, an antialiasing low-pass
filter is sufficient when interfacing with an ADC.
56nH 68nH 56nH
25ꢀ
100ꢀ
100ꢀ
Figure 56. Low-Pass Filter Schematic
Table 17. Component Values for the Low-Pass Filter Design
(1 dB Corner Frequency of 150 MHz)
The filter resides between the ADRF6821 and the ADC. The
low-pass filter eliminates all out of band signals that may alias
onto the actual band and degrade the performance of the
ADRF6821 and the ADC pair. Selection of the low-pass filter
center and bandwidth is application specific. Take into account
the trade-off between the amount of rejection required and the
insertion loss to choose the order of the filter. A higher order
filter also requires more layout space, which is another design
criterion.
Parameter
Value
56 nH
68 nH
8.2 pF
6.8 pF
15 pF
Type
Manufacturer
Coilcraft
Coilcraft
Murata
Murata
Murata
Inductors
0402 CS
0402 CS
0402 C0G
0402 C0G
0402 C0G
Capacitors
Figure 57 compares the measured low-pass filter response and
the normalized gain of the ADRF6821 LPF pair. Refer to the
highest gain of the ADRF6821 (without the low-pass filter) to
acheive normalization. The in band roll-off is associated to the
finite Q and trace and pad losses.
For the purposes of ADC interfacing, consider a DPD receiver
chain, correcting for a 70 MHz bandwidth signal. Assuming a
fifth-order correction, 350 MHz from the output of the power
amplifier must be sampled. With the use of a zero-IF receiver,
I and Q bandwidths are half of the 350 MHz, that is, 175 MHz.
Next, determine the sampling rate of the ADC. To relax the
antialiasing filter requirements, use a slightly oversampled
system. Considering the bandwidth of interest for I and Q
(that is, 175 MHz), 500 MSPS is a sufficiently large sampling
rate. With a 500 MSPS sampling rate, the second Nyquist zone
lies between 250 MHz and 500 MHz. Because there are no
interferers present in a DPD chain, only the replica of the signal
of interest in the second Nyquist zone (between 325 MHz and
500 MHz) is of concern. As a result, the antialiasing filter provides
sufficient attenuation starting from 325 MHz.
0
NORMALIZED GAIN OF ADRF6821 LPF
LPF RESPONSE
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
100 200 300 400 500 600 700 800 900 1000
IF FREQUENCY (MHz)
The required attenuation from the filter is determined with the
dynamic range requirement. As previously mentioned, in a DPD
receiver chain, ideally only the signal of interest is present.
Therefore, the filter requirements can be relaxed further. Because of
this, consider a 40 dB rejection at the aliased portion.
Figure 57. Frequency Response for the 150 MHz Low-Pass Filter and
Frequency Response for ADRF6821 LPF Pair
Considering the pass band, the stop band, and the attenuation
at stop band, a seventh-order Chebyshev low-pass filter is
suitable with a 0.1 dB ripple in-band. Keep in mind that the
ADRF6821 is optimized with a 100 Ω load at the output.
Therefore, design the filter for an input and output impedance
of differential 100 Ω. The Chebyshev filter design is discussed
extensively and is straightforward with the use of a filter wizard,
such as ADS built-in filter design tool from Keysight. Filter
design tools provide component values that are not necessarily
commercially available. It is recommended that designers
use commercially available component models and take into
account the layout effects. Figure 56 displays the component
values for the antialiasing LPF. Table 17 provides commercially
available component values for the low-pass filter design.
Rev. A | Page 30 of 61
Data Sheet
ADRF6821
One of the dominant sources of phase error in a system originates
from the demodulator where the quadrature phase split of the
LO signal occurs. The ADRF6821 offers phase and gain adjustment
of the I and Q paths independently to allow quadrature correction.
Adjusting the phase with the TRM_LODRV_CAPI bits
(Register 0x0092, Bits[3:0]) for the I path correction and the
TRM_LODRV_CAPQ bits (Register 0x0092, Bits[7:4]) for the
Q path correction accesses the quadrature correction. Adjust
the I_MIXER_GAIN_ADJ bits (Register 0x003A, Bits[3:2]) and
the Q_MIXER_GAIN_ADJ bits (Register 0x003A, Bits[5:4]) for
the I and Q outputs, respectively, to achieve gain correction.
Figure 60 shows uncalibrated and calibrated image rejection for
an LO frequency of 2800 MHz and across temperature.
45
IMAGE REJECTION
For direct conversion systems, maximizing image rejection is
key to achieving performance and optimizing bandwidth. The
amplitude and phase mismatch of the baseband I and Q paths
directly translates to degradation in image rejection, as is shown
in the following equation. The equation translates the gain and
quadrature phase mismatch to the image rejection ratio (IRR)
performance.
1+ Ae2 + 2Aecos(ϕe )
IRR (dB) =10log
1+ Ae2 + 2Aecos(ϕe )
where:
Ae is the amplitude error and is shown in Figure 58 for various
LO frequencies.
φe is the phase error and is shown in Figure 59 for various LO
frequencies.
CORRECTED
40
35
The image rejection calculated with the given phase and gain
mismatches is shown in Figure 60.
30
25
20
15
10
5
UNCORRECTED
0.50
LO = 2800MHz
LO = 2000MHz
LO = 1000MHz
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
+105°C
+27°C
–40°C
0
0
50
100 150 200 250 300 350 400 450 500
IF FREQUENCY (MHz)
Figure 60. Corrected and Uncorrected Image Rejection vs. IF Frequency for
Various Temperatures, fLO = 2800 MHz
For any correction circuit, it is important to observe the effect
of temperature on the correction level and settings. Figure 61
shows how the correction with a given phase and gain setting
holds across temperature.
0
50
100 150 200 250 300 350 400 450 500
IF FREQUENCY (MHz)
Figure 58. Gain Mismatch (Error) Between I and Q Outputs vs. IF Frequency
4.5
TRM_LODRV_CAPI = 15
TRM_LODRV_CAPI = 8
TRM_LODRV_CAPI = 0
4.5
LO = 2800MHz
4.0
LO = 2000MHz
LO = 1000MHz
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
50
100 150 200 250 300 350 400 450 500
IF FREQUENCY (MHz)
0
50
100 150 200 250 300 350 400 450 500
IF FREQUENCY (MHz)
Figure 61. Phase Mismatch vs. IF Frequency (fLO = 2800 MHz) for Various
Phase Setting Values
Figure 59. Phase Mismatch (Error) Between I and Q Outputs vs. IF Frequency
Rev. A | Page 31 of 61
ADRF6821
Data Sheet
PLL/VCO Supply Domain
POWER SUPPLY CONFIGURATION
The PLL/VCO supply domain requires specific attention;
otherwise, performance degradation can result. The ADRF6821
incorporates an ultralow noise PLL and VCO that are sensitive
to any noise and/or frequency component at the supply pins.
These unwanted noise and frequency components degrade
the performance of the overall system. To avoid performance
degradation, the ADRF6821 evaluation board employs the
PLL/VCO supply domain circuit shown in Figure 63. The supply
circuit in Figure 63 uses the HMC1060, an ultralow noise, LDO
with four isolated outputs. Noise performance and isolated outputs
make the HMC1060 an ideal solution for the PLL/VCO supply
domain. For additional configuration options, refer to the
ADRF6821-EVALZ user guide.
The ADRF6821 incorporates two main supply domains, namely
RF/IF and PLL/VCO. The RF/IF supply domain includes the
supplies related to the RF switch, the DSA, the mixer, the mixer
LO drivers, and the IF amplifier. The PLL/VCO supply domain
includes the P F D / C P, the VCO, the dividers, and the output
drivers.
RF/IF Supply Domain
Connect the RF/IF supply domain pins together with beads in
between and decoupling capacitors specific to each pin as shown
in Figure 62. The RF/IF supply pins draw a combined 350 mA
approximately. For the RF/IF supply domain, the ADRF6821
evaluation board employs the ADM7170, a low noise and high
power supply rejection ratio (PSRR) linear regulator that is
capable of delivering 500 mA.
The power supply rejection (PSR) of the RF/IF supply pins allow
the use of a switching supply to reduce the power consumption
on the linear regulators. The ADRF6821 evaluation board includes
the ADP2370 switching regulator and allows the observation of
the operation with a switching supply. The ADP2370 is a low
quiescent current buck regulator capable of delivering an output
current of 800 mA with a selectable switching frequencies of
600 kHz and 1.2 MHz. See the ADRF6821-EVALZ user guide
on how to configure the switching supply for RF/IF domain.
BEAD
VCC_3V3_I
10µF
0.1µF
0.1µF
100pF
100pF
100pF
100pF
BEAD
10µF
VCC_3V3_Q
VCC_LO1
BEAD
0.1µF
BEAD
0.1µF
ADM7170
VCC_LO2
10µF
BEAD
0.1µF
VCC_IFMIX_I
100pF
100pF
BEAD
0.1µF
VCC_IFMIX_Q
VCC_IFMIX_I
VCC_IFMIX_Q
BEAD
0.1µF
100pF
100pF
BEAD
0.1µF
Figure 62. RF/IF Domain Power Supply Circuit
Rev. A | Page 32 of 61
Data Sheet
ADRF6821
BEAD
10µF
VCCVCO_3V3
VCCCP_3V3
0.1µF
100pF
100pF
100pF
100pF
100pF
100pF
0.1µF
BEAD
0.1µF
10µF
VR1
VR2
VR3
VR4
BEAD
0.1µF
VCCPFD_3V3
VCCREF_3V3
VBAT_DIG_3V3
HMC1060
BEAD
0.1µF
10µF
BEAD
0.1µF
BEAD
0.1µF
VCCLO_AUX_3V3
VCCLO_MIX_3V3
10µF
BEAD
VCCDIV_3V3
100pF
VCCFBDIV_3V3
100pF
0.1µF
Figure 63. PLL/VCO Domain Power Supply Circuit
Rev. A | Page 33 of 61
ADRF6821
Data Sheet
The ADRF6821 incorporates a very low noise PLL/VCO and
care must be taken when designing the PCB routing around the
PLL/VCO pins. It is required to put the decoupling capacitors
for the supply pins as close as possible. If 0402 capacitors are
used, putting all of the decoupling capacitors close to the pin
becomes problematic. In such a case, place the smaller value
decoupling capacitor as close as possible to the pin. It is a good
practice to keep the first capacitor of the loop filter close to the
CPOUT pin, and the last capacitor close to the VTUNE pin, as
can be seen in Figure 65.
LAYOUT
Careful layout of the ADRF6821 is necessary for optimizing
performance and minimizing stray parasitics. Because the
ADRF6821 supports two channels, the layout of the RF section
is critical in achieving isolation between channels. Figure 64
shows the recommended layout for the RF inputs. The best
layout approach is to keep the traces short and direct. In
addition, for improved isolation, do not route the RF input
traces in parallel to each other and spread the traces immediately
after each one leaves the pins. Keep the traces as far away from
each other as possible (and at an angle, if possible) to prevent
cross coupling.
The input impedance of the RF inputs is 50 Ω, and the traces
leading to the pin must have a 50 Ω characteristic impedance.
Terminate the unused RF inputs with a dc blocking capacitor to
ground.
Figure 65. PLL/VCO Domain Layout
Figure 64. RF/IF Domain Layout
Rev. A | Page 34 of 61
Data Sheet
ADRF6821
REGISTER MAP AND REGISTER DESCRIPTIONS
Register addresses not listed in Table 18 are reserved, unused, or open registers.
Table 18.
Reg
Addr
(Hex)
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
RW
0000
ADI_SPI_
CONFIG
[7:0]
SOFTRESET_
LSB_FIRST_
ENDIAN_
SDOACTIVE_
SDOACTIVE
ENDIAN
LSB_FIRST
SOFTRESET
0x00
R/W
0001
SPI_
CONFIG_B
[7:0]
SINGLE_
INSTRUCTION
CSB_STALL
MASTER_
SLAVE_RB
RESERVED
SOFT_RESET
MASTER_
SLAVE_
0x00
R/W
TRANSFER
0003
0004
CHIPTYPE
[7:0]
[7:0]
CHIPTYPE
0x01
0x13
R
R
PRODUCT_
ID_L
PRODUCT_ID, Bits[7:0]
0005
PRODUCT_
ID_H
[7:0]
PRODUCT_ID, Bits[15:8]
0x00
R
000A
000B
000C
SCRATCHPAD
SPI_REV
[7:0]
[7:0]
[7:0]
SCRATCHPAD
SPI_REV
0x00
0x00
0x56
R/W
R
VENDOR_
ID_L
VENDOR_ID, Bits[7:0]
R
000D
0020
0030
0031
0032
0033
VENDOR_
ID_H
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
VENDOR_ID, Bits[15:8]
0x04
0x00
0x00
0x00
0x00
0x00
R
MASTER_
CONFIG
RESERVED
RFSW_SEL0
EN_ANALOG_
MASTER
SPI_18_33_SEL
EN_SW
R/W
R/W
R/W
R/W
R/W
RF_SWITCH
RESERVED
SEL_RFSW_
SPI_CONTROL
RFSW_SEL1
RFSW_SEL1_IN
ATTEN_DSA
EN_IMXBIAS_I EN_MIXIBIASGEN
CODE_MIXER_DRVR
RFSW_SEL0_IN
EN_MIX_Q
ENB_SW_
1P8_GEN
DSA_
CONTROL
RESERVED
ENB_DSA_
1P8_GEN
EN_DSA
DEMOD_
ENABLES
RESERVED
EN_IMXBIAS_Q
EN_MIX_I
ENB_MIX_
1P8_GEN
DEMOD_
LO_COM_
CTRL
0034
DEMOD_
OUT_COM_
CTRL
[7:0]
CODE_MIXER_OCM
0x00
R/W
003A
0040
DEMOD_
SPARES
[7:0]
[7:0]
RESERVED
Q_MIXER_GAIN_ADJ
I_MIXER_GAIN_ADJ
MIXER_GAIN_PEAK
0x00
0x00
R/W
R/W
DEMOD_
DRIVER_
COM_CTRL
EN_ICMLOBIAS_Q
EN_
EN_ICMOBIAS_Q
EN_DC_DAC_I
EN_ICMOBIAS_I
ICMLOBIAS_I
0050
0051
0052
DC_CTRL
[7:0]
[7:0]
[7:0]
RESERVED
EN_DC_DAC_Q
ENB_DCCOMP_
1P8_GEN
0x00
0x00
0x00
R/W
R/W
R/W
DC_COMP_I_
CHAN_RF0
CODE_DC_IDAC_RF0
CODE_DC_QDAC_RF0
DC_
COMP_Q_
CHAN_RF0
0053
0054
DC_
COMP_I_
CHAN_RF1
[7:0]
[7:0]
CODE_DC_IDAC_RF1
CODE_DC_QDAC_RF1
0x00
0x00
R/W
R/W
DC_
COMP_Q_
CHAN_RF1
0060
0070
0080
0090
LPF_BW_SEL
[7:0]
[7:0]
[7:0]
[7:0]
RESERVED
RESERVED
SEL_LPF_
BW_LSB
SEL_LPF_
BW_MSB
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
IF_AMP_
CTRL
EN_IFAMP_Q
EN_IFAMP_I
LO_CTRL
RESERVED
SEL_LODRV_
PREDRVQ_POL
SEL_LODRV_
PREDRVI_POL
RESERVED
EN_LO_
DIVIDER_
CTRL
RESERVED
RESERVED
EN_LODRV_
PREDRVQ
EN_LODRV_
PREDRVI
EN_LODRV_
DRVQ
EN_LODRV_DRVI
EN_DIVPATH_
QUADDIV
EN_DIVPATH_
BUF
EN_IBIASGEN
0092
1021
LO_PHASE_
ADJ
[7:0]
[7:0]
TRM_LODRV_CAPQ
ARSTB_
TRM_LODRV_CAPI
0x00
0xFF
R/W
R/W
BLOCK_
RESETS
ARSTB_
ARSTB_
BLOCK_NDIV
ARSTB_
BLOCK_RDIV
ARSTB_
BLOCK_
DSMOSTG
ARSTB_BLOCK_
DSMCORE
ARSTB_
BLOCK_
DSMALL
BLOCK_LKD
BLOCK_
AUTOCAL
1109
SIG_PATH_
9_NORMAL
[7:0]
RESERVED
TRM_MIXLODRV_DRV_POUT
TRM_XLODRV_DRV_POUT
RESERVED
0x0A
R/W
Rev. A | Page 35 of 61
ADRF6821
Data Sheet
Reg
Addr
(Hex)
1200
1201
1202
1203
1204
1205
Name
Bits
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
0x89
0x01
0x00
0x00
0x00
0x00
RW
INT_L
INT_DIV, Bits[7:0]
INT_DIV, Bits[15:8]
FRAC, Bits[7:0]
FRAC, Bits[15:8]
FRAC, Bits[23:16]
PHASE, Bits[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
INT_H
FRAC1_L
FRAC1_M
FRAC1_H
SD_PHASE_
L_0
1206
1207
SD_PHASE_
M_0
[7:0]
[7:0]
PHASE, Bits[15:8]
PHASE, Bits[23:16]
MOD2, Bits[7:0]
0x00
0x00
R/W
R/W
SD_PHASE_
H_0
1208
1209
120B
120C
120E
1214
MOD_L
MOD_H
SYNTH
R_DIV
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
0x00
0x00
0x01
0x03
0x04
0x48
R/W
R/W
R/W
R/W
R/W
R/W
RESERVED
MOD2, Bits[13:8]
RESERVED
PRE_SEL
EN_FBDIV
RDIV2_SEL
RESERVED
R_DIV
DOUBLER_EN
SYNTH_0
RESERVED
RESERVED
RESERVED
MULTI_FUNC_
SYNTH_
CTRL_0214
LD_BIAS
LDP
RESERVED
1215
1217
121C
SI_BAND_0
SI_VCO_SEL
[7:0]
[7:0]
[7:0]
SI_BAND_SEL
0x00
0x00
0x20
R/W
R/W
R/W
SI_VCO_SEL
VCO_
TIMEOUT_L
VCO_TIMOUT[7:0]
VCO_BAND_DIV
121D
121E
121F
122A
122C
VCO_
TIMEOUT_H
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
RESERVED
VCO_TIMEOUT[9:8]
0x00
0x14
0x00
0x02
0x03
R/W
R/W
R/W
R/W
R/W
VCO_
BAND_DIV
VCO_FSM
RESERVED
DISABLE_
RESERVED
RESERVED
CAL
SD_CTRL
RESERVED
SD_EN_FRAC0
SD_EN_OUT_
OFF
SD_SM_2
RESERVED
CP_HIZ
MULTI_
RESERVED
FUNC_
SYNTH_
CTRL_022C
122D
MULTI_
[7:0]
EN_PFD_CP
BLEED_POL
RESERVED
INT_ABP
RESERVED
BLEED_EN
0x81
R/W
FUNC_
SYNTH_
CTRL_022D
122E
122F
1233
1234
1235
CP_CURR
BICP
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
RESERVED
CP_CURRENT
0x0F
0x08
0x00
0x00
0x00
R/W
R/W
R/W
R/W
R/W
BICP
FRAC2_L
FRAC2_H
FRAC2, Bits[7:0]
RESERVED
FRAC2, Bits[13:8]
MULTI_
FUNC_
RESERVED
PHASE_ADJ_EN
RESERVED
SYNTH_
CTRL_0235
1240
124D
1401
VCO_LUT_
CTRL
[7:0]
[7:0]
[7:0]
RESERVED
RESERVED
SI_VCO_FORCE_
CAPSVCOI
RESERVED
SI_VCO_FORCE_
VCO
SI_VCO_
FORCE_CAPS
0x00
0x00
0x00
R/W
R
LOCK_
DETECT
RESERVED
LOCK_DETECT
MULTI_
FUNC_CTRL
SPI_1P8_3P3_
CTRL
RESERVED
R/W
140E
1414
1541
LO_CNTRL2
LO_CNTRL8
[7:0]
[7:0]
[7:0]
EN_BIAS_R
MIX_OE
RESERVED
LO_OE
REFBUF_EN
USEEXT_LOI
RESERVED
OUT_DIVRATIO
0xB3
0x02
0x00
R/W
R/W
R
FRAC2_L_
SLAVE
FRAC2_SLV, Bits[7:0]
1542
1543
1544
1545
FRAC2_H_
SLAVE
[7:0]
[7:0]
[7:0]
[7:0]
RESERVED
FRAC2_SLV, Bits[13:8]
0x00
0x00
0x00
0x00
R
R
R
R
FRAC_L_
SLAVE
FRAC_SLV, Bits[7:0]
FRAC_SLV, Bits[15:8]
FRAC_SLV, Bits[23:16]
FRAC_M_
SLAVE
FRAC_H_
SLAVE2
Rev. A | Page 36 of 61
Data Sheet
ADRF6821
Reg
Addr
(Hex)
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
RW
1546
PHASE_L_
SLAVE
[7:0]
PHASE_SLV, Bits[7:0]
0x00
R
1547
1548
1549
154A
154B
154C
1583
PHASE_
M_SLAVE2
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
PHASE_SLV, Bits[15:8]
PHASE_SLV, Bits[23:16]
INT_DIV_SLV, Bits[7:0]
INT_DIV_SLV, Bits[15:8]
R_DIV_SLV
0x00
0x00
0x89
0x01
0x03
0x00
0x00
R
PHASE_
H_SLAVE3
R
INT_DIV_
L_SLAVE
R
INT_DIV_
H_SLAVE
R
R_DIV_
SLAVE
RESERVED
R
RDIV2_
SEL_SLAVE
RESERVED
DSM_LAUNCH_DLY
RDIV2_SEL_SLV
R
DISABLE_
CFG
RESERVED
DISABLE_
FREQHOP
DISABLE_
DBLBUFFERING
DISABLE_
PHASEADJ
R/W
Rev. A | Page 37 of 61
ADRF6821
Data Sheet
REGISTER DESCRIPTIONS
Address: 0x0000, Reset: 0x00, Name: ADI_SPI_CONFIG
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 ] SO FT RESET _ ( R/W )
SOFTRESET_
[ 0 ] SO FT RESET ( R/W )
SOFTRESET
[ 6 ] LSB_FIRST _ ( R/W )
LSB_FIRST_
[ 1] LSB_FIRST ( R/W )
LSB_FIRST
[ 5] ENDIAN_ ( R/W )
ENDIAN_
[ 2] ENDIAN ( R/W )
ENDIAN
[ 4 ] SDO ACT IVE_ ( R/W )
SDOACTIVE_
[ 3] SDO ACT IVE ( R/W )
SDOACTIVE
Table 19. Bit Descriptions for ADI_SPI_CONFIG
Bits
Bit Name
Settings Description
SOFTRESET_
LSB_FIRST_
ENDIAN_
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Access
7
SOFTRESET_
LSB_FIRST_
ENDIAN_
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
6
5
4
SDOACTIVE_
SDOACTIVE
ENDIAN
SDOACTIVE_
SDOACTIVE
ENDIAN
3
2
1
LSB_FIRST
SOFTRESET
LSB_FIRST
0
SOFTRESET
Address: 0x0001, Reset: 0x00, Name: SPI_CONFIG_B
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] SINGLE_INSTRUCTION (R/W)
[0] MASTER_SLAVE_TRANSFER (R/W)
Single Instruction
Master Slave Transfer
[6] CSB_STALL (R/W)
[2:1] SOFT_RESET (R/W)
CSB Stall
Soft Reset
[5] MASTER_SLAVE_RB (R/W)
[4:3] RESERVED
Master Slave RB
Table 20. Bit Descriptions for SPI_CONFIG_B
Bits
Bit Name
Settings Description
Reset
Access
R/W
R/W
R/W
R/W
R/W
R/W
7
SINGLE_INSTRUCTION
CSB_STALL
Single Instruction
CSB Stall
0x0
0x0
0x0
0x0
0x0
0x0
6
5
MASTER_SLAVE_RB
RESERVED
Master Slave Readback (RB)
Reserved
[4:3]
[2:1]
0
SOFT_RESET
Soft Reset
MASTER_SLAVE_TRANSFER
Master Slave Transfer
Address: 0x0003, Reset: 0x01, Name: CHIPTYPE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:0] CHIPTYPE (R)
Chip Type, Read Only
Table 21. Bit Descriptions for CHIPTYPE
Bits
Bit Name Settings Description
CHIPTYPE Chip Type, Read Only
Reset
0x1
Access
[7:0]
R
Rev. A | Page 38 of 61
Data Sheet
ADRF6821
Address: 0x0004, Reset: 0x13, Name: PRODUCT_ID_L
7
6
5
4
3
2
1
0
0
0
0
1
0
0
1
1
[ 7 :0 ] PRO DUCT _ID[ 7 :0 ][ 7 :0 ] ( R)
PRODUCT_ID
Table 22. Bit Descriptions for PRODUCT_ID_L
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
PRODUCT_ID, Bits[7:0]
PRODUCT_ID
0x13
R
Address: 0x0005, Reset: 0x00, Name: PRODUCT_ID_H
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] PRO DUCT _ID[ 7 :0 ][ 15:8 ] ( R)
PRODUCT_ID
Table 23. Bit Descriptions for PRODUCT_ID_H
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
PRODUCT_ID, Bits[15:8]
PRODUCT_ID
0x13
R
Address: 0x000A, Reset: 0x00, Name: SCRATCHPAD
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] SCRAT CHPAD ( R/W )
SCRATCHPAD
Table 24. Bit Descriptions for SCRATCHPAD
Bits
Bit Name
Settings Description
Reset
Access
[7:0]
SCRATCHPAD
SCRATCHPAD
0x0
R/W
Address: 0x000B, Reset: 0x00, Name: SPI_REV
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] SPI_REV (R)
SPI Register Map Rev
Table 25. Bit Descriptions for SPI_REV
Bits
Bit Name Settings Description
SPI_REV SPI Register Map Rev
Reset
0x0
Access
[7:0]
R
Address: 0x000C, Reset: 0x56, Name: VENDOR_ID_L
7
6
5
4
3
2
1
0
0
1
0
1
0
1
1
0
[ 7 :0 ] VENDO R_ID[ 7 :0 ][ 7 :0 ] ( R)
VEND O R_ID
Table 26. Bit Descriptions for VENDOR_ID_L
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
VENDOR_ID, Bits[7:0]
VENDOR_ID
0x456
R
Rev. A | Page 39 of 61
ADRF6821
Data Sheet
Address: 0x000D, Reset: 0x04, Name: VENDOR_ID_H
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
0
[ 7 :0 ] VENDO R_ID[ 7 :0 ][ 15:8 ] ( R)
VEND O R_ID
Table 27. Bit Descriptions for VENDOR_ID_H
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
VENDOR_ID, Bits[15:8]
VENDOR_ID
0x456
R
Address: 0x0020, Reset: 0x00, Name: MASTER_CONFIG
Controls master enable, SPI mode, sleep mode, and the input word for the dc DAC.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:2] RESERVED
[0] SPI_18_33_SEL (R/W)
3.3V SPI Output Level Selection
[1] EN_ANALOG_MASTER (R/W)
Master Enable
Table 28. Bit Descriptions for MASTER_CONFIG
Bits Bit Name
Settings Description
Reset Access
[7:2] RESERVED
Reserved.
0x0
0x0
0x0
R
1
0
EN_ANALOG_MASTER
SPI_18_33_SEL
Master Enable. Master enable for the DPD analog blocks. Active high.
3.3 V SPI Output Level Selection. The high level is 3.3 V, and the low level is 1.8 V.
R/W
R/W
Address: 0x0030, Reset: 0x00, Name: RF_SWITCH
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 ] RESERVED
[ 0 ] EN_SW ( R/W )
RF SW Enable (0:off 1:on)
[ 6 ] SEL_RFSW _SPI_CO NT RO L ( R/W )
SPI Override for Pin Switch Selection
[ 1 ] EN B_SW _1 P8 _GEN ( R/W )
RF SW 1.8V Reference Enable (1:off
0:on), Active Low
[ 5] RFSW _SEL1 ( R/W )
Select RF1 Input
[ 2 ] RFSW _SEL0 _IN ( R)
External RF Switch Status (RFSEL0)
[ 4 ] RFSW _SEL0 ( R/W )
Select RF0 Input
[ 3 ] RFSW _SEL1 _IN ( R)
External RF Switch Status (RFSEL1)
Table 29. Bit Descriptions for RF_SWITCH
Bits Bit Name
Settings Description
Reset Access
7
6
5
RESERVED
Reserved.
0x0
0x0
0x0
R
SEL_RFSW_SPI_CONTROL
RFSW_SEL1
SPI Override for Pin Switch Selection.
R/W
R/W
Select RF1 Input. Software control for the RF channel selection (requires
that SEL_RFSW_SPI_CONTROL is set to 1).
0
1
Not selected (internal 50 Ω termination).
RF channel selected (signal connected to signal path).
4
3
RFSW_SEL0
Select RF0 Input. Software control for the RF channel selection (requires
that SEL_RFSW_SPI_CONTROL is set to 1).
Not selected (internal 50 Ω termination).
0x0
0x0
R/W
R
0
1
RF channel selected (signal connected to signal path).
RFSW_SEL1_IN
External RF Switch Status (RFSEL1). Readback status of the external RF
channel selection pin (RF_SEL1).
0
1
Not selected (internal 50 Ω termination).
RF channel selected (signal connected to signal path).
Rev. A | Page 40 of 61
Data Sheet
ADRF6821
Bits Bit Name
Settings Description
External RF Switch Status (RFSEL0). Readback status of the external RF
Reset Access
2
1
0
RFSW_SEL0_IN
0x0
0x0
0x0
R
channel selection pin (RF_SEL0).
0
1
Not selected (internal 50 Ω termination).
RF channel selected (signal connected to signal path).
ENB_SW_1P8_GEN
EN_SW
RF SW 1.8 V Reference Enable (0: off and 1: on). Active low. Note that the
input is active low; therefore, the default value of 0 enables this circuit.
R/W
R/W
0
1
On.
Off.
RF SW Enable (0: off and 1: on). Enable for the RF channel switch. This
must be enabled whenever RF Channel 1 or RF Channel 2 is used (either
closed or set to open (that is, termination).
0
1
Off.
On.
Address: 0x0031, Reset: 0x00, Name: DSA_CONTROL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :6 ] RESERVED
[ 0 ] EN_DSA ( R/W )
DSA Enable (0:off 1:on)
[ 5:2] AT T EN_DSA ( R/W )
DSA Attenuation Control
0: 0 dB.
[ 1 ] EN B_D SA_1 P8 _GEN ( R/W )
DSA 1.8V Reference Enable (1:off 0:on),
Active Low.
1: 1 dB.
10: 2 dB.
...
1101: 13 dB.
1110: 14 dB.
1111: 15 dB.
Table 30. Bit Descriptions for DSA_CONTROL
Bits
[7:6]
[5:2]
Bit Name
RESERVED
ATTEN_DSA
Settings Description
Reset Access
Reserved.
0x0
0x0
R
DSA Attenuation Control. Controls the digital step attenuation in 1 dB steps.
R/W
0
1
0 dB.
1 dB.
10 2 dB.
…
…
1101 13 dB.
1110 14 dB.
1111 15 dB.
1
0
ENB_DSA_1P8_GEN
EN_DSA
DSA 1.8 V Reference Enable (1: off and 0: on). Active low.
0x0
R/W
R/W
DSA Enable (0: off and 1: on). This bit must be set to enable the RF digital step 0x0
attenuator.
Rev. A | Page 41 of 61
ADRF6821
Data Sheet
Address: 0x0032, Reset: 0x00, Name: DEMOD_ENABLES
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :6 ] RESERVED
[ 0 ] EN B_M IX_1 P8 _GEN ( R/W )
MIX 1.8V Reference Enable (1:off 0:on),
Active Low
[ 5] EN_IM XBIAS_Q ( R/W )
Q Channel Mixer Bias Current Enable
(0:off 1:on)
[ 1] EN_M IX_I ( R/W )
I Channel Mixer Enable (0:off 1:on)
[ 4 ] EN_IM XBIAS_I ( R/W )
I Channel Mixer Bias Current Enable
(0:off 1:on)
[ 2 ] EN _M IX_Q ( R/W )
Q Channel Mixer Enable (0:off 1:on)
[ 3] EN_M IXIBIASGEN ( R/W )
Mixer Bias Current Enable (0:off 1:on)
Table 31. Bit Descriptions for DEMOD_ENABLES
Bits
[7:6]
5
Bit Name
Settings Description
Reset Access
RESERVED
Reserved.
0x0
0x0
R
EN_IMXBIAS_Q
Q Channel Mixer Bias Current Enable (0: off and 1: on). Mixer bias current
enable. This must be enabled whenever the mixer is enabled. The master
mixer bias, EN_MIXBIASGEN, must also be enabled as well.
R/W
4
EN_IMXBIAS_I
I Channel Mixer Bias Current Enable (0: off and 1: on). Mixer bias current
enable. This must be enabled whenever the mixer is enabled. The master
mixer bias, EN_MIXBIASGEN, must also be enabled as well.
0x0
R/W
3
2
EN_MIXIBIASGEN
EN_MIX_Q
Mixer Bias Current Enable (0: off and 1: on). Master mixer bias current is
enabled and must be enabled whenever the mixer is enabled.
0x0
0x0
R/W
R/W
Q Channel Mixer Enable (0: off and 1: on). Enable for the mixer. For the mixer
to correctly function, the following bits must also be enabled or set to 45:
EN_MIXBIAS_x, EN_MIXBIASGEN, EN_ICMOBIAS_x, and CODE_MIXER_OCM.
1
0
EN_MIX_I
I Channel Mixer Enable (0: off and 1: on). Enable for the mixer. For the mixer to 0x0
correctly function the following bits must also be enabled or set to 45:
EN_MIXBIAS_x, EN_MIXBIASGEN, EN_ICMOBIAS_x, and CODE_MIXER_OCM.
R/W
R/W
ENB_MIX_1P8_GEN
Mixer 1.8 V Reference Enable (0: off and 1: on). Active low.
0x0
Address: 0x0033, Reset: 0x00, Name: DEMOD_LO_COM_CTRL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] CO DE_M IXER_DRVR ( R/W )
Mixer LO Common-Mode Control
Table 32. Bit Descriptions for DEMOD_LO_COM_CTRL
Bits
Bit Name
Settings Description
Reset Access
0x0 R/W
[7:0]
CODE_MIXER_DRVR
Mixer LO Common-Mode Control. Determines the dc level applied to the
mixer LO driver LDO.
Address: 0x0034, Reset: 0x00, Name: DEMOD_OUT_COM_CTRL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] CO DE_M IXER_O CM ( R/W )
Mixer Output Stage Common-Mode
Control
Table 33. Bit Descriptions for DEMOD_OUT_COM_CTRL
Bits
Bit Name
Settings Description
Reset Access
R/W
[7:0]
CODE_MIXER_OCM
Mixer Output Stage Common-Mode Control. Determines the dc level applied 0x0
to the mixer output LDO.
Rev. A | Page 42 of 61
Data Sheet
ADRF6821
Address: 0x003A, Reset: 0x20, Name: DEMOD_SPARES
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :6 ] RESERVED
[ 1:0 ] M IXER_GAIN_PEAK ( R/W )
Frequency Selective Gain Adjustment
for the Mixer
[ 5:4 ] Q _M IXER_GAIN_ADJ( R/W )
Q Mixer Gain Adjustment
[ 3:2] I_M IXER_GAIN_ADJ( R/W )
I Mixer Gain Adjustment
Table 34. Bit Descriptions for DEMOD_SPARES
Bits
[7:6]
[5:4]
Bit Name
Settings Description
Reset Access
RESERVED
Reserved.
0x0
R
Q_MIXER_GAIN_ADJ
Q Mixer Gain Adjustment. Allows the individual mixer gains to be adjusted in 0x0
0.2 dB steps (gains are adjusted relative to each other) to improve I/Q
balance.
R/W
[3:2]
[1:0]
I_MIXER_GAIN_ADJ
MIXER_GAIN_PEAK
I Mixer Gain Adjustment. Allows the individual mixer gains to be adjusted in
0.2 dB steps (gains are adjusted relative to each other) to improve I/Q
balance.
Frequency Selective Gain Adjustment for the Mixer. It compensates for the
frequency dependent loss in RF front end. 0 for no compensation, and
3 (decimal) for maximum compensation.
0x0
R/W
R/W
0x0
Address: 0x0040, Reset: 0x00, Name: DEMOD_DRIVER_COM_CTRL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :4 ] RESERVED
[ 3] EN_ICM LO BIAS_Q ( R/W )
Q Channel LO Driver Common-Mode
Control Enable (0:off 1:on)
[ 0 ] EN_ICM O BIAS_I ( R/W )
I Channel Mixer Common-Mode Control
Enable (0:off 1:on)
[ 1] EN_ICM O BIAS_Q ( R/W )
Q Channel Mixer Common-Mode Control
Enable (0:off 1:on)
[ 2] EN_ICM LO BIAS_I ( R/W )
I Channel LO Driver Common-Mode Control
Enable (0:off 1:on)
Table 35. Bit Descriptions for DEMOD_DRIVER_COM_CTRL
Bits
[7:4]
3
Bit Name
Settings Description
Reset Access
RESERVED
Reserved.
0x0
0x0
R
EN_ICMLOBIAS_Q
Q Channel LO Driver Common-Mode Control Enable (0: off and 1: on). LO path
driver LDO bias current. This must be enabled to turn on the LDO for the LO
driver block which interfaces to the mixer.
R/W
2
1
0
EN_ICMLOBIAS_I
EN_ICMOBIAS_Q
EN_ICMOBIAS_I
I Channel LO Driver Common-Mode Control Enable (0: off and 1: on). LO path
driver LDO bias current. This must be enabled to turn on the LDO for the LO
driver block which interfaces to the mixer.
0x0
0x0
0x0
R/W
R/W
R/W
Q Channel Mixer Common-Mode Control Enable (0: off and 1: on). Mixer LDO
bias current. This must be enabled to turn on the LDO for the mixer. This is
required whenever the mixer is enabled.
I Channel Mixer Common-Mode Control Enable (0: off and 1: on). Mixer LDO
bias current. This must be enabled to turn on the LDO for the mixer. This is
required whenever the mixer is enabled.
Rev. A | Page 43 of 61
ADRF6821
Data Sheet
Address: 0x0050, Reset: 0x00, Name: DC_CTRL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :3] RESERVED
[ 0 ] ENB_DCCO M P_1P8 _GEN ( R/W )
DC DAC 1.8V Reference Enable (1:off
0:on), Active Low.
[ 2] EN_DC_DAC_Q ( R/W )
DC Compensation Q Channel Enable
(0: off 1: on)
[ 1] EN_DC_DAC_I ( R/W )
DC Compensation I Channel Enable (0:
off 1: on)
Table 36. Bit Descriptions for DC_CTRL
Bits
[7:3]
2
Bit Name
Settings Description
Reset Access
RESERVED
Reserved.
0x0
0x0
R
EN_DC_DAC_Q
DC Compensation Q Channel Enable (0: off and 1: on). Enables the dc
compensation DAC.
R/W
1
0
EN_DC_DAC_I
DC Compensation I Channel Enable (0: off and 1: on). Enables the dc
compensation DAC.
0x0
0x0
R/W
R/W
ENB_DCCOMP_1P8_GEN
DC DAC 1.8 V Reference Enable (1: off and 0: on). Active Low.
Address: 0x0051, Reset: 0x00, Name: DC_COMP_I_CHAN_RF0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] CODE_DC_IDAC_RF0 (R/W)
DC Compensation I Channel
Table 37. Bit Descriptions for DC_COMP_I_CHAN_RF0
Bits
Bit Name
Settings Description
Reset Access
0x0 R/W
[7:0]
CODE_DC_IDAC_RF0
DC Compensation I Channel. Controls the dc correction applied to the IF
path. LSB is approximately ½ mV referred to the output. Value is signed
magnitude notation. 0xFF is the most negative, and 0x7F is the most positive.
Address: 0x0052, Reset: 0x00, Name: DC_COMP_Q_CHAN_RF0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] CODE_DC_QDAC_RF0 (R/W)
DC Compensation Q Channel
Table 38. Bit Descriptions for DC_COMP_Q_CHAN_RF0
Bits
Bit Name
Settings Description
Reset Access
0x0 R/W
[7:0]
CODE_DC_QDAC_RF0
DC Compensation Q Channel. Controls the dc correction applied to the IF
path. LSB is approximately ½ mV referred to the output. Value is signed
magnitude notation. 0xFF is the most negative, and 0x7F is the most positive.
Address: 0x0053, Reset: 0x00, Name: DC_COMP_I_CHAN_RF1
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] CODE_DC_IDAC_RF1 (R/W)
DC Compensation I Channel
Table 39. Bit Descriptions for DC_COMP_I_CHAN_RF1
Bits
Bit Name
Settings Description
Reset Access
0x0 R/W
[7:0]
CODE_DC_IDAC_RF1
DC Compensation I Channel. Controls the dc correction applied to the IF
path. LSB is approximately ½ mV referred to the output. Value is signed
magnitude notation. 0xFF is the most negative, and 0x7F is the most positive.
Rev. A | Page 44 of 61
Data Sheet
ADRF6821
Address: 0x0054, Reset: 0x00, Name: DC_COMP_Q_CHAN_RF1
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] CODE_DC_QDAC_RF1 (R/W)
DC Compensation Q Channel
Table 40. Bit Descriptions for DC_COMP_Q_CHAN_RF1
Bits
Bit Name
Settings Description
Reset Access
[7:0]
CODE_DC_QDAC_RF1
DC Compensation Q Channel. Controls the dc correction applied to the IF
path. LSB is approximately ½ mV referred to the output. Value is signed
magnitude notation. 0xFF is the most negative, and 0x7F is the most positive.
0x0
R/W
Address: 0x0060, Reset: 0x00, Name: LPF_BW_SEL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :2] RESERVED
[ 0 ] SEL_LPF_BW _M SB ( R/W )
MSB for LPF Bandwidth Select
[ 1] SEL_LPF_BW _LSB ( R/W )
LSB for LPF Bandwidth Select
Table 41. Bit Descriptions for LPF_BW_SEL
Bits
[7:2]
1
Bit Name
Settings Description
Reset Access
RESERVED
Reserved.
0x0
0x0
0x0
R
SEL_LPF_BW_LSB
SEL_LPF_BW_MSB
LSB for LPF Bandwidth Select. See the Theory of Operation section.
MSB for LPF Bandwidth Select. See the Theory of Operation section.
R/W
R/W
0
Address: 0x0070, Reset: 0x00, Name: IF_AMP_CTRL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :2] RESERVED
[ 1 ] EN _IFAM P_Q ( R/W )
[ 0 ] EN_IFAM P_I ( R/W )
I Channel IF Amplifier Enable (0:off 1:on)
Q Channel IF Amplifier Enable (0:off
1:on)
Table 42. Bit Descriptions for IF_AMP_CTRL
Bits Bit Name
Settings Description
Reset Access
[7:2] RESERVED
Reserved.
0x0
0x0
0x0
R
1
0
EN_IFAMP_Q
EN_IFAMP_I
Q Channel IF Amplifier Enable (0: off and 1: on). IF output amplifier enable.
I Channel IF Amplifier Enable (0: off and 1: on). IF output amplifier enable.
R/W
R/W
Address: 0x0080, Reset: 0x00, Name: LO_CTRL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :3] RESERVED
[ 0 ] RESERVED
[ 2] SEL_LO DRV_PREDRVQ _PO L ( R/W )
Invert Q Channel LO Polarity
[ 1] SEL_LO DRV_PREDRVI_PO L ( R/W )
Invert I Channel LO Polarity
Table 43. Bit Descriptions for LO_CTRL
Bits Bit Name
Settings Description
Reset Access
[7:3] RESERVED
Reserved.
0x0
R
2
1
0
SEL_LODRV_PREDRVQ_POL
Invert Q Channel LO Polarity. Selects the polarity for the Q channel LO path. 0x0
0: normal polarity.
1: inverted polarity.
R/W
SEL_LODRV_PREDRVI_POL
RESERVED
Invert I Channel LO Polarity. Selects the polarity for the I channel LO path.
0x0
0x0
R/W
R/W
0: normal polarity.
1: inverted polarity.
Reserved.
Rev. A | Page 45 of 61
ADRF6821
Data Sheet
Address: 0x0090, Reset: 0x00, Name: EN_LO_DIVIDER_CTRL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 ] RESERVED
[ 0 ] EN_IBIASGEN ( R/W )
LO Path Bias Current Enable (0:off 1:on)
Both Paths
[ 6 ] EN_LO DRV_PREDRVQ ( R/W )
Q Channel LO PreDriver Enable (0:off
1:on)
[ 1] EN_DIVPAT H_BUF ( R/W )
LO Divider Path Buffer Enable (0:off
1:on)
[ 5] EN_LO DRV_PREDRVI ( R/W )
I Channel LO PreDriver Enable (0:off
1:on)
[ 2] EN_DIVPAT H_Q UADDIV ( R/W )
LO Divider Path I/Q Divider Enable (0:off
1:on)
[ 4 ] EN_LO DRV_DRVQ ( R/W )
Q Channel LO Driver Enable (0:off 1:on)
[ 3] EN_LO DRV_DRVI ( R/W )
I Channel LO Driver Enable (0:off 1:on)
Table 44. Bit Descriptions for EN_LO_DIVIDER_CTRL
Bits
Bit Name
Settings Description
Reset Access
7
RESERVED
Reserved.
0x0
0x0
R
6
EN_LODRV_PREDRVQ
Q Channel LO Predriver Enable (0: off and 1: on). LO path mixer predriver
enable. This must be enabled whenever LO path is enabled.
R/W
5
4
3
2
EN_LODRV_PREDRVI
EN_LODRV_DRVQ
EN_LODRV_DRVI
I Channel LO Predriver Enable (0: off and 1: on). LO path mixer predriver
enable. This must be enabled whenever LO path is enabled.
0x0
R/W
R/W
R/W
R/W
Q Channel LO Driver Enable (0: off and 1: on). LO path mixer driver enable. 0x0
This must be enabled whenever LO path is enabled.
I Channel LO Driver Enable (0: off and 1: on). LO path mixer driver enable.
This must be enabled whenever LO path is enabled.
0x0
EN_DIVPATH_QUADDIV
LO Divider Path I/Q Divider Enable (0: off and 1: on). Blocks required to be
enabled in this path are: EN_DIVPATH_BUF, EN_LODRVR_DRVx,
EN_LODRVR_PREDRVRx, EN_IBIASGEN, EN_ICMLOBIAS_x,
CODE_MIXER_DRVR.
0x0
1
0
EN_DIVPATH_BUF
EN_IBIASGEN
LO Divider Path Buffer Enable (0: off and 1: on). Blocks required to be
enabled in this path are: EN_DIVPATH_QUADDIV, EN_LODRVR_DRVx,
EN_LODRVR_PREDRVRx, EN_IBIASGEN, EN_ICMLOBIAS_x,
CODE_MIXER_DRVR.
0x0
0x0
R/W
R/W
LO Path Bias Current Enable (0: off and 1) Both Paths.
Address: 0x0092, Reset: 0x00, Name: LO_PHASE_ADJ
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :4 ] T RM _LO DRV_CAPQ ( R/W )
Q Channel LO Phase Adjustment
[ 3:0 ] T RM _LO DRV_CAPI ( R/W )
I Channel LO Phase Adjustment
Table 45. Bit Descriptions for LO_PHASE_ADJ
Bits
Bit Name
Settings Description
Reset Access
[7:4]
TRM_LODRV_CAPQ
Q Channel LO Phase Adjustment. LO Quadrature Phase Adjust. Valid range is
from 0x0 to 0xF. For no compensation or adjustment, both TRM_LODRV_CAPI
and TRM_LODRV_CAPQ must be set to the same value.
0x0
R/W
[3:0]
TRM_LODRV_CAPI
I Channel LO Phase Adjustment. LO Quadrature Phase Adjust. Valid range is
from 0x0 to 0xF. For no compensation or adjustment, both TRM_LODRV_CAPI
and TRM_LODRV_CAPQ must be set to the same value.
0x0
R/W
Rev. A | Page 46 of 61
Data Sheet
ADRF6821
Address: 0x1021, Reset: 0xFF, Name: BLOCK_RESETS
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
[ 7 ] RESERVED
[ 0 ] ARST B_BLO CK_DSM ALL ( R/W )
RSTB - Delta-Sigma Modulator Reference
Counters, Core, Output Stage (+ N Divider)
[ 6 ] ARST B_BLO CK_LKD ( R/W )
RSTB - Lockdetect
[ 1] ARST B_BLO CK_DSM CO RE ( R/W )
RSTB - Delta-Sigma Modulator Core
and Output Stage (+ N Divider)
[ 5] ARST B_BLO CK_AUT O CAL ( R/W )
RSTB - Autocalibration of Counters
[ 4 ] ARST B_BLO CK_NDIV ( R/W )
RSTB - N Divider
[ 2] ARST B_BLO CK_DSM O ST G ( R/W )
RSTB - Delta-Sigma Modulator Output
Stage (and N Divider)
[ 3] ARST B_BLO CK_RDIV ( R/W )
RSTB - Reference Divider
Table 46. Bit Descriptions for BLOCK_RESETS
Bits Bit Name
Settings Description
Reset Access
7
6
5
4
3
2
1
0
RESERVED
Reserved.
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ARSTB_BLOCK_LKD
ARSTB_BLOCK_AUTOCAL
ARSTB_BLOCK_NDIV
ARSTB_BLOCK_RDIV
ARSTB_BLOCK_DSMOSTG
ARSTB_BLOCK_DSMCORE
ARSTB_BLOCK_DSMALL
RSTB – Lockdetect
RSTB – Autocalibration of Counters
RSTB – N Divider (integer divider)
RSTB – Reference Divider
RSTB – Delta-Sigma Modulator Output Stage (and N Divider)
RSTB – Delta-Sigma Modulator Core and Output Stage (+N Divider)
RSTB – Delta-Sigma Modulator Reference Counters, Core, Output Stage
(+N Divider)
Address: 0x1109, Reset: 0x0A, Name: SIG_PATH_9_NORMAL
7
6
5
4
3
2
1
0
0
0
0
0
1
0
1
0
[ 7 :5] RESERVED
[ 0 ] RESERVED
[ 4 :3] T RM _M IXLO DRV_DRV_PO UT ( R/W )
LO Output to Mixer Power Level
[ 2:1] T RM _XLO DRV_DRV_PO UT ( R/W )
Auxiliary LO Output Power Level
Table 47. Bit Descriptions for SIG_PATH_9_NORMAL
Bits
[7:5]
[4:3]
[2:1]
0
Bit Name
Settings Description
Reset
0x0
Access
R
RESERVED
Reserved
TRM_MIXLODRV_DRV_POUT
TRM_XLODRV_DRV_POUT
RESERVED
LO Output to Mixer Power Level
Auxiliary LO Output Power Level
Reserved
0x1
R/W
R/W
R
0x1
0x0
Address: 0x1200, Reset: 0x89, Name: INT_L
7
6
5
4
3
2
1
0
1
0
0
0
1
0
0
1
[7:0] INT_DIV[7:0] (R/W)
Integer-N Word - Optionally Double
Buffered.
Table 48. Bit Descriptions for INT_L
Bits
Bit Name Settings Description
Reset
Access
[7:0]
INT_DIV,
Bits[7:0]
Integer-N Word—Optionally Double Buffered. Writing the LSB of the integer
word normally causes an autotune event.
0x189
R/W
Rev. A | Page 47 of 61
ADRF6821
Data Sheet
Address: 0x1201, Reset: 0x01, Name: INT_H
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:0] INT_DIV[15:8] (R/W)
Integer-N Word - Optionally Double
Buffered.
Table 49. Bit Descriptions for INT_H
Bits Bit Name Settings Description
Reset
Access
[7:0] INT_DIV,
Bits[15:8]
Integer-N Word—Optionally Double Buffered. Writing the LSB 0x189
of the integer word normally causes an autotune event.
R/W
Address: 0x1202, Reset: 0x00, Name: FRAC1_L
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] FRAC[ 7 :0 ] ( R/W )
FRAC-N Word - Optionally Double Buffered
Table 50. Bit Descriptions for FRAC1_L
Bits Bit Name
Settings Description
FRAC-N Word – Optionally Double Buffered. Lower 8 bits of 24-bit FRAC value.
Reset Access
[7:0] FRAC, Bits[7:0]
0x0
R/W
Address: 0x1203, Reset: 0x00, Name: FRAC1_M
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] FRAC[ 15:8 ] ( R/W )
FRAC-N Word - Optionally Double Buffered
Table 51. Bit Descriptions for FRAC1_M
Bits Bit Name
Settings Description
Reset Access
0x0 R/W
[7:0] FRAC, Bits[15:8]
FRAC-N Word – Optionally Double Buffered. Lower 8 bits of 24-bit FRAC value.
Address: 0x1204, Reset: 0x00, Name: FRAC1_H
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] FRAC[ 23:16 ] ( R/W )
FRAC-N Word - Optionally Double Buffered
Table 52. Bit Descriptions for FRAC1_H
Bits Bit Name
Settings Description
Reset Access
0x0 R/W
[7:0] FRAC, Bits[23:16]
FRAC-N Word – Optionally Double Buffered. Lower 8 bits of 24-Bit FRAC value.
Rev. A | Page 48 of 61
Data Sheet
ADRF6821
Address: 0x1205, Reset: 0x00, Name: SD_PHASE_L_0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] PHASE[7:0] (R/W)
Sigma-Delta Phase Word
Table 53. Bit Descriptions for SD_PHASE_L_0
Bits
Bit Name
Settings Description
Reset Access
[7:0]
PHASE,
Bits[7:0]
Sigma-Delta Phase Word. If phase adjust mode is enabled (PHASE_ADJ_EN = 1), the
phase in the DSM is incremented by this amount on each phase adjustment trigger.
The phase adjustment trigger can be caused by the SPI via a write to the LSB of this
register (provided DISABLE_PHASEADJ = 0) or from the GPI port. The value is
represented as an unsigned 24-bit fractional number, in units of VCO cycles. It,
therefore, has a resolution of 21 µ°. For example, to adjust the phase by 5° of the
fundamental VCO, program this word to (5°/360°) × 224 = 233,017. This process can
be done repetitively to effectively recede by multiple VCO cycles or to embed the
PLL itself inside the phase or frequency control loops under some other supervisory
control. The phase adjust feature cannot be done any faster than once every five PFD
cycles and by no more than 180° on any individual adjustment.
0x0
R/W
Address: 0x1206, Reset: 0x00, Name: SD_PHASE_M_0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] PHASE[15:8] (R/W)
Sigma-Delta Phase Word
Table 54. Bit Descriptions for SD_PHASE_M_0
Bits
Bit Name
Settings Description
Reset Access
0x0 R/W
[7:0]
PHASE,
Bits[15:8]
Sigma-Delta Phase Word. If phase adjust mode is enabled (PHASE_ADJ_EN = 1), the
phase in the DSM is incremented by this amount on each phase adjustment trigger.
The phase adjustment trigger can be caused by the SPI via a write to the LSB of this
register (provided DISABLE_PHASEADJ = 0) or from the GPI port. The value is
represented as an unsigned 24-bit fractional number, in units of VCO cycles. It,
therefore, has a resolution of 21 µ°. For example, to adjust the phase by 5° of the
fundamental VCO, program this word to (5°/360°) × 224 = 233,017. This process can be
done repetitively to effectively recede by multiple VCO cycles or to embed the PLL
itself inside the phase or frequency control loops under some other supervisory
control. The phase adjust feature cannot be done any faster than once every five PFD
cycles and by no more than 180° on any individual adjustment.
Address: 0x1207, Reset: 0x00, Name: SD_PHASE_H_0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] PHASE[23:16] (R/W)
Sigma-Delta Phase Word
Table 55. Bit Descriptions for SD_PHASE_H_0
Bits Bit Name
Settings Description
Reset Access
0x0 R/W
[7:0] PHASE,
Bits[23:16]
Sigma-Delta Phase Word. If phase adjust mode is enabled (PHASE_ADJ_EN = 1), the
phase in the DSM is incremented by this amount on each phase adjustment trigger.
The phase adjustment trigger can be caused by the SPI via a write to the LSB of this
register (provided DISABLE_PHASEADJ = 0) or from the GPI port. The value is
represented as an unsigned 24-bit fractional number, in units of VCO cycles. It,
therefore, has a resolution of 21 µ°. For example, to adjust the phase by 5° of the
fundamental VCO, program this word to (5°/360°) × 224 = 233,017. This process can
be done repetitively to effectively recede by multiple VCO cycles or to embed the
PLL itself inside the phase or frequency control loops under some other supervisory
control. The phase adjust feature cannot be done any faster than once every five PFD
cycles, and by no more than 180° on any individual adjustment.
Rev. A | Page 49 of 61
ADRF6821
Data Sheet
Address: 0x1208, Reset: 0x00, Name: MOD_L
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] M O D2[ 7 :0 ][ 7 :0 ] ( R/W )
MOD2 word.
Table 56. Bit Descriptions for MOD_L
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
MOD2, Bits[7:0]
MOD2 word; lower bits
0x0
R/W
Address: 0x1209, Reset: 0x00, Name: MOD_H
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :6 ] RESERVED
[ 5:0 ] M O D2[ 7 :0 ][ 13:8 ] ( R/W )
MOD2 word.
Table 57. Bit Descriptions for MOD_H
Bits
[7:6]
[5:0]
Bit Name
Settings
Description
Reset
0x0
Access
R
RESERVED
Reserved
MOD2, Bits[13:8]
MOD2 word; upper bits
0x0
R/W
Address: 0x120B, Reset: 0x01, Name: SYNTH
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[ 7 :2] RESERVED
[ 0 ] EN_FBDIV ( R/W )
Enable Feedback Divider
[ 1] PRE_SEL ( R/W )
Prescaler Select
0: Disable 2x Prescaler.
1: Enable 2x Prescaler.
Table 58. Bit Descriptions for SYNTH
Bits
[7:2]
1
Bit Name
RESERVED
PRE_SEL
Settings
Description
Reserved.
Reset
0x0
0x0
Access
R
Prescaler Select
R/W
0
1
Disable 2× Prescaler
Enable 2× Prescaler
0
EN_FBDIV
Enable Feedback Divider
0x1
R/W
Address: 0x120C, Reset: 0x03, Name: R_DIV
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
1
[7] RESERVED
[6:0] R_DIV (R/W)
R Divider Word
Table 59. Bit Descriptions for R_DIV
Bits
7
Bit Name
RESERVED
R_DIV
Settings
Description
Reserved.
R Divider Word. Lower 8 bits of 10-bit reference R divider word.
Reset
0x0
Access
R
[6:0]
0x3
R/W
Rev. A | Page 50 of 61
Data Sheet
ADRF6821
Address: 0x120E, Reset: 0x04, Name: SYNTH_0
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
0
[ 7 :4 ] RESERVED
[ 0 ] RDIV2_SEL ( R/W )
Reference Divide by 2
[ 3] DO UBLER_EN ( R/W )
Reference Doubler Enable - Optionally
Double-Buffered
0: Reference Divide by 2 Disabled.
1: Reference Divide by 2 Enabled.
[ 2:1] RESERVED
Table 60. Bit Descriptions for SYNTH_0
Bits
[7:4]
3
Bit Name
Settings
Description
Reset
Access
R
RESERVED
DOUBLER_EN
RESERVED
RDIV2_SEL
Reserved
0x0
0x0
0x2
0x0
Reference Doubler Enable—Optionally Double Buffered
Reserved
R/W
R/W
R/W
[2:1]
0
Reference Divide by 2
0
1
Reference Divide by 2 Disabled
Reference Divide by 2 Enabled
Address: 0x1214, Reset: 0x48, Name: MULTI_FUNC_SYNTH_CTRL_0214
7
6
5
4
3
2
1
0
0
1
0
0
1
0
0
0
[7:6] LD_BIAS (R/W)
Lock Detect Bias
00: 40uA.
[2:0] RESERVED
01: 30uA.
10: 20uA.
11: 10uA.
[5:3] LDP (R/W)
Lock Detect Precision
000: Check 1024 Consecutive PFD Cycles
for Lock.
001: Check 2048 Consecutive PFD Cycles.
010: Check 4096 Consecutive PFD Cycles.
011: Check 8192 Consecutive PFD Cycles.
Table 61. Bit Descriptions for MULTI_FUNC_SYNTH_CTRL_0214
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
LD_BIAS
Lock Detect Bias
00 40 µA.
01 30 µA.
10 20 µA.
11 10 µA.
0x1
0x1
0x0
R/W
R/W
R/W
[5:3]
[2:0]
LDP
Lock Detect Precision
000 Check 1024 Consecutive PFD Cycles for Lock.
001 Check 2048 Consecutive PFD Cycles.
010 Check 4096 Consecutive PFD Cycles.
011 Check 8192 Consecutive PFD Cycles.
Reserved.
RESERVED
Address: 0x1215, Reset: 0x00, Name: SI_BAND_0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] SI_BAND_SEL ( R/W )
Manually Programmed VCO Band
Table 62. Bit Descriptions for SI_BAND_0
Bits Bit Name
Settings Description
Reset Access
[7:0] SI_BAND_SEL
Manually Programmed VCO Band.
0x0
R/W
Rev. A | Page 51 of 61
ADRF6821
Data Sheet
Address: 0x1217, Reset: 0x00, Name: SI_VCO_SEL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :4 ] RESERVED
[ 3:0 ] SI_VCO _SEL ( R/W )
Manual VCO Core Select
Table 63. Bit Descriptions for SI_VCO_SEL
Bits
[7:4]
[3:0]
Bit Name
RESERVED
SI_VCO_SEL
Settings Description
Reset Access
Reserved
0x0
0x0
R
Manual VCO Core Select
R/W
Address: 0x121C, Reset: 0x20, Name: VCO_TIMEOUT_L
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
0
[ 7 :0 ] VCO _T IM EO UT [ 7 :0 ] ( R/W )
Main VCO Calibration Timeout
Table 64. Bit Descriptions for VCO_TIMEOUT_L
Bits Bit Name
[7:0] VCO_TIMEOUT[7:0]
Settings Description
Reset Access
0x20 R/W
Main VCO Calibration Timeout. This value sets what a timing unit is in the
VCO calibration. It is represented in a number of phase frequency detector
(PFD) periods. For example, 32 is 32 PFD cycles. At a 30.72 MHz PFD rate, this
timer represents an approximately 1 µs period. It is recommended that the user
program this value, depending on their PFD rate, to represent approximately
1 µs to 2 µs. A longer value than necessary leads to longer autocalibration times,
and shorter values may risk autotune accuracy due to insufficient settling times.
Address: 0x121D, Reset: 0x00, Name: VCO_TIMEOUT_H
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :2] RESERVED
[ 1:0 ] VCO _T IM EO UT [ 9 :8 ] ( R/W )
Main VCO Calibration Timeout
Table 65. Bit Descriptions for VCO_TIMEOUT_H
Bits Bit Name
Settings Description
Reset Access
[7:2] RESERVED
[1:0] VCO_TIMEOUT[9:8]
Reserved.
0x0
0x0
R
R/W
Main VCO Calibration Timeout. This value sets what a timing unit is in the
VCO calibration. It is represented in a number of PFD periods. For example,
32 is 32 PFD cycles. At a 30.72 MHz PFD rate, this timer represents an
approximately 1 µs period. It is recommended that the user program this value,
depending on their PFD rate, to represent approximately 1 µs to 2 µs. A longer
value than necessary leads to longer autocalibration times, and shorter values
may risk autotune accuracy due to insufficient settling times.
Address: 0x121E, Reset: 0x14, Name: VCO_BAND_DIV
7
6
5
4
3
2
1
0
0
0
0
1
0
1
0
0
[ 7 :0 ] VCO _BAND_DIV ( R/W )
AFC Measurement Resolution
Table 66. Bit Descriptions for VCO_BAND_DIV
Bits Bit Name
[7:0] VCO_BAND_DIV
Settings Description
Reset Access
0x14 R/W
AFC Measurement Resolution. This value sets how long a single automatic
frequency calibration (AFC) measurement cycle lasts. The AFC measurement
lasts 16 × VCO_BAND_DIV. It is required that the user program this value,
depending on their PFD rate, to represent approximately 10 µs. A longer value
than necessary leads to longer autocalibration times, and shorter values may
risk autotune accuracy due to insufficient frequency measurement resolution.
Address: 0x121F, Reset: 0x00, Name: VCO_FSM
Rev. A | Page 52 of 61
Data Sheet
ADRF6821
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 ] RESERVED
[ 5:0 ] RESERVED
[ 6 ] DISABLE_CAL ( R/W )
Disable VCO Automatic Level Control
(ALC) and Automatic Frequency Control
(AFC) Calibration
0: Power Down Synthesizer.
1: Power Up Synthesizer.
Table 67. Bit Descriptions for VCO_FSM
Bits
Bit Name
Settings Description
Reset Access
7
RESERVED
DISABLE_CAL
Reserved.
0x0
0x0
R
6
Disable VCO Automatic Level Control (ALC) and Automatic Frequency Control
(AFC) Calibration. The PLL does not reset the calibration machine or trigger a new
calibration if set to 1 on a frequency hop to maintain ALC and capacitor positions.
R/W
0
1
Power-Down Synthesizer.
Power-Up Synthesizer.
Reserved.
[5:0]
RESERVED
0x0
R/W
Address: 0x122A, Reset: 0x02, Name: SD_CTRL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
[ 7 :6 ] RESERVED
[ 0 ] RESERVED
[ 5] SD_EN_FRAC0 ( R/W )
Sigma-Delta Enable with FRAC =
[ 1 ] SD _SM _2 ( R/W )
Loss of Lock (LOL) Enabled
0
[ 4 ] SD _EN _O UT _O FF ( R/W )
Sigma-Delta Enable, Output Off
[ 3:2] RESERVED
Table 68. Bit Descriptions for SD_CTRL
Bits
[7:6]
5
Bit Name
Settings Description
Reset Access
RESERVED
Reserved.
0x0
0x0
R/W
R/W
SD_EN_FRAC0
Sigma-Delta Enable with FRAC = 0. The DSM normally recognizes a FRAC value
of all 0, and disables itself. Setting this mode can keep the DSM running even
when a zero FRAC is presented.
4
SD_EN_OUT_OFF
Sigma-Delta Enable, Output Off. Keeps the DSM core enabled and clocking but
ignores the output of the DSM and instead multiplexes the N divider setpoint
from the double buffer data directly.
0x0
R/W
[3:2]
1
RESERVED
SD_SM_2
RESERVED
Reserved.
0x0
R
Loss of Lock (LOL) Enabled. Enables the CSP/LOL circuit. Recommend Reserved 1. 0x1
Reserved. 0x0
R/W
R/W
0
Address: 0x122C, Reset: 0x03, Name: MULTI_FUNC_SYNTH_CTRL_022C
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
1
[7:2] RESERVED
[1:0] CP_HIZ (R/W)
Charge Pump Tristate
0: Charge Pump Tristate Mode 0.
1: Charge Pump Tristate Mode 1.
2: Charge Pump Tristate Mode 2.
3: Charge Pump Tristate Mode 3.
Table 69. Bit Descriptions for MULTI_FUNC_SYNTH_CTRL_022C
Bits
[7:2]
[1:0]
Bit Name
RESERVED
CP_HIZ
Settings
Description
Reset
0x0
Access
Reserved
R
Charge Pump Tristate
0x3
R/W
0
1
2
3
Charge Pump Tristate Mode 0
Charge Pump Tristate Mode 1
Charge Pump Tristate Mode 2
Charge Pump Tristate Mode 3
Rev. A | Page 53 of 61
ADRF6821
Data Sheet
Address: 0x122D, Reset: 0x81, Name: MULTI_FUNC_SYNTH_CTRL_022D
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
1
[7] EN_PFD_CP (R/W)
[0] BLEED_EN (R/W)
Enable Phase Detector and Charge
Pump
Bleed Enable
[1] RESERVED
[6] BLEED_POL (R/W)
Selects the Bleed Polarity
[2] INT_ABP (R/W)
Integer-N ABP Select
[5:3] RESERVED
Table 70. Bit Descriptions for MULTI_FUNC_SYNTH_CTRL_022D
Bits
Bit Name
EN_PFD_CP
BLEED_POL
RESERVED
INT_ABP
Settings
Description
Reset
0x1
0x0
0x0
0x0
0x0
0x1
Access
R/W
R/W
R
7
Enable Phase Detector and Charge Pump.
Selects the Bleed Polarity.
Reserved.
6
[5:3]
2
Integer-N ABP Select. Shortens the reset delay of the PFD by four inverters.
R/W
R
1
RESERVED
BLEED_EN
Reserved.
0
Bleed Enable.
R/W
Address: 0x122E, Reset: 0x0F, Name: CP_CURR
7
6
5
4
3
2
1
0
0
0
0
0
1
1
1
1
[7:4] RESERVED
[3:0] CP_CURRENT (R/W)
Main Charge Pump Current
Table 71. Bit Descriptions for CP_CURR
Bits
[7:4]
[3:0]
Bit Name
Settings
Description
Reset
Access
R
RESERVED
CP_CURRENT
Reserved
0x0
0xF
Main Charge Pump Current
R/W
Address: 0x122F, Reset: 0x08, Name: BICP
7
6
5
4
3
2
1
0
0
0
0
0
1
0
0
0
[7:0] BICP (R/W)
Binary Scaled Bleed Current
Table 72. Bit Descriptions for BICP
Bits
Bit Name
Settings
Description
Reset
Access
R/W
[7:0]
BICP
Binary Scaled Bleed Current
0x8
Address: 0x1233, Reset: 0x00, Name: FRAC2_L
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] FRAC2[ 7 :0 ] ( R/W )
FRAC2 Word for Exact Frequency Mode
- Optionally Double Buffered
Table 73. Bit Descriptions for FRAC2_L
Bits
Bit Name
Settings
Description
FRAC2 Word for Exact Frequency Mode—Optionally Double Buffered
Reset
0x0
Access
[7:0]
FRAC2, Bits[7:0]
R/W
Rev. A | Page 54 of 61
Data Sheet
ADRF6821
Address: 0x1234, Reset: 0x00, Name: FRAC2_H
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :6 ] RESERVED
[ 5:0 ] FRAC2[ 13:8 ] ( R/W )
FRAC2 Word for Exact Frequency Mode
- Optionally Double Buffered
Table 74. Bit Descriptions for FRAC2_H
Bits
[7:6]
[5:0]
Bit Name
Settings
Description
Reset
0x0
Access
R
RESERVED
Reserved
FRAC2, Bits[13:8]
FRAC2 Word for Exact Frequency Mode—Optionally Double Buffered
0x0
R/W
Address: 0x1235, Reset: 0x00, Name: MULTI_FUNC_SYNTH_CTRL_0235
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:2] RESERVED
[0] RESERVED
[1] PHASE_ADJ_EN (R/W)
DSM Phase Adjust Enable
Table 75. Bit Descriptions for MULTI_FUNC_SYNTH_CTRL_0235
Bits Bit Name
Settings Description
Reset Access
[7:2] RESERVED
Reserved.
0x0
0x0
R
1
PHASE_ADJ_EN
DSM Phase Adjust Enable. If 1, a phase-adjust trigger causes a phase shift in the
Δ-Σ by the amount programmed in the phase word. The phase trigger is either
caused by a write to the LSB of the phase word or through a general-purpose
input (GPI) trigger. See GPI1_FUNC_SEL for more information.
R/W
0
RESERVED
Reserved.
0x0
R
Address: 0x1240, Reset: 0x00, Name: VCO_LUT_CTRL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :5] RESERVED
[ 0 ] SI_VCO _FO RCE_CAPS ( R/W )
Force the SPI to Cap-Select at the Output
of the Look Up Table (LUT)
[ 4 ] SI_VCO _FO RCE_CAPSVCO I ( R/W )
Manual VCO Capacitor Select
[ 1] SI_VCO _FO RCE_VCO ( R/W )
Force the VCO Select and the Output
of the Look Up Table (LUT) from SI_VCO_SEL
[ 3:2] RESERVED
Table 76. Bit Descriptions for VCO_LUT_CTRL
Bits Bit Name
Settings Description
Reset Access
[7:5] RESERVED
Reserved
0x0
0x0
0x0
0x0
R
4
SI_VCO_FORCE_CAPSVCOI
Manual VCO Capacitor Select
Reserved
R/W
R/W
R/W
[3:2] RESERVED
1
SI_VCO_FORCE_VCO
Force the VCO Select and the Output of the Look Up Table (LUT) from
SI_VCO_SEL
0
SI_VCO_FORCE_CAPS
Force the SPI to Capacitor Select at the Output of the Look Up Table (LUT)
0x0
R/W
Address: 0x124D, Reset: 0x00, Name: LOCK_DETECT
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:1] RESERVED
[0] LOCK_DETECT (R)
State of the Lock Detect Signal
Table 77. Bit Descriptions for LOCK_DETECT
Bits
[7:1]
0
Bit Name
Settings
Description
Reset
0x0
Access
RESERVED
Reserved
R
R
LOCK_DETECT
State of the Lock Detect Signal
Rev. A | Page 55 of 61
0x0
ADRF6821
Data Sheet
Address: 0x1401, Reset: 0x00, Name: MULTI_FUNC_CTRL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:5] RESERVED
[3:0] RESERVED
[4] SPI_1P8_3P3_CTRL (R/W)
SPI Supply Control
0: 1.8V Read Back.
1: 3.3V Read Back.
Table 78. Bit Descriptions for MULTI_FUNC_CTRL
Bits
[7:5]
4
Bit Name
Settings
Description
Reserved
Reset
0x0
Access
R
RESERVED
SPI_1P8_3P3_CTRL
SPI Supply Control
1.8 V Read Back
3.3 V Read Back
Reserved
0x0
R/W
0
1
[3:0]
RESERVED
0x0
R
Address: 0x140E, Reset: 0xB3, Name: LO_CNTRL2
7
6
5
4
3
2
1
0
1
0
1
1
0
0
1
1
[7] EN_BIAS_R (R/W)
[4:0] RESERVED
Enable the Resistor Bias
[5] REFBUF_EN (R/W)
[6] RESERVED
Reference Buffer Enable
Table 79. Bit Descriptions for LO_CNTRL2
Bits Bit Name Settings Description
Reset Access
7
EN_BIAS_R
Enable the Resistor Bias. Selects the resistor bias instead of the band gap based bias
for the LO path.
0x1
R/W
6
5
RESERVED
Reserved.
0x0
R/W
R/W
R/W
REFBUF_EN
Reference Buffer Enable.
Reserved.
0x1
[4:0] RESERVED
0x13
Rev. A | Page 56 of 61
Data Sheet
ADRF6821
Address: 0x1414, Reset: 0x02, Name: LO_CNTRL8
Recommended register for use to control the LO path from a single spot. By programming this register, the individual blocks enable and
configuration bits are set appropriately.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
[ 7 ] M IX_O E ( R/W )
[ 4 :0 ] O UT _DIVRAT IO ( R/W )
Output Path Divide Ratio
1: /1.
Mix Output Enable
[ 6 ] LO _O E ( R/W )
LO Path Output Enable
10: /2.
100: /4.
1000: /8.
10000: /16.
[ 5] USEEXT _LO I ( R/W )
Use External LO Path
Table 80. Bit Descriptions for LO_CNTRL8
Bits
Bit Name
Settings Description
Reset Access
7
MIX_OE
Mix Output Enable. When disabled (OE = 0), mute = 1, or DIVRATIO = 0, the mute
depth is selected via GEN_MUTE_DEPTH. Note that the mute depth can be
artificially restricted if the other output path is still enabled and relies on a shared
branch of the LO chain.
0x0
R/W
6
LO_OE
LO Path Output Enable. When disabled (OE = 0), MUTE = 1, or DIVRATIO = 0, the
mute depth is selected via GEN_MUTE_DEPTH. Note that the mute depth can be
artificially restricted if the other output path is still enabled and relies on a shared
branch of the LO chain.
0x0
R/W
5
USEEXT_LOI
Use External LO Path.
0x0
0x2
R/W
R/W
[4:0]
OUT_DIVRATIO
Output Path Divide Ratio. Sets the divide ratio from the fundamental VCOs or the
external input path to the output paths. Nominally, the internal VCO range is
4 GHz to 8 GHz.
0
1
Mute
/1.
10 /2.
100 /4.
1000 /8.
10000 /16.
Address: 0x1541, Reset: 0x00, Name: FRAC2_L_SLAVE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] FRAC2_SLV[ 7 :0 ] ( R)
FRAC2 Word Double Buffered Value
Table 81. Bit Descriptions for FRAC2_L_SLAVE
Bits
Bit Name
Settings
Description
FRAC2 Word Double Buffered Value
Reset
Access
[7:0]
FRAC2_SLV, Bits[7:0]
0x0
R
Address: 0x1542, Reset: 0x00, Name: FRAC2_H_SLAVE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :6 ] RESERVED
[ 5:0 ] FRAC2_SLV[ 13:8 ] ( R)
FRAC2 Word Double Buffered Value
Table 82. Bit Descriptions for FRAC2_H_SLAVE
Bits
[7:6]
[5:0]
Bit Name
Settings
Description
Reset
0x0
Access
RESERVED
Reserved
R
R
FRAC2_SLV, Bits[13:8]
FRAC2 Word Double Buffered Value
0x0
Rev. A | Page 57 of 61
ADRF6821
Data Sheet
Address: 0x1543, Reset: 0x00, Name: FRAC_L_SLAVE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] FRAC_SLV[ 7 :0 ][ 7 :0 ] ( R)
FRAC-N Word Double Buffered Value
Table 83. Bit Descriptions for FRAC_L_SLAVE
Bits Bit Name Settings Description
[7:0] FRAC_SLV, Bits[7:0] FRAC-N Word Double Buffered Value. Lower 8 bits of 24-Bit FRAC value.
Reset Access
0x0
R
Address: 0x1544, Reset: 0x00, Name: FRAC_M_SLAVE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] FRAC_SLV[ 7 :0 ][ 15:8 ] ( R)
FRAC-N Word Double Buffered Value
Table 84. Bit Descriptions for FRAC_M_SLAVE
Bits Bit Name Settings Description
[7:0] FRAC_SLV, Bits[15:8] FRAC-N Word Double Buffered Value. Lower 8 bits of 24-Bit FRAC value.
Reset Access
0x0
R
Address: 0x1545, Reset: 0x00, Name: FRAC_H_SLAVE2
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :0 ] FRAC_SLV[ 7 :0 ][ 23:16 ] ( R)
FRAC-N Word Double Buffered Value
Table 85. Bit Descriptions for FRAC_H_SLAVE2
Bits Bit Name Settings Description
[7:0] FRAC_SLV, Bits[23:16] FRAC-N Word Double Buffered Value. Lower 8 bits of 24-Bit FRAC value.
Reset
Access
0x0
R
Address: 0x1546, Reset: 0x00, Name: PHASE_L_SLAVE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] PHASE_SLV[7:0] (R)
Sigma-Delta Phase Word
Table 86. Bit Descriptions for PHASE_L_SLAVE
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
PHASE_SLV, Bits[7:0]
Sigma-Delta Phase Word. Lower 8 bits of 24-bit SD phase word.
0x0
R
Address: 0x1547, Reset: 0x00, Name: PHASE_M_SLAVE2
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] PHASE_SLV[15:8] (R)
Sigma-Delta Phase Word
Table 87. Bit Descriptions for PHASE_M_SLAVE2
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
PHASE_SLV, Bits[15:8]
Sigma-Delta Phase Word. Lower 8 bits of 24-bit SD phase word.
0x0
R
Rev. A | Page 58 of 61
Data Sheet
ADRF6821
Address: 0x1548, Reset: 0x00, Name: PHASE_H_SLAVE3
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] PHASE_SLV[23:16] (R)
Sigma-Delta Phase Word
Table 88. Bit Descriptions for PHASE_H_SLAVE3
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
PHASE_SLV, Bits[23:16]
Sigma-Delta Phase Word. Lower 8 bits of 24-bit SD phase word.
0x0
R
Address: 0x1549, Reset: 0x89, Name: INT_DIV_L_SLAVE
7
6
5
4
3
2
1
0
1
0
0
0
1
0
0
1
[7:0] INT_DIV_SLV[7:0] (R)
Integer-N Word - Double Buffered
Readback Value
Table 89. Bit Descriptions for INT_DIV_L_SLAVE
Bits Bit Name
Settings Description
Reset Access
0x189
[7:0] INT_DIV_SLV,
Bits[7:0]
Integer-N Word – Double Buffered Readback Value. Readback Data from the N
divider setpoint (NSETPOINT) double buffer output.
R
Address: 0x154A, Reset: 0x01, Name: INT_DIV_H_SLAVE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:0] INT_DIV_SLV[15:8] (R)
Integer-N Word - Double Buffered
Readback Value
Table 90. Bit Descriptions for INT_DIV_H_SLAVE
Bits
Bit Name
Settings Description
Integer-N Word – Double Buffered Readback Value. Readback Data from the
SETPOINT double buffer output.
Reset Access
[7:0]
INT_DIV_SLV,
Bits[15:8]
0x189
R
N
Address: 0x154B, Reset: 0x03, Name: R_DIV_SLAVE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
1
[7] RESERVED
[6:0] R_DIV_SLV (R)
R Divider Word
Table 91. Bit Descriptions for R_DIV_SLAVE
Bits
Bit Name
RESERVED
R_DIV_SLV
Settings
Description
Reset
Access
7
Reserved.
0x0
0x3
R
R
[6:0]
R Divider Word. Lower 8 bits of 10-bit reference R divider word.
Rev. A | Page 59 of 61
ADRF6821
Data Sheet
Address: 0x154C, Reset: 0x00, Name: RDIV2_SEL_SLAVE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:1] RESERVED
[0] RDIV2_SEL_SLV (R)
Reference Divide by 2
0: Reference Divide by 2 Disabled.
1: Reference Divide by 2 Enabled.
Table 92. Bit Descriptions for RDIV2_SEL_SLAVE
Bits
[7:1]
0
Bit Name
Settings
Description
Reset
0x0
Access
RESERVED
Reserved.
R
R
RDIV2_SEL_SLV
Reference Divide by 2
0x0
0
1
Reference Divide by 2 Disabled
Reference Divide by 2 Enabled
Address: 0x1583, Reset: 0x00, Name: DISABLE_CFG
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :5] RESERVED
[ 0 ] DISABLE_PHASEADJ( R/W )
Disable the Phase Adjust from the SPI
Register
[ 4 :3] DSM _LAUNCH_DLY ( R/W )
Delay the DSM Clock Launch.
[ 1] DISABLE_DBLBUFFERING ( R/W )
If Double Buffering Is Disabled, a R_DIV
Write Resets Rdivider
[ 2] DISABLE_FREQ HO P ( R/W )
Disable the Generation of Frequency
Hop from the SPI Register
Table 93. Bit Descriptions for DISABLE_CFG
Bits Bit Name
Settings Description
Reset Access
[7:5] RESERVED
Reserved.
0x0
0x0
0x0
0x0
0x0
R
[4:3] DSM_LAUNCH_DLY
Delay the DSM Clock Launch.
R/W
R/W
R/W
R/W
2
1
0
DISABLE_FREQHOP
Disable the Generation of the Frequency Hop from the SPI Register.
If Double Buffering Is Disabled, a R_DIV Write Resets RDIVIDER.
Disable the Phase Adjust from the SPI Register.
DISABLE_DBLBUFFERING
DISABLE_PHASEADJ
Rev. A | Page 60 of 61
Data Sheet
ADRF6821
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
8.10
8.00 SQ
7.90
0.30
0.25
0.20
PIN 1
INDICATOR
AREA
PIN 1
INDICATOR AREA OPTIONS
(SEE DETAIL A)
43
56
1
42
0.50
BSC
*
6.80
EXPOSED
PAD
6.70 SQ
6.60
29
14
28
15
0.45
0.40
0.35
TOP VIEW
SIDE VIEW
BOTTOM VIEW
6.50 REF
0.20 MIN
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.203 REF
*
COMPLIANT TO JEDEC STANDARDS MO-220-WLLD-5
WITH EXCEPTION TO EXPOSED PAD DIMENSION.
Figure 66. 56-Lead Lead Frame Chip Scale Package [LFCSP]
8 mm × 8 mm Body and 0.75 mm Package Height
(CP-56-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
ADRF6821ACPZ
ADRF6821ACPZ-RL7
ADRF6821-EVALZ
−40°C to +105°C
−40°C to +105°C
56-Lead Lead Frame Chip Scale Package [LFCSP]
56-Lead Lead Frame Chip Scale Package [LFCSP], Reel
Evaluation Board
CP-56-16
CP-56-16
1 Z = RoHS Compliant Part.
©2017–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14807-0-8/18(A)
Rev. A | Page 61 of 61
相关型号：
©2020 ICPDF网 联系我们和版权申明