ADRF6658_技术文档

Wideband, Dual Rx Mixers

with Integrated IF Amplifiers

Data Sheet

ADRF6658

FEATURES

GENERAL DESCRIPTION

Wideband, dual-channel, active downconversion mixers

Low distortion, fast settling, IF DGAs

RF input frequency range: 690 MHz to 3.8 GHz

Programmable baluns on RF inputs

For RF = 1950 MHz, IF = 281 MHz, high linearity mode

Voltage conversion gain, including IF filter loss:

−5 dB to +26.5 dB

Input IP3: 29 dBm at minimum DGA gain

Input P1dB: 12 dBm at minimum DGA gain

SSB NF: 13 dB at maximum DGA gain

Output IP3: 40 dBm at maximum DGA gain

Output P1dB: 19 dBm at maximum DGA gain

Channel isolation: 52 dB

Differential and single-ended LO input modes

Differential IF output impedance: 100 Ω

Flexible power-down modes for low power operation

Power-up time after enabling channels: 100 ns, typical

Programmable via a 3-wire serial port interface (SPI)

Single 3.3 V supply

The ADRF6658 is a high performance, low power, wideband,

dual-channel radio frequency (RF) downconverter with

integrated intermediate frequency (IF) digitally controlled

amplifiers (DGAs) for wideband, low distortion base station

radio receivers.

The dual Rx mixers are doubly balanced Gilbert cell mixers

with high linearity and excellent image rejection. Both mixers

convert 50 Ω RF inputs to open-collector broadband IF outputs.

Internal tunable baluns on the RF inputs enable suppression of

RF signal harmonics and attenuation of out-of-band signals

before the mixer inputs, reducing input reflections and out-of-

band interference signals. A flexible local oscillator (LO)

architecture allows the use of differential or single-ended LO

signals.

The dual-channel IF DGAs are based on the ADL5201 and

ADL5202 and have a fixed, differential output impedance of

100 Ω. The gain is adjustable over a 31.5 dB range with a 0.5 dB

step size via the on-chip SPI, or through independent, 6-bit

parallel ports that support latch functionality. Each channel,

from the mixer inputs to the IF amplifier outputs, together with

an LC interstage band-pass filter, achieves a maximum voltage

conversion gain of 26.5 dB.

High linearity mode: 440 mA

Low power mode: 260 mA

APPLICATIONS

Cellular base stations and wireless infrastructure receivers

(W-CDMA, TD-SCDMA, WiMAX, GSM, LTE, PCS, DCS, DECT)

Active antenna systems

PTP radio link down converters

Wireless LANs and CATV equipment

Fabricated with the Analog Devices, Inc., high speed SiGe

process, the ADRF6658 is available in a compact, 7 mm ×

7 mm, 48-lead LFCSP package, and operates over the −40°C to

+105°C temperature range.

FUNCTIONAL BLOCK DIAGRAM

MIX OUT+ MIX OUT–

A0 TO A5

LOV

DD

MIX

V

CH EN

DGA IN– DGA IN+ LATCH

DGA

V

DV

DD

A

DD

A

DD

MIX RF

A

IN

IF OUT+

LATCH A

A

+22dB

100Ω

IF OUT–

A

MIXA

0dB TO 31.5dB

SDO

DATA

CLK

LE

LO

+

CONTROL

REGISTERS

IN

ADRF6658

–

IN

0dB TO 31.5dB

LATCH B

MIX RF

B

IN

MIXB

IF OUT+

B

+22dB

100Ω

IF OUT–

B

MIX

V

MIX OUT+ MIX OUT– CH EN DGA IN– DGA IN+

LATCH

B0 TO B5

DGA V

B DD

AGND

B

DD

B

Figure 1.

Rev. A

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADRF6658

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Register 5 ..................................................................................... 19

Register 6 ..................................................................................... 20

Register 7 ..................................................................................... 21

Register 8 Through Register 12................................................ 22

Register 13................................................................................... 23

Register 14................................................................................... 24

Register 15................................................................................... 25

Applications Information.............................................................. 26

Basic Connections...................................................................... 26

Input Tuning ............................................................................... 26

Register Initialization Sequence ............................................... 26

Standard Register Settings......................................................... 27

Readback ..................................................................................... 27

Daisy-Chain Mode..................................................................... 28

IF Filter ........................................................................................ 30

Outline Dimensions....................................................................... 31

Ordering Guide .......................................................................... 31

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Supplemental Information for Mixers and IF DGAs .............. 5

Timing Specifications .................................................................. 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ........................................... 10

Theory of Operation ...................................................................... 13

Dual Mixer Cores ....................................................................... 13

DGA Basic Structure.................................................................. 13

Serial Input Shift Registers........................................................ 14

Program Modes .......................................................................... 14

Register Maps.................................................................................. 15

Register 0 Through Register 4 .................................................. 18

REVISION HISTORY

11/15—Rev. 0 to Rev. A

Changes to Features Section............................................................ 1

Changes to Total Current, Low Power Mode Parameter,

Table 1 ................................................................................................ 4

Change to Figure 4 ........................................................................... 8

Changes to Mixer A Enabled Section and Mixer B Enabled

Section.............................................................................................. 23

Changes to Figure 51 Caption ...................................................... 31

1/15—Revision 0: Initial Version

Rev. A | Page 2 of 31

Data Sheet

ADRF6658

SPECIFICATIONS

MIX_AV_DD= MIX_BV_DD= DV_DD= LOV_DD= DGA_AV_DD= DGA_BV_DD= 3.3 V 5%; AGND = 0 V. T_A= T_MINto T_MAX. The operating

temperature range = −40°C to +105°C. Parameters are measured on a standard test circuit with an IF filter; f_RF= 1.95 GHz, RF input

power (P_RF) = −10 dBm, f_LO= 2.231 GHz, LO input power (P_LO) = 0 dBm, and f_IF= 281 MHz, using standard register settings. For IP2 and

IP3 measurements, f_RF1= 1.949 GHz and f_RF2= 1.951 GHz, maximum DGA gain, high linearity mode, unless otherwise noted. R_SOURCE

50 Ω, R_LOAD= 100 Ω, differential.

=

Table 1.

Parameter

Min

Typ

0

Max

Unit

Test Conditions/Comments

OPERATING CONDITIONS

RF Input Frequency

LO Power Level

690

−6

690

3800

+6

4100

MHz

dBm

MHz

LO Frequency

CHANNEL CHARACTERISTICS

RF Input Return Loss

−12

dB

Register 13, Bits[DB12:DB7] programmed

according to RF frequency

IF Output Return Loss

IF Lower Cutoff Frequency¹

−10

10

dB

MHz

Within IF filter passband

f_−3dB, MIX_xOUT_yconnected to DGA_xIN_ythrough a

dc block capacitor

IF Upper Cutoff Frequency

520

MHz

f_−3dB, MIX_xOUT_yconnected to DGA_xIN_ythrough a

dc block capacitor

Voltage Conversion Gain

Input P1dB

26.5

−5

dB

Maximum DGA gain

Minimum DGA gain

High Linearity Mode

Low Power Mode

Second Order Input Intercept (IIP2)

12

4

49

dBm

Register 13, Bits[DB24:DB22] = 4

Register 13, Bits[DB24:DB22] = 1

P_RF= 0 dBm per tone, minimum DGA gain, high

linearity mode

Third Order Input Intercept (IIP3)

High Linearity Mode

Low Power Mode

SSB NF

P_RF= 0 dBm per tone, minimum DGA gain

29

17

dBm

High linearity mode

RF = 855 MHz

RF = 1950 MHz

12.8

13

dB

RF = 3795 MHz

14.4

25

dB

With a 5 dBm Blocker

LO to RF Leakage

LO to IF Leakage

RF to IF Leakage

2 LO − 2 RF

3 LO − 3 RF

IF Output and LO Leakage

Intermodulation Spur

−30

−40

−50

−55

−100

dBm

dBc

Relative to IF output level

−70

f_LO= 3.249 GHz, f_RF= 3.5 GHz, IF DGA output power

(P_IFOUT) = 9 dBm, f_SPUR= 237 MHz and 265 MHz

Channel Isolation

52

dB

f_RF= 1.95 GHz, f_LO= 2.231 GHz, maximum DGA gain

Register 13, Bits[DB24:DB22] changing from 4 to 1

Mixer V to I Bias Adjustment Effects

Amplitude Variation

Gain Step

Gain Conformance Error

Phase Conformance Error

Output P1dB

0.19

0.5

0.05

0.5

19

40

100

−65

dB

Any two adjacent steps

Degrees Any two adjacent steps

dBm

Ω

dBc

Maximum DGA gain

Output IP3

Differential Output Impedance

Second Harmonic Level

Third Harmonic Level

At 2 V p-p

Rev. A | Page 3 of 31

ADRF6658

Data Sheet

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LOGIC INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_INH/I_INL

Input Capacitance, C_IN

LOGIC OUTPUTS

1.17

−0.5

3.6

+0.63

1

V

µA

pF

2

SDO (Pin 32)

Output High Voltage, V_OH

Output High Current, I_OH

Output Low Voltage, V_OL

POWER SUPPLIES

DV_DD

V_LOGIC− 0.4

V

µA

V

V_LOGICselected with Register 5, Bit DB24

500

0.4

I_OL= 500 µA

3.15

3.3

3.45

V

MIX_AV_DD, MIX_BV_DD, DGA_AV_DD,

DGA_BV_DD, and LOV_DD

DV_DD

The voltages on these pins must equal DV_DD

External IF_XOUT Pull-Up Supply

DV_DD

V

Mixer Current in High Linearity

Mode

80

mA

Mixer V to I bias (Register 13, Bits[DB24:DB22]) = 4

Mixer Current in Low Power Mode

IF DGA Current

40

140

mA

Mixer V to I bias (Register 13, Bits[DB24:DB22]) = 1

Per amplifier

Total Current

Dual Rx enabled

High Linearity Mode

Low Power Mode

Low Power Sleep Mode

Standby Mode

440

260

450

65

550

mA

µA

Mixer V to I bias (Register 13, Bits[DB24:DB22]) = 4

Mixer V to I bias (Register 13, Bits[DB24:DB22]) = 1

1000

mA

Both mixers and DGAs in standby mode

From standby mode to normal operation

TIMING²

Channel Power-Up from Standby

Mode After Changing State of

CH_AEN or CH_BEN

100

400

ns

¹DC-coupled; lower cutoff frequency determined mostly by external components.

²Not tested in production; guaranteed by characterization.

Rev. A | Page 4 of 31

Data Sheet

ADRF6658

SUPPLEMENTAL INFORMATION FOR MIXERS AND IF DGAS

MIX_AV_DD= MIX_BV_DD= DV_DD= LOV_DD= DGA_AV_DD= DGA_BV_DD= 3.3 V 5%; AGND = 0 V. T_A= T_MINto T_MAX. The operating

temperature range = −40°C to +105°C. Parameters are measured on a standard test circuit with an IF filter; f_RF= 1.95 GHz, PRF =

−10 dBm, f_LO= 2.231 GHz, and f_IF= 281 MHz, using standard register settings, maximum DGA gain, high linearity mode, unless

otherwise noted. For IP2 and IP3 measurements, f_RF1= 1.949 GHz and f_RF2= 1.951 GHz, minimum DGA gain.

Table 2.

Parameter

Min Typ

Max Unit

Test Conditions/Comments

MIXER CHARACTERISTICS

Voltage Conversion Gain

Input P1dB

7

dB

High Linearity Mode

Low Power Mode

Second-Order Input Intercept (IIP2)

Third-Order Input Intercept (IIP3)

High Linearity Mode

Low Power Mode

12

4

55

dBm

0 dBm per tone, minimum DGA gain

29

17

dBm

SSB NF

RF = 1950 MHz

12

dB

LO to RF Leakage

LO to IF Leakage

RF to IF Leakage

IF DGAs

Voltage Gain

Gain Step

Gain Conformance Error

Phase Conformance Error

Output P1dB

Output IP3 (OIP3)

Bandwidth

−30

−40

−50

dBm

dBc

Relative to IF output level

Any two adjacent steps

22

dB

0.5

0.05

0.5

19

40

520

7

Degrees Any two adjacent steps

dBm

MHz

dB

SSB NF

Second Harmonic Level

Third Harmonic Level

−65

dBc

At 2 V p-p

Rev. A | Page 5 of 31

ADRF6658

Data Sheet

TIMING SPECIFICATIONS

MIX_AV_DD= MIX_BV_DD= DV_DD= LOV_DD= DGA_AV_DD= DGA_BV_DD= 3.3 V 5% ; AG N D = 0 V. 1.8 V and 3.3 V logic levels used. T_A= T_MIN

to T_MAX, unless otherwise noted.

Table 3.

Parameter

Symbol

Min

20

Typ

Max

Unit

ns

Test Conditions/Comments

LE Setup Time

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

DATA to CLK Setup Time

DATA to CLK Hold Time

CLK High Duration

CLK Low Duration

CLK to LE Setup Time

LE Pulse Width

10

25

10

20

CLK Low to SDO Output Valid

20

During readback

Timing Diagram

t₄

t₅

CLK

t₂

t₃

DB3

(CONTROL BIT C4)

DB2

(CONTROL BIT C3)

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

DB31 (MSB)

DB30

DATA

LE

t₇

t₁

t₆

LE

Figure 2. SPI Write Operation Timing Diagram

CLK

REGISTER 5: NEW DATA

(NEW REGISTER ADDRESS IN READBACK ADDRESS FIELD)

DATA

LE

NEXT OPERATION

REGISTER 5: OLD DATA

(OLD REGISTER ADDRESS IN READBACK ADDRESS FIELD)

REGISTER 5: NEW DATA

(NEW REGISTER ADDRESS IN READBACK ADDRESS FIELD)

READBACK

ADDRESS

t₈

READ DATA

FROM OLD

REGISTER (MSB)

READ DATA

FROM OLD

REGISTER

READ DATA

FROM OLD

REGISTER (LSB)

READ DATA

FROM NEW

REGISTER (MSB)

READ DATA

FROM NEW

REGISTER (LSB)

READ DATA

FROM NEW

REGISTER

SDO

Figure 3. SPI Readback Operation Timing Diagram

Rev. A | Page 6 of 31

Data Sheet

ADRF6658

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Table 4.

Parameter

Rating

Supply Voltage Pins¹to GND²

Supply Voltage Pins¹to DV_DD

Digital Input Output (I/O) Voltage to GND −0.3 V to DV_DD+ 0.3 V

Analog I/O Voltage to GND

RF Input Power

LO Input Power

−0.3 V to +3.9 V

−0.3 V to +0.3 V

−0.3 V to DV_DD+ 0.3 V

20 dBm

10 dBm

The ADRF6658 is a high performance RF integrated circuit,

and it is ESD sensitive. Take proper precautions for handling

and assembly.

ESD Ratings

Human Body Model (HBM)

Field Induced Charged Device Model 500 V

(FICDM)

1.5 kV

ESD CAUTION

Operating Temperature Range

Storage Temperature Range

Maximum Junction Temperature

−40°C to +105°C

−65°C to +125°C

150°C

Thermal Resistance (θ_JA), with Exposed

Pad Soldered

27.26°C/W

Reflow Soldering

Peak Temperature

Time at Peak Temperature

260°C

40 sec

¹The supply voltage pins include MIX_AV_DD, DV_DD, MIX_BV_DD, DGA_BV_DD, LOV_DD, and

DGA_AV_DD

.

²GND = AGND = DGND = 0 V

³The digital I/O pins include LATCH_A, CH_AEN, CH_BEN, LATCH_B, B5 to B0, LE, CLK,

DATA, SDO, and A0 to A5.

Rev. A | Page 7 of 31

ADRF6658

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

MIX

V

1

2

3

4

5

6

7

8

9

36 IF OUT+

A

DD

35

34 AGND

33 LOV

IF OUT–

MIX RF

A

IN

AGND

LATCH

CH EN

C

DV

CH EN

LATCH

AGND

A

DD

32 SDO

31 LO

A

REG

ADRF6658

TOP VIEW

(Not to Scale)

IN+

30

LO

DD

IN–

29 DATA

28 CLK

27 LE

B

10

11

12

MIX RF

26 IF OUT–

B

IN

DD

MIX

V

25 IF OUT+

B

NOTES

1. CONNECT THE EXPOSED PAD TO GROUND THROUGH A

LOW IMPEDANCE PATH, USING AN ARRAY OF VIAS FROM

THE PAD TO THE PCB GROUND PLANE.

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

MIX_AV_DD

Supply for Mixer A. The voltage level on this pin must be equal to that on DV_DD. Place decoupling capacitors

to the ground plane as close as possible to this pin.

2

3

4

MIX_ARF_IN

AGND

LATCH_A

RF Input for Mixer A. This pin has an input impedance of 50 Ω.

Analog Ground. This is a ground return path for MIX_AV_DD(Pin 1).

Channel A Latch Buffer Control. This pin controls the latch buffer between the 6-bit parallel control port

(Pin A0 to Pin A5) and the Channel A DGA.

5

6

CH_AEN

C_REG

Channel A Enable. This pin provides external control of the power-down mode for Channel A.

Internal Regulator Output. A capacitor of approximately 220 nF must be placed between this output and

ground.

7

DV_DD

Supply Connection for Digital Circuits. The voltage on this pin ranges from 3.15 V to 3.45 V. Place decoupling

capacitors to the ground plane as close as possible to this pin.

8

9

CH_BEN

LATCH_B

Channel B Enable. This pin provides external control of the power-down mode for Channel B.

Channel B Latch Buffer Control. This pin controls the latch buffer between the 6-bit parallel control port

(Pin B0 to Pin B5) and the Channel B DGA.

10

11

12

AGND

MIX_BRF_IN

MIX_BV_DD

Analog Ground. This is a ground return path for MIX_BV_DD(Pin 12).

RF Input for Mixer B. This pin has an input impedance 50 Ω.

Supply for Mixer B. The voltage level on this pin must be equal to that on D_VDD. Place decoupling capacitors

to the ground plane as close as possible to this pin.

13, 14

MIX_BOUT+,

MIX_BOUT−

Differential Mixer B Outputs, 300 Ω Impedance. A pull-up inductor must be connected to each of these

output pins. The values of the inductors depend on the IF frequency range.

15

16, 17

AGND

DGA_BIN−,

DGA_BIN+

Analog Ground. This is a ground return path for DGA_BV_DD(Pin 18).

Differential DGA B Inputs, 300 Ω Impedance.

18

DGA_BV_DD

Supply for DGA B. The voltage level on this pin must be equal to that on DV_DD. Place decoupling capacitors

to the analog ground plane as close as possible to this pin.

19, 20, 21,

22, 23, 24

B5, B4, B3, B2,

B1, B0

6-Bit Parallel Control Ports for DGA B.

25, 26

IF_BOUT+,

IF_BOUT−

Channel B Differential IF Outputs, 100 Ω Resistance from DGA B. Requires a pull-up inductor dependent on

IF frequency.

27

LE

Latch Enable. When the LE input pin goes low, data is clocked into the 32-bit shift register on the CLK rising

edge. Only the last 32 bits are retained. When the LE input pin goes high, the data stored in the shift register

is loaded into one of the 16 registers, the relevant latch being selected by the four LSBs of the 32-bit word.

Rev. A | Page 8 of 31

Data Sheet

ADRF6658

Pin No.

Mnemonic

Description

28

CLK

Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high

impedance CMOS input.

29

30

DATA

LO_IN−

Serial Data Input. The serial data input is loaded MSB first with the four LSBs control the destination for the

data. This input is a high impedance CMOS input.

Complimentary External Local Oscillator Input. In differential LO mode, this pin is one of the input pins of

the differential input and must be ac-coupled. In single-ended LO mode, terminate this pin to ground with a

capacitor.

31

LO_IN+

External Local Oscillator Input. In differential LO mode, this pin one of the input pins of the differential input.

In single-ended LO mode, it is the input of the LO signal. AC couple this pin.

32

33

SDO

LOV_DD

Serial Data Output. This output is used to read back the register content.

Power Supply for the LO Path. The voltage level on this pin must be equal to that on DVDD. Place

decoupling capacitors to the ground plane as close as possible to this pin.

34

AGND

Analog Ground. This is a ground return path for LOV_DD(Pin 33).

35, 36

IF_AOUT−,

IF_AOUT+

Channel A Differential IF Outputs, 100 Ω Resistance from DGA A. Requires a pull-up inductor dependent on

IF frequency.

37, 38, 39,

40, 41, 42

A0, A1, A2, A3, 6-Bit Parallel Control Ports for DGA A.

A4, A5

43

DGA_AV_DD

Supply for DGA A. The voltage level on this pin must be equal to that on DV_DD. Place decoupling capacitors

to the analog ground plane as close as possible to this pin.

44, 45

DGA_AIN+,

DGA_AIN−

Differential DGA A Inputs, 300 Ω Impedance.

46

AGND

Analog Ground. This is a ground return path for DGA_AV_DD(Pin 43).

47, 48

MIX_AOUT−,

MIX_AOUT+

Differential Mixer A Outputs, 300 Ω Impedance. A pull-up inductor must be connected to each of these

output pins. The values of the inductors depend on the IF frequency range.

49

EP

Exposed Pad. Connect the exposed pad to ground through a low impedance path, using an array of vias

from the pad to the PCB ground plane.

Rev. A | Page 9 of 31

ADRF6658

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

30

50

45

40

35

30

25

20

15

10

DGA GAIN CODE: 63, +105°C

DGA GAIN CODE: 63, +25°C

DGA GAIN CODE: 63, –40°C

25

20

15

DGA GAIN CODE: 32, +105°C

DGA GAIN CODE: 32, +25°C

DGA GAIN CODE: 32, –40°C

10

5

BALUN CODE 0

BALUN CODE 1

BALUN CODE 2

BALUN CODE 3

BALUN CODE 4

BALUN CODE 5

BALUN CODE 6

BALUN CODE 7

DGA GAIN CODE: 0, +105°C

DGA GAIN CODE: 0, +25°C

DGA GAIN CODE: 0, –40°C

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

RF FREQUENCY (GHz)

Figure 5. Power Gain vs. RF Frequency and Balun Codes

Figure 8. Noise Figure vs. RF Frequency and DGA Gain Codes

0

–1

–2

–3

–4

–5

–6

–7

–8

–9

–10

–5

–10

–15

–20

–25

–30

–35

–40

–45

–50

BALUN CODE 0

BALUN CODE 1

BALUN CODE 10

BALUN CODE 11

BALUN CODE 100

BALUN CODE 101

BALUN CODE 110

BALUN CODE 111

+105°C 3.6V

+105°C 3.3V

+105°C 3.0V

+25°C 3.6V

+25°C 3.3V

+25°C 3.0V

–40°C 3.6V

–40°C 3.3V

–40°C 3.0V

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

FREQUENCY (GHz)

RF FREQUENCY (GHz)

Figure 6. RF Input Return Loss vs. Frequency and Balun Codes

Figure 9. Input P1dB (IP1dB) vs. RF Frequency, DV_DDat Maximum Gain

18

30

+105°C 3.6V

+105°C 3.3V

+105°C 3.0V

+25°C 3.6V

+25°C 3.3V

+25°C 3.0V

–40°C 3.6V

–40°C 3.3V

–40°C 3.0V

25

20

15

10

5

16

14

12

10

8

DGA GAIN CODE: 0, +105°C

DGA GAIN CODE: 0, +25°C

DGA GAIN CODE: 0, –40°C

DGA GAIN CODE: 32, +105°C

DGA GAIN CODE: 32, +25°C

DGA GAIN CODE: 32, –40°C

0

–5

–10

–15

–20

DGA GAIN CODE: 63, +105°C

DGA GAIN CODE: 63, +25°C

DGA GAIN CODE: 63, –40°C

6

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

1.0

1.5

2.0

2.5

3.0

3.5

4.0

RF FREQUENCY (GHz)

Figure 10. IP1dB vs. RF Frequency and DV_DDat Minimum Gain

Figure 7. Power Conversion Gain vs. RF Frequency for

DGA Gain Code = 0, 32, and 63

Rev. A | Page 10 of 31

Data Sheet

ADRF6658

40

35

30

25

20

15

10

100

90

80

70

60

50

40

30

20

10

0

CHANNEL A

CHANNEL B

IIP3 DGA GAIN CODE: 0 IN TONE POW = –25dBm

IIP3 DGA GAIN CODE: 24 IN TONE POW = –15dBm

IIP3 DGA GAIN CODE: 32 IN TONE POW = –10dBm

IIP3 DGA GAIN CODE: 41 IN TONE POW = –5dBm

IIP3 DGA GAIN CODE: 63 IN TONE POW = 0dBm

5

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

400

500

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

RF FREQUENCY (GHz)

Figure 11. IIP3 vs. RF Frequency

Figure 14. Channel Isolation

30

20

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

3.3V –40°C

3.3V 0°C

3.3V +25°C

3.3V +85°C

3.3V +105°C

3.6V –40°C

3.6V 0°C

3.6V +25°C

3.6V +85°C

3.6V +105°C

3.0V –40°C

3.0V 0°C

3.0V +25°C

3.0V +85°C

3.0V +105°C

10

0

–10

–20

–30

–40

–50

–60

–70

DGA0

DGA24

DGA32

DGA41

DGA63

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

150

200

250

300

350

IF FREQUENCY (GHz)

RF FREQUENCY (GHz)

Figure 12. Power Conversion Gain vs. IF Frequency

Figure 15. RF Feedthrough at Maximum Gain, Relative to IF Output Level

0

50

40

3.0V –40°C

3.0V 0°C

3.0V +25°C

3.0V +85°C

3.0V +105°C

3.3V –40°C

3.3V 0°C

3.3V +25°C

3.3V +85°C

3.3V +105°C

3.6V –40°C

3.6V 0°C

3.6V +25°C

3.6V +85°C

3.6V +105°C

–10

–20

–30

–40

–50

–60

–70

–80

–90

30

20

10

0

–10

–20

–30

–40

–50

DGA0 IN TONEPOW = –25dBm +25°C 3.3V

DGA24 IN TONEPOW = –15dBm +25°C 3.3V

DGA32 IN TONEPOW = –10dBm +25°C 3.3V

DGA41 IN TONEPOW = –5dBm +25°C 3.3V

DGA63 IN TONEPOW = –0dBm +25°C 3.3V

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

50

100

150

200

250

300

350

400

450

LO FREQUENCY (GHz)

IF FREQUENCY (MHz)

Figure 16. LO Feedthrough at Maximum Gain, Relative to IF Output Level

Figure 13. OIP3 vs. IF Frequency

Rev. A | Page 11 of 31

ADRF6658

Data Sheet

0

–5

LATCHx

–10

–15

–20

–25

–30

–35

–40

–45

–50

IFxOUT

5ns/DIV

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (MHz)

Figure 17. IF DGA Output Return Loss Measured Through Balun

Figure 20. Gain Step Response, Maximum Gain to Minimum Gain

16

14

12

10

8

REGISTER 14, A5 TO A0 OR B5 TO B0

IFxOUT

6

4

2

0

BIAS = 0

BIAS = 1

BIAS = 2

BIAS = 3

BIAS = 4

BIAS = 5

5ns/DIV

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

RF FREQUENCY (GHz)

Figure 21. Gain Step Response, Minimum Gain to Maximum Gain

Figure 18. IP1dB vs. RF Frequency and V to I Bias

0.20

0

CHxEN

IFxOUT

–0.20

–0.40

–0.60

–0.80

–1.00

–1.20

–1.40

DEVIATION FROM IDEAL LEVEL

STEP ACCURACY

10ns/DIV

0

4

8

12 16 20 24 28 32 36 40 44 48 52 56 60 64

DGA GAIN CODE

Figure 22. Channel Enable Response

Figure 19. DGA Step Accuracy

Rev. A | Page 12 of 31

Data Sheet

ADRF6658

THEORY OF OPERATION

DUAL MIXER CORES

DGA BASIC STRUCTURE

The ADRF6658 provides two double balanced active mixers

based on the Gilbert cell design. The RF inputs, LO inputs, and

IF outputs of the mixers are all differential, providing maximum

usable bandwidth at the input and output ports. The mixers are

designed for a 50 Ω input impedance and a 300 Ω output

impedance, with external RF chokes connected to the supply.

In each channel, the ADRF6658 has a built-in, variable gain

DGA. Each amplifier consists of a digitally controlled, passive

attenuator of a 300 Ω differential input impedance followed by a

highly linear transconductance amplifier with feedback. The

output impedance of the gain amplifier is 100 Ω, differentially.

The input impedance of the DGA block matches the output

impedance of the internal mixer.

Mixer RF Inputs

The gain of each amplifier can be programmed independently,

either via the DGA control bits in the serial control registers, or

via an external, 6-bit parallel port. The choice of serial or

parallel control is determined by the DGA control select bit, Bit

DB22 in Register 7. Programming this bit to 0 allows the gain to

be set by programming Register 14 (Bits[DB17:DB12] for

Channel A, or Bits[DB11:DB6] for Channel B). When the DGA

Control Select bit is set to 1, the gain is set by the binary value

applied to the 6-bit, external parallel control interface (Pin A5

through Pin A0 for Channel A, or Pin B5 through Pin B0 for

Channel B).

At the RF input of each channel (MIX_ARF_INand MIX_BRF_IN) of

the ADRF6658, a tunable balun converts the single-ended input

signal into differential form, to be fed into the mixer section.

The tuning of the balun is controlled by the two sets of register

bits: RF balun input cutoff (C_IN) in Register 13, Bits[DB12:DB10],

and RF balun output cutoff (C_OUT) in Register 13, Bits[DB9:DB7].

Mixers Bias Circuit

A band gap reference circuit generates the reference currents

used by mixers. The bias current for the LO circuit of the

mixers can be programmed via the mixer LO I_BIASbits in

Register 13, Bits[DB26:DB25].

EXTERNAL

CONTROL

PARALLEL

PORT

INTERNAL

CONTROL

REGISTER 14

LATCH

CONTROL

RF Voltage to Current (V to I) Converter

DGA

The differential RF input signal, created in the internal balun

from the external, single-ended RF signal provided to the

MIX_ARF_INor MIX_BRF_INpin, is applied to a V to I converter that

converts the differential input voltage to output currents. The

V to I converter provides a 50 Ω input impedance. The V to I

section bias current can be adjusted up or down using the mixer

V to I I_BIASbits in Register 13, Bits[DB24:DB22]. Adjusting the

current up improves IIP3 and P1dB input, but degrades the SSB

NF. Adjusting the current down improves the SSB NF but

degrades IIP3 and the input P1dB. The conversion gain remains

nearly constant over a wide range of mixer V to I I_BIASsettings,

allowing the device to be adjusted dynamically without

affecting the conversion gain. A setting of 3 or 4 provides a

good trade-off of IP3 and SSB NF.

CONTROL

SELECT

MUX

REGISTER 7

LATCH

ATTENUATOR

0dB TO 31.5dB

VOUT+

VOUT–

VIN+

VIN–

300Ω

100Ω

+22dB

Figure 23. Simplified Schematic

Input System

The dc voltage level at the inputs of each amplifier is set to

approximately 1.1 V by two independent internal voltage

reference circuits. These reference circuits are not accessible and

cannot be adjusted.

Mixer Power-Down

It is possible to power down either mixer by programming the

relevant bits. For Channel A, program the Mixer A enable bit

(Bit DB5 in Register 13). For Channel B, program the Mixer B

Enable bit (Bit DB4 in Register 13). The mixers can be powered

down independently.

Power down each amplifier by setting Bit DB5 and Bit DB4.in

Register 14. When powered down, the total current of each

amplifier reduces to 10 μA (typical). The dc level at the inputs

remains at approximately 1.6 V, regardless of the state of

Bit DB5 and Bit DB4 in Register 14.

Mixer Output

The mixer load uses a pair of 150 Ω resistors connected to the

positive supply. This provides a 300 Ω differential output resistance,

which matches the input impedance of the internal IF DGA

block. Pull the mixer outputs to the positive supply externally

using a pair of RF chokes, or by using an output transformer

with the center tap connected to the positive supply. The mixer

outputs are dc-coupled, and they can operate up to

approximately 500 MHz into a 300 Ω load.

Rev. A | Page 13 of 31

ADRF6658

Data Sheet

Output Amplifier

Gain Control

The gain of the output amplifier is set to 22 dB when driving

a 100 Ω load. The input resistance of this amplifier is set to

300 Ω in matched condition, and its output resistance is set to

100 Ω. If the load resistance is different from 100 Ω, use the

following equations to determine the resulting gain and

input/output resistances:

The gain of each amplifier can be adjusted using the parallel

control interface or the SPI. The gain step size is 0.5 dB. Each

amplifier has a maximum gain of +22 dB (Code 0) to −9.5 dB

(Code 63). LATCH_Aor LATCH_Bmust be at or transitioned to

logic high after programming through the parallel or serial

interface for the gain change to take effect.

A_V= 0.15 × (3800)/R_L

The NF of each amplifier is approximately 4 dB at the maxi-

mum gain setting, relative to a 300 Ω source. This represents

approximately 22.5 nV√Hz noise referred to the amplifier

output. The NF increases as the gain is reduced, and this increase

is equal to the reduction in gain. The linearity of the device

measured at the output is first-order independent of the gain

setting. From −4 dB to +22 dB gain, OIP3 is approximately

40 dBm into a 100 Ω load at 281 MHz (+1 dBm per tone). At

gain settings below −4 dB, OIP3 drops to approximately 28 dBm.

R

_IN= (3800 + R_L)/(1 + 0.15 × R_L)

S21 (Gain) = 2 × R_IN/(R_IN+ 300) × A_V

_OUT= (2000 + R_S)/(1 + 0.09 × R_S)

R

where:

Av is the voltage gain.

R_Lis the load resistance.

_INis the input resistance.

S21 is the insertion gain.

_OUTis the output resistance.

R

SERIAL INPUT SHIFT REGISTERS

R

Data is clocked into the 32-bit shift register on each rising edge

of CLK, MSB first. Data transfers from the shift register to one

of sixteen latches on the rising edge of LE. The destination latch

is determined by the state of the four control bits (C4, C3, C2,

and C1) in the shift register. As shown in Figure 2, these are the

four LSBs: DB3, DB2, DB1, and DB0. See Table 6 for the truth

table for these bits. Figure 27 through Figure 42 describe the

function of the control registers in the ADRF6658. The Register

Maps section summarizes how to program the latches.

Note that at the maximum attenuation setting, R_S, as seen by

the output amplifier, is the output resistance of the attenuator,

which is 300 Ω. However, at minimum attenuation, R_Sis the

source resistance connected to the DGA inputs of the device.

The dc current to the outputs of each amplifier is supplied

through two external chokes. The inductance of the chokes and

the resistance of the load, in parallel with the output resistance

of the device, adds a low frequency pole to the response. The

parasitic capacitance of the chokes adds to the output capacitance

of the device. This total capacitance, in parallel with the load

and output resistance, sets the high frequency pole of the

device. Generally, the larger the inductance of the choke, the

higher its parasitic capacitance. Therefore, this trade-off must

be considered when the value and type of the choke are

selected.

PROGRAM MODES

Table 6 and Figure 27 through Figure 42 show how to set up the

program modes in the ADRF6658.

Table 6. Truth Table for Control Bits C4, C3, C2, and C1

Control Bits

C4

0

1

C3

0

1

0

1

C2

0

1

0

1

0

1

0

1

C1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Register

Register 0 (R0)

Register 1 (R1)

Register 2 (R2)

Register 3 (R3)

Register 4 (R4)

Register 5 (R5)

Register 6 (R6)

Register 7 (R7)

Register 8 (R8)

Register 9 (R9)

Register 10 (R10)

Register 11 (R11)

Register 12 (R12)

Register 13 (R13)

Register 14 (R14)

Register 15 (R15)

For an operation frequency of 45 MHz to 500 MHz when

driving a 100 Ω load, 1.2 μH chokes with a self resonant

frequency (SRF) of 375 MHz or higher are recommended (such

as the 0805AF-122XJRB from Coilcraft). If higher value chokes

are used, gain peaking may occur at the low frequency end of

the pass band due to ac-coupling in the internal feedback path

of the amplifier. The supply current of each amplifier takes

about 80 mA through the two chokes combined in high linearity

mode (Register 13, Bits[DB24:DB22] = 4). The current increases

with temperature at approximately 2.5 mA per 10°C.

Rev. A | Page 14 of 31

Data Sheet

ADRF6658

REGISTER MAPS

REGISTER 0

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

C4(0) C3(0) C2(0) C1(0)

0

REGISTER 1

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

C4(0) C3(0) C2(0) C1(1)

0

REGISTER 2

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

C4(0) C3(0) C2(1) C1(0)

0

REGISTER 3

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

C4(0) C3(0) C2(1) C1(1)

0

REGISTER 4

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

C4(0) C3(1) C2(0) C1(0)

1

REGISTER 5

READBACK

ADDRES

CONTROL BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

RA2 RA1 SDL

0

RA4

RA3

C3(1) C2(0) C1(1)

C4(0)

Figure 24. Register Summary (Register 0 Through Register 5)

Rev. A | Page 15 of 31

ADRF6658

Data Sheet

REGISTER 6

CONTROL BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

1

0

DCE

0

1

0

LOS

0

1

0

PLB

0

PLI

0

C3(1) C2(1) C1(0)

C4(0)

REGISTER 7

RESERVED

CONTROL BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

DCS

0

1

0

C3(1) C2(1) C1(1)

C4(0)

REGISTER 8

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

C4(1) C3(0) C2(0) C1(0)

REGISTER 9

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C4(1) C3(0) C2(0) C1(1)

0

REGISTER 10

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C4(1) C3(0) C2(1) C1(0)

0

Figure 25. Register Summary (Register 6 Through Register 10)

Rev. A | Page 16 of 31

Data Sheet

ADRF6658

REGISTER 11

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

C4(1) C3(0) C2(1) C1(1)

0

REGISTER 12

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

C4(1) C3(1) C2(0) C1(0)

0

REGISTER 13

MIXER

LO

IBIAS

MIXER

V TO I

IBIAS

MIXER

V TO I

RDAC

MIXER

V TO I

CDAC

RF BALUN

INPUT

CUT OFF

RF BALUN

OUTPUT

CUT OFF

RESERVED

CONTROL BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

MB5 MB4 MB3 MB2 MB1 MR4 MR3 MR2 MR1 MC5 MC4 MC3 MC2 MC1 IC3

IC2

IC1 OC3 OC2 OC1

0

MAE MBE

C4(1)

0

C3(1) C2(0) C1(1)

REGISTER 14

DGA A

GAIN

DGA B

GAIN

RESERVED

CONTROL BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

1

0

1

0

AG6 AG5 AG4 AG3 AG2 AG1 BG6 BG5 BG4 BG3 BG2 BG1 DAE DBE

C4(1)

1

0

C3(1) C2(1) C1(0)

REGISTER 15

RESERVED

CONTROL BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DLP MSB

0

1

0

1

0

1

C3(1) C2(1) C1(1)

C4(1)

Figure 26. Register Summary (Register 11 Through Register 15)

Rev. A | Page 17 of 31

ADRF6658

Data Sheet

REGISTER 0 THROUGH REGISTER 4

Program Register 0 through Register 4 with the assigned values as shown in the register maps, Figure 27 through Figure 31.

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

C4(0) C3(0) C2(0) C1(0)

0

Figure 27. Register 0 (R0), Hexadecimal Code = 0x00000010

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

C4(0) C3(0) C2(0) C1(1)

0

Figure 28. Register 1 (R1), Hexadecimal Code = 0x00000001

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

C4(0) C3(0) C2(1) C1(0)

0

Figure 29. Register 2 (R2), Hexadecimal Code = 0x00000002

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

C4(0) C3(0) C2(1) C1(1)

0

Figure 30. Register 3 (R3), Hexadecimal Code = 0x00000003

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

C4(0) C3(1) C2(0) C1(0)

1

Figure 31. Register 4 (R4), Hexadecimal Code = 0x38000004

Rev. A | Page 18 of 31

Data Sheet

ADRF6658

SDO Output Level

REGISTER 5

Bit DB24 changes the logic level of the SDO output. When

programmed to 0, the SDO output is compatible with a 1.8 V

logic. When set to 1, the SDO output uses 3.3 V as the high

level.

Control Bits

Program Register 5 by setting Bits[C4:C1] to 0101. Figure 32

shows the input data format for programming this register.

Readback Address

The readback address bits, Bits[DB31:DB28], determine which

register content is read on the SDO output. Readback

functionality is explained in the Readback section.

READBACK

ADDRESS

CONTROL BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

RA2 RA1

0

SDL

0

RA4

RA3

C3(1) C2(0) C1(1)

C4(0)

SDO OUTPUT

LOGIC LEVEL

0

1

1.8V

3.3V

RA4 RA3 RA2 RA1

READBACK ADDRESS

REGISTER 0

REGISTER 1

REGISTER 2

REGISTER 3

REGISTER 4

REGISTER 5

REGISTER 6

REGISTER 7

REGISTER 8

REGISTER 9

REGISTER 10

REGISTER 11

REGISTER 12

REGISTER 13

REGISTER 14

REGISTER 15

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Figure 32. Register 5 (R5)

Rev. A | Page 19 of 31

ADRF6658

Data Sheet

Local Oscillator Input Buffer Standby Mode

REGISTER 6

Bit DB15 controls the standby mode of the buffer on the LO

input when both channels are disabled by pins CH_AEN and

CH_BEN. In this case, if the LOIN standby bit is programmed to

0, the buffer on the LO input is in low power mode. When this

bit is set to 1 while both channels are disabled, the buffer on the

LO input works in normal mode, ensuring a shorter time of

return to normal operation mode after any of the channels are

enabled.

Control Bits

Program Register 6 by setting Bits[C4:C1] to 0110. Figure 33

shows the input data format for programming this register.

Daisy-Chain Enable

To enable daisy-chain mode for programming multiple devices,

set Bit DB20 to 1. This feature is described in detail in the

Daisy-Chain Mode section. Programming this bit to 0 disables

this feature.

Bit DB8 controls the power up of the LO buffer. If DB8 is set to

0, the LO buffer is disabled.

Bit DB10 provides direct control of the LO buffer power modes.

Set this bit to 1 for normal mode, and 0 for standby mode.

In normal operation mode, the LO input buffer typically

consumes about 20 mA. In standby mode, this current is

reduced to 6 mA.

CONTROL BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

RESERVED

1

0

1

0

DCE

0

1

0

LOS

0

1

0

PLB

0

PLI

0

C3(1) C2(1) C1(0)

C4(0)

POWER-UP LO

BUFFER

DAISY-CHAIN

ENABLE

LOIN BUFFER

STANDBY

PU LO IN

DCE

LOS

0

1

DISABLED

0

1

DISABLED

ENABLED

0

1

LOW POWER MODE

ENABLED FOR NORMAL OPERATION

POWER UP LO

BUFFER BIAS (BAND-GAP)

PU LO BIAS

0

1

DISABLED

ENABLED FOR NORMAL OPERATION

Figure 33. Register 6 (R6)

Rev. A | Page 20 of 31

Data Sheet

ADRF6658

DGA Control Select

REGISTER 7

Bit DB22 selects the mode of control for the IF DGA. When this

bit is programmed to 0, the gain of each DGA block is set by

value of the relevant fields in Register 14: Bits[DB17:DB12] set

the DGA A gain for Channel A, and Bits[DB11:DB6] set the

DGA B gain for Channel B. When Bit DB22 in Register 7 is set

to 1, the gain is controlled by the external parallel ports: Pin A5

through Pin A0 for Channel A, and Pin B5 through Pin B0 for

Channel B.

Control Bits

Program Register 7 by setting Bits[C4:C1] to 0111. Figure 34

shows the input data format for programming this register.

RESERVED

CONTROL BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

DCS

0

1

0

C3(1) C2(1) C1(1)

C4(0)

DGA CONTROL

SELECT

DCS

0

1

GAIN SET BY SPI REGISTER

GAIN SET BY EXTERNAL PINS

Figure 34. Register 7 (R7)

Rev. A | Page 21 of 31

ADRF6658

Data Sheet

REGISTER 8 THROUGH REGISTER 12

Program Register 8 through Register 12 with the assigned values as shown in the register maps, Figure 35 through Figure 39.

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

C4(1) C3(0) C2(0) C1(0)

Figure 35. Register 8 (R8), Hexadecimal Code = 0x00000008

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

C4(1)

C1(1)

C3(0) C2(0)

0

Figure 36. Register 9 (R9), Hexadecimal Code = 0x00000009

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

C4(1)

C1(0)

C3(0) C2(1)

0

Figure 37. Register 10 (R10), Hexadecimal Code = 0x0000000A

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

C4(1) C3(0) C2(1) C1(1)

0

Figure 38. Register 11 (R11), Hexadecimal Code = 0x0000000B

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

C4(1) C3(1) C2(0) C1(0)

0

Figure 39. Register 12 (R12), Hexadecimal Code = 0x0000000C

Rev. A | Page 22 of 31

Data Sheet

ADRF6658

RF Balun Input Cutoff

REGISTER 13

Bits[DB12:DB10] select the input cutoff frequency of the balun

on the RF mixer input.

Control Bits

Program Register 13 by setting Bits[C4:C1] to 1101. This

register controls the built in phase-locked loop (PLL)

synthesizer. Figure 40 shows the input data format for

programming this register.

RF Balun Output Cutoff

Bits[DB9:DB7] select the output cutoff frequency of the balun

on the RF mixer input.

Mixer LO Bias Current

Mixer A Enabled

Bits[DB26:DB25] set the value of the bias current of the mixer

LO inputs.

Bit DB5 powers up or switches off the mixer in Channel A. This

option enables power saving if the mixer is not being used in

the circuit.

Mixer V to I Converter Bias Current

Bits[DB24:DB22] set the value of the V to I converter bias

current (I_BIAS) used on the mixer LO input.

Switching off Mixer A changes the supply current for this mixer

from 80 mA to 5 mA.

Mixer V to I CDAC

Mixer B Enabled

Bits[DB17:DB13] set the value of CDAC bits that determines

the capacitance component in the distortion correction circuit.

These bits optimize the linearity correction in the mixer V to I

converter as a function of RF frequency.

Bit DB4 powers up or switches off the mixer in Channel B. This

option enables power saving if the mixer is not being used in

the circuit.

Switching off Mixer B changes the supply current for this mixer

from 80 mA to 5 mA.

MIXER

V TO I

CDAC

RF BALUN

INPUT

CUT OFF

RF BALUN

OUTPUT

CUT OFF

MIXER

LO

IBIAS

MIXER

V TO I

IBIAS

RESERVED

CONTROL BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

MB5 MB4 MB3 MB2 MB1

0

MC5 MC4 MC3 MC2 MC1 IC3

IC2

IC1 OC3 OC2 OC1

0

MAE MBE

0

C3(1) C2(0) C1(1)

C4(1)

IC3

0

IC2

0

IC1

0

RF BALUN INPUT CUT-OFF

ABOVE 1.78GHz

MIXER LO

BIAS CURRENT

MIXER B

MB5 MB4

MBE

ENABLED

DISABLED

ENABLED

0

1

0

1

0

1

200µA

0

1

1.40GHz TO 1.78GHz

1.18GHz TO 1.40GHz

1.03GHz TO 1.18GHz

0.91GHz TO 1.03GHz

0.84GHz TO 0.91GHz

0.77GHz TO 0.84GHz

BELOW 0.77GHz

0

1

0

1

0

300µA

0

1

500µA

1

0

700µA

1

0

1

MIXER A

ENABLED

MAE

1

0

1

0

1

DISABLED

ENABLED

MIXER VOLTAGE-TO-CURRENT

CONVERTER BIAS CURRENT

MB3 MB2 MB1

0

1

0

1

0

1

0

1

0

1

0

1

0.5mA

MIXER VOLTAGE-TO-CURRENT

MC5 MC4 MC3 MC2 MC1 CDAC

1.0mA

OC3 OC2 OC1 RF BALUN OUTPUT CUT-OFF

1.5mA

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.7mA

ABOVE 1.78GHz

1

1.40GHz TO 1.78GHz

1.18GHz TO 1.40GHz

1.03GHz TO 1.18GHz

0.91GHz TO 1.03GHz

0.84GHz TO 0.91GHz

0.77GHz TO 0.84GHz

BELOW 0.77GHz

2.0mA

0

1

0

2

2.3mA

0

1

3

RESERVED

...

1

...

1

...

1

...

0

...

1

...

29

30

31

1

0

1

Figure 40. Register 13 (R13)

Rev. A | Page 23 of 31

ADRF6658

Data Sheet

DGA Channel A Gain Control

REGISTER 14

Bits[DB11:DB6] set the gain in the DGA block in Channel B if

the DCS bit (Register 7, Bit DB22) bit is 0. The gain is set by the

value of the programmed attenuator in the DGA block in

Channel B. The maximum value of the gain is +22 dB, and the

minimum value is −9.5 dB. Figure 41 shows the corresponding

values of the programmed gain and the binary word written to

Bits[DB11:DB6].

Control Bits

Program Register 14 by setting Bits[C4:C1] to 1110. This

register controls the built in PLL synthesizer. Figure 41 shows

the input data format for programming this register.

DGA Channel A Gain Control

Bits[DB17:DB12] set the gain in the DGA block in Channel A if

the DGA control select bit (DCS, Register 7, Bit DB22) bit is 0.

The gain is set by the value of the programmed attenuator in the

DGA block in Channel A. The maximum value of the gain is

+22 dB, and the minimum value is −9.5 dB. Figure 41 shows the

corresponding values of the programmed gain and the binary

word written to Bits[DB17:DB12]. LATCH_Amust be at logic

low for the gain to change, and the new gain value is latched

into the DGA when LATCH_Agoes high.

DGA Channel A Enable

Bit DB5 powers up or powers down the DGA block in

Channel A. To reduce the device power consumption, power

down the DGA block in Channel A if not in use.

DGA Channel B Enable

Bit DB4 powers up or powers down the DGA block in Channel B.

To reduce the device power consumption, power down the

DGA block in Channel B if not in use.

DGA A

GAIN

DGA B

GAIN

RESERVED

CONTROL BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

AG6 AG5 AG4 AG3 AG2 AG1 BG6 BG5 BG4 BG3 BG2 BG1 DAE DBE

1

0

1

0

1

0

1

0

C3(1) C2(1) C1(0)

C4(1)

DIGITALLY CONTROLLED GAIN

AMPLIFIER IN CHANNEL B—ENABLE

DIGITALLY CONTROLLED GAIN

AMPLIFIER IN CHANNEL A—GAIN VALUE

DBE

AG6 AG5 AG4 AG3 AG2 AG1

0

1

DISABLED

ENABLED

0

1

0

1

0

1

22.0dB

21.5dB

21.0dB

20.5dB

...

... ... ... ... ... ...

DIGITALLY CONTROLLED GAIN

AMPLIFIER IN CHANNEL A—ENABLE

DAE

1

0

1

–9.0dB

–9.5dB

0

1

DISABLED

ENABLED

GAIN DECREASED BY 0.5dB STEP

DIGITALLY CONTROLLED GAIN

AMPLIFIER IN CHANNEL B—GAIN VALUE

BG6 BG5 BG4 BG3 BG2 BG1

0

1

0

1

0

1

22.0dB

21.5dB

21.0dB

20.5dB

...

... ... ... ... ... ...

1

0

1

–9.0dB

–9.5dB

GAIN DECREASED BY 0.5 dB STEP

Figure 41. Register 14 (R14)

Rev. A | Page 24 of 31

Data Sheet

ADRF6658

Mixer Standby Mode

REGISTER 15

DB14 determines whether a mixer enters a low power mode or

completely shuts off when the channel is disabled using

Register 13, Bits DB4 and DB5. When DB14 is 0, the mixer is

powered down. When DB14 is 1, the mixer stays in a low power

mode. The band gap reference for the mixer bias circuit remains

on in either case.

Control Bits

Program Register 15 by setting Bits[C4:C1] to 1111. This

register controls the built in DGA block.

Figure 42 shows the input data format for programming this

register.

DGAs—Low Power Mode

When set to 1, Bit DB16 enables the DGA low power mode.

When programmed to 0, both DGA blocks work in normal

mode.

In normal mode, the typical current used by each DGA block is

approximately 140 mA. In low power mode, this current

reduces to 23 mA.

RESERVED

CONTROL BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DLP MSB

0

1

0

1

C3(1) C2(1) C1(1)

C4(1)

MSM MIXER STANDBY MODE

0

1

MIXER TURNED OFF WHEN CHANNE L ENABLE = 0

MIXER IN LOW POWER WHEN CHANNEL ENABLE = 0

DIGITALLY CONTROLLED GAIN

AMPLIFIERS—LOW POWER MODE

DLP

0

1

DISABLED

ENABLED

Figure 42. Register 15 (R15)

Rev. A | Page 25 of 31

ADRF6658

Data Sheet

APPLICATIONS INFORMATION

1µF

3.3V

IN

OUT

IF FILTER

1µF

C5

0.1µF

C6

0.1µF

LATCH_A

IN2 OUT2

A

C7

0.1µF

C8

0.1µF

C12

0.1µF

3.3V

CH_AEN

6

C13

0.1µF

A0 TO A5

LOV_DD

MIX_AV_DD

MIX_AOUT+ MIX_AOUT–

DGA_AIN–

DGA_AIN+

DGA_AV_DD

DV_DD

1µF 1µF

37 42

33

1

48

47

5

45

44

4

43

7

LATCH_A

C16

1µF

MUX

RF_IN

A

IF_AOUT+

IF_AOUT–

MIX_ARF_IN

36

35

2

+22dB

100Ω

LATCH A

C17

1µF

SPI

MIXA

INTERFACE

0dB TO 31.5dB

SDO

32

DATA

29

28

27

LO_IN

+

–

31

30

CONTROL

REGISTERS

CLK

LE

ADRF6658

0dB TO 31.5dB

LATCH B

RF_INB

C19

1µF

MIX_BRF_IN

11

MIXB

IF_BOUT+

IF_BOUT–

25

26

+22dB

100Ω

C18

1µF

C_REG

6

MUX

LATCH_B

1µF 1µF

12

13

14

8

16

17

9

18

3, 10, 15, 34, 46, EP

19 24

DGA_BV_DD

DGA_BIN+

B0 TO B5

MIX_BV_DD

MIX_BOUT+

MIX_BOUT–

DGA_BIN–

AGND

C14

0.1µF

6

3.3V

CH_BEN

C10

C9

0.1µF

1µF

B

LATCH_B

24 TO 19

3.3V

IN2 OUT2

IF FILTER

3.3V

IN

OUT

C15

0.1µF

Figure 43. Basic Connections

BASIC CONNECTIONS

REGISTER INITIALIZATION SEQUENCE

The basic connections for the ADRF6658 are shown in Figure 43.

At initial power-up, after applying correct voltages to the supply

pins, the ADRF6658 registers load in the following sequence:

INPUT TUNING

1. Register 15

2. Register 14

3. Register 13

4. Register 12

5. Register 11

6. Register 10

7. Register 9

8. Register 8

9. Register 7

10. Register 6

11. Register 5

12. Register 4

13. Register 3

14. Register 2

15. Register 1

16. Register 0

Conversion gain and input return loss can be optimized for an

input frequency range

IIP3 Optimization

Input IP3 can be optimized by writing to the Mixer CDAC bits

(Register 13, Bits[DB17:DB13]). Examples of optimum settings

are listed in Table 7.

Table 7. IIP3 Optimization Settings

RF

IIP3 for IF DGA at

CDAC, Bits[DB17:DB13] Minimum Gain

Frequency

(MHz)

(Decimal Value)

(dBm)

750

900

1950

2700

3800

26

25

12

10

3

36

32

29

25

26

Rev. A | Page 26 of 31

Data Sheet

ADRF6658

STANDARD REGISTER SETTINGS

Figure 44. Register Settings for Standard Test Configuration

CLK

REGISTER 5: NEW DATA

(NEW REGISTER ADDRESS IN READBACK ADDRESS FIELD)

DATA

LE

NEXT OPERATION

REGISTER 5: OLD DATA

(OLD REGISTER ADDRESS IN READBACK ADDRESS FIELD)

REGISTER 5: NEW DATA

(NEW REGISTER ADDRESS IN READBACK ADDRESS FIELD)

READBACK

ADDRESS

READ DATA

FROM OLD

REGISTER (MSB)

READ DATA

FROM OLD

REGISTER

READ DATA

FROM OLD

REGISTER (LSB)

READ DATA

FROM NEW

REGISTER (MSB)

READ DATA

FROM NEW

REGISTER

READ DATA

FROM NEW

REGISTER (LSB)

SERIAL DATA

OUTPUT

Figure 45. Timing Diagram for Readback Operation

The data from new Register N, where N = 0 to 15, is available

on the SDO output during the next write operation to the

device after setting the correct register number by programming

the readback address (Bits[DB31:DB28] in Register 5), as shown

in Figure 45. To read the register values without changing the

device settings, write a special no operation (NOP) command to

the device. The format for this command is all zeros (0x00000000).

Writing all zeros to Register 0 does not change any settings in

this register due to the internal detection circuit, but allows the

clock signal to be provided to the device so that readback can be

performed.

READBACK

The address of the register that is read back is written to the

readback address in Register 5, Bits[DB31:DB28].

After initialization of the device, the readback address stores a

number from 0 to 15, depending on the value written to

Bits[DB31:DB28] in Register 5. If the readback is performed

after initialization but before a new value is written to the

readback address field, the data read on the serial data output

pin (the SDO pin) during the time of next write to the device

(for example, during a new value write to Register 5) is the data

stored in the register pointed to by the previous value of the

readback address field. This is shown in Figure 45.

Rev. A | Page 27 of 31

ADRF6658

Data Sheet

of the controller as well as simplifying the layout by removing

multiple selection lines. The daisy chain also removes the necessity

of connecting the data input of each slave device directly to the

controller data output. To use the daisy chain, all slave devices

must use the same SPI protocol.

DAISY-CHAIN MODE

In a system with one controller using the SPI for programming

multiple devices, a dedicated signal for selecting a chip is used

to address each device. In the ADRF6658, the function of chip

select input is performed by the LE pin. As the number of

devices increases, so does the number of lines used for device

selection. Additionally, as both clock and data lines are routed

from the controller outputs to the relevant inputs of each

device, the layout become more complex. Using more outputs

on the controlling device for the simple selection of different

devices may become unacceptable due to the limited number of

the controller outputs. In extreme situations, in a system with a

numerous devices, additional controllers may be necessary to

assure the correct addressing of each device.

Figure 46shows a traditional solution using multiple signals for

selecting each device; Figure 47 shows a system using a daisy chain.

Writing to N independent devices in a traditional system

demands programming each of the devices in sequence. As each

write operation ends at a different time, so do the changes to the

device settings. This may be a drawback for applications requiring

synchronized changes to multiple devices. When using daisy-chain

functionality, all slave devices must be programmed at the same

time. To write to selected devices only, write an NOP command

(0x00000000) to the devices requiring unchanged configuration.

This command does not change any internal register settings

of the device to which it is written.

To simplify the system, an alternative solution is the daisy-chain

function, enabled by programming Bit DB20 in Register 6 of the

ADRF6658. The daisy-chain function allows propagation of the

signal through a string of slave devices, saving multiple outputs

CONTROLLER

(MICROCONTROLLER,

DSP)

CLK

DATA OUT

DEV. 1

CLK

DATA

LE

DEV. 2

CLK

DATA

LE1

LE2

LE3

SDO

DEV. 3

LE

CLK

SDO

DATA

LE

SDO

DATA IN

Figure 46. System with Traditional Multiple Chip Select

CONTROLLER

(MICROCONTROLLER,

DSP)

CLK

DATA OUT

DEV. 1

CLK

DATA

LE

DEV. 2

CLK

DATA

LE

SDO

DEV. 3

CLK

DATA

LE

SDO

LE

SDO

DATA IN

Figure 47. System with Daisy-Chain Functionality

Rev. A | Page 28 of 31

Data Sheet

ADRF6658

Writing to a single, 32-bit register in each of the N devices with

daisy chain functionality enabled is possible by writing N × 32 bits

while the LE signal is kept low, then raising the LE signal. As

new register settings are written to the device on the rising edge of

the LE signal, the programmed register in multiple devices are

updated at the same time. Figure 48 shows the timing diagram

for writing to multiple devices.

devices. In daisy-chain mode, the data is written to or read from

all the devices in sequence, as shown in Figure 49.

The data from the new Register M, where M = 0 to 15, is available

on the SDO output during the next write operation to the device

after setting the correct register number by programming the read-

back address (Bits[DB31:DB28] in Register 5), as shown in

Figure 49. To avoid changing the register settings when read-

back is performed, an NOP command (0x00000000) can be

used as the next operation.

During readback on a single device, the data available on the

SDO output shows the content of the registers which addresses

are currently stored in the readback address fields of the relevant

CLK

DATA

LE

DEVICE N DATA

DEVICE 1 DATA

LE

Figure 48. Timing Diagram for Writing to Multiple Devices Using Daisy-Chain Functionality for N Devices

CLK

DEVICE N: REGISTER 5

(NEW READBACK ADDRESS)

DEVICE 1: REGISTER 5

(NEW READBACK ADDRESS)

DEVICE N: NEXT OPERATION

DATA

LE

DEVICE 1: NEXT OPERATION

READBACK

ADDRESS

IN DEVICE N

OLD REGISTER ADDRESS IN READBACK ADDRESS FIELD

DEVICE N

NEW REGISTER ADDRESS IN READBACK ADDRESS FIELD

DEVICE N

...

READBACK

ADDRESS

IN DEVICE 1

OLD REGISTER ADDRESS IN READBACK ADDRESS FIELD

DEVICE 1

NEW REGISTER ADDRESS IN READBACK ADDRESS FIELD

DEVICE 1

READ DATA

DEVICE N, OLD REGISTER

READ DATA

DEVICE 1, OLD REGISTER

READ DATA

DEVICE N, NEW REGISTER

READ DATA

DEVICE 1, NEW REGISTER

SDO

Figure 49. Timing Diagram for Readback from Multiple Devices Using Daisy-Chain Functionality for N Devices

Rev. A | Page 29 of 31

ADRF6658

Data Sheet

The filter design is optimized to produce the best flatness and

stop-band rejection at the presence of device parasitics, using

standard Electronic Industries Association (EIA) E24 values,

also known as standard 5% values.

IF FILTER

The IF filter used in the ADRF6658 evaluation is of a fifth order

Butterworth design, shown in Figure 50, with a center frequency of

281 MHz and a bandwidth of 200 MHz.

L16

24nH

L18

27nH

C16

13pF

C18

11pF

C14

C10

L10

C12

3.3pF

L12

L14

150nH

6.8pF

82nH

3.9pF

120nH

MIX OUT+

DGA IN+

A

C11

6.8pF

C13

3.3pF

C15

3.9pF

L11

82nH

L13

120nH

L15

150nH

MIX OUT–

DGA IN–

A

L17

24nH

L19

27nH

C17

13pF

C19

11pF

Figure 50. IF Filter

Rev. A | Page 30 of 31

Data Sheet

ADRF6658

OUTLINE DIMENSIONS

7.00

BSC SQ

0.30

0.23

0.18

PIN 1

INDICATOR

PIN 1

INDICATOR

48

37

36

1

0.50

BSC

EXPOSED

PAD

4.25

4.10 SQ

3.95

12

13

25

24

0.45

0.40

0.35

0.20 MIN

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-WKKD.

Figure 51. 48-Lead Lead Frame Chip Scale Package [LFCSP]

7 mm × 7 mm Body and 0.75 mm Package Height

(CP-48-5)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range Package Description

Package Option

CP-48-5

ADRF6658BCPZ

ADRF6658BCPZ-RL7 −40°C to +105°C

EV-ADRF6658SD1Z

−40°C to +105°C

48-Lead Lead Frame Chip Scale Package [LFCSP], Tray

48-Lead Lead Frame Chip Scale Package [LFCSP], 7” Tape and Reel

Evaluation Board

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D12223-0-11/15(A)

Rev. A | Page 31 of 31


型号：	ADRF6658
厂家：	ADI
描述：	Wideband, Dual Rx Mixers with Integrated IF Amplifiers
文件：	总31页 (文件大小：679K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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