ADRF5730BCCZN [ADI]
0.5 dB LSB, 6-Bit, Silicon Digital Attenuator, 100 MHz to 40 GHz;
| 型号： | ADRF5730BCCZN |
| 厂家： | 
ADI |
| 描述： | 0.5 dB LSB, 6-Bit, Silicon Digital Attenuator, 100 MHz to 40 GHz 衰减器 射频 微波 |
| 文件： | 总19页 (文件大小：635K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0.5 dB LSB, 6-Bit, Silicon Digital
Attenuator, 100 MHz to 40 GHz
Data Sheet
ADRF5730
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Ultrawideband frequency range: 100 MHz to 40 GHz
Attenuation range: 0.5 dB steps to 31.5 dB
Low insertion loss with impedance match
2.1 dB up to 18 GHz
24 23 22 21 20 19
2.9 dB up to 26 GHz
4.8 dB up to 40 GHz
1
18
LE
PS
VDD
2
3
4
5
6
17
16
15
14
13
VSS
SERIAL/
PARALLEL
INTERFACE
Attenuation accuracy with impedance match
(0.10 + 1.0% of attenuation state) up to 18 GHz
(0.15 + 0.8% of attenuation state) up to 26 GHz
(0.35 + 2.5% of attenuation state) up to 40 GHz
Typical step error with impedance match
0.18 dB up to 18 GHz
GND
GND
ATTIN
GND
GND
GND
6-BIT DIGITAL
ATTENUATOR
ATTOUT
GND
7
8
9
10 11 12
PACKAGE
BASE
0.23 dB up to 26 GHz
GND
0.51 dB up to 40 GHz
Figure 1.
High input linearity
P0.1dB insertion loss state: 30 dBm
P0.1dB other attenuation states: 27 dBm
IP3: 50 dBm typical
High RF input power handling: 27 dBm average, 30 dBm peak
Tight distribution in relative phase
No low frequency spurious signals
SPI and parallel mode control, CMOS/LVTTL compatible
RF settling time (0.1 dB of final RF output): 250 ns
24-terminal, 4 mm × 4 mm LGA package
Pin compatible with ADRF5720, low frequency cutoff version
APPLICATIONS
Industrial scanners
Test and instrumentation
Cellular infrastructure: 5G millimeter wave
Military radios, radars, electronic counter measures (ECMs)
Microwave radios and very small aperture terminals (VSATs)
GENERAL DESCRIPTION
The ADRF5730 is a silicon, 6-bit digital attenuator with 31.5 dB
attenuation control range in 0.5 dB steps.
The ADRF5730 is pin-compatible with the ADRF5720 low
frequency cutoff version, which operates from 9 kHz to 40 GHz.
This device operates from 100 MHz to 40 GHz with better than
4.8 dB of insertion loss and excellent attenuation accuracy. The
ADRF5730 has a radio frequency (RF) input power handling
capability of 27 dBm average and 30 dBm peak for all states.
The ADRF5730 RF ports are designed to match a characteristic
impedance of 50 Ω. For wideband applications, impedance
matching on the RF transmission lines can further optimize high
frequency insertion loss, return loss, and attenuation accuracy
characteristics. Refer to the Electrical Specifications section, the
Typical Performance Characteristics section, and the Applications
Information section for more details.
The ADRF5730 requires a dual supply voltage of +3.3 V and
−3.3 V. The device features serial peripheral interface (SPI), parallel
mode control, and complementary metal-oxide semiconductor
(CMOS)-/low voltage transistor to transistor logic (LVTTL)-
compatible controls.
The ADRF5730 comes in a 24-terminal, 4 mm × 4 mm, RoHS-
compliant, land grid array (LGA) package and operates from
−40°C to +105°C.
Rev. 0
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rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2018 Analog Devices, Inc. All rights reserved.
www.analog.com
ADRF5730
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Insertion Loss, Return Loss, State Error, Step Error, and
Relative Phase ................................................................................8
Input Power Compression and Third-Order Intercept......... 12
Theory of Operation ...................................................................... 13
Power Supply............................................................................... 13
RF Input and Output ................................................................. 13
Serial or Parallel Mode Selection ............................................. 13
Serial Mode Interface................................................................. 14
Using SEROUT........................................................................... 14
Parallel Mode Interface.............................................................. 15
Applications Information.............................................................. 16
Evaluation Board........................................................................ 16
Probe Matrix Board ................................................................... 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
Applications....................................................................................... 1
Functional Block Diagram................................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Specifications............................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
Power Derating Curves................................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Interface Schematics..................................................................... 7
Typical Performance Characteristics ............................................. 8
REVISION HISTORY
7/2018—Revision 0: Initial Version
Rev. 0 | Page 2 of 19
Data Sheet
ADRF5730
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VDD = 3.3 V, VSS = −3.3 V, digital voltages = 0 V or VDD, case temperature (TCASE) = 25°C, and 50 Ω system, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
FREQUENCY RANGE
INSERTION LOSS (IL)
With Impedance Match
100
40,000 MHz
See Figure 44
100 MHz to 10 GHz
10 GHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
See Figure 43
1.6
2.1
2.9
3.8
4.8
dB
dB
dB
dB
dB
Without Impedance Match
100 MHz to 10 GHz
10 GHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
ATTIN and ATTOUT, all attenuation states
See Figure 44
1.6
2.1
2.7
3.7
5.2
dB
dB
dB
dB
dB
RETURN LOSS
With Impedance Match
100 MHz to 10 GHz
10 GHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
See Figure 43
20
19
13
11
11
dB
dB
dB
dB
dB
Without Impedance Match
100 MHz to 10 GHz
10 GHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
19
18
16
13
9
dB
dB
dB
dB
dB
ATTENUATION
Range
Between minimum and maximum
attenuation states
Between any successive attenuation states
Referenced to insertion loss
See Figure 44
31.5
0.5
dB
dB
Step Size
Accuracy
With Impedance Match
100 MHz to 10 GHz
10 GHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
(0.10 + 0.6% of state)
dB
dB
dB
dB
dB
(0.10 + 1.0% of state)
(0.15 + 0.8% of state)
(0.20 + 2.0% of state)
(0.35 + 2.5% of state)
Without Impedance Match
See Figure 43
100 MHz to 10 GHz
10 GHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
(0.10 + 0.5% of state)
(0.10 + 1.0% of state)
(0.15 + 0.8% of state)
(0.25 + 1.8% of state)
(0.40 + 5.0% of state)
dB
dB
dB
dB
dB
Rev. 0 | Page 3 of 19
ADRF5730
Data Sheet
Parameter
Test Conditions/Comments
Between any successive state
See Figure 44
Min
Typ
Max
Unit
Step Error
With Impedance Match
100 MHz to 10 GHz
10 GHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
See Figure 43
0.11
dB
dB
dB
dB
dB
0.18
0.23
0.3
0.51
Without Impedance Match
100 MHz to 10 GHz
10 GHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
Referenced to insertion loss
See Figure 44
10 GHz
18 GHz
26 GHz
35 GHz
40 GHz
See Figure 43
10 GHz
18 GHz
26 GHz
35 GHz
40 GHz
0.11
0.19
0.23
0.26
0.65
dB
dB
dB
dB
dB
RELATIVE PHASE
With Impedance Match
Without Impedance Match
SWITCHING CHARACTERISTICS
15
30
50
75
Degrees
Degrees
Degrees
Degrees
Degrees
100
15
30
50
75
110
Degrees
Degrees
Degrees
Degrees
Degrees
All attenuation states at input power = 10 dBm
10% to 90% of RF output
50% triggered control (CTL) to 90% of RF output
Rise and Fall Time (tRISE and tFALL
On and Off Time (tON and tOFF
)
35
125
ns
ns
)
RF Amplitude Settling Time
0.1 dB
0.05 dB
Overshoot
Undershoot
50% triggered CTL to 0.1 dB of final RF output
50% triggered CTL to 0.05 dB of final RF output
250
350
1
ns
ns
dB
dB
−2.5
RF Phase Settling Time
5°
1°
INPUT LINEARITY1
0.1 dB Power Compression (P0.1dB)
Insertion Loss State
Other Attenuation States
Third-Order Intercept (IP3)
f = 5 GHz
50% triggered CTL to 5° of final RF output
50% triggered CTL to 1° of final RF output
100 MHz to 30 GHz
160
180
ns
ns
30
27
50
dBm
dBm
dBm
Two-tone input power = 14 dBm per tone,
Δf = 1 MHz, all attenuation states
DIGITAL CONTROL INPUTS
LE, PS, D0, D1, D2, D3/SEROUT,2 D4/SERIN,
D5/CLK pins
Voltage
Low (VINL)
0
1.2
0.8
3.3
V
V
High (VINH
Current
Low (IINL
High (IINH
)
)
<1
33
<1
µA
µA
µA
)
D0, D1, D2
LE, PS, D3/SEROUT2, D4/SERIN, D5/CLK pins
Rev. 0 | Page 4 of 19
Data Sheet
ADRF5730
Parameter
Test Conditions/Comments
D3/SEROUT pin2
Min
Typ
Max
Unit
DIGITAL CONTROL OUTPUT
Voltage
Low (VOUTL
)
0
0.3
V
High (VOUTH
)
VDD 0.3
V
Current (IOUTL, IOUTH
SUPPLY CURRENT
)
0.5
mA
VDD and VSS pins
Positive Supply Current
Negative Supply Current
117
−117
µA
µA
RECOMMENDED OPERATING
CONDITIONS
Supply Voltage
Positive (VDD)
Negative (VSS)
3.15
−3.45
0
3.45
−3.15
VDD
V
V
V
Digital Control Voltage
RF Input Power 3
ATTIN
f = 100 MHz to 30 GHz, TCASE = 85°C,4 all
attenuation states
Steady state average
Steady state peak
Hot switching average
Hot switching peak
Steady state average
Steady state peak
Hot switching average
Hot switching peak
27
30
24
27
18
21
15
18
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
°C
ATTOUT (Bidirectional Use)
Case Temperature (TCASE
)
−40
+105
1 Input linearity performance degrades over frequency, see Figure 30 and Figure 31.
2 The D3/SEROUT pin is an input in parallel control mode and an output in serial control mode. See Table 5 for the pin function descriptions.
3 For power derating over frequency, see Figure 2 to Figure 3. Applicable for all ATTIN and ATTOUT power specifications.
4 For 105°C operation, the power handling degrades from the TCASE = 85°C specifications by 3 dB.
TIMING SPECIFICATIONS
See Figure 34, Figure 35, and Figure 36 for the timing diagrams.
Table 2.
Parameter
Description
Min
70
15
Typ
Max
Unit
tSCK
tCS
tCH
tLN
tLEW
tLES
tCKN
tPH
tPS
Minimum serial period, see Figure 34
Control setup time, see Figure 34
Control hold time, see Figure 34
LE setup time, see Figure 34
Minimum LE pulse width, see Figure 34 and Figure 36
Minimum LE pulse spacing, see Figure 34
Serial clock hold time from LE, see Figure 34
Hold time, see Figure 36
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
15
10
630
0
10
2
Setup time, see Figure 36
Clock to output (SEROUT) time, see Figure 35
tCO
20
Rev. 0 | Page 5 of 19
ADRF5730
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
POWER DERATING CURVES
2
Parameter
Rating
Positive Supply Voltage
Negative Supply Voltage
Digital Control Input Voltage
−0.3 V to +3.6 V
−3.6 V to +0.3 V
−0.3 V to VDD + 0.3 V
0
–2
–4
RF Input Power1 (f = 100 MHz to
30 GHz, TCASE = 85°C2)
–6
ATTIN
–8
Steady State Average
Steady State Peak
Hot Switching Average
Hot Switching Peak
ATTOUT
Steady State Average
Steady State Peak
Hot Switching Average
Hot Switching Peak
Temperature
28 dBm
31 dBm
25 dBm
28 dBm
–10
–12
–14
–16
19 dBm
22 dBm
16 dBm
19 dBm
10k
100k
1M
10M
100M
1G
10G
100G
FREQUENCY (Hz)
Figure 2. Power Derating vs. Frequency, Low Frequency Detail, TCASE = 85°C
2
0
–2
Junction (TJ)
Storage
Reflow
135°C
−65°C to +150°C
260°C
–4
Continuous Power Dissipation (PDISS
)
0.5 W
–6
ESD Sensitivity
–8
Human Body Model (HBM)
ATTIN and ATTOUT Pins
Digital Pins
500 V
2000 V
1250 V
–10
–12
–14
Charged Device Model (CDM)
1 For power derating over frequency, see Figure 2 and Figure 3. Applicable for
all ATTIN and ATTOUT power specifications.
–16
26 28 30 32 34 36 38 40 42 44 46 48 50
2 For 105°C operation, the power handling degrades from the TCASE = 85°C
specifications by 3 dB.
FREQUENCY (GHz)
Figure 3. Power Derating vs. Frequency, High Frequency Detail, TCASE = 85°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJC is the junction to case bottom (channel to package bottom)
thermal resistance.
Table 4. Thermal Resistance
Package Type
θJC
Unit
CC-24-5
100
°C/W
Rev. 0 | Page 6 of 19
Data Sheet
ADRF5730
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24 23 22 21 20 19
1
2
3
4
5
6
18
17
16
15
14
13
LE
PS
VDD
VSS
ADRF5730
GND
GND
ATTIN
GND
GND
TOP VIEW
GND
(Not to Scale)
ATTOUT
GND
7
8
9
10 11 12
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED
TO THE RF AND DC GROUND OF THE PCB.
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
LE
PS
Latch Enable Input. See the Theory of Operation section for more information.
Parallel or Serial Control Interface Selection Input. See the Theory of Operation section for more
information.
3, 4, 6 to 13, 15, 16
5
GND
ATTIN
Ground. These pins must be connected to the RF and dc ground of the PCB.
Attenuator Input. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is
necessary when the RF line potential is equal to 0 V dc.
14
ATTOUT
Attenuator Output. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is
necessary when the RF line potential is equal to 0 V dc.
17
18
19
20
21
22
VSS
VDD
D0
D1
D2
Negative Supply Input.
Positive Supply Input.
Parallel Control Input for 0.5 dB Attenuator Bit. See the Theory of Operation section for more information.
Parallel Control Input for 1 dB Attenuator Bit. See the Theory of Operation section for more information.
Parallel Control Input for 2 dB Attenuator Bit. See the Theory of Operation section for more information.
D3/SEROUT Parallel Control Input for 4 dB Attenuator Bit (D3).
Serial Data Output (SEROUT). See the Theory of Operation section for more information.
23
24
D4/SERIN
D5/CLK
EPAD
Parallel Control Input for 8 dB Attenuator Bit (D4).
Serial Data Input (SERIN). See the Theory of Operation section for more information.
Parallel Control Input for 16 dB Attenuator Bit (D5).
Serial Clock Input (CLK). See the Theory of Operation section for more information.
Exposed Pad. The exposed pad must be connected to the RF and dc ground of the PCB.
INTERFACE SCHEMATICS
VDD
VDD
VDD
VDD
LE, PS, D3/SEROUT,
D4/SERIN, D5/CLK
D0, D1, D2
100kΩ
Figure 5. Digital Input Interface (LE, PS, D3/SEROUT, D4/SERIN, D5/CLK)
Figure 7. Digital Input Interface (D0, D1, D2)
ATTIN,
ATTOUT
Figure 6. ATTIN and ATTOUT Interface
Rev. 0 | Page 7 of 19
ADRF5730
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
INSERTION LOSS, RETURN LOSS, STATE ERROR, STEP ERROR, AND RELATIVE PHASE
VDD = 3.3 V, VSS = −3.3 V, digital voltages = 0 V or VDD, TCASE = 25°C, and a 50 Ω system, unless otherwise noted. Measured on probe
matrix board using ground signal ground (GSG) probes close to the RF pins. See the Applications Information section for details on
evaluation and probe matrix boards.
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
+105°C
+85°C
+25°C
–40°C
+105°C
+85°C
+25°C
–40°C
0
5
10
15
20
25
30
35
40
45
0
5
10
15
20
25
30
35
40
45
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 8. Insertion Loss vs. Frequency over Temperature with Impedance Match
Figure 11. Insertion Loss vs. Frequency over Temperature Without Impedance
Match
0
–5
0
–5
–10
–15
–20
–25
–30
–35
–10
–15
–20
–25
–30
–35
0
5
10
15
20
25
30
35
40
45
0
5
10
15
20
25
30
35
40
45
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 9. Normalized Attenuation vs. Frequency for All States at Room
Figure 12. Normalized Attenuation vs. Frequency for All States at Room
Temperature, with Impedance Match
Temperature Without Impedance Match
0
0
–5
–10
–15
–20
–25
–30
–35
–40
–5
–10
–15
–20
–25
–30
–35
–40
STATE 0dB
STATE 1dB
STATE 4dB
STATE 16dB
STATE 0.5dB
STATE 2dB
STATE 8dB
STATE 0dB
STATE 1dB
STATE 4dB
STATE 16dB
STATE 0.5dB
STATE 2dB
STATE 8dB
–45
–50
–45
–50
STATE 31.5dB
STATE 31.5dB
0
5
10
15
20
25
30
35
40
45
0
5
10
15
20
25
30
35
40
45
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 10. Input Return Loss vs. Frequency (Major States Only) with Impedance
Match
Figure 13. Input Return Loss vs. Frequency (Major States Only) Without
Impedance Match
Rev. 0 | Page 8 of 19
Data Sheet
ADRF5730
0
0
–5
STATE 0dB
STATE 1dB
STATE 4dB
STATE 16dB
STATE 0.5dB
STATE 2dB
STATE 8dB
–5
STATE 31.5dB
–10
–15
–20
–25
–30
–35
–40
–10
–15
–20
–25
–30
–35
–40
–45
–50
STATE 0dB
STATE 0.5dB
STATE 2dB
STATE 8dB
STATE 1dB
STATE 4dB
STATE 16dB
–45
–50
STATE 31.5dB
0
5
10
15
20
25
30
35
40
45
0
5
10
15
20
25
30
35
40
45
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 14. Output Return Loss vs. Frequency (Major States Only) with
Impedance Match
Figure 17. Output Return Loss vs. Frequency (Major States Only) Without
Impedance Match
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.2
–0.4
–0.6
STATE 0dB
STATE 1dB
STATE 4dB
STATE 16dB
STATE 0.5dB
STATE 2dB
STATE 8dB
STATE 0dB
STATE 1dB
STATE 4dB
STATE 16dB
STATE 0.5dB
STATE 2dB
STATE 8dB
–0.8
–1.0
–0.8
–1.0
STATE 31.5dB
STATE 31.5dB
0
5
10
15
20
25
30
35
40
45
0
5
10
15
20
25
30
35
40
45
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 15. Step Error vs. Frequency (Major States Only) with Impedance
Match
Figure 18. Step Error vs. Frequency (Major States Only) Without Impedance
Match
0.8
0.6
0.8
5GHz
20GHz
35GHz
10GHz
25GHz
40GHz
15GHz
30GHz
45GHz
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
5GHz
20GHz
35GHz
10GHz
25GHz
40GHz
15GHz
30GHz
45GHz
–1.2
–1.4
ATTENUATION STATE (dB)
ATTENUATION STATE (dB)
Figure 16. Step Error vs. Attenuation State over Frequency with Impedance
Match
Figure 19. Step Error vs. Attenuation State over Frequency Without
Impedance Match
Rev. 0 | Page 9 of 19
ADRF5730
Data Sheet
2.5
2.0
1.5
1.0
0.5
0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–0.5
–1.0
–1.5
STATE 0dB
STATE 0.5dB
STATE 2dB
STATE 8dB
STATE 0dB
STATE 1dB
STATE 4dB
STATE 16dB
STATE 0.5dB
STATE 2dB
STATE 8dB
STATE 1dB
STATE 4dB
STATE 16dB
–1.0
–1.5
STATE 31.5dB
STATE 31.5dB
0
5
10
15
20
25
30
35
40
45
0
5
10
15
20
25
30
35
40
45
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 20. State Error vs. Frequency (Major States Only) with Impedance
Match
Figure 23. State Error vs. Frequency (Major States Only) Without Impedance
Match
2.5
2.5
5GHz
20GHz
35GHz
10GHz
25GHz
40GHz
15GHz
30GHz
45GHz
5GHz
20GHz
35GHz
10GHz
25GHz
40GHz
15GHz
30GHz
45GHz
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–0.5
–1.0
–1.5
–2.0
–2.5
ATTENUATION STATE (dB)
ATTENUATION STATE (dB)
Figure 21. State Error vs. Attenuation State over Frequency with Impedance
Match
Figure 24. State Error vs. Attenuation State over Frequency Without
Impedance Match
120
120
STATE 0dB
STATE 1dB
STATE 4dB
STATE 16dB
STATE 0.5dB
STATE 2dB
STATE 8dB
STATE 0dB
STATE 1dB
STATE 4dB
STATE 16dB
STATE 0.5dB
STATE 2dB
STATE 8dB
110
100
90
80
70
60
50
40
30
20
10
0
110
100
90
80
70
60
50
40
30
20
10
0
STATE 31.5dB
STATE 31.5dB
0
5
10
15
20
25
30
35
40
45
0
5
10
15
20
25
30
35
40
45
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 22. Relative Phase vs. Frequency (Major States Only) with Impedance
Match
Figure 25. Relative Phase vs. Frequency (Major States Only) Without
Impedance Match
Rev. 0 | Page 10 of 19
Data Sheet
ADRF5730
120
100
80
60
40
20
0
120
5GHz
20GHz
35GHz
10GHz
25GHz
40GHz
15GHz
30GHz
45GHz
5GHz
20GHz
35GHz
100
10GHz
25GHz
40GHz
15GHz
30GHz
45GHz
80
60
40
20
0
ATTENUATION STATE (dB)
ATTENUATION STATE (dB)
Figure 27. Relative Phase vs. Attenuation State over Frequency
Without Impedance Match
Figure 26. Relative Phase vs. Attenuation State over Frequency
with Impedance Match
Rev. 0 | Page 11 of 19
ADRF5730
Data Sheet
INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT
35
35
30
25
20
15
10
5
30
25
20
15
10
STATE 0dB
STATE 1dB
STATE 4dB
STATE 16dB
STATE 0.5dB
STATE 2dB
STATE 8dB
STATE 0dB
STATE 1dB
STATE 4dB
STATE 16dB
STATE 0.5dB
STATE 2dB
STATE 8dB
5
0
STATE 31.5dB
STATE 31.5dB
0
0
10
20
30
40
10k
100k
1M
10M
100M
1G
FREQUENCY (GHz)
FREQUENCY (Hz)
Figure 28. Input P0.1dB vs. Frequency (Major States Only)
Figure 30. Input P0.1dB vs. Frequency (Major States Only), Low Frequency
Detail
80
80
70
60
50
40
30
20
70
60
50
40
30
20
10
0
STATE 0dB
STATE 1dB
STATE 4dB
STATE 16dB
STATE 0.5dB
STATE 2dB
STATE 8dB
STATE 0dB
STATE 1dB
STATE 4dB
STATE 16dB
STATE 0.5dB
STATE 2dB
STATE 8dB
10
0
STATE 31.5dB
STATE 31.5dB
0
5
10
15
20
25
30
35
40
10k
100k
1M
10M
100M
1G
FREQUENCY (GHz)
FREQUENCY (Hz)
Figure 29. Input IP3 vs. Frequency (Major States Only)
Figure 31. Input IP3 vs. Frequency (Major States Only), Low Frequency Detail
Rev. 0 | Page 12 of 19
Data Sheet
ADRF5730
THEORY OF OPERATION
The ADRF5730 incorporates a 6-bit fixed attenuator array that
offers an attenuation range of 31.5 dB in 0.5 dB steps. An
integrated driver provides both serial and parallel mode control
of the attenuator array (see Figure 32).
RF INPUT AND OUTPUT
Both RF ports (ATTIN and ATTOUT) are dc-coupled to 0 V.
No dc blocking is required at the RF ports when the RF line
potential is equal to 0 V.
Note that when referring to a single function of a multifunction
pin in this section, only the portion of the pin name that is
relevant is mentioned. For full pin names of the multifunction
pins, refer to the Pin Configuration and Function Descriptions
section.
The RF ports are internally matched to 50 Ω. Therefore,
external matching components are not required. For wideband
applications, use impedance matching to improve insertion loss,
return loss, and attenuation accuracy performance at high
frequencies. See the Impedance Matching section.
POWER SUPPLY
The ADRF5730 supports bidirectional operation at a lower
power level. The power handling of the ATTIN and ATTOUT
ports are different. Therefore, the bidirectional power handling is
defined by the ATTOUT port. Refer to the RF input power
specifications in Table 1.
The ADRF5730 requires a positive supply voltage applied to the
VDD pin and a negative supply voltage applied to the VSS pin.
Bypassing capacitors are recommended on the supply lines to
filter high frequency noise.
The power-up sequence is as follows:
SERIAL OR PARALLEL MODE SELECTION
1. Connect GND.
2. Power up VDD.
The ADRF5730 can be controlled in either serial or parallel mode
by setting the PS pin to high or low, respectively (see Table 6).
3. Power up VSS.
Table 6. Mode Selection
4. Apply the digital control inputs. The relative order of the
digital control inputs is not important. However, powering
the digital control inputs before the VDD supply can
inadvertently forward bias and damage the internal ESD
protection structures.
PS
Control Mode
Low
High
Parallel
Serial
5. Apply an RF input signal to ATTIN or ATTOUT.
The power-down sequence is the reverse order of the power-up
sequence.
Table 7. Truth Table
Digital Control Input1
D5
D4
D3
D2
D1
D0
Attenuation State (dB)
Low
Low
Low
Low
Low
Low
High
High
Low
Low
Low
Low
Low
High
Low
High
Low
Low
Low
Low
High
Low
Low
High
Low
Low
Low
High
Low
Low
Low
High
Low
Low
High
Low
Low
Low
Low
High
Low
High
Low
Low
Low
Low
Low
High
0 (reference)
0.5
1.0
2.0
4.0
8.0
16.0
31.5
1 Any combination of the control voltage input states shown in Table 7 provides an attenuation equal to the sum of the bits selected.
Rev. 0 | Page 13 of 19
ADRF5730
Data Sheet
D0
D1
D2
D3
D4
D5
SERIN
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D Q
SEROUT
CLK
PS
PARALLEL OR SERIAL SELECT
6-BIT OR 8-BIT LATCH
LE
RF
INPUT
RF
OUTPUT
0.5dB
1dB
2dB
4dB
8dB
16dB
Figure 32. Simplified Circuit Diagram
SERIAL MODE INTERFACE
USING SEROUT
The ADRF5730 supports a 3-wire SPI: serial data input (SERIN),
clock (CLK), and latch enable (LE). The serial control interface
is activated when PS is set to high.
The ADRF5730 also features a serial data output, SEROUT.
SEROUT outputs the serial input data at the 8th clock cycle, and
can control a cascaded attenuator using a single SPI bus. Figure 35
shows the serial out timing diagram.
The ADRF5730 attenuation states can be controlled using 6-bit
or 8-bit SERIN data. If an 8-bit word is used to control the state
of the attenuator, the first two bits, D7 and D6, are don’t care
bits. It does not matter if these two bits are held low or high, or
if they are omitted altogether. Only Bits[D0:D5] set the state of
the attenuator.
When using the attenuator in a daisy-chain operation, 8-bit
SERIN data must be used due to the 8 clock cycle delay between
SERIN and SEROUT.
It is optional to use a 1 kΩ resistor between SEROUT on the
first attenuator and SERIN of the next attenuator to filter the
In serial mode, the SERIN data is clocked most significant bit
(MSB) first on the rising CLK edges into the shift register. Then,
LE must be toggled high to latch the new attenuation state into
the device. LE must be set to low to clock new SERIN data into
the shift register as CLK is masked to prevent the attenuator
value from changing if LE is kept high. See Figure 34 in
conjunction with Table 2 and Table 7.
signal (see Figure 33).
4
3
2
1
WITHOUT 1kΩ
WITH 1kΩ
0
0
50
100 150 200 250 300 350 400 450 500
TIME (ns)
Figure 33. Using a Resistor on SEROUT
Rev. 0 | Page 14 of 19
Data Sheet
ADRF5730
[FIRST IN]
[LAST IN]
LSB
PS
X
OPTIONAL OPTIONAL
MSB
D5
tCS tCH
D[7:0]
NEXT WORD
SERIN
X
D7
D6
D4
D3
D2
D1
D0
X
X
tLN
tLEW
tCKN
CLK
LE
tSCK
tLES
Figure 34. Serial Control Timing Diagram
PS
X
SERIN
X
D5
D4
D3
D2
D1
D0
X
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK
LE
SEROUT
X
D5
D4
D3
D2
D1
D0
X
tCO
Figure 35. Serial Output Timing Diagram
Latched Parallel Mode
PARALLEL MODE INTERFACE
To enable latched parallel mode, the LE pin must be kept low
when changing the control voltage inputs (D0 to D5) to set the
attenuation state. When the desired state is set, LE must be
toggled high to transfer the 6-bit data to the bypass switches of
the attenuator array, and then toggled low to latch the change
into the device until the next desired attenuation change (see
Figure 36 in conjunction with Table 2).
The ADRF5730 has six digital control inputs, D0 (LSB) to D5
(MSB), to select the desired attenuation state in parallel mode, as
shown in Table 7. The parallel control interface is activated when
PS is set to low.
There are two modes of parallel operation: direct parallel and
latched parallel.
Direct Parallel Mode
PS
X
To enable direct parallel mode, the LE pin must be kept high.
The attenuation state is changed by the control voltage inputs
(D0 to D5) directly. This mode is ideal for manual control of the
attenuator.
tPS
tPH
D5 TO D0
LE
X
X
tLEW
Figure 36. Latched Parallel Mode Timing Diagram
Rev. 0 | Page 15 of 19
ADRF5730
Data Sheet
APPLICATIONS INFORMATION
Thru calibration can be used to calibrate out the board loss effects
from the ADRF5730-EVALZ evaluation board measurements to
determine the device performance at the pins of the IC. Figure 39
shows the typical board loss for the ADRF5730-EVALZ evaluation
board at room temperature, the embedded insertion loss, and the
de-embedded insertion loss for the ADRF5730.
0
EVALUATION BOARD
The ADRF5730-EVALZ is a 4-layer evaluation board. The top
and bottom copper layer are 0.5 oz (0.7 mil) plated to 1.5 oz
(2.2 mil) and are separated by dielectric materials. The stackup
for this evaluation board is shown in Figure 37.
G = 6mil
W = 16mil
1.5oz Cu (2.2mil)
1.5oz Cu (2.2mil)
RO4003
1.5oz Cu (2.2mil)
T = 2.2mil
H = 12mil
–1
–2
–3
–4
–5
–6
–7
0.5oz Cu (0.7mil)
0.5oz Cu (0.7mil)
1.5oz Cu (2.2mil)
–8
THRU LOSS
EMBEDDED INSERTION LOSS
–9
DE-EMBEDDED INSERTION LOSS
–10
Figure 37. Evaluation Board Stackup
0
5
10
15
20
25
30
35
40
45
FREQUENCY (GHz)
All RF and dc traces are routed on the top copper layer, whereas
the inner and bottom layers are grounded planes that provide a
solid ground for the RF transmission lines. The top dielectric
material is 12 mil Rogers RO4003, offering optimal high
frequency performance. The middle and bottom dielectric
materials provide mechanical strength. The overall board
thickness is 62 mil, which allows 2.4 mm RF launchers to be
connected at the board edges.
Figure 39. Insertion Loss vs. Frequency
Figure 38 shows the actual ADRF5730 evaluation board with
component placement.
Two power supply ports are connected to the VDD and VSS test
points, TP1 and TP2, and the ground reference is connected to
the GND test point, TP4. On the supply traces, VDD and VSS, a
100 pF bypass capacitor is used to filter high frequency noise.
Additionally, unpopulated components positions are available
for applying extra bypass capacitors.
All the digital control pins are connected through digital signal
traces to the 2 × 9-pin header, P1. There are provisions for a
resistor capacitor (RC) filter that helps eliminate dc-coupled
noise. The ADRF5730 was evaluated without an external RC
filter, the series resistors are 0 Ω, and shunt capacitors are
unpopulated on the evaluation board.
Figure 38. Evaluation Board, Top View
The RF input and output ports (ATTIN and ATTOUT) are
connected through 50 Ω transmission lines to the 2.4 mm RF
launchers, J1 and J2, respectively. These high frequency RF
launchers are connected by contact and are not soldered onto
the board.
The RF transmission lines are designed using a coplanar
waveguide (CPWG) model, with a trace width of 16 mil and
ground clearance of 6 mil to have a characteristic impedance of
50 Ω. For optimal RF and thermal grounding, as many through
vias as possible are arranged around transmission lines and
under the exposed pad of the package.
A thru calibration line connects the unpopulated J3 and J4
launchers. This transmission line is used to estimate the loss of
the PCB over the environmental conditions being evaluated.
The ADRF5730-EVALZ does not have high frequency
impedance matching implemented on the RF transmission
lines. For more details on the impedance matched circuit, refer
to the Impedance Matching portion of the Probe Matrix Board
section.
The schematic of the ADRF5730-EVALZ evaluation board is
shown in Figure 40.
Rev. 0 | Page 16 of 19
Data Sheet
ADRF5730
R5
P1
R6
D3_SEROUT
D4_SERIN
D2
D1
0
R4
0
PS
LE
1
3
5
7
2
6
4
8
10
12
14
16
18
R7
D5_CLK
D4_SERIN
D3_SEROUT 9
D2
D1
D0
0
R8
0
R3
0
D0
D5_CLK
0
11
13
15
17
VDD
R2
0
25
C1
100pF
LE
PS
EPAD
VSS
1
2
3
4
5
6
18
17
16
15
14
13
LE
VDD
VSS
87759-1850
R1
0
AGND
PS
C2
100pF
GND
GND
ATTIN
GND
GND
ADRF5730
GND
ATTOUT
GND
J3
DNI
J4
DNI
J1
J2
THRU CAL
ATTIN
ATTOUT
Figure 40. Evaluation Board Schematic
Table 8. Evaluation Board Components
Component
Default Value
Description
C1, C2
100 pF
Capacitor, C0402 package
J1 to J4
P1
R1 to R11
TP1, TP2, TP4
U1
Not applicable
Not applicable
0 Ω
Not applicable
ADRF5730
2.4 mm end launch connector (Southwest Microwave: 1492-04A-5)
2 × 9-pin header
Resistor, 0402 package
Through-hole mount test point
ADRF5730 digital attenuator, Analog Devices, Inc.
Rev. 0 | Page 17 of 19
ADRF5730
Data Sheet
The probe matrix board includes a thru reflect line (TRL)
PROBE MATRIX BOARD
calibration kit, allowing board loss de-embedding. The actual
board duplicates the same layout in matrix form to assemble
multiple devices at one time. All S-parameters were measured
on this board.
The probe matrix board is a 4-layer board. Similar to the evaluation
board, the probe matrix board also uses a 12 mil Rogers RO4003
dielectric. The top and bottom copper layers are 0.5 oz (0.7 mil)
plated to 1.5 oz (2.2 mil). The RF transmission lines are designed
using a CPWG model with a width of 16 mil and ground
spacing of 6 mil to have a characteristic impedance of 50 Ω.
Impedance Matching
Impedance matching at the RF pins can improve insertion loss,
return loss, and attenuation accuracy at high frequencies. Figure 43
and Figure 44 show the difference in the transmission lines at
the ATTIN and ATTOUT pins.
Figure 41 and Figure 42 show the cross sectional view and the
top view of the board, respectively. Measurements are made
using GSG probes at close proximity to the RF pins. Unlike the
evaluation board, probing reduces reflections caused by
mismatch arising from connectors, cables, and board layout,
resulting in a more accurate measurement of the device
performance.
The dimensions of the 50 Ω lines are 16 mil trace width and
6 mil gap. To implement this impedance matched circuit, the
pad length is extended by 5 mil (from 17 mil to 22 mil). The
calibration reference kit does not include the 5 mil matching
line and, therefore, the measured insertion loss includes the
losses of the matching circuit.
G = 6mil
W = 16mil
1.5oz Cu (2.2mil)
1.5oz Cu (2.2mil)
RO4003
1.5oz Cu (2.2mil)
T = 2.2mil
H = 12mil
0.5oz Cu (0.7mil)
6
17
16
0.5oz Cu (0.7mil)
1.5oz Cu (2.2mil)
10
6
Figure 41. Probe Matrix Board Stackup
Figure 43. Without Impedance Match
22
10
16
Figure 44. With Impedance Match
Figure 42. Probe Matrix Board Top View
Rev. 0 | Page 18 of 19
Data Sheet
ADRF5730
OUTLINE DIMENSIONS
4.10
4.00
3.90
0.30
0.25
0.20
0.35
0.30
0.25
CHAMFERED
PIN 1 (0.2 × 45°)
PIN 1
CORNER AREA
24
19
18
1
2.50
2.40 SQ
2.30
2.50 REF
SQ
EXPOSED
PAD
13
6
0.50
BSC
12
7
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.125
BSC
0.375
BSC
0.85
0.75
0.65
FOR PROPER CONNECTION OF
THE EXPOSED PADS, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.530 REF
SECTION OF THIS DATA SHEET.
0.240
0.220
0.200
Figure 45. 24-Terminal Land Grid Array [LGA]
4 mm × 4 mm Body and 0.75 mm Package Height
(CC-24-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADRF5730BCCZN
ADRF5730BCCZN-R7
ADRF5730-EVALZ
Temperature Range
−40°C to +105°C
−40°C to +105°C
Package Description
Package Option
24-Terminal Land Grid Array [LGA]
24-Terminal Land Grid Array [LGA]
Evaluation Board
CC-24-5
CC-24-5
1 Z = RoHS Compliant Part.
©2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15958-0-7/18(0)
Rev. 0 | Page 19 of 19
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