ADRF5160BCPZ [ADI]
High Power, 88 W Peak, Silicon SPDT, Reflective Switch, 0.7 GHz to 4.0 GHz;
| 型号： | ADRF5160BCPZ |
| 厂家： | 
ADI |
| 描述： | High Power, 88 W Peak, Silicon SPDT, Reflective Switch, 0.7 GHz to 4.0 GHz 光电二极管 |
| 文件： | 总12页 (文件大小：351K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Power, 88 W Peak, Silicon SPDT,
Reflective Switch, 0.7 GHz to 4.0 GHz
Data Sheet
ADRF5160
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
V
CTL
DD
Reflective, 50 Ω design
Low insertion loss: 0.7 dB typical to 2.0 GHz
High power handling at TCASE = 105°C
Long-term (>10 years) average
CW power: 43 dBm
ADRF5160
RF1
RF2
Peak power: 49 dBm
LTE average power (8 dB PAR): 41 dBm
Single event (<10 sec) average
LTE average power (8 dB PAR): 44 dBm
High linearity
PACKAGE
BASE
RFC
GND
P0.1dB: 47 dBm typical
GND
IP3: 70 dBm typical
ESD ratings
Figure 1.
HBM: 4 kV, Class 3A
CDM: 1.25 kV
Single positive supply: 5 V
Positive control, CMOS/TTL compatible
32-lead, 5 mm × 5 mm LFCSP package
APPLICATIONS
Wireless infrastructure
Military and high reliability applications
Test equipment
Pin diode replacement
GENERAL DESCRIPTION
The ADRF5160 is a silicon-based, high power, 0.7 GHz to
4.0 GHz, silicon, single-pole, double-throw (SPDT) reflective
switch in a leadless, surface-mount package. The switch is ideal
for high power and cellular infrastructure applications, such as
long-term evolution (LTE) base stations. The ADRF5160 has
high power handling of 41 dBm (8 dB PAR LTE, long-term
(>10 years) average typical), a low insertion loss of 0.7 dB typical
to 2.0 GHz, an input third-order intercept (IP3) of 70 dBm
(typical), and a 0.1 dB compression point (P0.1dB) of 47 dBm.
On-chip circuitry operates at a single positive supply voltage of
5 V at a typical supply current of 1.1 mA, making the ADRF5160
an ideal alternative to pin diode-based switches.
The ADRF5160 comes in an RoHS compliant, compact, 32-lead,
5 mm × 5 mm LFCSP.
Rev. 0
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2018 Analog Devices, Inc. All rights reserved.
www.analog.com
ADRF5160
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Interface Schematics .....................................................................5
Typical Performance Characteristics ..............................................6
Theory of Operation .........................................................................8
Applications Information .................................................................9
Evaluation Board ...........................................................................9
Typical Application Circuit....................................................... 10
Outline Dimensions....................................................................... 12
Ordering Guide .......................................................................... 12
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
REVISION HISTORY
5/2018—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
Data Sheet
ADRF5160
SPECIFICATIONS
VDD = 5 V, VCTL = 0 V/VDD, TA = 25°C, and the device is a 50 Ω system, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min Typ
Max Unit
FREQUENCY RANGE
INSERTION LOSS
0.7
0.7
0.8
0.9
4.0
GHz
dB
dB
0.7 GHz to 2.0 GHz
2.0 GHz to 3.5 GHz
3.5 GHz to 4.0 GHz
1.01
dB
ISOLATION
RFC to RF1 and RF2 (Worst Case)
0.7 GHz to 2.0 GHz
2.0 GHz to 4.0 GHz
0.7 GHz to 2.0 GHz
2.0 GHz to 4.0 GHz
53
45
51
35
dB
dB
dB
dB
RF1 to RF2
RETURN LOSS
RFC
0.7 GHz to 2.0 GHz
2.0 GHz to 4.0 GHz
0.7 GHz to 2.0 GHz
2.0 GHz to 4.0 GHz
20
19
19
18
dB
dB
dB
dB
RF1 and RF2 (On State)
SWITCHING CHARACTERISTICS
Rise and Fall Time (tRISE, tFALL
)
10%/90% radio frequency output (RFOUT
50% VCTL to 10%/90% RFOUT
)
0.27
1.2
µs
µs
On and Off Time (tON, tOFF
)
INPUT LINEARITY
0.1 dB Compression (P0.1dB)
Third-Order Intercept (IP3)
47
dBm
Two-tone input power = 30 dBm per tone at 1 MHz tone spacing
0.7 GHz to 2.0 GHz
2.0 GHz to 4.0 GHz
72
70
1.1
dBm
dBm
mA
SUPPLY CURRENT
DIGITAL CONTROL INPUT
Low Voltage
High Voltage
Low and High Current
RECOMMENDED OPERATING CONDITIONS
Supply Voltage Range (VDD)
Control Voltage Range (VCTL
RF Input Power
Case Temperature (TCASE) = 105°C2
VDD = 4.5 V to 5.4 V, TCASE = −40°C to +105°C
0
0.8
5
V
V
µA
1.3
<1
4.5
0
5.4
VDD
V
V
)
Continuous wave (CW)
43
41
44
45
41
44
47.5
41
44
49
41
44
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
8 dB peak average ratio (PAR) LTE, long-term (>10 years) average
8 dB PAR LTE, single event (<10 sec) average
CW
8 dB PAR LTE, long-term (>10 years) average
8 dB PAR LTE, single event (<10 sec) average
CW
8 dB PAR LTE, long-term (>10 years) average
8 dB PAR LTE, single event (<10 sec) average
CW
8 dB PAR LTE, long-term (>10 years) average
8 dB PAR LTE, single event (<10 sec) average
TCASE = 85°C
TCASE = 25°C
TCASE = −40°C
TCASE Range
−40
+105 °C
1 Guaranteed by design for device to device and over operating temperature variation.
2 Peak power is 49 dBm, which corresponds to a PAR of 8 dB at LTE long-term.
Rev. 0 | Page 3 of 12
ADRF5160
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
Rating
Supply Voltage Range (VDD)
Control Voltage Range (VCTL
RF Input Power1
Channel Temperature
Maximum Peak Reflow Temperature
(Moisture Sensitivity Level 3 (MSL3))2
−0.3 V to +5.4 V
−0.3 V to VDD + 0.3 V
49.7 dBm
135°C
260°C
)
Table 3. Thermal Resistance
Package Type
θJC
Unit
HCP-32-1
8.4
°C/W
Storage Temperature Range
−65°C to +150°C
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM)
Charged Device Model (CDM)
ESD CAUTION
4 kV (Class 3A)
1.25 kV
1 For the recommended operating conditions, see Table 1.
2 See the Ordering Guide for additional information.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 4 of 12
Data Sheet
ADRF5160
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
GND
GND
RF1
GND
GND
GND
GND
1
2
3
4
5
6
7
8
24 GND
23
GND
22 GND
ADRF5160
RF2
GND
GND
21
20
19
TOP VIEW
(Not to Scale)
18 GND
17 GND
NOTES
1. EXPOSED PAD. EXPOSED PAD MUST BE
CONNECTED TO RF/DC GROUND.
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1 to 3, 5 to 11, 13 to 20, 22 to 27, 30 to 32
GND
RF1
RFC
RF2
VCTL
Ground. The package bottom has an exposed metal pad that must connect to
the PCB RF/dc ground.
RF Port 1. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is
required on this pin. See Figure 3 for the interface schematic.
RF Common Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking
capacitor is required on this pin. See Figure 3 for the interface schematic.
RF Port 2. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is
required on this pin. See Figure 3 for the interface schematic.
4
12
21
28
Control Input Pin. See Figure 4 for the VCTL interface schematic. Refer to Table 5
for the signal path and the recommended input control voltage range shown in
Table 1.
29
VDD
Supply Voltage Pin.
EPAD
Exposed Pad. Exposed pad must be connected to RF/dc ground.
INTERFACE SCHEMATICS
V
V
DD
DD
V
CTL
RFC,
RF1,
RF2
Figure 3. RFC, RF1, and RF2 Interface Schematic
Figure 4. Control Input (VCTL) Interface Schematic
Rev. 0 | Page 5 of 12
ADRF5160
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–40°C
+25°C
+85°C
+105°C
RF1
RF2
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
0
1
2
3
4
5
0
1
2
3
4
5
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 5. Insertion Loss for RF1 and RF2 vs. Frequency at VDD = 5 V
Figure 8. Insertion Loss vs. Frequency for Various Temperatures at VDD = 5 V
0
0
RF1
RF2
RF1
RF2
–10
–10
–20
–30
–40
–50
–60
–70
–80
–90
–20
–30
–40
–50
–60
–70
–80
–90
0
1
2
3
4
5
0
1
2
3
4
5
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 6. Isolation Between RFC and RF1 and RF2 vs. Frequency at VDD = 5 V
Figure 9. Isolation Between RF1 and RF2 vs. Frequency at VDD = 5 V
0
RFC
RF1
RF2
–5
–10
–15
–20
–25
–30
–35
–40
0
1
2
3
4
5
FREQUENCY (GHz)
Figure 7. Return Loss vs. Frequency at VDD = 5 V
Rev. 0 | Page 6 of 12
Data Sheet
ADRF5160
80
75
70
65
60
55
50
55
50
45
40
35
30
–40°C
+25°C
+85°C
+105°C
–40°C
+25°C
+85°C
+105°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 10. Input Third-Order Intercept (IP3) vs. Frequency for Various
Temperatures, VDD = 5 V
Figure 12. Input 0.1dB Compression (P0.1dB) vs. Frequency for Various
Temperatures, VDD = 5 V
RF1
RF2
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
FREQUENCY (GHz)
Figure 11. Input 0.1dB Power Compression (P0.1dB) vs. Frequency, VDD = 5 V
Rev. 0 | Page 7 of 12
ADRF5160
Data Sheet
THEORY OF OPERATION
The ADRF5160 requires a single-supply voltage applied to the
The ideal power-up sequence is as follows:
1. Connect GND.
V
DD pin. Bypassing capacitors are recommended on the supply
line to minimize RF coupling.
2. Power up VDD
.
The ADRF5160 is controlled via a digital control voltage
applied to the VCTL pin. A bypassing capacitor is recommended
on this digital signal line to improve the RF signal isolation.
3. Power up the digital control input. Power the digital
control input before the VDD supply to avoid inadvertently
forward biasing and damaging the ESD protection
structures.
The ADRF5160 is internally matched to 50 Ω at the RF input
port (RFC) and the RF output ports (RF1 and RF2). Therefore,
no external matching components are required. The RFx pins
are dc-coupled, and dc blocking capacitors are required on the
RFx lines. The design is bidirectional, meaning that the input
and outputs are interchangeable.
4. Power up the RF input.
Depending on the logic level applied to the VCTL pin, one RF
output port (for example, RF1) is set to on mode, by which an
insertion loss path is provided from the input to the output.
While the other RF output port (for example, RF2) is set to off
mode, by which the output is isolated from the input.
Table 5. Switch Operation Mode
Signal Path
Digital Control Input (VCTL
)
RF1 to RFC
RF2 to RFC
Low
High
Isolation (off)
Insertion loss (on)
Insertion loss (on)
Isolation (off)
Rev. 0 | Page 8 of 12
Data Sheet
ADRF5160
APPLICATIONS INFORMATION
To ensure maximum heat dissipation and to reduce thermal rise
on the board, some application considerations are essential. The
evaluation board must be attached to a copper support plate at
the bottom of the board. The ADRF5160-EVALZ comes with
this support plate attachment. Attach this evaluation board with
its support plate to a heat sink using thermal grease during all
high power operations. Figure 14 shows the board temperature
vs. the RF power input tested with the preceding conditions and
EVALUATION BOARD
The ADRF5160-EVALZ can withstand high power levels and
temperatures at which the device operates.
The ADRF5160-EVALZ evaluation board is constructed with
eight metal layers and dielectrics between each layer, as shown
in Figure 13. Each metal layer has a 1 oz (1.3 mil) copper
thickness, and the external layers are plated to 2 oz.
precautions (the evaluation board and support plate are attached
to a heat sink). The temperature rise is less than 8°C up to
48 dBm of RF power input, which provides the required
thermal dissipation when operating at high power levels.
The top dielectric material is 10 mil Rogers RO4350, which
exhibits a low thermal coefficient, offering control over thermal
rise of the board. The dielectrics between other metal layers are
FR4. The overall board thickness is 62 mil.
G = 13mil
W = 18mil
36
35
34
33
32
31
30
29
28
27
26
1.5oz Cu (2.1mil)
1.5oz Cu (2.1mil)
1.5oz Cu (2.1mil)
T = 2.1 mil
H = 10mil
RO4350 = 10mil
1oz Cu (1.3mil)
FR4
1oz Cu (1.3mil)
25
43.0 43.5 44.0 44.5 45.0 45.5 46.0 46.5 47.0 47.5 48.0
FR4
RF POWER INPUT (dBm)
Figure 14. ADRF5160-EVALZ Evaluation Board Temperature Rise
(Oven Temperature Set to 25°C)
1oz Cu (1.3mil)
FR4
C1
1oz Cu (1.3mil)
TP1
TP3
FR4
1oz Cu (1.3mil)
FR4
C2
R1
1oz Cu (1.3mil)
FR4
1.5oz Cu (2.1mil)
TP2
Figure 13. ADRF5160-EVALZ Evaluation Board Cross Sectional View
C3
The top copper layer has all RF and dc traces. The other seven
layers provide sufficient ground and help handle the thermal
rise on the ADRF5160-EVALZ. In addition, via holes are
provided around transmission lines and under the exposed pad
of package, as shown in Figure 15, for proper thermal
grounding. RF transmission lines on the board are of a coplanar
wave guide design with a width of 18 mils and ground spacing
of 13 mils.
Figure 15. ADRF5160-EVALZ Evaluation Board Layout
Rev. 0 | Page 9 of 12
ADRF5160
Data Sheet
impedance, and the package ground leads and backside ground
slug must connect directly to the ground plane. The evaluation
board shown in Figure 16 is available from Analog Devices, Inc.,
upon request.
TYPICAL APPLICATION CIRCUIT
Generate the evaluation PCB used in the typical application
circuit shown in Figure 17 with proper RF circuit design
techniques. Signal lines at the RF port must have a 50 Ω
J1
GND
VDD
C1
TP3
TP1
RFC
J2
C2
R1
4 3
2 1
TP2
600-01533-00-2
C3
VCTL
J3
Figure 16. ADRF5160-EVALZ Evaluation Board Component Placement
Table 6. Bill of Materials for the ADRF5160-EVALZ Evaluation Board
Reference Designator
Description
C1 to C3
24 pF, 200 V ultralow, effective series resistance (ESR) capacitors, 0402
package
C4
0.3 pF, 200 V ultralow ESR capacitor, 0402 package
Test point connectors
0 Ω resistor, 0402 package
TP1, TP2, TP3
R1
J1, J2, J3
U1
PCB1
PCB mount, SubMiniature Version A (SMA) connectors
ADRF5160 SPDT switch
ADRF5160-EVALZ2 evaluation PCB
1 The circuit board material is Roger 4350 or Arlon 25FR.
2 Reference to this evaluation board number when ordering the complete evaluation board.
Rev. 0 | Page 10 of 12
Data Sheet
ADRF5160
V
V
CTL
DD
R1
0Ω
32 31 30 29 28 27 26 25
GND
GND
GND
RF1
GND
GND
GND
RF2
ADRF5160
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
C1
C3
RF1
RF2
GND
GND
GND
GND
GND
GND
GND
GND
9
10 11 12 13 14 15 16
C4
C2
RFC
Figure 17. Typical Application Circuit
Rev. 0 | Page 11 of 12
ADRF5160
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
5.10
5.00 SQ
4.90
0.30
0.25
0.18
PIN 1
PIN 1
INDIC ATOR AREA OPTIONS
INDICATOR
(SEE DETAIL A)
25
32
24
1
0.50
BSC
3.80
3.70 SQ
3.60
EXPOSED
PAD
17
8
16
9
0.45
0.40
0.35
0.20 MIN
TOP VIEW
BOTTOM VIEW
3.50 REF
0.90
0.85
0.80
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-4.
Figure 18. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.85 mm Package Height
(HCP-32-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +105°C
−40°C to +105°C
MSL Rating2
MSL3
Package Description
Package Option
HCP-32-1
HCP-32-1
ADRF5160BCPZ
ADRF5160BCPZ-R7
ADRF5160-EVALZ
32-lead Lead Frame Chip Scale Package [LFCSP]
32-lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
MSL3
1 Z = RoHS Compliant Part.
2 See the Absolute Maximum Ratings section for additional information.
©2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16518-0-5/18(0)
Rev. 0 | Page 12 of 12
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