ADRF5042BCCZN [ADI]
Nonreflective, 100 MHz to 44 GHz Silicon SP4T Switch;
| 型号： | ADRF5042BCCZN |
| 厂家： | 
ADI |
| 描述： | Nonreflective, 100 MHz to 44 GHz Silicon SP4T Switch |
| 文件： | 总12页 (文件大小：562K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Nonreflective, 100 MHz to 44 GHz
Silicon SP4T Switch
Data Sheet
ADRF5042
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Ultrawideband frequency range: 100 MHz to 44 GHz
Nonreflective 50 Ω design
Low insertion loss
1.8 dB up to 18 GHz
2.8 dB up to 40 GHz
3.2 dB up to 44 GHz
High isolation
50 dB up to 18 GHz
39 dB up to 40 GHz
35 dB up to 44 GHz
High input linearity
P0.1dB: 26 dBm typical
IP3: 47 dBm typical
EN
V1
1
2
3
4
5
6
7
19
18
17
16
15
14
13
GND
RF2
50Ω
50Ω
GND
RFC
GND
VSS
LS
GND
GND
GND
RF3
50Ω
50Ω
GND
High power handling
24 dBm through path
24 dBm terminated path
All off state control
Figure 1.
Logic select control
No low frequency spurs
Settling time (0.1 dB final RF output): 30 ns
24-terminal, 3 mm × 3 mm land grid array (LGA) package
Pin compatible with ADRF5043, low frequency cutoff version
APPLICATIONS
Industrial scanners
Test instrumentation
Cellular infrastructure—millimeterwave (mmWave) 5G
Military radios, radars, electronic counter measures (ECMs)
Microwave radios and very small aperture terminals (VSATs)
GENERAL DESCRIPTION
The ADRF5042 is a nonreflective SP4T switch manufactured in
the silicon on insulator (SOI) process.
The ADRF5042 has enable and logic select controls to feature
all off state and port mirroring, respectively.
The ADRF5042 operates from 100 MHz to 44 GHz with an
insertion loss of lower than 3.2 dB and an isolation of higher
than 35 dB. The device has a RF input power handling
capability of 24 dBm for both through and terminated paths.
The ADRF5042 is pin compatible with the ADRF5043 low
frequency cutoff version, which operates from 9 kHz to 44 GHz.
The ADRF5042 comes in a 24-terminal, 3 mm × 3 mm, RoHS
compliant, land grid array (LGA) package and can operate from
−40°C to +105°C.
The ADRF5042 requires a dual-supply voltage of +3.3 V and
−3.3 V. The device employs CMOS- and low voltage transistor
to transistor logic (LVTTL)-compatible controls.
Rev. 0
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Tel: 781.329.4700
Technical Support
©2020 Analog Devices, Inc. All rights reserved.
www.analog.com
ADRF5042
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configuration and Function Descriptions..............................6
Interface Schematics .....................................................................6
Typical Performance Characteristics ..............................................7
Insertion Loss, Return Loss, and Isolation ................................7
Input Power Compression and Third-Order Intercept............9
Theory of Operation ...................................................................... 10
Application Information................................................................ 11
Evaluation Board ........................................................................ 11
Outline Dimensions....................................................................... 12
Ordering Guide .......................................................................... 12
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
Electrostatic Discharge (ESD) Ratings ...................................... 5
Power Derating Curves................................................................ 5
ESD Caution.................................................................................. 5
REVISION HISTORY
7/2020—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
Data Sheet
ADRF5042
SPECIFICATIONS
Positive supply voltage (VDD) = 3.3 V, negative supply voltage (VSS) = −3.3 V, V1 pin voltage (V1) = 0 V or 3.3 V, V2 pin voltage (V2) = 0 V
or 3.3 V, LS = 0 V or 3.3 V, EN = 0 V or 3.3 V, and TCASE = 25°C on a 50 Ω system, unless otherwise noted. RFx refers to RF1 to RF4. VCTL
is the digital control inputs voltage.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
FREQUENCY RANGE
INSERTION LOSS
f
100
44,000
MHz
Between RFC and RFx (On)
100 MHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
40 GHz to 44 GHz
1.8
2.2
2.5
2.8
3.2
dB
dB
dB
dB
dB
ISOLATION
Between RFC and RFx (Off)
100 MHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
40 GHz to 44 GHz
50
46
41
39
35
dB
dB
dB
dB
dB
RETURN LOSS
RFC and RFx (On)
100 MHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
40 GHz to 44 GHz
100 MHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
40 GHz to 44 GHz
16
14
13
13
14
24
22
15
12
10
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
RFx (Off)
SWITCHING
Rise and Fall Time
On and Off Time
Settling Time
tRISE, tFALL
tON, tOFF
10% to 90% of RF output
50% VCTL to 90% of RF output
3
14
ns
ns
0.1 dB
0.05 dB
50% VCTL to 0.1 dB of final RF output
50% VCTL to 0.05 dB of final RF output
30
36
ns
ns
INPUT LINEARITY1
0.1 dB Power Compression
1 dB Power Compression
Third-Order Intercept
P0.1dB
P1dB
IP3
f = 500 MHz to 40 GHz
f = 500 MHz to 40 GHz
Two-tone input power = 15 dBm each tone,
f = 500 MHz to 40 GHz, Δf = 1 MHz
26
27
47
dBm
dBm
dBm
Second-Order Intercept
IP2
Two-tone input power = 15 dBm each tone,
f = 10 GHz, Δf = 1 MHz
120
60
dBm
VIDEO FEEDTHROUGH2
SUPPLY CURRENT
Positive Supply Current
Negative Supply Current
DIGITAL CONTROL INPUTS
Voltage
mV p-p
VDD, VSS pins
IDD
ISS
370
−100
µA
µA
V1, V2, EN, LS pins
Low
High
VINL
VINH
0
1.2
0.8
3.3
V
V
Rev. 0 | Page 3 of 12
ADRF5042
Data Sheet
Parameter
Current
Low
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
IINL
IINH
3
6
µA
µA
High
RECOMMENDED OPERATING
CONDITONS
Supply Voltage
Positive
Negative
Digital Control Inputs Voltage
RFx Input Power3
Through Path
VDD
VSS
VCTL
PIN
3.15
−3.45
0
3.45
−3.15
VDD
V
V
V
f = 500 MHz to 44 GHz, TCASE = 85°C4
Average
Peak
Average
Peak
Average
Peak
24
24
24
24
24
24
+105
dBm
dBm
dBm
dBm
dBm
dBm
°C
Terminated Path
Hot Switching
Case Temperature
TCASE
−40
1 For input linearity performance over frequency, see Figure 18 to Figure 21.
2 Video feedthrough is the spurious dc transient measured at the RF ports in a 50 Ω test setup, without an RF signal present while switching the control voltage.
3 For power derating over frequency, see Figure 2.
4 For 105°C operation, the power handling degrades from the TCASE = 85°C specification by 3 dB.
Rev. 0 | Page 4 of 12
Data Sheet
ADRF5042
ABSOLUTE MAXIMUM RATINGS
For recommended operating conditions, see Table 1.
ELECTROSTATIC DISCHARGE (ESD) RATINGS
The following ESD information is provided for handling of ESD
sensitive devices in an ESD protected area only.
Table 2.
Parameter
Rating
Supply Voltage
Positive
Negative
Digital Control Inputs1
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
−0.3 V to +3.6 V
−3.6 V to +0.3 V
−0.3 V to VDD + 0.3 V or 3.3 mA,
whichever occurs first
ESD Ratings for ADRF5042
Table 4. ADRF5042, 24-Terminal LGA
ESD Model
Withstand Threshold (V)
RFx Input Power (f2 = 500 MHz
to 44 GHz, TCASE = 85°C3)
Through Path
Average
Peak
Terminated Path
Average
Peak
Hot Switching
Average
HBM
RFx Pins
375
Supply and Digital Control Pins
2000
26 dBm
26 dBm
POWER DERATING CURVES
2
25 dBm
25 dBm
0
–2
–4
25 dBm
25 dBm
Peak
–6
Temperature
Junction, TJ
Storage Range
Reflow
–8
135°C
−65°C to +150°C
260°C
–10
–12
–14
–16
–18
1 Overvoltages at digital control inputs are clamped by internal diodes.
Current must be limited to the maximum rating given.
2 For power derating over frequency, see Figure 2.
3 For 105°C operation, the power handling degrades from the TCASE = 85°C
specification by 3 dB.
10k
100k
1M
10M
100M
1G
10G
100G
FREQUENCY (Hz)
Figure 2. Power Derating vs. Frequency, Low Frequency Detail, TCASE = 85°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJC is the junction to case bottom (channel to package bottom)
thermal resistance.
Table 3. Thermal Resistance
Package Type
1
θJC
Unit
CC-24-12
Through Path
Terminated Path
468
200
°C/W
°C/W
1 θJC was determined by simulation under the following conditions: the heat
transfer is due solely to thermal conduction from the channel through the
ground pad to the PCB, and the ground pad is held constant at the
operating temperature of 85°C.
Rev. 0 | Page 5 of 12
ADRF5042
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
19
18
17
16
15
14
13
GND
RF2
EN
V1
GND
GND
GND
RF3
GND
RFC
GND
VSS
LS
ADRF5042
TOP VIEW
(Not to Scale)
GND
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED
TO THE RF AND DC GROUND.
Figure 3. Pin Configuration (Top View)
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
EN
V1
GND
Enable Input. See Table 6 for the truth table. See Figure 5 for the interface schematic.
Control Input 1. See Table 6 for the truth table. See Figure 5 for the interface schematic.
Ground. The GND pins must be connected to the RF and dc ground of the PCB.
3, 5, 9, 11 to 13, 15 to
17, 19 to 21, 23
4
RFC
RF Common Port. RFC is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is required
when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic.
6
7
8
10
VSS
LS
VDD
RF4
Negative Supply Voltage.
Logic Select Input. See Table 6 for the truth table. See Figure 5 for the interface schematic.
Positive Supply Voltage.
RF Throw Port 4. RF4 is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is required
when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic.
14
18
22
24
RF3
RF2
RF1
RF Throw Port 3. RF3 is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is required
when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic.
RF Throw Port 2. RF2 is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is required
when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic.
RF Throw Port 1. RF1 is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is required
when the RF line potential is equal to 0 V dc.
Control Input 2. See Table 6 for the truth table. See Figure 5 for the interface schematic.
Exposed Pad. The exposed pad must be connected to the RF and dc ground.
V2
EPAD
INTERFACE SCHEMATICS
VDD
VDD
RFC,
RF1,
RF2,
RF3,
RF4
V1, V2,
EN, LS
Figure 4. RFC and RF1 to RF4 Pin Interface Schematic
Figure 5. V1, V2, EN, and LS Pin Interface Schematic
Rev. 0 | Page 6 of 12
Data Sheet
ADRF5042
TYPICAL PERFORMANCE CHARACTERISTICS
INSERTION LOSS, RETURN LOSS, AND ISOLATION
VDD = 3 . 3 V, V SS = −3.3 V, VCTL = 0 V or 3.3 V, and TCASE = 25°C on a 50 Ω system, unless otherwise noted. Measured on the evaluation board.
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
RF1
RF2
RF3
RF4
T
T
T
T
= +105°C
= +85°C
= +25°C
= –40°C
CASE
CASE
CASE
CASE
0
5
10
15
20
25
30
35
40
45
50
50
50
0
5
10
15
20
25
30
35
40
45
50
50
50
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 6. Insertion Loss for RFC to RFx On vs. Frequency
Figure 9. Insertion Loss for RFC to RF1 On vs. Frequency
over Various Temperatures
0
–5
0
–5
RF1
RF2
RF3
RF4
RFC
RF1
RF2
RF3
RF4
–10
–15
–20
–25
–30
–35
–40
–45
–50
–10
–15
–20
–25
–30
–35
–40
–45
–50
0
5
10
15
20
25
30
35
40
45
0
5
10
15
20
25
30
35
40
45
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 7. Return Loss for RFC and RFx On vs. Frequency
Figure 10. Return Loss for RFx Off vs. Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
RF2
RF3
RF4
RF1
RF3
RF4
0
5
10
15
20
25
30
35
40
45
0
5
10
15
20
25
30
35
40
45
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 8. Isolation for RFC to RFx Off vs. Frequency, RFC to RF1 Path On
Figure 11. Isolation for RFC to RFx Off vs. Frequency, RFC to RF2 Path On
Rev. 0 | Page 7 of 12
ADRF5042
Data Sheet
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
RF1
RF2
RF3
RF1
RF2
–10
RF4
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 12. Isolation for RFC to RFx Off vs. Frequency, RFC to RF3 Path On
Figure 15. Isolation for RFC to RFx Off vs. Frequency, RFC to RF4 Path On
0
0
RF1 TO RF2
RF1 TO RF2
RF1 TO RF3
RF1 TO RF3
–10
–10
RF1 TO RF4
RF1 TO RF4
RF2 TO RF3
RF2 TO RF3
–20
–20
–30
–40
–50
–60
–70
–80
–90
–100
RF2 TO RF4
RF2 TO RF4
RF3 TO RF4
RF3 TO RF4
–30
–40
–50
–60
–70
–80
–90
–100
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 13. Channel to Channel Isolation vs. Frequency, RFC to RF1 Path On
Figure 16. Channel to Channel Isolation vs. Frequency, RFC to RF2 Path On
0
0
RF1 TO RF2
RF1 TO RF2
RF1 TO RF3
–10
RF1 TO RF3
RF1 TO RF4
RF2 TO RF3
RF2 TO RF4
RF3 TO RF4
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
RF1 TO RF4
RF2 TO RF3
RF2 TO RF4
–20
RF3 TO RF4
–30
–40
–50
–60
–70
–80
–90
–100
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 14. Channel to Channel Isolation vs. Frequency, RFC to RF3 Path On
Figure 17. Channel to Channel Isolation vs. Frequency, RFC to RF4 Path On
Rev. 0 | Page 8 of 12
Data Sheet
ADRF5042
INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT
VDD = 3 . 3 V, V SS = − 3 . 3 V, VCTL = 0 V or 3.3 V, and TCASE = 25°C on a 50 Ω system, unless otherwise noted. Measured on the evaluation board.
30
28
26
24
22
20
18
16
14
12
10
30
28
26
24
22
20
18
16
14
12
10
T
T
T
T
= +105°C
= +85°C
= +25°C
= –40°C
CASE
CASE
CASE
CASE
T
T
T
T
= +105°C
= +85°C
= +25°C
= –40°C
CASE
CASE
CASE
CASE
0
5
10
15
20
25
30
35
40
10k
100k
1M
10M
100M
1G
FREQUENCY (GHz)
FREQUENCY (Hz)
Figure 18. Input P0.1dB vs. Frequency over Various Temperatures
Figure 20. Input P0.1dB vs. Frequency, Low Frequency Detail
over Various Temperatures
60
55
50
45
40
35
30
60
55
50
45
40
35
30
25
20
T
T
T
T
= +105°C
= +85°C
= +25°C
= –40°C
CASE
CASE
CASE
CASE
T
T
T
T
= +105°C
= +85°C
= +25°C
= –40°C
CASE
CASE
CASE
CASE
25
20
0
5
10
15
20
25
30
35
40
10k
100k
1M
10M
100M
1G
FREQUENCY (GHz)
FREQUENCY (Hz)
Figure 19. Input IP3 vs. Frequency over Various Temperatures
Figure 21. Input IP3 vs. Frequency, Low Frequency Detail
over Various Temperatures
Rev. 0 | Page 9 of 12
ADRF5042
Data Sheet
THEORY OF OPERATION
The ADRF5042 requires a positive supply voltage applied to the
VDD pin and a negative supply voltage applied to the VSS pin.
Bypassing capacitors are recommended on the supply lines to
minimize RF coupling.
The insertion loss path conducts the RF signal between the
selected RF throw port and the RF common port. The switch
design is bidirectional with equal power handling capabilities.
The RF input signal can be applied to the RFC port or the
selected RF throw port. The isolation paths provide high loss
between the insertion loss path and the unselected RF throw
ports that are terminated to internal 50 Ω resistors.
All of the RF ports (RFC, RF1 to RF4) are dc-coupled to 0 V,
and no dc blocking is required at the RF ports when the RF line
potential is equal to 0 V. The RF ports are internally matched to
50 Ω. Therefore, external matching networks are not required.
The ideal power-up sequence is as follows:
The ADRF5042 integrates a driver to perform logic functions
internally and to provide the user with the advantage of a
simplified CMOS-/LVTTL-compatible control interface. The
driver features four digital control input pins (EN, LS, V1, and
V2) that control the state of the RFx paths (see Table 6).
1. Connect GND to ground.
2. Power up VDD and VSS. Powering up VSS after VDD
avoids current transients on VDD during ramp up.
3. Apply a control voltage to the digital control inputs (EN,
LS, V1, and V2). Applying a control voltage to the digital
control inputs before the VDD supply can inadvertently
forward bias and damage the internal ESD protection
structures. Use a series 1 kΩ resistor to limit the current
flowing into the control pin in such cases. If the control
pins are not driven to a valid logic state (that is, controller
output is in high impedance state) after VDD is powered
up, it is recommended to use a pull-up or pull-down
resistor.
The logic select input (LS) allows the user to define the control
input logic sequence for the RF path selections. The logic level
applied to the V1 and V2 pins determines which RFx port is in
the insertion loss state while the other three paths are in the
isolation state.
When the EN pin is logic high, all four RFx paths are in
isolation state regardless of the logic state of LS, V1, V2. RFx
ports are terminated to internal 50 Ω resistors, and RFC
becomes reflective.
4. Apply an RF input signal.
The ideal power-down sequence is the reverse order of the
power-up sequence.
Table 6. Control Voltage Truth Table
Digital Control Inputs
RFx Paths
EN
LS
V1
V2
RFC to RF1
RFC to RF2
RFC to RF3
RFC to RF4
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
High
High
High
High
Low
High
Low
High
Low
High
Low
Low
Low
High
High
Low
Insertion loss (on)
Isolation (off)
Isolation (off)
Isolation (off)
Isolation (off)
Isolation (off)
Isolation (off)
Insertion loss (on)
Isolation (off)
Isolation (off)
Insertion loss (on)
Isolation (off)
Isolation (off)
Isolation (off)
Isolation (off)
Insertion loss (on)
Isolation (off)
Isolation (off)
Isolation (off)
Isolation (off)
Insertion loss (on)
Isolation (off)
Isolation (off)
Insertion loss (on)
Isolation (off)
Isolation (off)
Isolation (off)
Isolation (off)
Isolation (off)
Isolation (off)
Insertion loss (on)
Insertion loss (on)
Isolation (off)
Isolation (off)
Isolation (off)
Isolation (off)
Low
High
High
Low or high
High
Low or high
High Low or high
Rev. 0 | Page 10 of 12
Data Sheet
ADRF5042
APPLICATION INFORMATION
All RF traces are routed on the top copper layer, whereas the
inner and bottom layers are grounded planes that provide a
solid ground for the RF transmission lines. The top dielectric
material is 8 mil Rogers RO4003, offering optimal high
frequency performance. The middle and bottom dielectric
materials provide mechanical strength. The total board
thickness is 62 mil, which allows 2.4 mm RF launchers to be
connected at the board edges.
EVALUATION BOARD
All measurements in this data sheet are measured on the
ADRF5042-EVALZ evaluation board. Figure 24 shows the
simplified application circuit for ADRF5042-EVALZ evaluation
board. See the ADRF5042-EVALZ user guide for more
information on using the evaluation board.
The design of the ADRF5042-EVALZ board serves as a layout
recommendation. The Gerber files of the ADRF5042-EVALZ
evaluation board are available at www.analog.com/EVAL-
ADRF5042.
The RF transmission lines were designed using a coplanar
waveguide (CPWG) model, with a trace width of 14 mil and a
ground clearance of 7 mil to have a characteristic impedance of
50 Ω. The RF transmission lines are tapered at the RFC or RFx
pin transition, as shown in Figure 23. For optimal RF and
thermal grounding, arrange as many plated through vias as
possible around the transmission lines and under the exposed
pad of the package.
The ADRF5042-EVALZ is a 4-layer evaluation board. The outer
copper (Cu) layers are 0.5 oz (0.7 mil) plated to 1.5 oz (2.2 mil)
and are separated by dielectric materials. Figure 22 shows the
cross sectional view of the evaluation board stackup.
G = 7mil
W = 14mil
1.5oz Cu (2.2mil)
1.5oz Cu (2.2mil)
1.5oz Cu (2.2mil)
T = 2.2mil
H = 8mil
RO4003
0.5oz Cu (0.7mil)
0.5oz Cu (0.7mil)
1.5oz Cu (2.2mil)
Figure 22. Evaluation Board Stackup, Cross Sectional View
Figure 23. RF Trasmission Lines
CMOS/
LVTTL
EN
V1
1
2
3
4
5
6
7
19
50Ω
RF2
18
17
16
15
14
13
CMOS/
LVTTL
50Ω
ADRF5042
RFC
TOP VIEW
(Not to Scale)
–3.3V
50Ω
VSS
LS
RF3
100pF
CMOS/
LVTTL
100pF
Figure 24. Application Circuit
Rev. 0 | Page 11 of 12
ADRF5042
Data Sheet
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
1.60
REF
PIN 1
INDICATOR
AREA
0.40
BSC
PIN 1
INDICATOR
(C0.225 ×0.45°)
19
1
20
24
18
1.50 BSC
SQ
2.40
REF
EXPOSED
PAD
6
7
13
12
0.250
0.200
0.150
TOP VIEW
BOTTOM VIEW
0.125 REF
0.125 REF
0.325
0.275
0.225
0.808
0.738
0.668
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.530 REF
SIDE VIEW
SECTION OF THIS DATA SHEET.
0.248
0.208
0.168
SEATING
PLANE
Figure 25. 24-Terminal Land Grid Array [LGA]
3 mm × 3 mm Body and 0.738 mm Package Height
(CC-24-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +105°C
−40°C to +105°C
Package Description
Package Option
CC-24-12
CC-24-12
Marking Code
ADRF5042BCCZN
ADRF5042BCCZN-R7
ADRF5042-EVALZ
24-Terminal Land Grid Array [LGA]
24-Terminal Land Grid Array [LGA]
Evaluation Board
042
042
1 Z = RoHS Compliant Part.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D23793-7/20(0)
Rev. 0 | Page 12 of 12
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