ADRF5019-EVALZ [ADI]
Silicon, SPDT Switch, Nonreflective, 100 MHz to 13 GHz;
| 型号： | ADRF5019-EVALZ |
| 厂家： | 
ADI |
| 描述： | Silicon, SPDT Switch, Nonreflective, 100 MHz to 13 GHz 光电二极管 |
| 文件： | 总12页 (文件大小：338K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Silicon, SPDT Switch, Nonreflective,
100 MHz to 13 GHz
Data Sheet
ADRF5019
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Nonreflective 50 Ω design
Low insertion loss: 0.8 dB at 8 GHz
High isolation: 45 dB at 8 GHz
High input linearity
GND
GND
RFC
GND
1
2
3
4
12
V
DD
P1dB: 39 dBm
IP3: 60 dBm typical
High power handling
35 dBm insertion loss path
27 dBm hot switching
ESD rating: 2 kV (Class 2) HBM
No low frequency spurious
0.05 dB RF settling time: 375 ns
0.1 dB RF settling time: 300 ns
16-lead, 3 mm × 3 mm LFCSP
Pin-compatible with HMC1118, low frequency cutoff version
50Ω
50Ω
ADRF5019
11 LS
10
9
V
V
CTRL
SS
PACKAGE
BASE
GND
Figure 1.
APPLICATIONS
Test instrumentation
Microwave radios and very small aperture terminals (VSATs)
Military radios, radars, and electronic counter measures (ECMs)
Fiber optics and broadband telecommunications
GENERAL DESCRIPTION
The ADRF5019 is a nonreflective, single pole, double throw
(SPDT) RF switch manufactured in a silicon process.
The ADRF5019 can also operate with a single positive supply
voltage (VDD) applied. The negative supply voltage (VSS) is tied
to ground. Even in single-supply operation mode, the ADRF5019
can cover the 100 MHz to 13 GHz operating frequency and
maintain good power handling performance. See the
Applications Information section for more details.
The ADRF5019 operates from 100 MHz to 13 GHz with better
than 0.8 dB insertion loss and 45 dB of isolation at 8 GHz. The
ADRF5019 has a nonreflective design, and the RF ports are
internally terminated to 50 Ω.
The ADRF5019 is pin-compatible with the HMC1118, the low
frequency cutoff version, which operates from 9 kHz to 13.0 GHz.
The ADRF5019 switch requires a dual supply voltage of +3.3 V
and −2.5 V and positive control voltage inputs. This switch
employs complementary metal-oxide semiconductor (CMOS)-
compatible and low voltage transistor transistor logic (LVTTL)-
compatible controls.
The ADRF5019 comes in a 16-lead, lead frame chip scale
package (LFCSP) and operates from −40°C to +105°C.
Rev. 0
Document Feedback
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Tel: 781.329.4700
©2019 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADRF5019
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characterics ..................................................7
Insertion Loss, Return Loss, and Isolation ................................7
Input Compression and Input Third-Order Intercept .............8
Theory of Operation ...................................................................... 10
RF Input and Output ................................................................. 10
Power Supply............................................................................... 10
Applications Information.............................................................. 11
Layout Considerations............................................................... 11
Board Layout............................................................................... 11
RF and Digital Controls ............................................................ 11
Outline Dimensions....................................................................... 12
Ordering Guide .......................................................................... 12
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Specifications............................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
Power Derating Curves................................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Interface Schematics..................................................................... 6
REVISION HISTORY
8/2019—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
Data Sheet
ADRF5019
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VDD = 3.3 V, VSS = −2.5 V, LS = 3.3 V, VCTRL = 0 V or 3.3 V, and TCASE = 25°C in a 50 Ω system, unless otherwise noted.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
FREQUENCY RANGE
f
100
13,000
MHz
INSERTION LOSS
IL
Between RFC and RF1 or RFC and RF2 (On)
100 MHz to 3 GHz
100 MHz to 8 GHz
100 MHz to 10 GHz
100 MHz to 13 GHz
0.6
0.8
1.0
1.5
dB
dB
dB
dB
RETURN LOSS
RL
Between RFC and RF1 or RFC and RF2 (On)
100 MHz to 3 GHz
100 MHz to 8 GHz
100 MHz to 13 GHz
100 MHz to 3 GHz
100 MHz to 8 GHz
100 MHz to 13 GHz
26
22
9
26
14
5
dB
dB
dB
dB
dB
dB
RF1 or RF2 (Off)
ISOLATION
Between RFC and RF1 or RCF and RF2 (Off)
100 MHz to 3 GHz
100 MHz to 8 GHz
100 MHz to 10 GHz
100 MHz to 13 GHz
50
45
35
25
dB
dB
dB
dB
SWITCHING CHARACTERISTICS
Dual Supply
VDD = 3.3 V, VSS = −2.5 V
10% to 90% of RF output
50% of triggered digital control input voltage
(VCTL) to 90% of RF output
Rise Time and Fall Time
On Time and Off Time
tRISE, tFALL
tON, tOFF
35
150
ns
ns
RF Settling Time
0.1 dB
0.05 dB
50% of triggered VCTL to 0.1 dB of final RF output
50% of triggered VCTL to 0.05 dB of final RF output
VDD = 3.3 V, VSS = 0 V
300
375
ns
ns
Single Supply
Rise Time and Fall Time
On Time and Off Time
INPUT LINEARITY1
Dual Supply
tRISE, tFALL
tON, tOFF
10% to 90% of RF output
50% of triggered VCTL to 90% of RF output
100 MHz to 13 GHz
180
285
ns
ns
VDD = 3.3 V, VSS = −2.5 V
Input Compression
0.1 dB
1 dB
P0.1dB
P1dB
38
39
dBm
dBm
Intermodulation Distortion
Input Third-Order Intercept
IIP3
Two tone input power = 12 dBm each tone,
Δf = 1 MHz
60
dBm
Single Supply
VDD = 3.3 V, VSS = 0 V
Input Compression
0.1 dB
1 dB
P0.1dB
P1dB
25
28
dBm
dBm
Intermodulation Distortion
Input Third-Order Intercept
IIP3
Two tone input power = 12 dBm each tone,
Δf = 1 MHz
55
dBm
SUPPLY CURRENT
VDD pin and VSS pin
Positive Supply Current
Negative Supply Current
IDD
ISS
20
0.5
µA
µA
Rev. 0 | Page 3 of 12
ADRF5019
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
DIGITAL CONTROL INPUTS
VCTRL pin and LS pin
Voltage
Low
High
VINL
VINH
0
2
0.8
3.3
V
V
Current
Low and High Current
RECOMMENDED OPERATING CONDITONS
Supply Voltage
IINL, IINH
<1
µA
Positive
Negative
Digital Control Input Voltage
RF Input Power, Dual Supply2
Insertion Loss Path
VDD
VSS
VCTL
PIN
3.0
−2.75
0
3.6
−2.25
VDD
V
V
V
VDD = 3.3 V, VSS = −2.5 V, f = 2 GHz, TCASE = 85°C3
RF signal is applied to RFC or through
connected RF1 or RF2
35
dBm
Isolation Path
Hot Switching
RF signal is applied to the terminated RF1 or RF2
27
27
dBm
dBm
RF signal is present at RFC while switching
between RF1 and RF2
VDD = 3.3 V, VSS = 0 V, f = 2 GHz, TCASE = 85°C3
RF signal is applied to RFC or through
connected RF1 or RF2
RF Input Power, Single Supply2
Insertion Loss Path
PIN
27
dBm
Isolation Path
Hot Switching
RF signal is applied to the terminated RF1 or RF2
RF signal is present at RFC while switching
between RF1 and RF2
22
22
dBm
dBm
Case Temperature
TCASE
−40
+105
°C
1 For input linearity performance vs. frequency, see Figure 13 to Figure 20.
2 For power derating vs. frequency, see Figure 2 and Figure 3. Power derating is applicable for insertion loss path, terminated path, and hot switching power
specifications.
3 For operation at 105°C, the power handling degrades from the TCASE = 85°C specification by 3 dB.
Rev. 0 | Page 4 of 12
Data Sheet
ADRF5019
ABSOLUTE MAXIMUM RATINGS
Table 2.
POWER DERATING CURVES
5
Parameter
Rating
Positive Supply Voltage
Negative Supply Voltage
Digital Control Inputs
Voltage
−0.3 V to +3.7 V
−2.8 V to +0.3 V
0
–5
−0.3 V to VDD + 0.3 V
3 mA
Current
RF Input Power, Dual Supply1 (VDD = 3.3 V,
–10
–15
–20
–25
V
SS = −2.5 V, f = 2 GHz at TCASE = 85°C2)
Insertion Loss Path
Isolation Path
Hot Switching
37 dBm
28 dBm
30 dBm
TERMINATED
HOT SWITCHING
THROUGH
RF Input Power, Dual Supply1 (VDD = 3.3 V,
VSS = 0 V, f = 2 GHz at TCASE = 85°C2)
0.01
0.1
1
10
100
1000
10000
Insertion Loss Path
Isolation Path
Hot Switching
RF Input Power Under Unbiased
Condition (VDD, VSS = 0 V)
Temperature
28 dBm
23 dBm
23 dBm
23 dBm
FREQUENCY (MHz)
Figure 2. Power Derating vs. Frequency, Low Frequency Detail,
CASE = 85°C
T
5
Junction, TJ
Storage Range
Reflow
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM)
135°C
−65°C to +150°C
260°C
0
–5
2 kV (Class 2)
–10
–15
–20
–25
1 For power derating vs. frequency, see Figure 2 and Figure 3. Power derating
is applicable for insertion loss path, terminated path, and hot switching power
specifications.
2 For operation at 105°C, the power handling degrades from the TCASE = 85°C
specification by 3 dB.
TERMINATED
HOT SWITCHING
THROUGH
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
0
1
2
3
4
4
6
7
8
9
10 11 12 13
FREQUENCY (GHz)
Figure 3. Power Derating vs. Frequency, High Frequency Detail,
CASE = 85°C
T
ESD CAUTION
THERMAL RESISTANCE
Thermal resistance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJC is the junction to case bottom (channel to package bottom)
thermal resistance.
Table 3. Thermal Resistance
Package Type
θJC
Unit
CP-16-38
Through Path
Terminated Path
106
100
°C/W
°C/W
Rev. 0 | Page 5 of 12
ADRF5019
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADRF5019
GND
GND
RFC
GND
1
2
3
4
12
V
DD
11 LS
TOP VIEW
(Not to Scale)
10
9
V
V
CTRL
SS
NOTES
1. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO THE RF AND DC GROUND
OF THE PCB.
Figure 4. Pin Configuration (Top View)
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Description
1, 2, 4 to 6, 8, 13, 15, 16 GND
Ground. These pins must be connected to the RF and dc ground of the PCB.
3
RFC
RF Common Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is
required when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic.
7
RF2
RF Throw Port 2. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is
required when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic.
9
VSS
Negative Supply Voltage Pin. See Figure 8 for the interface schematic.
10
11
12
14
VCTRL
LS
VDD
RF1
Control Input Pin. See Figure 6 for interface schematic. See Table 5 for the truth table.
Logic Select Input Pin. See Figure 6 for the interface schematic. See Table 5 for the truth table.
Positive Supply Voltage Pin. See Figure 7 for the interface schematic.
RF Throw Port 1. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is
required when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic.
EPAD
Exposed Pad. The exposed pad must be connected to the RF and dc ground of the PCB.
INTERFACE SCHEMATICS
V
DD
RFC, RF1, RF2
CLAMP
GND
GND
Figure 7. VDD Pin Interface Schematic
Figure 5. RFC, RF1, and RF2 Pin Interface Schematic
V
SS
V
DD
V
DD
CLAMP
V
, LS
CTRL
GND
GND
Figure 6. Digital Pins Interface Schematic
Figure 8. VSS Pin Interface Schematic
Rev. 0 | Page 6 of 12
Data Sheet
ADRF5019
TYPICAL PERFORMANCE CHARACTERICS
INSERTION LOSS, RETURN LOSS, AND ISOLATION
VDD = 3.3 V, V SS = −2.5 V, VCTRL and LS = 0 V or VDD, and TCASE = 25°C in a 50 Ω system, unless otherwise noted.
0
0
–10
–20
–30
–40
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–50
–60
–70
T
T
T
T
= +105°C
= +85°C
= +25°C
= –40°C
–80
CASE
CASE
CASE
CASE
RFC TO RF1
RFC TO RF2
–90
–100
0
3
6
9
12
15
0
3
6
9
12
15
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 9. Insertion Loss vs. Frequency over Temperature
Figure 11. Isolation Between RFC and RFx Ports vs. Frequency
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–5
–10
–15
–20
–25
–30
–35
RF1, RF2 ON
RF1, RF2 OFF
RFC
RF1 ON
RF2 ON
–90
–100
0
3
6
9
12
15
0
3
6
9
12
15
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 12. Isolation Between RF1 and RF2 Ports vs. Frequency
Figure 10. Return Loss vs. Frequency
Rev. 0 | Page 7 of 12
ADRF5019
Data Sheet
INPUT COMPRESSION AND INPUT THIRD-ORDER INTERCEPT
VDD = 3.3 V, VCTRL and LS = 0 V or VDD, and TCASE = 25°C in a 50 Ω system, unless otherwise noted. All of the large signal performance
parameters are measured on the ADRF5019-EVALZ evaluation board.
40
40
35
30
25
35
30
25
20
15
10
20
15
10
0.1dB COMPRESSION POINT
1dB COMPRESSION POINT
0.1dB COMPRESSION POINT
1dB COMPRESSION POINT
0
1
2
3
4
5
6
7
8
9
10 11 12 13
0
1
2
3
4
5
6
7
8
9
10 11 12 13
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 13. P0.1dB and P1dB Input Compression vs. Frequency, VSS = −2.5 V
Figure 16. P0.1dB and P1dB Input Compression vs. Frequency, VSS = 0 V
40
35
30
25
40
35
30
25
20
15
20
15
0.1dB COMPRESSION POINT
1dB COMPRESSION POINT
0.1dB COMPRESSION POINT
1dB COMPRESSION POINT
10
0.01
10
0.01
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 17. P0.1dB and P1dB Input Compression vs. Frequency (Low
Frequency Detail), VSS = 0 V
Figure 14. P0.1dB and P1dB Input Compression vs. Frequency (Low
Frequency Detail), VSS = −2.5 V
40
40
35
30
25
20
35
30
25
20
T
T
T
T
= +105°C
= +85°C
= +25°C
= –40°C
T
T
T
T
= +105°C
= +85°C
= +25°C
= –40°C
CASE
CASE
CASE
CASE
CASE
CASE
CASE
CASE
15
10
15
10
0
1
2
3
4
5
6
7
8
9
10 11 12 13
0
1
2
3
4
5
6
7
8
9
10 11 12 13
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 18. P1dB Input Compression Point vs. Frequency over Temperature
(Low Frequency Detail), VSS = 0 V
Figure 15. P1dB Input Compression Point vs. Frequency over Temperature,
SS = −2.5 V
V
Rev. 0 | Page 8 of 12
Data Sheet
ADRF5019
70
70
65
60
55
50
45
40
35
30
65
60
55
50
45
40
35
30
T
T
T
= +105°C
= +25°C
= –40°C
T
T
T
= +105°C
= +25°C
= –40°C
CASE
CASE
CASE
CASE
CASE
CASE
25
20
25
20
0
1
2
3
4
5
6
7
8
9
10 11 12 13
0
1
2
3
4
5
6
7
8
9
10 11 12 13
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 19. Input IP3 vs. Frequency over Temperature, VSS = −2.5 V
Figure 21. Input IP3 vs. Frequency over Temperature, VSS = 0 V
70
70
65
60
55
50
65
60
55
50
45
40
35
30
45
40
35
30
T
T
T
= +105°C
= +25°C
= –40°C
T
T
T
= +105°C
= +25°C
= –40°C
CASE
CASE
CASE
CASE
CASE
CASE
25
20
25
20
0.01
0.1
1
10
100
1000
0.01
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 20. Input IP3 vs. Frequency over Temperature (Low Frequency Detail),
SS = −2.5 V
Figure 22. Input IP3 vs. Frequency over Temperature (Low Frequency Detail),
SS = 0 V
V
V
Rev. 0 | Page 9 of 12
ADRF5019
Data Sheet
THEORY OF OPERATION
The ADRF5019 integrates a driver to perform logic functions
internally and to provide the user with the advantage of a
simplified positive voltage control interface. The driver features
two digital control input pins (VCTRL and LS) that control the
state of the RF paths, determining which RF port is in the
insertion loss state and which path is in the isolation state (see
Table 5).
POWER SUPPLY
The ADRF5019 requires a positive supply voltage applied to the
DD pin and a negative supply voltage applied to the VSS pin.
V
Bypassing capacitors are recommended on the supply lines to
filter high frequency noise.
The ideal power-up sequence is as follows:
1. Connect to GND.
RF INPUT AND OUTPUT
2. Power up the VDD and VSS voltages. Power up VSS after VDD
to avoid current transients on VDD during ramp up.
3. Power up the digital control inputs. The order of the digital
control inputs is not important. However, powering the
digital control inputs before the VDD voltage supply can
inadvertantly forward bias and damage the internal ESD
protection structures. To avoid this damage, use a series
1 kΩ resistor to limit the current flowing into the control
pin. Use pull-up or pull-down resistors if the controller
output is in a high impedance state after the VDD voltage is
powered up and the control pins are not driven to a valid
logic state.
The RF ports (RFC, RF1, and RF2) are dc-coupled to 0 V, and
no dc blocking is required at the RF ports when the RF line
potential is equal to 0 V.
The RF ports are internally matched to 50 Ω. Therefore,
external matching networks are not required.
The ADRF5019 is bidirectional with equal power handling
capabilities. An RF input signal (RFIN) can be applied to the
RFC port or to the RF1 port or the RF2 port.
The insertion loss path conducts the RF signal between the
selected RF throw port and the RF common port. The isolation
path provides high loss between the insertion loss path and the
unselected RF throw port, which is nonreflective, by using an
internal 50 Ω termination resistor.
4. Apply an RF input signal to RFC, RF1, or RF2.
The ideal power-down sequence is the reverse order of the
power-up sequence.
Single-Supply Operation
The ADRF5019 can operate with a single positive supply voltage
applied to the VDD pin and VSS pin connected to ground.
However, some performance degradations can occur in the
input compression and input third-order intercept.
Table 5. Control Voltage Truth Table
Digital Control Inputs
RF Paths
LS
VCTRL
Low
High
Low
RF1 to RFC
RF2 to RFC
High
High
Low
Low
Insertion loss (on)
Isolation (off)
Isolation (off)
Isolation (off)
Insertion loss (on)
Insertion loss (on)
Isolation (off)
High
Insertion loss (on)
Rev. 0 | Page 10 of 12
Data Sheet
ADRF5019
APPLICATIONS INFORMATION
LAYOUT CONSIDERATIONS
RF AND DIGITAL CONTROLS
All measurements in this data sheet are measured on the
ADRF5019-EVALZ evaluation board. The design of the
ADRF5019-EVALZ board serves as a layout recommendation
for ADRF5019 application.
The RF transmission lines use a coplanar waveguide (CPWG)
model with a width of 18 mil and a ground spacing (G) of 13 mil
and have a characteristic impedance of 50 Ω. For optimal RF
and thermal grounding, as many plated through vias as possible
are arranged around the transmission lines and under the
exposed pad of the package.
See the ADRF5019-EVALZ user guide for more information on
using the evaluation board.
The RF input and output ports (RFC, RF1, and RF2) are
connected through 50 Ω transmission lines to the SMA
launchers. On the VDD and VSS supply traces, a 100 pF bypass
capacitor filters high frequency noise.
BOARD LAYOUT
The ADRF5019-EVALZ is a 4-layer board. The outer copper
(Cu) layers are 0.7 mil to 2.2 mil plated and are separated by
dielectric materials. Figure 23 shows the ADRF5019-EVALZ
board stack up.
Figure 24 shows the simplified application circuit for the
ADRF5019.
The board layout and stackup shown in Figure 23 are used to
make the measurements included in this data sheet.
RF1
G = 13mil
W = 18mil
V
DD
100pF
1.5oz Cu (2.2mil)
1.5oz Cu (2.2mil)
RO4350
1.5oz Cu (2.2mil)
T = 2.2mil
H = 10mil
1
2
3
4
12
11
10
9
GND
GND
RFC
GND
V
DD
0.5oz Cu (0.7mil)
LS
LS
ADRF5019
U1
V
RFC
V
CTRL
CTRL
V
V
SS
SS
100pF
GND
0.5oz Cu (0.7mil)
1.5oz Cu (2.2mil)
RF2
Figure 24. Simplified Application Circuit
Figure 23. ADRF5019-EVALZ Stack Up
All RF and dc traces are routed on the top copper layer. The
inner and bottom layers are ground planes that provide a solid
ground for the RF transmission lines. The top dielectric material
(H) is 10 mil Rogers RO4350, which allows optimal RF
performance. The middle and bottom dielectric layers provide
mechanical strength. The overall evaluation board thickness is
approximately 62 mil, which allows Subminiature Version A
(SMA) connectors to be connected at the board edges.
Rev. 0 | Page 11 of 12
ADRF5019
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
3.10
3.00 SQ
2.90
0.30
0.25
0.20
PIN 1
INDICATOR
AREA
PIN 1
IONS
INDICATOR AR EA OP T
(SEE DETAIL A)
13
16
0.50
BSC
12
1
EXPOSED
PAD
1.92
1.70 SQ
1.48
9
4
5
8
*
0.35
0.30
0.25
0.20 MIN
BOTTOM VIEW
TOP VIEW
SIDE VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.95
0.85
0.75
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
*
COMPLIANT WITH JEDEC STANDARDS MO-220-VEED-4
WITH THE EXCEPTION OF PACKAGE EDGE TO LEAD EDGE.
Figure 25. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.85 mm Package Height
(CP-16-38)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADRF5019BCPZN
ADRF5019BCPZN-R7
ADRF5019-EVALZ
Temperature Range
−40°C to +105°C
−40°C to +105°C
Package Description
Package Option Marking Code
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
CP-16-38
CP-16-38
S4Z
S4Z
1 Z = RoHS Compliant Part.
©2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D21247-0-8/19(0)
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