ADP5056ACCZ-R7 [ADI]
Triple Buck Regulator Integrated Power Solution;型号: | ADP5056ACCZ-R7 |
厂家: | ADI |
描述: | Triple Buck Regulator Integrated Power Solution |
文件: | 总31页 (文件大小:962K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Triple Buck Regulator
Integrated Power Solution
Data Sheet
ADP5056
FEATURES
TYPICAL APPLICATION CIRCUIT
Wide input voltage range: 2.75 V to 18 V
Bias input voltage range: 4.5 V to 18 V
RT
VBIAS
(V
= 4.5V
TO 18.0V)
BIAS
INT
REG
OSC
VREG
C1
V
SYNC/MODE
Operation up to 150°C junction temperature
−0.62% to +0.69% feedback voltage accuracy (−40°C to +125°C
junction temperature)
Channel 1 and Channel 2: 7 A synchronous buck regulator
(9.4 A minimum valley current limit)
Channel 1 and Channel 2: 14 A output in parallel operation
Channel 3: 3 A synchronous buck regulator (4.2 A minimum
valley current limit)
RAMP1
2.75V
TO 18.0V
BST1
C3
SW1
PVIN1
C2
L1
VOUT1
C4
CHANNEL 1
7A BUCK
FB1
COMP1
PGND
EN1
RAMP2
250 kHz to 2500 kHz adjustable switching frequency
External compensation for fast load transient response
Precision enable pin with 0.615 V accurate reference voltage
Programmable power-up and power-down sequence
Selective FPWM/PSM mode selection
BST2
PVIN2
C5
C6
L2
VOUT2
C7
SW2
FB2
CHANNEL 2
7A BUCK
COMP2
PGND
EN2
RAMP3
Frequency synchronization input or output
Power-good flag for three channels
Active output discharge switch
BST3
PVIN3
C8
C9
L3
VOUT3
C10
SW3
FB3
CHANNEL 3
3A BUCK
UVLO, overcurrent protection, and TSD protection
43-terminal, 5 mm × 5.5 mm LGA package
COMP3
PGND
EN3
APPLICATIONS
GND
GND
PWRGD
CFG1
LOGIC
Small cell base stations
Field programmable gate array (FPGA) and processor
applications
CFG2
GND
Security and surveillance
Medical applications
Figure 1.
GENERAL DESCRIPTION
The ADP5056 combines three high performance buck regulators
in a 43-terminal land grid array (LGA) package that meets the
demanding performance and board space requirements. The
device enables direct connection to high input voltages up to
18 V with no preregulators.
The switching frequency of the ADP5056 can be programmed
or synchronized to an external clock. The ADP5056 contains an
enable pin (ENx) on each channel for easy power-up sequencing
or adjustable undervoltage lockout (UVLO) threshold.
The ADP5056 integrates start-up/shutdown sequence control,
forced pulse-width modulation/power saving mode (FPWM/PSM)
selection, an output discharge switch, and a power-good signal.
All channels integrate both high-side and low-side power metal-
oxide semiconductor field effect transistors (MOSFETs) to achieve
an efficiency optimized solution. Channel 1 and Channel 2
deliver a programmable output current of 3.5 A or 7 A, or
provide a single output with up to 14 A of current in parallel
operation. Channel 3 delivers a programmable output current
of 1.5 A or 3 A.
The ADP5056 is rated at −40°C to +150°C junction temperature.
Note that throughout this data sheet, multifunction pins, such
as SYNC/MODE, are referred to either by the entire pin name
or by a single function of the pin, for example, SYNC, when
only that function is relevant.
Rev. 0
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Tel: 781.329.4700
Technical Support
©2020 Analog Devices, Inc. All rights reserved.
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ADP5056
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
UVLO........................................................................................... 20
Power-Good Function............................................................... 20
Power-Up at High Temperature ............................................... 20
Thermal Shutdown .................................................................... 20
Applications Information.............................................................. 21
Programming the Adjustable Output Voltage........................ 21
Voltage Conversion Limitations............................................... 21
Current-Limit Setting................................................................ 21
Soft Start Setting......................................................................... 21
Inductor Selection ...................................................................... 21
Output Capacitor Selection....................................................... 22
Input Capacitor Selection.......................................................... 22
Programming the UVLO Input................................................ 23
Slope Compensation Setting..................................................... 23
Compensation Components Design ....................................... 23
Power Dissipation....................................................................... 24
Junction Temperature................................................................ 24
Typical Application Circuits ..................................................... 25
Design Example.............................................................................. 28
Setting the Switching Frequency.............................................. 28
Setting the Output Voltage........................................................ 28
Setting the Configurations (CFG1 and CFG2) .......................... 28
Selecting the Inductor................................................................ 28
Selecting the Output Capacitor ................................................ 29
Designing the Compensation Network................................... 29
Selecting the Input Capacitor ................................................... 29
Circuit Board Layout Recommendations ................................... 30
Outline Dimensions....................................................................... 31
Ordering Guide .......................................................................... 31
Applications....................................................................................... 1
Typical Application Circuit ............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Buck Regulator Specifications .................................................... 5
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 14
Buck Regulator Operational Modes......................................... 14
Adjustable Output Voltages....................................................... 14
Internal Regulators (VREG) ..................................................... 14
Separate Supply Applications.................................................... 14
Bootstrap Circuitry .................................................................... 15
Active Output Discharge Switch .............................................. 15
Precision Enabling...................................................................... 15
Sequence Mode........................................................................... 15
Oscillator ..................................................................................... 16
Synchronization Input/Output ................................................. 16
Soft Start ...................................................................................... 17
Function Configurations (CFG1 and CFG2) ......................... 17
Parallel Operation....................................................................... 18
Fast Transient Mode................................................................... 19
Startup with Precharged Output .............................................. 19
Current-Limit Protection .......................................................... 19
REVISION HISTORY
5/2020—Revision 0: Initial Version
Rev. 0 | Page 2 of 31
Data Sheet
ADP5056
FUNCTIONAL BLOCK DIAGRAM
CLK1
VBIAS
POWER-ON
RESET
V
RT
REG
INTERNAL
REGULATOR
(POR, UVLO)
CLK2
VREG
GND
GND
GND
OSCILLATOR
CLK3
SYNC/MODE
HOUSEKEEPING
LOGIC
CFG1
DIGITAL
DECODER
CFG2
PWRGD
CHANNEL 1 – BUCK
PVIN1
UVLO1
–
+
0.615V
EN1
100nF
25V
V
REG
0.9µA
2.6µA
BST1
SW1
ICS
Q1
HICCUP
+
–
AND
DRIVER
LATCH-UP
OCP
½ × PVIN1
RAMP1
COMP1
SLOPE COMP
+
V
REG
CMP1
–
Q2
CONTROL LOGIC
AND MOSFET
DRIVER WITH
ANTICROSS
V
DRIVER
REF
+
EA1
–
CLK1
PROTECTION
FB1
PGND
ZERO
CROSS
–
107% × V
REF
+
+
*
–
+
ICS
A
CS1
93% × V
REF
–
PVIN2
CHANNEL 2 – BUCK
EN2
RAMP2
COMP2
FB2
100nF
25V
DUPLICATE CHANNEL 1
BST2
SW2
PGND
PVIN3
BST3
SW3
EN3
RAMP3
COMP3
FB3
CHANNEL 3 – BUCK
DUPLICATE CHANNEL 1
PGND
*
A
IS THE CURRENT SENSING AMPLIFIER OF CHANNEL 1.
CS1
Figure 2.
Rev. 0 | Page 3 of 31
ADP5056
Data Sheet
SPECIFICATIONS
Input voltage (VIN) = bias input voltage (VBIAS) = 12 V, VREG voltage (VREG) = 4.8 V, TJ = −40°C to +150°C for minimum and maximum
specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 1.
Parameter
Symbol
VIN
Min
2.75
4.5
Typ
Max
18
Unit
V
Test Conditions/Comments
PVIN1 pin, PVIN2 pin, PVIN3 pin
VBIAS pin
WIDE INPUT VOLTAGE RANGE
BIAS INPUT VOLTAGE RANGE
QUIESCENT CURRENT
Operating Quiescent Current
Shutdown Current of Three Channels
UNDERVOLTAGE LOCKOUT
Power Input
Rising Threshold
Falling Threshold
Hysteresis
Bias Input Voltage
VBIAS
18
V
VBIAS pin
No switching, all ENx pins high
All ENx pins low
IQ(3-BUCKS)
ISHDN(3-BUCKS)
6.2
42
7.5
80
mA
µA
UVLOPVINx
VUVLO1-RISING
VUVLO1-FALLING
VHYS1
UVLOVBIAS
VUVLO2-RISING
VUVLO2-FALLING
VHYS2
PVIN1 pin, PVIN2 pin, PVIN3 pin
2.5
2.22
0.30
2.75
4.50
V
V
V
VBIAS pin
Rising Threshold
Falling Threshold
Hysteresis
4.20
3.80
0.40
V
V
V
3.60
OSCILLATOR CIRCUIT
Switching Frequency
fSW
530
600
1200
1800
630
kHz
kHz
kHz
kHz
RT = 280 kΩ
RT = 140 kΩ
RT = 94.2 kΩ
1140
1700
250
1250
1900
2500
Switching Frequency Range
Synchronization Input
Input Clock Range
Input Clock Pulse Width
Minimum On Time
fSYNC
250
2700
1.2
kHz
tSYNC_MIN_ON
tSYNC_MIN_OFF
VH(SYNC)
100
100
2.65
ns
ns
V
Minimum Off Time
Input Clock High Voltage
Input Clock Low Voltage
Synchronization Output
Clock Frequency
Positive Pulse Duty Cycle
Rise or Fall Time
VL(SYNC)
V
fCLK
fSW
50
2
kHz
%
ns
V
tCLK_PULSE_DUTY
tCLK_RISE_FALL
VH(SYNC_OUT)
High Level Voltage
VREG
PRECISION ENABLING
Enable Voltage Range
High Level Threshold
Low Level Threshold
Source Current (High Level)
Source Current (Low Level)
POWER GOOD
EN1 pin, EN2 pin, EN3 pin
VEN_RANGE
VTH_H(EN)
VTH_L(EN)
ITH_H(EN)
ITH_L(EN)
0
18
0.67
V
V
V
µA
µA
0.615
0.575
0.9
0.52
0.48
2.0
1.55
6.0
Above the rising threshold
Below the falling threshold
3.5
Rising High Threshold
Rising Low Threshold
Falling High Threshold
Falling Low Threshold
Internal Power-Good Hysteresis
Falling Delay for PWRGD Pin
VPWRGD(RISE_H)
VPWRGD(RISE_L)
VPWRGD(FALL_H)
VPWRGD(FALL_L)
VPWRGD(HYS)
105
95
107
93
%
%
%
%
%
ms
2
tPWRGD_FALL_DLY
4 × switching
period (tSW)
0 or tSET
Rising Delay for PWRGD Pin1
tPWRGD_RISE_DLY
ms
tSET = 2.6 ms when the resistor
value on the CFG2 pin (RCFG2) = 0 Ω
Rev. 0 | Page 4 of 31
Data Sheet
ADP5056
Parameter
Symbol
Min
Typ
0.1
10
Max
1
150
Unit
µA
mV
Test Conditions/Comments
Leakage Current for PWRGD Pin
Output Low Voltage for PWRGD Pin
THERMAL SHUTDOWN (TSD)
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
IPWRGD_LEAKAGE
VPWRGD_LOW
PWRGD pin current (IPWRGD) = 1 mA
TSHDN
THYS
175
15
°C
°C
1 tSET is the setting time programmed by CFG2.
BUCK REGULATOR SPECIFICATIONS
VIN = 12 V, VREG = 4.8 V, fSW = 600 kHz for all channels, TJ = −40°C to +150°C for minimum and maximum specifications, and TA = 25°C
for typical specifications, unless otherwise noted.
Table 2.
Parameter
Symbol
Min
Typ
Max
Unit Test Conditions/Comments
CHANNEL 1 BUCK REGULATOR
Continuous Output Current
IO
7
Determined by CFG1 pin configuration
(see Table 6), CFG1 resistor (RCFG1) = 0 Ω
3.5
Determined by CFG1 pin configuration
(see Table 6), RCFG1 = open
FB1 Pin
Feedback Voltage
Feedback Voltage Accuracy
Feedback Reference Voltage of
Channel 1 (VFB1) = 600 mV Default
600
mV
%
%
VFB1_DEFAULT −0.25
−0.62
+0.25
+0.69
TJ = 25°C
−40°C ≤ TJ ≤ +125°C
−0.62
+0.83
0.1
%
µA
−40°C ≤ TJ ≤ +150°C
Adjustable voltage
Feedback Bias Current
SW1 Pin
High-Side Power Field Effect Transistor
(FET) On Resistance
Low-Side Power FET On Resistance
Valley Current-Limit Threshold
IFB1
RDSON_HS(1)
RDSON_LS(1)
25
12
mΩ
Pin to pin measurement
Pin to pin measurement
Current limit of Channel 1 (ILIM1) = 7 A,
TJ = 25°C
mΩ
A
ITH(ILIM1)
9.4
4.4
A
ILIM1 = 3.5 A, TJ = 25°C
Negative Current-Limit Threshold
Minimum On Time
Minimum Off Time
Error Amplifier (EA), COMP1 Pin
EA Transconductance
Soft Start
ITH(ILIM1-NEG)
tMIN_ON1
tMIN_OFF1
−5.0
35
120
A
ns
ns
55
150
fSW = 250 kHz to 2500 kHz
fSW = 250 kHz to 2500 kHz
gm1
330
350
365
µS
Soft Start Time
Hiccup Time
Output Capacitor (COUT) Discharge Switch RDIS1
On Resistance
tSS1
tHICCUP1
0.83 × tSET
7 × tSET
85
ms
ms
Ω
tSET = 2.6 ms when RCFG2 = 0 Ω
CHANNEL 2 BUCK REGULATOR
Continuous Output Current
IO
7
Determined by CFG1 pin configuration
(see Table 6), RCFG1 = 0 Ω
3.5
Determined by CFG1 pin configuration
(see Table 6), RCFG1 = open
FB2 Pin
Feedback Voltage
Feedback Voltage Accuracy
Feedback Reference Voltage of
Channel 2 (VFB2) = 600 mV Default
600
mV
%
%
VFB2_DEFAULT −0.25
−0.62
+0.25
+0.69
TJ = 25°C
−40°C ≤ TJ ≤ +125°C
−0.62
+0.83
0.1
%
µA
−40°C ≤ TJ ≤ +150°C
Adjustable voltage
Feedback Bias Current
IFB2
Rev. 0 | Page 5 of 31
ADP5056
Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit Test Conditions/Comments
SW2 Pin
High-Side Power FET On Resistance
Low-Side Power FET On Resistance
Valley Current-Limit Threshold
RDSON_HS(2)
RDSON_LS(2)
ITH(ILIM2)
25
12
mΩ
mΩ
A
Pin to pin measurement
Pin to pin measurement
Current limit of Channel 2 (ILIM2) = 7 A,
TJ = 25°C
ILIM2 = 3.5 A, TJ = 25°C
9.4
4.4
A
Negative Current-Limit Threshold
Minimum On Time
Minimum Off Time
EA, COMP2 Pin
ITH(ILIM2-NEG)
tMIN_ON2
tMIN_OFF2
−5.0
35
120
A
ns
ns
55
150
fSW = 250 kHz to 2500 kHz
fSW = 250 kHz to 2500 kHz
EA Transconductance
Soft Start
gm2
330
350
365
µS
Soft Start Time
Hiccup Time
COUT Discharge Switch On Resistance
tSS2
tHICCUP2
RDIS2
0.83 × tSET
7 × tSET
85
ms
ms
Ω
tSET = 2.6 ms when the RCFG2 = 0 Ω
CHANNEL 1 AND CHANNEL 2 IN PARALLEL
OPERATION
Continuous Output Current
IO
14
Determined by CFG1 pin configuration
(see Table 6), RCFG1 = 23.7 kΩ
CHANNEL 3 BUCK REGULATOR
Continuous Output Current
IO
3
Determined by CFG1 pin configuration
(see Table 6), RCFG1 = 0 Ω
1.5
Determined by CFG1 pin configuration
(see Table 6) RCFG1 = open
FB3 Pin
Feedback Voltage
Feedback Voltage Accuracy
Feedback Reference Voltage of
Channel 3 (VFB3) = 600 mV Default
600
mV
%
%
VFB3_DEFAULT −0.25
−0.62
+0.25
+0.69
TJ = 25°C
−40°C ≤ TJ ≤ +125°C
−0.62
+0.83
0.1
%
µA
−40°C ≤ TJ ≤ +150°C
Adjustable voltage
Feedback Bias Current
SW3 Pin
IFB3
High-Side Power FET On Resistance
Low-Side Power FET On Resistance
Valley Current-Limit Threshold
RDSON_HS(3)
RDSON_LS(3)
ITH(ILIM3)
85
45
mΩ
mΩ
A
Pin-to-pin measurement
Pin-to-pin measurement
Current Limit of Channel 3 (ILIM3) = 3 A,
TJ = 25°C
4.2
2.1
A
ILIM3 = 1.5 A, TJ = 25°C
Negative Current-Limit Threshold
Minimum On Time
Minimum Off Time
EA, COMP3 Pin
ITH(ILIM3-NEG)
tMIN_ON3
tMIN_OFF3
−2.5
35
120
A
ns
ns
55
150
fSW = 250 kHz to 2500 kHz
fSW = 250 kHz to 2500 kHz
EA Transconductance
Soft Start
gm3
330
350
365
µS
Soft Start Time
Hiccup Time
COUT Discharge Switch On Resistance
tSS3
tHICCUP3
RDIS3
0.83 × tSET
7 × tSET
85
ms
ms
Ω
tSET = 2.6 ms when the RCFG2 = 0 Ω
Rev. 0 | Page 6 of 31
Data Sheet
ADP5056
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
Rating
VBIAS to GND
PVINx to PGND
SWx to PGND
RAMPx to GND
PGND to GND
BST1 to SW1
BST2 to SW2
BST3 to SW3
CFG1 and CFG2 to GND
ENx to GND
VREG to GND
SYNC/MODE to GND
RT to GND
PWRGD to GND
FB1, FB2, and FB3 to GND
COMPx to GND
Storage Temperature Range
−0.3 V to +21 V
−0.3 V to +21 V
−0.3 V to +21 V
−0.3 V to +21 V
−0.3 V to +0.3 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +21 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−65°C to +150°C
−40°C to +150°C
Thermal resistance values specified in Table 4 are simulated based
on JEDEC specs (unless specified otherwise) and are used in
compliance with JESD51-12. Using enhanced heat removal (PCB,
heat sink, airflow) technique improves thermal resistance values.
Table 4. Thermal Resistance
1
Package Type
θJA
θJC
θJB
ΨJT
ΨJB
Unit
CC-43-1
26.0 14.3
9.3
0.2
9.0
(°C/W)
1 For θJC test, 100 µm thermal interface material (TIM) is used. TIM is assumed
to have 3.6 W/mK.
ESD CAUTION
Operational Junction Temperature
Range
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 7 of 31
ADP5056
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
1
2
3
4
5
6
7
8
9
28 CFG1
27 CFG2
26 RAMP2
25 FB2
GND
RAMP1
FB1
COMP1
RT
24 COMP2
23 EN2
EN1
22 PWRGD
21 COMP3
20 FB3
ADP5056
GND
TOP VIEW
VREG
10
11
12
13
14
15
16
17
18
19
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
4
5
6
7
8
9
GND
GND
RAMP1
FB1
COMP1
RT
EN1
GND
VREG
This pin is for internal test purposes. Connect this pin to ground.
This pin is for internal test purposes. Connect this pin to ground.
Slope Compensation Setting for Channel 1. Connect a resistor from RAMP1 to ground to set the slope compensation.
Feedback Sensing Input for Channel 1.
Error Amplifier Output for Channel 1. Connect a resistance and capacitor (RC) network from this pin to ground.
Frequency Setting. Connect a resistor from RT to ground to program the switching frequency.
Enable Input for Channel 1.
Analog Ground.
Output of the Internal 4.8 V Regulator. The control circuitry is powered from this voltage on this pin. Place a 4.7 μF
ceramic capacitor (X7R or X5R) between this pin to GND.
10
11
VBIAS
Bias Input Voltage Pin to Supply Internal Regulator.
SYNC/MODE Synchronization Input/Output (SYNC). To synchronize the switching frequency of the device to an external clock,
connect this pin to an external clock with a frequency from 250 kHz to 2700 kHz. This pin can also be configured
as a synchronization output via the CFG1 pin configuration.
FPWM or Automatic PWM/PSM Selection Pin (MODE). When this pin is logic high, each channel works in FPWM
mode. When this pin is logic low, all channels operate in automatic PWM/PSM mode.
12
13
14
15
16
17
18
19
20
21
BST1
BST3
PGND
SW3
PVIN3
BST2
EN3
RAMP3
FB3
COMP3
Supply Rail for the High-Side Gate Drive in Channel 1. Place a 0.1 μF capacitor (X7R or X5R) between SW1 and BST1.
Supply Rail for the High-Side Gate Drive in Channel 3. Place a 0.1 μF capacitor (X7R or X5R) between SW3 and BST3.
Power Ground for all Channels.
Switching Node Output for Channel 3.
Power Input for Channel 3.
Supply Rail for the High-Side Gate Drive in Channel 2. Place a 0.1 μF capacitor (X7R or X5R) between SW2 and BST2.
Enable Input for Channel 3.
Slope Compensation Setting for Channel 3. Connect a resistor from RAMP3 to ground to set the slope compensation.
Feedback Sensing Input for Channel 3.
Error Amplifier Output for Channel 3. Connect an RC network from this pin to ground.
Rev. 0 | Page 8 of 31
Data Sheet
ADP5056
Pin No. Mnemonic
Description
22
23
24
25
26
27
PWRGD
EN2
COMP2
FB2
RAMP2
CFG2
Power Good Output for Selective Channels.
Enable Input for Channel 2.
Error Amplifier Output for Channel 2. Connect an RC network from this pin to ground.
Feedback Sensing Input for Channel 2.
Slope Compensation Setting for Channel 2. Connect a resistor from RAMP2 to ground to set the slope compensation.
System Configuration Pin 2. Connect one resistor from this pin to ground to program the tSET timer, fast transient
mode, and sequence mode.
28
CFG1
System Configuration Pin 1. Connect one resistor from this pin to ground to program the current limit, parallel
operation, and clock output settings.
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
PVIN2
PVIN2
PVIN2
SW2
SW2
SW2
PGND
PGND
PGND
SW1
SW1
SW1
Power Input for Channel 2.
Power Input for Channel 2.
Power Input for Channel 2.
Switching Node Output for Channel 2.
Switching Node Output for Channel 2.
Switching Node Output for Channel 2.
Power Ground for all Channels.
Power Ground for all Channels.
Power Ground for all Channels.
Switching Node Output for Channel 1.
Switching Node Output for Channel 1.
Switching Node Output for Channel 1.
Power Input for Channel 1.
PVIN1
PVIN1
PVIN1
Power Input for Channel 1.
Power Input for Channel 1.
Rev. 0 | Page 9 of 31
ADP5056
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
100
100
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
V
V
V
V
= 1.2V
= 1.8V
= 2.5V
= 3.3V
V
V
V
V
= 1.2V
= 1.8V
= 2.5V
= 3.3V
20
10
0
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
(A)
0
0.5
1.0
1.5
(A)
2.0
2.5
3.0
I
I
O
O
Figure 4. Channel 1/Channel 2 Efficiency Curve, VIN = 5 V, fSW = 600 kHz,
FPWM Mode
Figure 7. Channel 3 Efficiency Curve, VIN = 5 V, fSW = 600 kHz, FPWM Mode
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
V
V
V
V
V
= 1.2V
= 1.8V
= 2.5V
= 3.3V
= 5.0V
V
V
V
V
V
= 1.2V
= 1.8V
= 2.5V
= 3.3V
= 5.0V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
20
10
0
20
10
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
(A)
0
0.5
1.0
1.5
(A)
2.0
2.5
3.0
I
I
O
O
Figure 5. Channel 1/Channel 2 Efficiency Curve, VIN = 12 V, fSW = 600 kHz,
FPWM Mode
Figure 8. Channel 3 Efficiency Curve, VIN = 12 V, fSW = 600 kHz, FPWM Mode
100
90
80
70
60
50
40
100
90
80
70
60
50
40
V
V
V
V
V
V
V
V
= 1.2V, AUTO PWM/PSM
= 1.2V, FPWM
= 1.8V, AUTO PWM/PSM
= 1.8V, FPWM
= 2.5V, AUTO PWM/PSM
= 2.5V, FPWM
= 3.3V, AUTO PWM/PSM
= 3.3V, FPWM
V
V
V
V
V
V
V
V
= 1.2V, AUTO PWM/PSM
= 1.2V, FPWM
= 1.8V, AUTO PWM/PSM
= 1.8V, FPWM
= 2.5V, AUTO PWM/PSM
= 2.5V, FPWM
= 3.3V, AUTO PWM/PSM
= 3.3V, FPWM
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
30
20
10
0
30
20
10
0
0.01
0.1
1.0
0.01
0.1
1.0
I
(A)
I (A)
O
O
Figure 6. Channel 1/Channel 2 Efficiency Curve, VIN = 12 V, fSW = 600 kHz,
FPWM and Automatic PWM/PSM Modes
Figure 9. Channel 3 Efficiency Curve, VIN = 12 V, fSW = 600 kHz,
FPWM Mode and Automatic PWM/PSM Modes
Rev. 0 | Page 10 of 31
Data Sheet
ADP5056
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
fSW = 600kHz
fSW = 1.2MHz
fSW = 1.8MHz
fSW = 600kHz
fSW = 1.2MHz
fSW = 1.8MHz
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
(A)
0
0.5
1.0
1.5
(A)
2.0
2.5
3.0
I
I
O
O
Figure 10. Channel 1/Channel 2 Efficiency Curve, VIN = 12 V,
Output Voltage (VOUT) = 3.3 V, FPWM Mode (600 kHz, 1.2 MHz, 1.8 MHz)
Figure 13. Channel 3 Efficiency Curve, VIN = 12 V, VOUT = 3.3 V,
FPWM Mode (600 kHz, 1.2 MHz, 1.8 MHz)
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.1
–0.2
–0.3
–0.4
2
4
6
8
10
(V)
12
14
16
18
2
4
6
8
10
(V)
12
14
16
18
V
V
IN
IN
Figure 14. Channel 3 Line Regulation, VOUT = 1.2 V, IOUT = 3 A, fSW = 600 kHz,
FPWM Mode
Figure 11. Channel 1/Channel 2 Line Regulation, VOUT = 1.2 V, IOUT = 7 A,
fSW = 600 kHz, FPWM Mode
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.1
–0.2
–0.3
–0.4
0
1
2
3
4
5
6
7
0
0.5
1.0
1.5
(A)
2.0
2.5
3.0
I
(A)
I
OUT
OUT
Figure 12. Channel 1/Channel 2 Load Regulation, VIN = 12 V,
VOUT = 1.2 V, fSW = 600 kHz, FPWM Mode
Figure 15. Channel 3 Load Regulation, VIN = 12 V,
VOUT = 1.2 V, fSW = 600 kHz, FPWM Mode
Rev. 0 | Page 11 of 31
ADP5056
Data Sheet
0.5
70
65
60
55
50
45
40
35
30
25
20
V
V
V
= 4.5V
= 12V
= 18V
BIAS
BIAS
BIAS
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–50
–25
0
25
50
75
100
125
150
175
–50
–25
0
25
50
75
100
125
150
175
TEMPERATURE (°C)
TEMPERATURE FOR CHANNEL 1 (°C)
Figure 16. Feedback Voltage Accuracy vs. Temperature for Channel 1
Figure 19. Shutdown Current vs. Temperature (EN1, EN2, and EN3 Low)
750
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
700
650
600
550
500
–50
–25
0
25
50
75
100
125
150
175
–50
–25
0
25
50
75
100
125
150
175
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. Frequency vs. Temperature, VIN = 12 V
Figure 20. UVLO Threshold vs. Temperature
8
7
6
5
4
3
1
2
–50
–25
0
25
50
75
100
125
150
175
B
B
CH1 2.0mV/DIV
CH2 5.0V/DIV 1MΩ
20.0M
1.0µs/DIV 100MS/s
W:
W
: 20.0M
A
CH2
4.3V
TEMPERATURE (°C)
10.0ns/pt
Figure 18. Quiescent Current vs. Temperature
(Includes PVIN1, PVIN2, and PVIN3)
Figure 21. Channel 1/Channel 2 Steady State Waveform, VIN = 12 V,
VOUT = 1.2 V, IOUT = 7 A, fSW = 600 kHz, L = 1 µH, COUT = 47 µF × 6,
FPWM Mode, Channel 1 = VOUT, Channel 2 = Switching Point (SW)
Rev. 0 | Page 12 of 31
Data Sheet
ADP5056
1
1
4
2
3
2
B
B
B
B
B
B
CH1 2.0mV/DIV
CH2 5.0V/DIV 1MΩ
20.0M
100µs/DIV 20.0MS/s
A CH2 4.3V
50.0ns/pt
CH1 500mV/DIV 1MΩ
: 20.0M
: 20.0M
: 20.0M
: 500M
20.0ms/DIV 500kS/s
W:
: 20.0M
W
W
W
W
CH2 2.0V/DIV
CH3 2.0V/DIV
CH4 1.0A/DIV
A
CH2
1.96V
1MΩ
1MΩ
50Ω
W
2.0µs/pt
Figure 22. Channel 1/Channel 2 Steady State Waveform, VIN = 12 V,
Figure 25. Channel 1/Channel 2 Shutdown with Active Output Discharge,
VIN = 12 V, VOUT = 1.2 V, fSW = 600 kHz, L = 1 µH, COUT = 47 µF × 6,
Channel 1 = VOUT, Channel 2 = EN, Channel 3 = PWRGD, Channel 4 = IOUT
V
OUT = 1.2 V, IOUT = 10 mA, fSW = 600 kHz, L = 1 µH, COUT = 47 µF × 6,
Automatic PWM/PSM, Channel 1 = VOUT, Channel 2 = SW
T
1
1
4
4
B
B
CH1 50.0mV/DIV
CH4 2.0A/DIV
: 20.0M
: 500M
200µs/DIV 20.0MS/s
B
B
W
W
CH1 500mV/DIV 1MΩ
: 500M
: 20.0M
10.0ms/DIV 1.0MS/s
W
W
A
CH4
3.12A
50Ω
CH4 5.0A/DIV
50Ω
A
CH1
660mV
50.0ns/pt
1.0µs/pt
Figure 23. Load Transient, Channel 1/Channel 2 from 1.5 A to 5 A, VIN = 12 V,
Figure 26. Channel 1/Channel 2 Short-Circuit Protection Entry, VIN = 12 V,
VOUT = 1.0 V, fSW = 600 kHz, L = 1 µH, COUT = 47 µF × 6,
Channel 1 = VOUT, Channel 4 = IOUT
V
OUT = 3.3 V, fSW = 600 kHz, L = 1 µH, COUT = 47 µF × 6, 1 A/μs,
Channel 1 = VOUT, Channel 4 = IOUT
T
T
1
4
2
3
1
4
B
B
CH1 500mV/DIV 1MΩ
CH4 5.0AV/DIV 50Ω
500M
10.0ms/DIV 1.0MS/s
B
W:
W
CH1 500mV/DIV 1MΩ
: 20M
20.0ms/DIV 500kS/s
W
: 20.0M
A
CH1
670mV
B
B
B
CH2 5.0V/DIV 1MΩ
CH3 2.0V/DIV 1MΩ
CH4 5.0A/DIV 50Ω
: 500M
: 20M
A
CH1
600mV
W
W
1.0µs/pt
2.0ns/pt
: 500M
W
Figure 24. Channel 1/Channel 2 Soft Start with 7 A Resistance Load,
VIN = 12 V, VOUT = 1.2 V, fSW = 600 kHz, L = 1 µH, COUT = 47 µF × 6,
Channel 1 = VOUT, Channel 2 = EN, Channel 3 = PWRGD, Channel 4 = IOUT
Figure 27. Channel 1/Channel 2 Short-Circuit Protection Recovery, VIN = 12 V,
VOUT = 1.0 V, fSW = 600 kHz, L = 1 µH, COUT = 47 µF × 6, Channel 1= VOUT
,
Channel 4 = IOUT
Rev. 0 | Page 13 of 31
ADP5056
Data Sheet
THEORY OF OPERATION
The ADP5056 is a power management unit that combines three
high performance buck regulators in a 43-terminal LGA package
to meet demanding performance and board space requirements.
The device enables direct connection to high input voltages up
to 18 V with no preregulators to make applications simpler and
more efficient.
FPWM and Automatic PWM/PSM Modes
The buck regulators can be configured to always operate in
FPWM mode using the SYNC/MODE pin. In FPWM mode, the
regulator continues to operate at a fixed frequency even when the
output current is below the PWM/PSM threshold. In FPWM
mode, efficiency is lower compared to PSM mode under light
load conditions. The low-side MOSFET remains on when the
inductor current falls to less than 0 A, causing the ADP5056 to
enter continuous conduction mode (CCM).
BUCK REGULATOR OPERATIONAL MODES
PWM Mode
In PWM mode, the buck regulators in the ADP5056 operate at a
fixed frequency. An internal oscillator programmed by the RT
pin sets this frequency. The ADP5056 uses the low-side MOSFET
current for the PWM control, as shown in Figure 28. The valley
current information is captured at the end of the off period and
combines with the slope ramp to form the emulated current ramp
voltage. The resistor from the RAMPx pin to ground controls the
slope ramp voltage. At the start of each oscillator cycle, the high-
side MOSFET turns on, and the inductor current increases until
the emulated current ramp voltage crosses the COMPx voltage.
When the current ramp voltage crosses the COMPx voltage, it
turns off the high-side MOSFET and turns on the low-side
MOSFET, which in turn places a negative voltage across the
inductor, causing a reduction in the inductor current. The low-
The buck regulators can be configured to operate in automatic
PWM/PSM mode using the SYNC/MODE pin. In automatic
PWM/PSM mode, the buck regulators operate in either PWM
mode or PSM mode, depending on the output current. When
the average output current falls below the PWM/PSM threshold,
the buck regulator enters PSM mode operation. In PSM mode,
the regulator operates with a reduced switching frequency to
maintain high efficiency. The low-side MOSFET turns off when
the inductor current reaches 0 A, causing the regulator to operate
in discontinuous mode (DCM).
The user can alternate between FPWM mode and automatic
PWM/PSM mode during operation. The flexible configuration
capability during operation of the device enables efficient power
management.
side MOSFET stays on for the remainder of the cycle.
PVINx
PVINx
When a logic low level is applied to the SYNC/MODE pin, the
operational mode of all three buck regulators is automatic
PWM/PSM mode. When a logic high level is applied to the
SYNC/MODE pin, the operational mode of all three buck
regulators is FPWM mode.
I
RAMP
V
PWM
CLK
L
V
OUT
RAMP
S
R
Q
IN DH
DL
SW
C
OUT
R
C
RAMP
RAMP
A
*
CS
ADJUSTABLE OUTPUT VOLTAGES
R
R
TOP
The ADP5056 provides an adjustable output voltage via an external
resistor divider. For the adjustable output settings, use an external
resistor divider to set the desired output voltage via the feedback
reference voltage. The default reference voltage on each feedback
pin is 600 mV for each channel.
V
COMP
gm
BOT
R
C
C
0.6V
C
*
A
IS THE CURRENT SENSING AMPLIFIER.
CS
Figure 28. FlexMode™ PWM Control Architecture
INTERNAL REGULATORS (VREG)
PSM Mode
The internal VREG regulator in the ADP5056 provides a stable
4.8 V power supply for the internal circuitry. Connect a 4.7 µF
(X5R or X7R) ceramic capacitor between VREG and ground. The
internal VREG regulator is always active as long as the VBIAS
voltage is available.
To achieve higher efficiency at light loads, the buck regulators in
the ADP5056 smoothly transition to variable frequency PSM
operation when the output load falls below the PSM current
threshold. When the output voltage (VOUT) falls below regulation,
the buck regulator enters PWM mode for a few oscillator cycles
until the voltage increases to within regulation. During the idle
time between bursts, the MOSFET turns off, and the output
capacitor supplies all the output current.
SEPARATE SUPPLY APPLICATIONS
The ADP5056 supports separate input voltages for the three buck
regulators, meaning that the input voltages for the three buck
regulators can connect to different supply voltages. The
ADP5056 integrates 100 nF, 25 V, X8L ceramic capacitors to
provide local decoupling from PVIN1 and PVIN2 to power
ground in Channel 1 and Channel 2.
The PSM comparator monitors the internal compensation node,
which represents the peak inductor current information. The
average PSM current threshold depends on the VIN, the VOUT, the
inductor, and the output capacitor. Because the output voltage
occasionally falls below regulation and then recovers, the output
voltage ripple in PSM operation is larger than the ripple in the
FPWM mode of operation under light load conditions.
The VBIAS voltage provides the power supply for the internal
regulators and the control circuitry. Therefore, if the user plans
Rev. 0 | Page 14 of 31
Data Sheet
ADP5056
to use separate supply voltages for the buck regulators, the VBIAS
voltage must be greater than the UVLO threshold before the
other channels begin to operate.
The precision enable pin has an internal pull-down current
source (3.5 μA) that provides a default turn-off when the enable
pin is left open. When the enable pin exceeds 0.615 V (typical),
the regulator is enabled and the internal pull-down current source
at the enable pin decreases to 0.9 μA. The precision enabling uses
the ratio of the external resistor divider to program the UVLO
threshold to monitor either input voltage or output voltage,
while using the absolute value of the external resistor divider to
program the hysteresis window. For more information, see the
Programming the UVLO Input section.
Precision enabling can monitor the voltages of the PVIN1 pin,
the PVIN2 pin, and the PVIN3 pin and to delay the startup of
the outputs to ensure that the voltages of the PVIN1 pin, the
PVIN2 pin, and the PVIN3 pin are high enough to support the
outputs in regulation. For more information, see the Precision
Enabling section.
The ADP5056 supports cascading supply operation for the three
buck regulators. As shown in Figure 29, PVIN2 and PVIN3 are
powered from the Channel 1 output. In this configuration, the
Channel 1 output voltage must be higher than the UVLO
threshold for PVIN2 and PVIN3.
To force the regulator to automatically start up when input power is
applied, connect the enable pin to the VREG pin.
PVINx
R
TOP_EN
ENx
VBIAS
PVIN1
BUCK CHANNEL 1
V
OUT1
EN_CMP
+
V
IN
0.615V
–
R
BOT_EN
V
V
TO
OUT2
OUT3
PVIN2 TO
PVIN3
0.9µA 2.6µA
BUCK CHANNEL 2
Figure 30. Precision Enable Diagram for One Channel
Figure 29. Cascading Supply Application
SEQUENCE MODE
BOOTSTRAP CIRCUITRY
The ADP5056 integrates the sequence control on each channel.
When the ENx signal goes high, each channel controlled by the
sequencer begins a soft start after the delay time (tEN_DLYx) specified
by the CFG2 pin setting (see Table 7). Similarly, when the ENx
signal goes low, the channel turns off after the delay timer
(tDIS_DLYx). The turn on and turn off delay timer for all channels is
designed in an opposite manner to meet typical system sequence
requirements. The turn-on delay step is 3 × tSET timer, and the turn-
off delay step is 6 × tSET timer, which provides the output with
extra discharge time. The tSET timer can be set to 2.6 ms or
20.8 ms by the CFG2 pin configuration. For example, when the
CFG2 pin connects to 14.3 kΩ, the start-up sequence is set as
Channel 1, Channel 2, and Channel 3. The enable delay of
Channel 1, Channel 2, and Channel 3 are 0 ms, 7.8 ms, and
15.6 ms. The shutdown sequence is set as Channel 3, Channel 2,
and Channel 1. The disable delay of Channel 1, Channel 2, and
Channel 3 are 31.2 ms, 15.6 ms, and 0 ms. Figure 31 shows the
logical states of each channel controlled by the grouped ENx
signal, and it does not show soft start and output discharge ramps.
Each buck regulator in the ADP5056 has an integrated bootstrap
regulator. The bootstrap regulator requires a 0.1 μF ceramic
capacitor (X5R or X7R) between the BSTx pins and SWx pins to
provide the gate drive voltage for the high-side MOSFET.
ACTIVE OUTPUT DISCHARGE SWITCH
Each buck regulator in the ADP5056 integrates a discharge switch
from the switching node to ground. This switch is turned on when
the associated regulator is disabled, which helps to discharge the
output capacitor quickly. The typical value of the discharge switch
is 85 Ω for Channel 1 to Channel 3.
PRECISION ENABLING
The ADP5056 has an enable control pin for each regulator. The
enable control pin (ENx) features a precision enable circuit with
a 0.615 V reference voltage. When the voltage at the ENx pin is
greater than 0.615 V (typical high level threshold), the regulator
is enabled. When the ENx pin voltage falls below 0.575 V
(typical low level threshold), the regulator is disabled. The
ADP5056 turns off the low-side MOSFET only after the
inductor current reaches zero.
ENx
ON
CHANNEL x OFF
tEN_DLYx
tDIS_DLYx
Figure 31. Sequencer Mode
Rev. 0 | Page 15 of 31
ADP5056
Data Sheet
T
OSCILLATOR
By connecting a resistor from the RT pin to ground, the fSW of the
ADP5056 can be set to a value between 250 kHz and 2500 kHz.
Calculate the RT resistor value in kΩ as follows:
1
2
167,305
RT =
0.998
fSW
Figure 32 shows the typical relationship between the fSW and the RT
resistor. The adjustable frequency allows users to make decisions
based on the trade-off between efficiency and solution size.
3000
3
B
B
B
CH1 5.0V/DIV 1MΩ
CH2 5.0V/DIV 1MΩ
CH3 5.0V/DIV 1MΩ
: 500M
: 20.0M
: 20.0M
2.0µs/DIV 100MS/s
W
W
W
2500
2000
1500
1000
500
A
CH1
500mV
10.0ns/pt
Figure 34. 120° Phase Shift Waveforms, Three Buck Regulators:
Channel 1 = SW1, Channel 2 = SW2, Channel 3 = SW3
SYNCHRONIZATION INPUT/OUTPUT
The switching frequency of the ADP5056 can be synchronized
to an external clock with a frequency range from 250 kHz to
2700 kHz. The ADP5056 automatically detects the presence of
an external clock applied to the SYNC/MODE pin, and the
switching frequency transitions smoothly to the frequency of
the external clock. When the external clock signal stops, the
device automatically switches back to the internal clock and
continues to operate.
0
30
130
230
330
430
530
630
730
R
RESISTANCE (kΩ)
T
Figure 32. Switching Frequency vs. RT Resistance
Note that the internal switching frequency set by the RT pin must
be programmed to a value that is close to the external clock value
for successful synchronization. The suggested frequency difference
is less than 15% in typical applications.
Out-Of-Phase Operation
By default, the phase shift between Channel 1, Channel 2, and
Channel 3 is 120°. This value provides the benefits of out-of-
phase operation by reducing the input ripple current and
lowering the ground noise.
The SYNC/MODE pin can be configured as a synchronization
clock output by the CFG1 pin (refer to Table 6). A positive clock
pulse with a 50% duty cycle and VREG voltage level is generated
at the SYNC/MODE pin with a frequency equal to the internal
switching frequency set by the RT pin.
0° REFERENCE
CH1
120° PHASE SHIFT
CH2
Figure 35 shows two ADP5056 devices configured for frequency
synchronization mode. One ADP5056 device is configured as the
clock output to synchronize another ADP5056 device.
240° PHASE SHIFT
CH3
(CLOCK MASTER)
(SLAVE)
Figure 33. Phase Shift Diagram, Three Buck Regulators
SYNC/
MODE
SYNC/
In the in phase parallel operation configuration of Channel 1
and Channel 2, both channels operate in the same phase of
Channel 1.
MODE
CFG1
(CLOCK OUT) (SYNC IN)
CFG1
In the interleaved parallel operation configuration of Channel 1
and Channel 2, the phase shift between Channel 1, Channel 2, and
Channel 3 is 0°, 180°, and 240°.
R1
R2
ADP5056
ADP5056
(1)
(2)
Figure 35. Two ADP5056 Devices Configured for Synchronization Mode
Rev. 0 | Page 16 of 31
Data Sheet
ADP5056
In the configuration shown in Figure 35, the phase shift between
Channel 1 of the first ADP5056 device and Channel 1 of the
second ADP5056 device is 0° (see Figure 36).
Table 6. Configuration by the CFG1 Pin
RCFG1
(kΩ),
1%
Output Capability
GPIO
Channel 1
Channel 2
7 A
Channel 3
3 A
0 (GND)
14.3
SYNC/MODE 7 A
SYNC/MODE 7 A
SYNC/MODE 7 A
SYNC/MODE 7 A
SYNC/MODE Interleaved
T
7 A
1.5 A
3 A
16.9
3.5 A
20.0
3.5 A
1.5 A
3 A
1
23.7
Interleaved
parallel (14 A) parallel (14 A)
Open
32.4
SYNC/MODE 3.5 A
SYNC/MODE In phase
3.5 A
1.5 A
3 A
In phase
2
parallel (14 A) parallel (14 A)
39.2
47.5
57.6
71.5
90.9
127
Clock output
Clock output
Clock output
Clock output
Clock output
Clock output
7 A
7 A
3 A
7 A
7 A
1.5 A
3 A
7 A
3.5 A
3.5 A
7 A
3
7 A
1.5 A
3 A
3.5 A
Interleaved
parallel (14 A) parallel (14 A)
B
B
B
CH1 2.0V/DIV 1MΩ
CH2 5.0V/DIV 1MΩ
CH3 5.0V/DIV 1MΩ
: 500M
: 20.0M
: 20.0M
500ns/DIV 200MS/s
W
W
W
A
CH1
2.88V
Interleaved
3 A
5.0ns/pt
200
511
Clock output
Clock output
3.5 A
3.5 A
1.5 A
3 A
Figure 36. Waveforms of Two ADP5056 Devices Operating in
Synchronization Mode, Channel 1 = Synchronization Clock Output of First
ADP5056 Device, Channel 2 = SW1 of First ADP5056 Device, Channel 3 =
SW1 of Second ADP5056 Device
In phase
parallel (14 A) parallel (14 A)
In phase
Table 7. Configuration by the CFG2 Pin
SOFT START
RCFG2 (kΩ),
1%
tSET timer
(ms)
Fast
Transient Start-Up Sequence
The buck regulators in the ADP5056 include soft start circuitry
that ramps the output voltage in a controlled manner during
startup, thereby limiting the inrush current. The soft start time
for all channels is fixed at 0.83 × tSET timer (2.2 ms or 17.3 ms,
depending on RCFG2 value).
0 (GND)
14.3
2.6
2.6
Disable
Disable
No delay
Channel 1, Channel 2,
Channel 3
16.9
20
2.6
2.6
Disable
Disable
Channel 2, Channel 1,
Channel 3
Channel 3, Channel 1,
Channel 2
FUNCTION CONFIGURATIONS (CFG1 AND CFG2)
The ADP5056 includes the CFG1 pin and CFG2 pin to decode the
function configurations for all channels. The logic statuses of
each pin is decoded by connecting one resistor to ground. It is
recommended to use 1% resistor tolerance to achieve accurate
decoding.
23.7
32.4
2.6
2.6
Enable
Enable
No delay
Channel 1, Channel 2,
Channel 3
39.2
2.6
Enable
Channel 3, Channel 1,
Channel 2
Open
47.5
20.8
20.8
Disable
Disable
No delay
Channel 1, Channel 2,
Channel 3
Channel 2, Channel 1,
Channel 3
Channel 3, Channel 1,
Channel 2
No delay
Channel 1, Channel 2,
Channel 3
This decoder circuitry only works in the initiation stage of the
ADP5056 when VBIAS passes the power-on reset (POR)
threshold. Therefore, those configurations are latched into
internal registers and cannot be changed in operation.
57.6
71.5
20.8
20.8
Disable
Disable
The CFG1 pin can be used to program the SYNC/MODE pin or
CLKOUT, the load output capability, and parallel operation for
all channels. Table 6 provides the values of RCFG1 needed to set
different functionality in the CFG1 pin.
90.9
127
20.8
20.8
Enable
Enable
The CFG2 pin can be used to program the tSET timer (2.6 ms or
20.8 ms), fast transient functionality, and sequence for the three
channels. Table 7 provides the values of RCFG2 needed to set
different functionality in the CFG2 pin.
200
511
20.8
20.8
Enable
Enable
Channel 2, Channel 1,
Channel 3
Channel 3, Channel 1,
Channel 2
Rev. 0 | Page 17 of 31
ADP5056
Data Sheet
To configure a two-phase interleaved parallel operation, do the
following (see Figure 38):
PARALLEL OPERATION
The ADP5056 supports 2-phase parallel operation of Channel 1
and Channel 2 to provide a single output with up to 14 A of
current. The ADP5056 includes two different parallel operation
modes via the CFG1 pin configuration: in phase parallel operation
and interleaved parallel operation.
Use the CFG1 pin to select interleaved parallel operation,
as specified in Table 6.
Use the COMP1 pin as the compensation network.
Use the same RAMP1 and RAMP2 resistors.
Use the FB1 pin to set the output voltage.
Use the EN1 pin to enable the channel.
Connect the FB2 pin to ground (FB2 is ignored).
Leave the COMP2 pin open (COMP2 is ignored).
Connect the EN2 pin to ground (EN2 is ignored).
In Phase Parallel Operation
In phase parallel operation parallels internal MOSFETs and driver
circuitry between Channel 1 and Channel 2. In phase parallel
operation treats Channel 1 as the control master, and the Channel
2 control stage is ignored. The in phase parallel operation mode
uses a single inductor for external components and space saving. To
configure Channel 1 and Channel 2 for in phase parallel single
output operation, do the following (see Figure 37):
V
PVIN1
IN
PVIN2
V
OUT1
(UP TO 14A)
L1
SW1
FB1
CHANNEL 1
BUCK
Use the CFG1 pin to select in phase parallel operation, as
specified in Table 6.
CFG1
(7A)
RAMP1
Use the COMP1 pin as the compensation network.
Use the FB1 pin to set the output voltage.
Use the EN1 pin to enable the channel.
Connect the FB2 pin to ground (FB2 is ignored).
Leave the COMP2 pin open (COMP2 is ignored).
Leave the RAMP2 pin open (RAMP2 is ignored).
Connect the EN2 pin to ground (EN2 is ignored).
PGND
COMP1
L2
COMP2
RAMP2
SW2
FB2
CHANNEL 2
BUCK
(7A)
EN1
EN2
PGND
Figure 38. Interleaved Parallel Operation for Channel 1 and Channel 2
V
PVIN1
PVIN2
IN
The current balance in parallel configuration is well balanced
by careful designs of symmetrical printed circuit board (PCB)
layout and circuitry designs. Figure 39 and Figure 40 show the
typical current balance matching in the parallel output
configuration.
V
OUT1
L1
(UP TO 14A)
SW1
FB1
CHANNEL 1
BUCK
CFG1
(7A)
RAMP1
PGND
COMP1
T
COMP2
EN1
SW2
FB2
CHANNEL 2
BUCK
(7A)
RAMP2
EN2
PGND
1
Figure 37. In Phase Parallel Operation for Channel 1 and Channel 2
Interleaved Parallel Operation
The ADP5056 supports 2-phase interleaved parallel operation of
Channel 1 and Channel 2 to provide a single output with up to
14 A of current. In this mode, two channels operate in 180° out
of phase operation and rely on an individual control loop to achieve
current balance between the two channels. The interleaved parallel
operation mode uses two inductors with the advantages of ripple
current cancellation and higher equivalent switching frequency.
4
B
B
B
B
CH1 5.0V/DIV 1MΩ
CH2 5.0V/DIV 1MΩ
CH3 2.0A/DIV 50Ω
CH4 2.0A/DIV 50Ω
: 20.0M
: 20.0M
W
W
2.0µs/DIV 50.0MS/s
W
W
A
CH1
800mV
: 20.0M
: 20.0M
20.0ns/pt
Figure 39. Steady State Waveform in Interleaved Parallel Output
Configuration, VIN = 12 V, VOUT = 1.2 V, fSW = 600 kHz, FPWM Mode,
Channel 1 = SW1, Channel 2 = SW2, Channel 3 = Current of Inductor L1,
Channel 4 = Current of Inductor L2
Rev. 0 | Page 18 of 31
Data Sheet
ADP5056
8
7
6
5
4
3
2
1
0
1
4
2
3
IDEAL
CH1
CH2
B
B
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CH1 500mV/DIV 1MΩ
CH2 5.0V/DIV 1MΩ
CH3 2.0V/DIV 1MΩ
CH4 1.0A/DIV 50Ω
: 20M
20.0ms/DIV 500kS/s
W
W
: 20M
: 20M
A
CH1
870mV
TOTAL OUTPUT CURRENT [A]
B
B
2.0µs/pt
W
: 500M
W
Figure 40. Current Balance in Interleaved Parallel Output Configuration,
VIN = 12 V, VOUT = 1.2 V, fSW = 600 kHz, FPWM Mode
Figure 42. Channel 1 Startup with Precharged Ouput, VIN = 12 V, VOUT = 1.2 V,
f
SW = 600 kHz, FPWM Mode, Channel 1 = VOUT, Channel 2 = EN,
Channel 3 = PWRGD, Channel 4 = IOUT
FAST TRANSIENT MODE
The ADP5056 includes fast transient response for large load
step conditions. The ADP5056 feedback pin senses the output
voltage to determine if a load step has occurred. When the output
voltage falls below the specific threshold, the internal loop gain
gradually increases to improve the load transient response
speed. The fast enhanced transient threshold is at −2.5% × VOUT
with five times of nominal gM, where gM = 350 μA/V.
CURRENT-LIMIT PROTECTION
The ADP5056 uses the emulated current ramp voltage for cycle by
cycle current-limit protection to prevent current runaway. When
the emulated current ramp voltage reaches the valley current-
limit threshold plus the ramp voltage, the high-side MOSFET
turns off and the low-side MOSFET turns on until the next
cycle. If the overcurrent counter reaches 20, the device enters
hiccup mode, and the ADP5056 turns off the low-side MOSFET
only after the inductor current reaches zero. During hiccup
mode, the high-side MOSFET and low-side MOSFET are both
turned off. The device remains in this mode for seven soft start
cycles and then attempts to restart with soft start. If the current-
limit fault is cleared, the device resumes normal operation.
Otherwise, the device re-enters hiccup mode.
The CFG2 pin needs be programmable to turn on the fast
transient mode.
T
1
CYCLE-BY-CYCLE
THRESHOLD
CURRENT-LIMIT
PVINx
COMPARATOR
I
RAMP
V
RAMP
HICCUP
CONTROL
BLOCK
V
FB
R
C
RAMP
RAMP
4
PWM
B
B
CH1 50.0mV/DIV
CH4 2.0A/DIV
: 20.0M
: 20.0M
100µs/DIV 50MS/s
W
W
SWx
50Ω
A
CH4
3.04A
R1 51.5mV/DIV 100µs
20.0ns/pt
*
A
CS
Figure 41. Enable or Disable Fast Transient Mode, Load Transient
Comparison, VIN = 12 V, VOUT = 1.2 V, fSW = 600 kHz, FPWM Mode,
Channel 1 = VOUT with Fast Transient Mode Enable, Channel 3 = VOUT with
Fast Transient Mode Enable, Channel 4 = IOUT
*
A
IS THE CURRENT SENSING AMPLIFIER.
CS
Figure 43. Current-Limit Circuitry
STARTUP WITH PRECHARGED OUTPUT
The buck regulators in the ADP5056 include negative current-
limit protection circuitry to limit certain amounts of negative
current flowing through the low-side MOSFET switch and
high-side MOSFET body diode.
The buck regulators in the ADP5056 include a precharged start-up
feature to protect the low-side FETs from damage during
startup. If the output voltage is precharged before the regulator
is turned on, the regulator prevents reverse inductor current
(which discharges the output capacitor) until the internal soft
start reference voltage exceeds the precharged voltage on the
feedback (FBx) pin.
Rev. 0 | Page 19 of 31
ADP5056
Data Sheet
UVLO
Undervoltage lockout circuitry monitors both bias input voltage
(VBIAS pin) and power input voltage level (PVINx pin) of each
buck regulator in the ADP5056. If the power input voltage falls
below 2.22 V (typical falling threshold), the corresponding
channel is turned off. After the input voltage rises above 2.5 V
(typical rising threshold), the soft start period initiates, and the
corresponding channel enables when the ENx pin is high.
1
2
3
If the bias voltage falls below 3.8 V (typical falling threshold), all
channels turn off. After the bias voltage rises above 4.2 V (typical
rising threshold), a soft start initiates for each enabled channel.
B
B
B
POWER-GOOD FUNCTION
CH1 2.0V
CH2 500mV 1MΩ
CH3 1.0V 1MΩ
1MΩ
20.0M
20.0M
20.0M
M2.00ms
A CH1
440mV
W
W
W
The ADP5056 includes an open-drain, power-good output
(PWRGD pin) that becomes active high when the three buck
regulators are operating normally. The PWRGD pin monitors
the output voltage on three channels.
Figure 44. Power-Good Delay, VIN = 12 V, VOUT = 1.0 V, fSW = 600 kHz, FPWM
Mode, Channel 1 = EN, Channel 2 = VOUT, Channel 3 = PWRGD
POWER-UP AT HIGH TEMPERATURE
A logic high of the PWRGD signal indicates that the regulated
output voltage of the buck regulator is above 95% (typical) and
below 105% (typical) of the nominal output. When the regulated
output voltage of the buck regulator falls below 93% (typical) or
rises above 107% (typical) of the nominal output for a deglitched
time greater than approximately four switching cycles, the
PWRGD pin is set to 0.
Although the maximum operating junction temperature is
150°C, the ADP5056 has a lower temperature protection limit
of 125°C by which the device must be powered up. This 125°C
limit protects the internal nonvolatile memory, which is read on
this initial power-up. Power-up is the condition of VBIAS rising
above UVLOVBIAS. If power-up is attempted above 125°C, the
devices does not allow operation until the temperature drops
below 125°C. When this temperature is achieved and stored in
the volatile memory, the device is ready for normal operation
without the 125°C limit.
The output of the PWRGD pin is the logical AND of the internal
PWRGD signals on all channels. The output of the PWRGD pin
becomes high after the tSET delay and is 2.6 ms when the CFG2
pin is connected to ground. The tSET timer can be increased by
8× using the CFG2 pin configuration. If one internal PWRGD
signal fails, the PWRGD pin goes low with no delay.
THERMAL SHUTDOWN
If the ADP5056 junction temperature exceeds 175°C, the thermal
shutdown circuit turns off the IC, except for the internal linear
regulators. The ADP5056 turns off the low-side MOSFET only
after the inductor current reaches zero. Extreme junction
temperatures can be the result of high current operation, poor
circuit board design, or high ambient temperature. A 15°C
hysteresis is included so that the ADP5056 does not return to
operation after thermal shutdown until the on-chip temperature
falls below 160°C. When the device exits thermal shutdown, a soft
start is initiated for each enabled channel.
Rev. 0 | Page 20 of 31
Data Sheet
ADP5056
APPLICATIONS INFORMATION
PROGRAMMING THE ADJUSTABLE OUTPUT
VOLTAGE
The maximum output voltage for a given input voltage and
switching frequency can be calculated using the following
equation:
The output voltage of the ADP5056 is externally set by a resistive
voltage divider from the output voltage to the FBx pin. To limit
the degradation of the output voltage accuracy due to feedback
bias current, ensure that the bottom resistor in the divider is not
too large. A value of less than 50 kΩ is recommended.
V
OUT_MAX = VIN × (1 − tMIN_OFF × fSW) − (RDSON_HS − RDSON_LS) ×
OUT_MAX × (1 − tMIN_OFF × fSW) − (RDSON_LS + RL) × IOUT_MAX (2)
where:
MIN_OFF is the minimum off time.
OUT_MAX is the maximum output current.
I
t
I
The equation for the output voltage setting is
As shown in Equation 1 and Equation 2, reducing the switching
frequency eases the minimum on time and off time limitations.
V
OUT = VREF × (1 + (RTOP/RBOT))
where:
V
V
OUT is the output voltage.
REF is the feedback reference voltage, 0.6 V for Channel 1 to
CURRENT-LIMIT SETTING
The ADP5056 has two selectable current-limit thresholds for
Channel 1, Channel 2, and Channel 3. Ensure that the selected
current-limit value is larger than the peak current of the inductor
(IPEAK) for the current-limit configuration for all channels.
Channel 3.
R
R
TOP is the feedback resistor from VOUT to FBx.
BOT is the feedback resistor from FBx to ground.
VOLTAGE CONVERSION LIMITATIONS
SOFT START SETTING
For a given input voltage, upper and lower limitations on the
output voltage exist due to the minimum on time and the
minimum off time.
The buck regulators in the ADP5056 include soft start circuitry
that ramps the output voltage in a controlled manner during
startup, thereby limiting the inrush current. To set the soft start
time to a value of 2.2 ms or 17.3 ms, connect a resistor from the
CFG2 pin to ground (see the Soft Start section).
The minimum on time limits the output voltage for a given
input voltage and switching frequency. The minimum on time
for Channel 1 to Channel 3 is 50 ns (maximum).
INDUCTOR SELECTION
In FPWM mode, Channel 1 and Channel 2 can skip the switching
pulses to maintain the output regulation when the minimum on
time limit is exceeded. Careful selection of switching frequency is
required to avoid this condition.
The inductor value is determined by the switching frequency,
input voltage, output voltage, and inductor ripple current. Using
a small inductor value yields faster transient response but may
degrade efficiency due to the larger inductor ripple current.
Using a large inductor value yields a smaller ripple current and
improved efficiency but results in slower transient response.
Thus, a trade-off must be made between transient response and
efficiency. As a guideline, the inductor peak-to-peak ripple
current, ΔIL, is typically set to a value from 30% to 40% of the
maximum load current. Use the following equation to calculate
the inductor value:
To calculate the minimum output voltage in CCM for a given
input voltage and switching frequency, use the following
equation:
V
OUT_MIN = VIN × tMIN_ON × fSW − (RDSON_HS − RDSON_LS) ×
OUT_MIN × tMIN_ON × fSW − (RDSON_LS + RL) × IOUT_MIN
where:
I
(1)
V
OUT_MIN is the minimum output voltage.
L = ((VIN − VOUT) × D)/(ΔIL × fSW)
VIN is the input voltage.
t
MIN_ON is the minimum on time.
where:
f
SW is the switching frequency.
VOUT is the output voltage.
R
R
DSON_HS is the on resistance of the high-side MOSFET.
DSON_LS is the on resistance of the low-side MOSFET.
D is the duty cycle (D = VOUT/VIN).
ΔIL is the inductor ripple current.
I
OUT_MIN is the minimum output current.
The ADP5056 has internal slope compensation in the current
loop to prevent subharmonic oscillations when the duty cycle is
greater than 50%.
RL is the resistance of the output inductor.
The maximum output voltage for a given input voltage and
switching frequency is limited by the minimum off time and the
maximum duty cycle.
Use the following equation to calculate the peak inductor
current:
IPEAK = IOUT + (ΔIL/2)
The saturation current of the inductor must be larger than the
peak inductor current. For ferrite core inductors with a fast
saturation characteristic, ensure that the saturation current rating
Rev. 0 | Page 21 of 31
ADP5056
Data Sheet
of the inductor is higher than the current-limit threshold of the
buck regulator to prevent the inductor from becoming saturated.
The effective series resistance (ESR) of the output capacitor and
the capacitance value of the output capacitor determine the
output voltage ripple. Use the following equations to select
output capacitors that can meet the output ripple requirements:
To avoid overheating and poor efficiency, an inductor must be
chosen with an rms current rating that is greater than the
calculated maximum rms current. Calculate the rms current of
the inductor by using the following equation:
IL
COUT _ RIPPLE
8 fSW VOUT _ RIPPLE
2
IL
12
VOUT _ RIPPLE
2
IRMS
IOUT
RESR
where:
IL
Shielded ferrite core materials are recommended for low core
loss and low electromagnetic interference (EMI). Table 8 lists
recommended inductors.
ΔIL is the inductor ripple current.
ΔVOUT_RIPPLE is the allowable output voltage ripple.
R
ESR is the equivalent series resistance of the output capacitor.
Table 8. Recommended Inductors
Select the largest output capacitance given by COUT_UV, COUT_OV
and COUT_RIPPLE to meet both load transient and output ripple
requirements.
,
Vendor
Coilcraft
Toko
Series1
XAL5030, XEL5030
FDUE0650
Wurth
WE-HCI, WE-XHMI
Ceramic capacitors have very low ESR and provide optimal
ripple performance. For recommended starting values, see the
Typical Application Circuits section. Use X5R or X7R type
capacitors to achieve low output ripple and small output
deviation during transient response. Transient performance can
be improved with a higher value output capacitor and the
addition of a feedforward capacitor placed between VOUTx
and FBx. Increasing the output capacitance also decreases the
output voltage ripple. A lower value output capacitor can be
used to save space and cost, but transient performance suffers
and may cause loop instability. See the Typical Application
Circuits section for suggested capacitor values.
1 Visit the Coilcraft, Toko, and Wurth manufacturer websites for more
information about the recommended series inductors.
OUTPUT CAPACITOR SELECTION
The selected output capacitor affects both the output voltage
ripple and the loop dynamics of the regulator. For example,
during load step transients on the output, when the load is
suddenly increased, the output capacitor supplies the load until
the control loop can ramp up the inductor current, causing an
undershoot of the output voltage.
To calculate the output capacitance required to meet the
undershoot (voltage droop) requirement, use the following
equation:
When choosing a capacitor, calculate the effective capacitance
under the relevant operating conditions of voltage bias and
temperature. A physically larger capacitor or a capacitor with a
higher voltage rating may be required.
KUV ISTEP2 L
COUT _UV
2 V VOUT V
IN
OUT _UV
INPUT CAPACITOR SELECTION
where:
UV is a factor (typically set to 2).
ΔISTEP is the load step.
The input decoupling capacitor attenuates high frequency noise on
the input and acts as an energy reservoir. Use a ceramic capacitor
and place it near to the PVINx pin. The loop composed of the
input capacitor, the high-side MOSFET, and the low-side
MOSFET must be kept as small as possible. The voltage rating of
the input capacitor must be greater than the maximum input
voltage. Ensure that the rms current rating of the input
capacitor is larger than the following equation:
K
ΔVOUT_UV is the allowable undershoot on the output voltage.
Another example of the effect of the output capacitor on the loop
dynamics of the regulator is when the load is suddenly removed
from the output and the energy stored in the inductor rushes into
the output capacitor, causing an overshoot of the output voltage.
To calculate the output capacitance required to meet the
overshoot requirement, use the following equation:
IC
IOUT D 1 D
_ rms
IN
KOV ISTEP2 L
COUT _OV
2
2
V
VOUT_OV VOUT
OUT
where:
OV is a factor (typically set to 2).
ΔISTEP is the load step.
ΔVOUT_OV is the allowable overshoot on the output voltage.
K
Rev. 0 | Page 22 of 31
Data Sheet
ADP5056
PROGRAMMING THE UVLO INPUT
1
fz
fp
2 RESR COUT
The precision enable input can program the UVLO threshold of
the input voltage, as shown in Figure 30.
1
The precision turn on threshold is 0.615 V, and the turn off
threshold is 0.575 V. Use the following equations to calculate the
resistive voltage divider for the programmable VIN turn on
voltage and the VIN turn off voltage:
2 R R
C
OUT
ESR
where COUT is the output capacitance.
The ADP5056 uses a transconductance amplifier as the error
amplifier to compensate the system. Figure 45 shows the
simplified peak current mode control small signal circuit.
V
V
IN_RISING = (3.5 μA + 0.615 V/RBOT_EN) × RTOP_EN + 0.615 V
IN_FALLING = (0.9 μA + 0.575 V/RBOT_EN) × RTOP_EN + 0.575 V
V
V
OUT
OUT
where:
R
R
TOP
V
IN_RISING is the VIN turn on voltage.
V
IN_FALLING is the VIN turn off voltage.
V
C
R
COMP
C
OUT
–
gm
+
–
A
VI
R
R
BOT_EN is the resistor from ENx to ground.
TOP_EN is the resistor from VIN to ENx.
+
R
BOT
R
C
CP
ESR
C
SLOPE COMPENSATION SETTING
C
The slope compensation is necessary in a current mode control
architecture to prevent subharmonic oscillation and to maintain
a stable output. The ADP5056 uses the emulated current mode,
and the slope compensation is implemented by connecting a
resistor (RRAMPX) from the RAMPx pin to ground.
Figure 45. Simplified Peak Current Mode Control Small Signal Circuit
The compensation components, RC and CC, contribute a zero.
RC and the optional CCP contribute an optional pole.
Theoretically, an extra slope of VOUT/(2 × L) is enough to stabilize
the system. To guarantee that any noise is decimated in one
cycle and the system is stable from subharmonic oscillation, the
ADP5056 uses an extra slope of VOUT/L.
The closed-loop transfer equation is as follows:
TV(s)
1 RC CC s
RC CC CCP
RBOT
gm
Gvd(s)
RBOT RTOP CC CCP
Calculate the ramp resistor values, RRAMPx, in kΩ, by using the
following equations:
s 1
s
CC CCP
R
R
R
RAMP1= L1 × 500
RAMP2 = L2 × 500
RAMP3 = L3 × 226
The following guidelines show how to select the compensation
components—RC, CC, and CCP—for ceramic output capacitor
applications.
1. Determine the cross frequency (fC). Generally, fC is between
fSW/12 and fSW/6.
2. Calculate RC using the following equation:
where L1, L2, and L3 are the inductor values in each channel,
in ꢀH.
COMPENSATION COMPONENTS DESIGN
2 VOUT COUT fC
RC
For current mode control, the power stage can be simplified as a
voltage controlled current source that supplies current to the
output capacitor and load resistor. The simplified loop is
composed of one domain pole and a zero contributed by the
output capacitor ESR. The control-to-output transfer function is
shown in the following equations:
0.6 gm AVI
3. Place the compensation zero at the domain pole (fP).
Calculate CC using the following equation:
(R RESR )COUT
CC
RC
s
1
1
4. CCP is optional. CCP can be used to cancel the zero caused
by the ESR of the output capacitor. Calculate CCP using the
following equation:
2 fz
V
OUT (s)
Gvd (s)
AVI R
VCOMP (s)
s
2 fp
R
ESR COUT
CCP
where:
RC
s is the domain in the control to output transfer function.
AVI = 12.5 A/V for Channel 1 and Channel 2, 5 A/V for Channel 3.
R is the load resistance.
fz is the zero frequency.
fp is the pole frequency.
Rev. 0 | Page 23 of 31
ADP5056
Data Sheet
Transition Loss (PTRAN
)
POWER DISSIPATION
The total power dissipation in the ADP5056 simplifies to
PD = PBUCK1 + PBUCK2 + PBUCK3
Transition losses occur because the high-side MOSFET cannot
turn on or off instantaneously. During a switch node transition,
the MOSFET provides all the inductor current. The source to
drain voltage of the MOSFET is half the input voltage, resulting
in power loss. Transition losses increase with both load and input
voltage and occur twice for each switching cycle. Use the following
equation to estimate the transition loss:
where:
PD is the power dissipation in the package.
P
P
P
BUCK1 is the power dissipation of Channel 1.
BUCK2 is the power dissipation of Channel 2.
BUCK3 is the power dissipation of Channel 3.
P
TRAN = 0.5 × VIN × IOUT × (tR + tF) × fSW
Buck Regulator Power Dissipation
where:
The power dissipation (PLOSS) for each buck regulator includes
power switch conduction losses (PCOND), switching losses (PSW),
and transition losses (PTRAN). Other sources of power dissipation
exist, but these sources are generally less significant at the high
output currents of the application thermal limit.
tR is the rise time of the switch node.
tF is the fall time of the switch node.
JUNCTION TEMPERATURE
The junction temperature of the die is the sum of the ambient
temperature of the environment and the temperature rise of the
package due to power dissipation, as shown in the following
equation:
Use the following equation to estimate the power dissipation of
the buck regulator:
P
LOSS = PCOND + PSW + PTRAN
TJ = TA + TR
Power Switch Conduction Loss (PCOND
)
where:
Power switch conduction losses are caused by the flow of output
current through both the high-side and low-side power switches.
Each of these switches has internal on resistance (RDSON).
TJ is the junction temperature.
TA is the ambient temperature.
TR is the rise in temperature of the package due to power
dissipation.
Use the following equation to estimate the power switch
conduction loss:
The rise in temperature of the package is directly proportional
to the power dissipation in the package. The proportionality
constant for this relationship is the thermal resistance from the
junction of the die to the ambient temperature, as shown in the
following equation:
2
P
COND = (RDSON_HS × D + RDSON_LS × (1 − D)) × IOUT
where:
R
R
DSON_HS is the on resistance of the high-side MOSFET.
DSON_LS is the on resistance of the low-side MOSFET.
TR = θJA × PD
Switching Loss (PSW
)
where:
Switching losses are associated with the current drawn by the
driver to turn the power devices on and off at the switching
frequency. Each time a power device gate is turned on or off,
the driver transfers a charge from the input supply to the gate,
and then from the gate to ground. Use the following equation to
estimate the switching loss:
θJA is the thermal resistance from the junction of the die to the
ambient temperature of the package (see Table 4).
An important factor to consider is that the thermal resistance
value is based on a 4-layer, 4 inch × 3 inch PCB with 2.5 oz. of
copper, as specified in the JEDEC standard, whereas real-world
applications may use PCBs with different dimensions and a
different number of layers.
P
SW = (CGATE_HS + CGATE_LS) × VIN2 × fSW
where:
It is important to maximize the amount of copper used to
remove heat from the device. Copper exposed to air dissipates
heat better than copper used in the inner layers. Connect Pin 35,
Pin 36, and Pin 37 to the ground plane with the maximum
number of vias.
C
C
GATE_HS is the gate capacitance of the high-side MOSFET.
GATE_LS is the gate capacitance of the low-side MOSFET.
Rev. 0 | Page 24 of 31
Data Sheet
ADP5056
TYPICAL APPLICATION CIRCUITS
ADP5056
RT 280kΩ
12V
VBIAS
VREG
V
INTERNAL
REG
C1
OSCILLATOR
V
REG
SYNC/MODE
4.7µF
C2
4.7µF
BST1
PVIN1
EN1
0.1µF
SW1
L1
VOUT1
180pF
1.0V/7A (9A PEAK)
C3
22µF
V
DIG
0.8µH
C4
C5
C6
100µF
CHANNEL 1
7A BUCK
100µF
100µF
FB1
RAMP1
20kΩ
402kΩ
PGND
30.1kΩ
COMP1
22.1kΩ
1nF
ASIC
BST2
SW2
PVIN2
EN2
0.1µF
L2
VOUT2
180pF
1.3V/7A (9A PEAK)
C8
22µF
V
ANA
0.8µH
CHANNEL 2
7A BUCK
C9
C10
C11
100µF
RAMP2
100µF
100µF
FB2
402kΩ
20kΩ
16.9kΩ
COMP2
PGND
22.1kΩ
1nF
BST3
SW3
PVIN3
0.1µF
L3
1.8V/3A (4A PEAK)
VOUT3
180pF
C13
10µF
V
EN3
AUX
2.2µH
C14
47µF
C15
47µF
C16
47µF
C17
47µF
CHANNEL 3
3A BUCK
RAMP3
FB3
20kΩ
499kΩ
PGND
10kΩ
COMP3
35.7kΩ
470pF
PWRGD
GND
GND
CFG1
CFG2
LOGIC
14.3kΩ
GND
START UP SEQUENCE: 1.0V 1.3V 1.8V
SHUTDOWN SEQUENCE: 1.8V 1.3V 1.0V
(EN1/EN2/EN3 TURNS ON/OFF TOGETHER)
Figure 46. Typical Application, 12 V Input, fSW = 600 kHz, VOUT1 = 1.0 V, VOUT2 = 1.3 V, VOUT3 = 1.8 V, Sequence Mode
Rev. 0 | Page 25 of 31
ADP5056
Data Sheet
ADP5056
12V
VBIAS
VREG
RT 280kΩ
INTERNAL
C1
OSCILLATOR
V
REG
V
4.7µF
REG
SYNC/MODE
C2
4.7µF
BST1
PVIN1
EN1
0.1µF
SW1
L1
VOUT1
1.0V/7A
C3
22µF
V
CORE
0.8µH
180pF
C4
100µF
C5
100µF
C6
100µF
CHANNEL 1
7A BUCK
FB1
RAMP1
20kΩ
402kΩ
PGND
4.42kΩ
COMP1
PROCESSOR
22.1kΩ
1nF
BST2
SW2
PVIN2
EN2
0.1µF
L2
VOUT2
3.3V/3.5A
C8
22µF
INPUT/OUTPUT
3.3µH
180pF
C9
100µF
C10
100µF
C11
CHANNEL 2
7A BUCK
RAMP2
100µF
FB2
1.5MΩ
20kΩ
COMP2
PGND
4.42kΩ
30.1kΩ
1.5nF
BST3
SW3
PVIN3
0.1µF
L3
VOUT3
1.5V/1.5A
C13
10µF
EN3
2.2µH
C14
47µF
C15
47µF
C16
47µF
180pF
CHANNEL 3
3A BUCK
RAMP3
DDR MEMORY
FB3
499kΩ
20kΩ
13.3kΩ
PGND
DDR
TERMINATION
LDO
COMP3
30.9kΩ
470pF
PWRGD
GND
GND
CFG1
CFG2
LOGIC
GND
Figure 47. Typical Application, 12 V Input, fSW = 600 kHz, VOUT1 = 1.0 V, VOUT2 = 3.3 V, VOUT3 = 1.5 V
Rev. 0 | Page 26 of 31
Data Sheet
ADP5056
ADP5056
280kΩ
RT
12V
VBIAS
VREG
INTERNAL
V
REG
C1
OSCILLATOR
V
4.7µF
REG
SYNC/MODE
C2
4.7µF
BST1
PVIN1
EN1
0.1µF
SW1
L1
VOUT1
C4
1.0V/14A
C3
22µF
0.8µH
180pF
C5
100µF
C6
100µF
C7
100µF
CHANNEL 1
7A BUCK
100µF
RAMP1
FB1
20kΩ
402kΩ
PGND
30.1kΩ
COMP1
C9
100µF
C10
100µF
22.1kΩ
1nF
BST2
SW2
FB2
PVIN2
EN2
0.1µF
L2
C8
22µF
0.8µH
CHANNEL 2
7A BUCK
RAMP2
402kΩ
PGND
COMP2
PVIN3
BST3
SW3
0.1µF
L3
VOUT3
C13
10µF
1.5V/3A
EN3
2.2µH
C14
47µF
C15
47µF
C16
180pF
CHANNEL 3
3A BUCK
47µF
RAMP3
FB3
499kΩ
20kΩ
13.3kΩ
PGND
COMP3
30.9kΩ
470pF
PWRGD
GND
GND
CFG1
CFG2
LOGIC
23.7Ω
GND
Figure 48. Typical Channel 1/Channel 2 Interleaved Parallel Application, 12 V Input, fSW = 600 kHz, VOUT1 = 1.0 V, VOUT3 = 1.5 V
Rev. 0 | Page 27 of 31
ADP5056
Data Sheet
DESIGN EXAMPLE
This section provides an example of the step by step design
procedures and the external components required for Channel 1.
Table 9 lists the design requirements for this example.
SETTING THE CONFIGURATIONS (CFG1 AND CFG2)
The CFG1 pin can program the load output capability and parallel
operation for all channels. For this example, choose RCFG1 = 0 Ω
(see Table 6).
Table 9. Example Design Requirements for Channel 1
The CFG2 pin can program the tSET timer (2.6 ms or 20.8 ms),
fast transient functionality, and sequence for the ADP5056. For
this example, choose RCFG2 = 0 Ω (see Table 7).
Parameter
Specification
Input Voltage
Output Voltage
Output Current
Output Ripple
Load Transient
VPVIN1 = 12 V ꢀ5
VOUT1 = 1.2 V
IOUT1 = 7 A
ΔVOUT1_RIPPLE = 12 mV in CCM mode
ꢀ5 at 2ꢀ5 to 7ꢀ5 load transient, 1 A/μs
SELECTING THE INDUCTOR
The peak-to-peak ΔIL is set to 35% of the maximum output
current. Use the following equation to estimate the value of the
inductor:
Although this example shows step by step design procedures for
Channel 1, the procedures apply to all other buck regulator
channels (Channel 1 to Channel 3).
L = ((VIN − VOUT) × D)/(ΔIL × fSW)
where:
VIN = 12 V.
SETTING THE SWITCHING FREQUENCY
The first step is to determine the switching frequency for the
ADP5056 design. In general, higher switching frequencies
produce a smaller solution size due to the lower component
values required, whereas lower switching frequencies result in
higher conversion efficiency due to lower switching losses.
V
OUT = 1.2 V.
D is the duty cycle (D = VOUT/VIN = 0.1).
ΔIL = 35% × 7 A = 2.45 A.
f
SW = 600 kHz.
The resulting value for L is 0.73 μH. The closest standard inductor
value is 0.8 μH. Therefore, ΔIL is 2.25 A.
The switching frequency of the ADP5056 can be set to a value from
250 kHz to 2500 kHz by connecting a resistor from the RT pin to
ground. The selected resistor allows the user to make decisions
based on the trade-off between efficiency and solution size.
Calculate the peak inductor current by using the following
equation:
I
PEAK = IOUT + (ΔIL/2)
However, the highest supported switching frequency must be
assessed by checking the voltage conversion limitations enforced
by the minimum on time and the minimum off time (see the
Voltage Conversion Limitations section).
The calculated peak current for the inductor is 8.125 A.
Use the following equation to calculate the rms current of the
inductor:
In this design example, a switching frequency of 600 kHz is
used to achieve an optimal combination of small solution size
and high conversion efficiency. To set the switching frequency
to 600 kHz and calculate the value of the resistor from the RT
pin to ground, RT, use the following equations:
2
IL
12
2
IRMS
IOUT
The rms current of the inductor is approximately 7.03 A.
Therefore, an inductor with a minimum rms current rating of
7.03 A and a minimum saturation current rating of 8.125 A is
required. However, to prevent the inductor from reaching the
saturation point in current-limit conditions, it is recommended
that the inductor saturation current be higher than the maximum
peak current limit, typically 11.65 A, for reliable operation.
167,305
RT kΩ =
0.998
fSW kHz
167,305
RT kΩ =
= 280 kΩ
6000.998
Based on these requirements and recommendations, the
XAL5030-801ME, with a dc resistance of 5.14 mΩ, was selected
for this design.
Therefore, select the closest standard 1% resistor value for RT =
280 kΩ.
SETTING THE OUTPUT VOLTAGE
Select a 10 kΩ bottom resistor (RBOT) and then calculate the top
feedback resistor by using the following equation:
R
BOT = RTOP × (VREF/(VOUT − VREF))
where VREF is 0.6 V for Channel 1.
To set the output voltage to 1.2 V, choose the following resistor
values: RTOP = 10 kΩ, RBOT = 10 kΩ.
Rev. 0 | Page 28 of 31
Data Sheet
ADP5056
SELECTING THE OUTPUT CAPACITOR
DESIGNING THE COMPENSATION NETWORK
The output capacitor must meet the output voltage ripple and
load transient requirements. To meet the output voltage ripple
requirement, use the following equations to calculate the ESR
and capacitance:
For improved load transient and stability performance, set the
fC to fSW/10. In this example, fSW is set to 600 kHz. Therefore, fC
is set to 60 kHz.
For the 1.2 V output rail, the 47 μF ceramic output capacitor has
a derated value of 40 μF.
IL
COUT _ RIPPLE
8 fSW VOUT _ RIPPLE
Choose standard components: RC = 24.9 kΩ and CC = 1 nF. CCP
is optional.
VOUT _ RIPPLE
RESR
Figure 49 shows the Bode plot for the 1.2 V output rail. The cross
frequency is 58 kHz, and the phase margin is 63°.
IL
The calculated capacitance, COUT_RIPPLE, is 39 μF, and the calculated
RESR is 5.3 mΩ.
50
200
160
120
80
40
To meet the 5% overshoot and undershoot requirements, use
the following equations to calculate the capacitance:
30
20
KUV ISTEP2 L
10
40
COUT _UV
2 V VOUT V
0
0
IN
OUT _UV
–10
–20
–30
–40
–50
–40
–80
–120
–160
–200
KOV ISTEP2 L
COUT _OV
2
V
VOUT_OV VOUT
2
OUT
For estimation purposes, use KOV = KUV = 2. Therefore,
COUT_OV = 133 μF and COUT_UV = 15.1 μF.
100
1k
10k
100k
1M
The ESR of the output capacitor must be less than 5.3 mΩ, and
the output capacitance must be greater than 133 μF. It is
recommended that three ceramic capacitors be used (47 μF,
X5R, and 6.3 V), such as the GRM21BR60J476ME15 from
Murata with an ESR of 2 mΩ.
FREQUENCY (Hz)
Figure 49. Bode Plot for 1.2 V Output
SELECTING THE INPUT CAPACITOR
For the input capacitor, select a ceramic capacitor with a minimum
value of 10 μF. Place the input capacitor near to the PVIN1 pin.
In this example, one 10 μF, X5R, 25 V ceramic capacitor is
recommended.
Rev. 0 | Page 29 of 31
ADP5056
Data Sheet
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Optimal circuit board layout is essential to obtain the best
performance from the ADP5056 (see Figure 50). Poor layout
can affect the regulation and stability of the device, as well as
the EMI and electromagnetic compatibility (EMC) performance.
Refer to the following guidelines for an optimal PCB layout:
Maximize the amount of ground metal connecting Pin 35,
Pin 36, and Pin 37, and use as many vias as possible on the
component side to improve thermal dissipation.
Use a ground plane with several vias connecting to the
component side ground to further reduce noise interference
on sensitive circuit nodes.
Place the input capacitor, inductor, output capacitor, and
bootstrap capacitor near to the IC.
Place the decoupling capacitors near to the VREG pin and
VBIAS pin.
Use short, thick traces to connect the input capacitors to
the PVINx pins, and use dedicated power ground to connect
the input and output capacitor grounds to minimize the
connection length.
Place the frequency setting resistor near to the RT pin.
Place the feedback resistor divider near to the FBx pin. In
addition, keep the FBx traces away from the high current
traces and the switch node to avoid noise pickup.
Use size 0402 or 0603 resistors and capacitors to achieve
the smallest possible footprint solution on boards where
space is limited.
Use several high current vias, if required, to connect PVINx
and PGND to other power planes.
Use short, thick traces to connect the inductors to the SWx
pins and the output capacitors.
Ensure that the high current loop traces are as short and
wide as possible.
For recommended PCB assembly and manufacturing
procedures, visit the μModule® design and manufacturing
resources page.
Figure 50. Typical PCB Layout for the ADP5056
Rev. 0 | Page 30 of 31
Data Sheet
ADP5056
OUTLINE DIMENSIONS
5.15
5.00
4.85
0.10
0.115 BSC
BSC
0.35
0.30
0.25
3.35 BSC
A1
CORNER
AREA
6
3
7
5
4
2
1
A
B
C
D
E
F
0.30
0.25
0.20
0.38
BSC
0.50
BSC
5.65
5.50
5.35
0.215
BSC
4.00 REF
G
H
J
DETAIL A
0.55
0.50
0.45
0.70
0.65
0.60
1.13
BSC
K
0.375
0.90
0.85
0.80
0.375
BSC
BSC
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.10
BSC
0.50
BSC
0.30
0.25
0.20
0.115
BSC
0.913
0.863
0.813
0.68 REF
DETAIL A
0.65
0.60
0.55
0.30
BSC
0.213
0.183
0.153
0.30
0.25
0.20
SEATING
PLANE
Figure 51. 43-Terminal Land Grid Array [LGA]
(CC-43-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
ADP5056ACCZ-R7
ADP5056-EVALZ
−40°C to +150°C
43-Terminal Land Grid Array [LGA]
Evaluation Board
CC-43-1
1 Z = RoHS Compliant Part.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D17270-5/20(0)
Rev. 0 | Page 31 of 31
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