ADP5003CP-EVALZ_技术文档

Low Noise Micro PMU,

3 A Buck Regulator with 3 A LDO

ADP5003

Data Sheet

FEATURES

Low noise, dc power supply system

FUNCTIONAL BLOCK DIAGRAM

V

:

PVIN1

4.2V TO 15V

PVIN1

High efficiency buck for first stage conversion

High PSRR, low noise LDO regulator to remove switching

ripple

Adaptive LDO regulator headroom control option for

optimal efficiency and PSRR across full load range

3 A, low noise, buck regulator

C

EN1

PVIN1

VOUT1

V

:

SW1

COMP1

PVOUT1

BUCK

REGULATOR

3A

L1

0.6V TO 5.0V

R

C

R

C

PVOUT1

R

BOT1

VSET1

PGND1

TOP1

Wide input voltage range: 4.2 V to 15 V

Programmable output voltage range: 0.6 V to 5.0 V

0.3 MHz to 2.5 MHz internal oscillator

VREG

R

RT

C

VREG

V

:

PVINSYS

4.2V TO 15V

PVINSYS

PWRGD

SYSTEM

0.3 MHz to 2.5 MHz SYNC frequency range

3 A, low noise, NFET LDO regulator (active filter)

Wide input voltage range: 0.65 V to 5 V

Programmable output voltage range: 0.6 V to 3.3 V

Differential point of load remote sensing

3 µV rms output noise (independent of output voltage)

PSRR > 50 dB (to 100 kHz) with 400 mV headroom at 3 A

Ultrafast transient response

C

PVINSYS

SYNC

REFOUT

C

REFOUT

PVIN2

C

PVIN2

VSET2

VBUF

V

:

PVOUT2

0.6V TO 3.3V

LOW NOISE

LDO ACTIVE

FILTER

C

VBUF

Power-good output

3A

C

VREG_LDO

PVOUT2

LOAD

Precision enable inputs for both the buck regulator and LDO

−40°C to +125°C operating junction temperature range

32-lead, 5 mm × 5 mm, LFCSP

C

VREG_LDO

VFB2P

VFB2N

EN2

AGND1

AGND2

APPLICATIONS

Low noise power for high speed analog-to-digital converter

(ADC) and digital-to-analog converter (DAC) designs

Powering RF transceivers and clocking ICs

Figure 1.

GENERAL DESCRIPTION

The ADP5003 integrates a high voltage buck regulator and an

ultralow noise low dropout (LDO) regulator in a small, 5 mm ×

5 mm, 32-lead LFCSP package to provide highly efficient and

quiet regulated supplies.

programmed using resistor dividers.

The LDO regulator output can be accurately controlled at the

point of load (POL) using remote sensing that compensates for the

printed circuit board (PCB) trace impedance while delivering

high output currents.

The buck regulator is optimized to operate at high output

currents up to 3 A. The LDO is capable of a maximum output

current of 3 A and operates efficiently with low headroom

voltage while maintaining high power supply rejection.

Each regulator is activated via a dedicated precision enable

input. The buck switching frequency can be synchronized to

an external signal, or programmed with an external resistor.

The ADP5003 can operate in one of two modes. Adaptive mode

allows the LDO to operate with an optimized headroom by

adjusting the buck output voltage internally in response to the

LDO load current. Alternatively, the ADP5003 can operate in

independent mode, where both regulators operate separately

from each other, and where the output voltages are

Safety features in the ADP5003 include thermal shutdown (TSD),

input undervoltage lockout (UVLO) and independent current

limits for each regulator. The ADP5003 is rated for a −40°C to

+125°C operating junction temperature range.

Rev. A

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ADP5003

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Setting the Switching Frequency for the Buck Regulator ....... 22

Setting the Output Voltage for the Buck Regulator ................. 22

Selecting the Inductor for the Buck Regulator ......................... 22

Selecting the Output Capacitor for the Buck Regulator.......... 22

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 3

Specifications..................................................................................... 4

Buck Regulator Specifications .................................................... 5

LDO Specifications ...................................................................... 6

Adaptive Headroom Controller Specifications ........................ 6

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 15

Power Management Unit........................................................... 15

Buck Regulator............................................................................ 15

LDO Regulator............................................................................ 17

Power-Good ................................................................................ 18

Output Voltage of the Buck Regulator..................................... 18

Output Voltage of the LDO Regulator..................................... 18

Voltage Conversion Limitations ............................................... 18

Component Selection................................................................. 19

Compensation Components Design........................................ 21

Junction Temperature ................................................................ 21

Buck Regulator Design Example .................................................. 22

Designing the Compensation Network for the Buck Regulator

....................................................................................................... 23

Selecting the Input Capacitor for the Buck Regulator............. 23

Adaptive Headroom Control Design Example .......................... 24

Setting the Switching Frequency for the Buck Regulator Using

Adaptive Headroom Control.................................................... 24

Setting the Output Voltage for the LDO Regulator Using

Adaptive Headroom Control.................................................... 24

Selecting the Inductor for the Buck Regulator Using Adaptive

Headroom Control..................................................................... 24

Selecting the Output Capacitors for the Buck Regulator Using

Adaptive Headroom Control.................................................... 24

Designing the Compensation Network for the Buck

Regulator Using Adaptive Headroom Control....................... 25

Selecting the Input Capacitor for the Buck Regulator Using

Adaptive Headroom Control.................................................... 25

Recommended External Components for the Buck Regulator

....................................................................................................... 26

Buck Configurations ...................................................................... 28

Independent................................................................................ 28

Adaptive Headroom................................................................... 29

Layout Considerations................................................................... 30

Outline Dimensions....................................................................... 31

Ordering Guide .......................................................................... 31

Rev. A | Page 2 of 31

Data Sheet

ADP5003

REVISION HISTORY

Changes to Compensation Components Design Section,

3/2019—Rev. 0 to Rev. A

Figure 46 and Junction Temperature Section..............................21

Changes to Table 10, Setting the Switching Frequency for the

Buck Regulator Section, Setting the Output Voltage for the

Buck Regulator Section, Selecting the Inductor for the Buck

Regulator Section, and Selecting the Output Capacitor for the

Buck Regulator Section ..................................................................22

Deleted Figure 44; Renumbered Sequentially.............................22

Changes Figure 47...........................................................................23

Changes to Table 11, Setting the Output Voltage for the LDO

Regulator Using Adaptive Headroom Control Section, and

Selecting the Inductor for the Buck Regulator Using Adaptive

Headroom Control Section ...........................................................24

Changes Figure 48...........................................................................25

Changes to Recommended External Components for the Buck

Regulator Section and Table 12 Title............................................26

Changes to Figure 49 Caption and Figure 50..............................28

Changes to Adaptive Headroom Section and Figure 52............29

Changes to Layout Considerations Section and Figure 53........30

Updated Outline Dimensions........................................................31

Changes to Applications Section, General Description, and

Figure 1 ...............................................................................................1

Changes to Table 1 ............................................................................4

Changes to Table 2 ............................................................................5

Changes to Table 3 ............................................................................6

Changes to Table 5 ............................................................................7

Changes to Table 7 ............................................................................8

Updated Typical Performance Characteristics Section;

Renumbered Sequentially ................................................................9

Changes to Adaptive Headroom Control Section, Active Pull

Down Section, and Power-Good Section ....................................15

Changes to Oscillator Frequency Control Section .....................16

Add Figure 38 and Figure 39 .........................................................16

Changes to Current-Limit and Short-Circuit Protection

Section and Current Limit Section ...............................................17

Changes to Output Voltage of the Buck Regulator Section,

Figure 44, Output Voltage of the LDO Regulator Section,

Figure 45, and Voltage Conversion Limitations Section............18

Changes to Input Capacitor Section, Inductor Section, and

Table 9...............................................................................................20

11/2017—Revision 0: Initial Version

Rev. A | Page 3 of 31

ADP5003

Data Sheet

SPECIFICATIONS

V_PVIN1= V_PVINSYS= 4.2 V to 15 V, V_PVIN2= 0.65 V to 5 V, T_J= −40°C to +125°C for minimum/maximum specifications, and T_A= 25°C for

typical specifications, unless otherwise noted.

Table 1.

Parameter

Symbol

Min Typ Max Unit Test Conditions/Comments

INPUT VOLTAGE RANGE

V_PVIN1, V_PVINSYS4.2

15

5

V

V_PVIN2

0.65

THERMAL SHUTDOWN

Threshold

Hysteresis

T_SD

T_SD-HYS

155

15

°C

T_Jrising

SYNC INPUT

Input Logic

High

V_IH

1.1

V

Low

V_IL

V_I-LEAKAGE

0.4

1

V

µA

Input Leakage Current

ADAPTIVE MODE INPUT (VSET1)

Input Rising Threshold

Input Hysteresis

V_ADPR

V_ADPH

2.5

16

V

mV

PRECISION ENABLING

High Level Threshold

Low Level Threshold

Shutdown Mode

EN1, EN2 Pull-Down Resistance

INPUT CURRENT

V_{TH_H}

V_{TH_L}

V_{TH_S}

R_ENPD

1.125 1.15 1.175 V

1.025 1.05 1.075 V

0.4

V

1.5

MΩ

Both Channels Enabled

Both Channels Disabled

REFOUT CHARACTERISTICS

Output Voltage

I_STBY-NOSW

I_SHUTDOWN

0.5

5

1

10

mA No load, not switching

µA T_J= −40°C to +125°C

V_REFOUT

2.0

5

V

%

Accuracy

−0.5

+0.5

+2

VREG AND VREG_LDO CHARACTERISTICS

Output Voltage

Accuracy

Current Limit¹

V_REG, V_{REG_LDO}

V

%

mA

−2

10

POWER-GOOD PIN (PWRGD)

Power Good Threshold

Hysteresis

Output Voltage Level

Deglitch Time

PWRGD_F

PWRGD_FH

V_OL

80

85 90

2.5

25 50

60

%

Applies to VOUT1 and VFB2P to VFB2N

mV PWRGD pin sink current = 1 mA

µs

t_PWRGDD

PVINSYS UNDERVOLTAGE LOCKOUT (UVLO)

Input Voltage

Rising

Falling

UVLO_PVINSYSRISE

UVLO_PVINSYSFALL3.9

4.2

V

¹Do not use VREG and VREG_LDO to supply the external loads. This current limit protects against a pin short to ground.

Rev. A | Page 4 of 31

Data Sheet

ADP5003

BUCK REGULATOR SPECIFICATIONS

V_PVIN1= V_PVINSYS= 4.2 V to 15 V, V_PVIN2= 0.65 V to 5 V, T_J= −40°C to +125°C for minimum/maximum specifications, and T_A= 25°C for typical

specifications, unless otherwise noted.

Table 2.

Parameter

Symbol

Min Typ

Max Unit Test Conditions/Comments

OUTPUT CHARACTERISTICS

Programmable Output Voltage Range¹

Buck Regulator Gain

Error Amplifier Transconductance

Buck Output Voltage Accuracy²

Regulation

V_PVOUT1

A_BUCK

g_m1

0.6

5.0

V

2.5

509 600

−1

V_PVOUT1/V_VSET1

661

+1

µS

%

VOUT1 load current (I_LOAD1) = 10 mA

Line

Load

(ΔV_PVOUT1/V_PVOUT1)/ΔV_PVIN1

(ΔV_PVOUT1/V_PVOUT1)/ΔI_LOAD1

0.004

0.04

1.5

%/V I_LOAD1= 10 mA

%/A 0 mA ≤ I_LOAD1≤ 3 A, V_PVIN1= 12 V

Total Output Voltage Accuracy

OPERATING SUPPLY CURRENT

%

4.2 V ≤ V_PVIN1≤ 15 V, 1 mA ≤ I_LOAD1≤ 3 A

I_IN

3.8

mA

I_LOAD1= 0 mA, LDO disabled, buck

switching

SW1 CHARACTERISTICS

SW1 On Resistance

R_PFET

R_NFET

I_LIMIT1

130

60

200

100

mΩ

A

V_PVIN1= 15 V (PVIN1 to SW1)

V_PVIN1= 15 V (SW1 to PGND1)

Negative channel field effect

transistor (NFET) switch valley

current limit

Current Limit Threshold

3.5

−1

A

Negative current limit

Slew Rate

SLEW_SW1

t_{MIN_ON}

t_{MIN_OFF}

R_PDWN-B

t_SSBUCK

1.6

35

100

90

2

V/ns V_PVIN1= 15 V, I_LOAD1= 1 A

ns

Minimum On Time³

Minimum Off Time

128

BUCK REGULATOR ACTIVE PULL DOWN

BUCK REGULATOR SOFT START (SS)

HICCUP TIME

Ω

Channel disabled

ms

nA

t_HICCUP

33

10

VSETx ADJUSTABLE INPUT BIAS CURRENT

OSCILLATOR

I_VSET1, I_VSET2

150

Internal Switching Frequency 1

Internal Switching Frequency 2

SYNC

f_SW1

f_SW2

2.25 2.5

0.26 0.3

2.75 MHz R_RT≤ 71.2 kΩ

0.34 MHz R_RT= 600 kΩ

Frequency Range

f_SYNC

0.3

2.5

MHz

Minimum Pulse Width

Positive

Negative

20

10

ns

¹The switching frequency, minimum on time, and minimum off time may limit the output voltage range.

²The buck output voltage accuracy is relative to the nominal output voltage and accounts for reference voltage, gain, and offset error.

³The minimum on time indicates the minimum high-side turn on time to ensure fixed frequency switching.

Rev. A | Page 5 of 31

ADP5003

Data Sheet

LDO SPECIFICATIONS

V_PVIN1= V_PVINSYS= 4.2 V to 15 V, V_PVIN2= 0.65 V to 5 V, LDO headroom voltage (V_HR) = 300 mV, T_J= −40°C to +125°C for

minimum/maximum specifications, and T_A= 25°C for typical specifications, unless otherwise noted.

Table 3.

Parameter

Symbol

Min Typ

Max Unit

Test Conditions/Comments

OUTPUT CHARACTERISTICS

Programmable Output Voltage Range¹

LDO Gain

V_LDO

A_LDO

0.6

1.65

−1

3.3

+1

V

V_VFB2P-VFB2N

V_LDO/V_VSET2

VOUT2 load current (I_LOAD2) =

150 mA

Output Voltage Accuracy²

%

Regulation

Line

(ΔV_LDO/V_LDO)/ΔV_PVIN2

(ΔV_LDO/V_LDO)/ΔI_LOAD2

0.007

%/V

(V_PVOUT2+ V_HR) ≤ V_PVIN2≤ 6 V,

I

_LOAD2= 100 mA

Load

0.08

1.5

%/A

%

10 mA ≤ I_LOAD2≤ 3 A

(V_PVOUT2+ V_HR) ≤ V_PVIN2≤ 6 V,

10 mA ≤ I_LOAD2≤ 3 A

Total Output Voltage Accuracy

OPERATING SUPPLY CURRENT

I_GND

1.8

2.3

2.5

4.5

mA

I_LOAD2= 0 μA

I_LOAD2= 3 A

MINIMUM VOLTAGE REQUIREMENTS

PVINSYS to PVOUT2³

VREG_LDO to PVOUT2⁴

Dropout⁵

CURRENT-LIMIT THRESHOLD⁶

LDO SOFT START (SS) TIME

LDO ACTIVE PULL-DOWN

OUTPUT NOISE

V_{PVINSYS-PVOUT2}

V_{VREG_LDO-PVOUT2}

V_DROPOUT

I_LIMIT2

1.5

1.35

100

V

mV

A

Required to drive NFET

3.1

t_SSLDO

400

µs

Ω

R_PDWNLDO

N_PVOUT2

300

Channel disabled

3

µV rms 10 Hz to 100 kHz, I_LOAD2= 1 A

V_PVIN2= V_PVOUT2+ 0.3 V, I_LOAD2= 1A

LDO POWER SUPPLY REJECTION RATIO

V_PVOUT2= 1.3 V

PSRR_LDO

87

82

61

38

89

83

61

37

dB

1 kHz

10 kHz

100 kHz

1000 kHz

1 kHz

10 kHz

100 kHz

1000 kHz

V_PVOUT2= 3.3 V

¹Limited by minimum PVINSYS to PVOUT2 and VREG_LDO to PVOUT2 voltage.

²The LDO output voltage accuracy is relative to the nominal output voltage and accounts for reference voltage, gain, and offset error.

³PVINSYS must be higher than PVOUT2 by at least V_{PVINSYS-PVOUT2}to keep the LDO regulating.

⁴PVOUT2 must be lower than VREG_LDO by at least V_{VREG_LDO-PVOUT2}to keep the LDO regulating.

⁵The dropout voltage is the input to output voltage differential when the input voltage is set to the nominal output voltage.

⁶The current-limit threshold is the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V output

voltage is the current that causes the output voltage to drop to 90% of 1.0 V or 0.9 V.

ADAPTIVE HEADROOM CONTROLLER SPECIFICATIONS

V_PVIN1= V_PVINSYS= 4.2 V to 15 V, V_PVIN2= 0.65 V to 5 V, T_J= −40°C to +125°C for minimum/maximum specifications, and T_A= 25°C for typical

specifications, unless otherwise noted.

Table 4.

Parameter

HEADROOM VOLTAGE (PVIN2 − PVOUT2)

Symbol

V_HR

Min

Typ

160

280

400

Max

Unit

mV

Test Conditions/Comments

I_LOAD2= 1 mA

I_LOAD2= 1.5 A

I_LOAD2= 3 A

Rev. A | Page 6 of 31

Data Sheet

ADP5003

ABSOLUTE MAXIMUM RATINGS

Table 5.

THERMAL RESISTANCE

Thermal performance is directly linked to PCB design and

operating environment. Careful attention to PCB thermal

design is required.

Parameter

Rating

PVIN1/PVINSYS to AGND1/AGND2

PVIN2 to AGND1/AGND2

AGND1 to AGND2

PGND1 to AGND1/AGND2

PVOUT2 to AGND1/AGND2

−0.3 V to +16 V

−0.3 V to +6.0 V

−0.3 V to +0.3 V

−0.3 V to the lower of

(PVIN2 + 0.3 V) or +6.0 V

Table 6. Thermal Resistance

1

Package Type

θ_JA

θ_JC

20.95

Unit

°C/W

CP-32-7

46.91

¹θ_JAand θ_JCare based on a 4-layer PCB (two signal and two power planes)

with nine thermal vias connecting the exposed pad to the ground plane as

recommended in the Layout Considerations section.

VFB2N to AGND1/AGND2/PGND1

−0.3 V to +0.3 V

−0.3 V to the lower of (VREG

+ 0.3 V) or +6.0 V

VOUT1, VFB2P, EN1, EN2, SYNC, RT,

REFOUT, VBUF, VSET1, VSET2,

COMP1 to AGND1/AGND2

SW1 to PGND1

VREG, VREG_LDO to

−0.3 V to (PVIN1 + 0.3 V)

−0.3 V to the lower of

ESD CAUTION

AGND1/AGND2/PGND1/VFB2N

(PVINSYS + 0.3 V) or +6.0 V

VREG to VREG_LDO

Storage Temperature Range

Operating Junction Temperature

Range

−0.3 V to +0.3 V

−65°C to +150°C

−40°C to +125°C

Soldering Conditions

JEDEC J-STD-020

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Rev. A | Page 7 of 31

ADP5003

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

24 AGND1

23

22 RT

PGND1

VOUT1

EN1

1

2

3

4

5

6

7

8

VREG

ADP5003

21 COMP1

EN2

TOP VIEW

20

19

18

PWRGD

VSET1

REFOUT

SYNC

PVIN2

(Not to Scale)

17 VSET2

NOTES

1. EXPOSED THERMAL PAD. CONNECT THE

EXPOSED THERMAL PAD TO AGND1.

Figure 2. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic Description

1, 31, 32

2

3

PGND1

VOUT1

EN1

Buck Regulator Dedicated Power Ground.

Buck Regulator Feedback Input. Connect a short sense trace to the buck output capacitor.

Buck Regulator Precision Enable Pin. Drive the EN1 pin high to turn on the buck regulator, and drive the EN1 pin

low to turn off the buck regulator.

4

5

EN2

LDO Precision Enable Pin. Drive the EN2 pin high to turn on the LDO regulator, and drive the EN2 pin low to turn

off the LDO regulator.

Synchronization Input. To synchronize the switching frequency of the device to an external clock, connect this

pin to an external clock with a frequency from 300 kHz to 2.5 MHz.

SYNC

6 to 8

9 to 11

12

PVIN2

PVOUT2

VFB2P

LDO Regulator Power Input. Connect a 10 µF ceramic capacitor between this pin and AGND2.

LDO Regulator Power Output. Connect a 10 µF ceramic capacitor between this pin and AGND2.

LDO Regulator Positive Sense Feedback Input. Connect a sense trace to the LDO output at the load. Route this

pin alongside the VFB2N pin on the PCB.

13

VFB2N

LDO Regulator Ground Sense Feedback Input. Connect a sense trace to ground at the load. Route this pin

alongside the VFB2P pin on the PCB.

14

15

16

VBUF

AGND2

VREG_LDO

Output of the LDO Reference Buffer. Connect a 0.1 µF ceramic capacitor between this pin and VFB2N.

LDO Dedicated Analog Ground.

Internal Regulator Output for the LDO. Connect a 1 µF ceramic decoupling capacitor between this pin and

AGND2. Do not use this pin to power external devices.

17

18

VSET2

REFOUT

LDO Regulator Output Voltage Configuration Input.

Internal Reference Output Required for Driving the External Resistor Dividers for VSET1 and VSET2. Connect a

0.22 µF ceramic capacitor between this pin and AGND2.

19

VSET1

Buck Regulator Output Voltage Configuration Input. Connect this pin to VREG to enable adaptive headroom

control.

20

21

22

23

PWRGD

COMP1

RT

Power-Good Digital Output (Open-Drain NFET Pull-Down Driver).

Buck Regulator External Compensation Pin.

Resistor Adjustable Frequency Programming Input.

Internal Regulator Output. Connect a 1 µF ceramic decoupling capacitor between this pin and AGND1. Do not

use this pin to power external devices.

VREG

24

25

26, 27

28 to 30

AGND1

PVINSYS

PVIN1

SW1

Analog Ground.

System Power Supply for the ADP5003. Connect a 10 µF ceramic capacitor between this pin and AGND1.

Buck Regulator Power Input. Connect a 10 µF ceramic capacitor between this pin and PGND1.

Buck Regulator Switching Output.

EPAD

Exposed Thermal Pad. Connect the exposed thermal pad to AGND1.

Rev. A | Page 8 of 31

Data Sheet

ADP5003

TYPICAL PERFORMANCE CHARACTERISTICS

100

90

80

70

60

50

40

30

20

10

0

90

80

70

60

50

40

30

3.3V

2.5V

1.8V

1.3V

1.1V

20

10

0

3.3V

2.5V

1.8V

1.3V

1.1V

0

0.5

1.0

1.5

2.0

2.5

3.0

0

0.5

1.0

1.5

2.0

2.5

3.0

LOAD CURRENT (A)

Figure 6. Adaptive Mode Efficiency vs. Load Current, V_PVIN1= 5 V,

f_SW= 600 kHz at Various LDO Output Voltages

Figure 3. Buck Efficiency vs. Load Current, V_PVIN1= 5 V, f_SW= 600 kHz at

Various Buck Output Voltages

100

90

80

70

60

50

40

30

90

80

70

60

50

40

30

20

3.3V

2.5V

1.8V

1.3V

1.1V

20

10

0

3.3V

2.5V

1.8V

1.3V

1.1V

10

0

0.5

1.0

1.5

2.0

2.5

3.0

0

0.5

1.0

1.5

2.0

2.5

3.0

LOAD CURRENT (A)

Figure 7. Adaptive Mode Efficiency vs. Load Current, V_PVIN1= 12 V,

f_SW= 600 kHz at Various LDO Output Voltages

Figure 4. Buck Efficiency vs. Load Current, V_PVIN1= 12 V, f_SW= 600 kHz at

Various Buck Output Voltages

90

80

70

60

50

40

30

20

100

90

80

70

60

50

40

30

20

300kHz

10

0

10

0

600kHz

1MHz

0

0.5

1.0

1.5

2.0

2.5

3.0

0

0.5

1.0

1.5

2.0

2.5

3.0

LOAD CURRENT (A)

Figure 5. Buck Efficiency vs. Load Current, V_PVIN1= 12 V, V_PVOUT1= 3.3 V at

Various Buck Switching Frequencies

Figure 8. Adaptive Mode Efficiency vs. Load Current, V_PVIN1= 12 V,

V_PVOUT2= 3.3 V at Various Buck Switching Frequencies

Rev. A | Page 9 of 31

ADP5003

Data Sheet

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0.1A

1A

2A

3A

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

2A

3A

1

10

100

1k

10k

100k

1M

10M

1

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 9. LDO PSRR vs. Frequency, V_HR= 0.3 V, V_PVOUT2= 1.3 V at

Various LDO Load Currents

Figure 12. LDO PSRR vs. Frequency, V_HR= 0.3 V, V_PVOUT2= 3.3 V at

Various LDO Load Currents

0

0.2V

0.3V

0.4V

0.5V

0.3V

–10

0.4V

0.5V

–20

–30

–40

–50

–60

–70

–80

–90

–100

–30

–40

–50

–60

–70

–80

–90

–100

1

10

100

1k

10k

100k

1M

10M

1

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 13. LDO PSRR vs. Frequency, V_PVOUT2= 3.3 V, I_LOAD2= 1 A at Various LDO

Headroom Voltages

Figure 10. LDO PSRR vs. Frequency, V_PVOUT2= 1.3 V, I_LOAD2= 1 A at Various LDO

Headroom Voltages

1000

0.1A

1A

1000

0.9V

3.3V

3A

100

10

1

100

10

1

V

= 3.3V

PVOUT2

I

= 1A

PVOUT2

0.1

1

10

100

1k

10k

100k

1M

10M

1

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 14. LDO Noise Spectral Density vs. Frequency, V_PVOUT2= 3.3 V at

Various LDO Load Currents

Figure 11. LDO Noise Spectral Density vs. Frequency at Various LDO Output

Voltages

Rev. A | Page 10 of 31

Data Sheet

ADP5003

0.5

0.4

100000

10000

1000

100

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

10

1

3A

2A

1A

0.1

10

100

1k

10k

100k

1M

10M

0

0.5

1.0

1.5

2.0

2.5

3.0

FREQUENCY (Hz)

LOAD CURRENT (A)

Figure 15. Adaptive Mode Noise Spectral Density vs. Frequency at various

Load Currents, V_PVOUT1= V_PVIN2=3.7 V, V_PVOUT2= 3.3 V, f_SW= 2 MHz, L = 1.5 μH,

R_C= 23.7 kΩ, C_C= 1 nF, C_CP= 10 pF, C_PVOUT1= 22 μF

Figure 18. Buck Load Regulation, V_PVIN1= 12 V, V_PVOUT1= 3.3 V, f_SW= 600 kHz

0.5

0.4

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

0

0.5

1.0

1.5

2.0

2.5

3.0

4.2 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0

LOAD CURRENT (A)

INPUT VOLTAGE (V)

Figure 16. Buck Line Regulation, V_PVOUT1= 3.3 V, I_LOAD1= 1 A, f_SW= 600 kHz

Figure 19. LDO Load Regulation, V_PVOUT2= 3.3 V, V_HR= 0.3 V

0.5

0.4

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

–50

–20

10

40

70

100

130

HEADROOM (V)

TEMPERATURE (°C)

Figure 17. LDO Line Regulation, V_PVOUT2= 3.3 V, I_LOAD2= 1 A

Figure 20. REFOUT Voltage (V_REFOUT) vs. Temperature

Rev. A | Page 11 of 31

ADP5003

Data Sheet

3

3.0

2.5

2.0

1.5

1.0

0.5

0

2

1

0

–1

–2

–3

–50

4

6

8

10

12

14

–20

10

40

70

100

130

INPUT VOLTAGE (V)

TEMPERATURE (°C)

Figure 21. Switching Frequency vs. Temperature

Figure 24. Buck Quiescent Current vs. Input Voltage

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

4.0

3.5

3.0

2.5

2.0

1.5

1,0

0.5

0

0.5

1.0

1.5

2.0

2.5

3.0

0

0.5

1.0

1.5

2.0

2.5

3.0

LOAD CURRENT (A)

LOAD CURRENT( A)

Figure 25. Adaptive Mode Headroom vs. Load Current

Figure 22. LDO Quiescent Current vs. Load Current

I

L

I

L

1

V

SW1

V

SW1

2

3

1

V

PVOUT1

4

3

V

PVOUT1

CH1 5.00V

CH3 500mA ^B

M400ns

A CH1

5.70V

CH1 500mA

CH3 10mV Ω ^B

CH2 5V

M200ns

94ns

A CH2

8V

CH4 10.0mV Ω^B

T

0.000µs

W

T

Figure 23 SW1 Waveform, V_PVOUT1= 5 V, I_LOAD1= 100 mA, f_SW= 2 MHz,

L = 2.2 μH, R_C= 2.7 kΩ, C_C= 22 nF, C_CP= 22 pF, C_PVOUT1= 22 μF

Figure 26. SW1 Waveform, V_PVOUT1= 5 V, I_LOAD1= 3 A, f_SW= 2 MHz, L = 2.2 μH,

R_C= 2.7 kΩ, C_C= 22 nF, C_CP= 22 pF, C_PVOUT1= 22 μF

Rev. A | Page 12 of 31

Data Sheet

ADP5003

V

PVOUT1

V

PVOUT1

2

V

SW1

3

1

3

1

I

L

B

CH1 5.00A^BCH2 500mV

M20.0ms

40.0080ms

A CH2

510mV

B

W

CH1 5.00A^BCH2 500mV

M20.0ms

40.0080ms

A CH2

510mV

W

CH3 10.0V ^B

T

W

T

W

Figure 27. Entering Hiccup Mode

(V_SW1is the Voltage of the SW1 Pin, and I_Lis Inductor Current)

Figure 30. Exiting Hiccup Mode

V

/V

EN1 EN2

V

EN1

2

3

V

VOUT1

V

PVOUT2

V

PVOUT1

3

1

4

I

LOAD1

4

2

1

I

LOAD2

V

SW1

CH1 1.00A

CH3 2.00V

CH2 1.00V

CH4 1.00V

M1.00ms

A CH3

2.04V

B

CH1 1A

CH3 1V

CH2 2V

CH4 10V ^B

M400µs

A CH2

1.56V

W

T

3.00400ms

B

W

Figure 31. Adaptive Mode Startup, V_PVOUT2= 3.3 V, I_LOAD2= 1 A

(V_EN2is the EN2 voltage.)

Figure 28. Buck Startup, V_PVOUT1= 3.3V, I_LOAD1= 3 A

(V_EN1is the EN1 voltage.)

I

LOAD1

V

PVIN1

0.42V/µs

0.11V/µs

2.3A/µs

3.1A/µs

4

2

V

PVOUT1

V

PVOUT1

4

2

10V OFFSET

CH2 500mV

CH4 1A

M200µs

A CH4

1.46A

CH2 500mV ^BCH4 20.0mVΩ ^BM80µs

A CH2

12.4V

W

T

493.480µs

T

25.50%

Figure 32. Buck Load Transient, V_PVIN1= 12 V, V_PVOUT1= 1.2 V, I_LOAD1= 0.5 A to 3 A,

f_SW= 0.6 MHz, L = 2.2 μH, R_C= 3.48 kΩ, C_C= 2 nF, C_CP= 22 pF, C_PVOUT1= 44 μF

Figure 29. Buck Line Transient, V_PVIN1= 12 V to 13 V, V_PVOUT1= 1.2 V, I_LOAD1= 1A,

f_SW= 0.6 MHz, L = 2.2 μH, R_C= 3.48 kΩ, C_C= 2 nF, C_CP= 22 pF, C_PVOUT1= 44 μF

Rev. A | Page 13 of 31

ADP5003

Data Sheet

2.3A/µs

3A/µs

I

LOAD2

0.18V/µs

V

0.07V/µs

PVIN2

4

2

1

2

3V OFFSET

V

PVOUT2

V

PVOUT2

CH2 20.0mV

CH4 1.00A

M8.00µs

A CH4

1.34A

B

CH1 500mV CH2 1.00mV

M80.0µs

A CH1

3.81V

W

T

18.4800µs

T

200.960µs

Figure 33. LDO Line Transient, V_PVIN2= 3.6 V to 4.1 V, V_PVOUT2= 3.3 V,

I_LOAD2= 1 A

Figure 36. LDO Load Transient, V_PVIN2= 3.6 V, V_PVOUT2= 3.3 V,

I_LOAD2= 0.5 A to 3 A

0.45V/µs

0.14V/µs

V

PVIN1

1.2A/µs

1.3A/µs

I

LOAD2

3

4

V

PVOUT2

V

PVOUT2

4

2

10V OFFSET

CH2 500mV ^BCH4 1.00mV Ω ^B

M80µs

25.90%

A CH2

12.5V

W

CH3 500mA

CH4 10.0mVΩ ^BM80µs

A CH2

1.52V

W

T

24.70%

Figure 34. Adaptive Mode Line Transient, V_PVIN1= 11 V to 13 V, V_PVOUT2= 3.3 V,

Figure 37. Adaptive Mode Load Transient, V_PVIN1= 12 V, V_PVOUT2= 3.3 V,

_LOAD2= 1 A to 1.5 A, f_SW= 1.5 MHz, L = 2.2 μH, R_C= 3.48 kΩ, C_C= 22 nF,

C_CP= 22 pF, C_PVOUT1= 64 μF

I

_LOAD2= 1 A, f_SW= 1.5 MHz, L = 2.2 μH, R_C= 3.48 kΩ, C_C= 22 nF, C_CP= 22 pF,

C_PVOUT1= 64 μF

I

PVIN1

3

4

V

PVOUT2

CH3 1.00 A

CH4 20.0mV Ω ^B

M8.00µs

A CH3

920mA

T

24.7%

W

Figure 35. Adaptive Mode Load Transient, V_PVIN1= 12 V, V_PVOUT2= 3.3 V,

_LOAD2= 0.5 A to 3 A, f_SW= 1.5 MHz, L = 2.2 μH, R_C= 3.48 kΩ, C_C= 22 nF,

C_CP= 22 pF, C_PVOUT1= 64 μF

I

Rev. A | Page 14 of 31

Data Sheet

ADP5003

THEORY OF OPERATION

Active Pull Down

POWER MANAGEMENT UNIT

Both regulators have active pull-down resistors discharging the

respective output capacitors when the regulators are disabled.

The pull-down resistors are connected between VOUT1 to

AGND1 and PVOUT2 to AGND2. Active pull-down resistors

are disabled when the regulators are turned on.

The ADP5003 is a micropower management unit combining a

step-down (buck) dc-to-dc converter and an ultralow noise low

dropout linear (LDO)regulator. The high switching frequency

and 5 mm × 5 mm, 32-lead LFCSP package allow a compact

power management solution.

When the enable pins are asserted low, or a TSD or UVLO

event occurs, the active pull-down resistors enable to quickly

discharge the output capacitors. The pull-down resistors remain

engaged until the enable pins are asserted high, the fault event is

no longer present, or the VREG supply voltage falls to less than

the voltage required (approximately 1 V) to guarantee that the

pull-down resistor remains enabled.

Adaptive Headroom Control

The ADP5003 features a scheme to control the LDO headroom

voltage to ensure optimal operating efficiency while maintaining a

consistent power supply rejection ratio (PSRR) across the full

range of the LDO load current.

The scheme works by varying the headroom voltage across the

LDO NFET with respect to the LDO load current. Lower and

upper limits prevent the headroom from approaching zero volts

at light loads and from increasing more than necessary at high

loads.

Soft Start (SS)

Both regulators have an internal soft start function that ramps

the output voltage in a controlled manner on startup, thereby

limiting the inrush current. The soft start function reduces the

risk of noise spikes and voltage drops on the upstream supplies.

Precision Enable/Shutdown

The ADP5003 has individual enable pins (EN1 and EN2) to

control the regulators.

Power-Good

The ADP5003 has a dedicated power-good, open-drain, output

(PWRGD). PWRGD indicates whether one or more regulators

are outside the voltage limits specified by the power-good lower

limit (PWRGD_F) and the power-good upper limit (PWRGD_F+

PWRGD_FH). When either one or both of the regulator outputs

are outside the power-good limits, the PWRGD output pulls low.

PWRGD will continue to pull low, provided the VREG supply

voltage remains above approximately 1 V.

The precision enable function allows a precise turn on point for

the regulators to allow the possibility of external sequencing. A

voltage level higher than V_{TH_H}applied to the EN1 or EN2 pin

activates a regulator, whereas a level below V_{TH_L}turns off a

regulator. The buck is controlled by EN1, and the LDO is

controlled by the EN2 pin. When both EN1 and EN2 fall below

V

_{TH_S}, the ADP5003 enters shutdown mode.

Undervoltage Lockout (UVLO)

When in adaptive mode, PWRGD only monitors the LDO

output, and when in standalone mode, PWRGD only monitors

the regulator/regulators that are enabled.

To protect against the input voltage being too low, UVLO

circuitry is integrated into the system. If the input voltage on

PVINSYS drops to less than the UVLO_PVINSYSFALLthreshold, all

channels shut down.

BUCK REGULATOR

Control Scheme

The device is enabled again when the voltage on PVINSYS rises

to more than the UVLO_PVINSYSRISEthreshold, provided the enable

pins remain active.

The buck regulator operates with a fixed frequency, emulated

peak current mode, pulse-width modulation (PWM) control

architecture, where the duty cycle of the integrated switches is

adjusted and regulates the output voltage. At the start of each

oscillator cycle, the positive channel field effect transistor (PFET)

switch is turned on, sending a positive voltage across the inductor.

Current in the inductor increases until the emulated current

sense signal crosses the peak inductor current threshold, which

turns off the PFET switch and turns on the NFET synchronous

rectifier. Turning on the NFET synchronous rectifier creates a

negative voltage across the inductor, which causes the inductor

current to decrease. The synchronous rectifier stays on for the

remainder of the cycle. By adjusting the peak inductor current

threshold, the buck regulator can regulate the output voltage.

Thermal Shutdown (TSD)

In the event that the junction temperature rises above T_SD, the

thermal shutdown circuit turns off both regulators. Extreme

junction temperatures can be the result of high current operation,

poor circuit board design, or a high ambient temperature. A

hysteresis value of T_SD-HYSis included so that when thermal

shutdown occurs, the regulators do not return to operation until

the on-chip temperature drops below T_SD− T_SD-HYS. When

emerging from thermal shutdown, both regulators restart with

soft start control.

Rev. A | Page 15 of 31

ADP5003

Data Sheet

The emulated inductor current scheme senses the current in the

inductor during the off phase of the cycle, when the NFET is

conducting, and uses this inductor current to generate the

emulated current sense signal during the on time of the cycle.

This scheme allows the low duty cycles necessary for high input

voltage, V_IN, to output voltage, V_OUT, conversion ratios.

External Oscillator Synchronization

The SYNC pin is dedicated for oscillator synchronization and

allows the ADP5003 to lock to an external clock.

When an applied external clock signal is present at the SYNC pin,

the buck regulator operates in sync with this signal.

When alternating between external clocks and the internal

oscillator, the presence of an external frequency causes a

multiplexer to switch between the internal oscillator and the

external SYNC frequency. The output of this multiplexer acts as

the frequency reference to an internal phase-locked loop (PLL),

which ensures that changing between the two modes of operation

results in a smooth transition between the different frequencies.

Oscillator Frequency Control

The ADP5003 buck regulator oscillator frequency is controlled

by using the RT pin or the SYNC pin. To define the buck

regulator internal switching frequency, connect the RT pin via a

resistor to AGND1. Figure 38 shows the relationship of the buck

oscillator frequency and the RT resistor value.

3.0

Buck Startup

2.5

2.0

1.5

1.0

0.5

0

The buck regulator turns on with a controlled soft start ramp to

limit inrush current. The reference of the buck is ramped

during t_SSBUCK, which is typically 2 ms (see Figure 39).

t_SSBUCK

V

EN1

2

V

PVOUT1

4

1

3

10k

100k

1M

I

LOAD1

RT RESISTOR (Ω)

Figure 38. Buck Oscillator Frequency vs. RT Resistor (R_RT

)

V

SW1

To determine the oscillator frequency (f_SW), use the following

equation:

B

CH1 1.00A ^B

CH3 5.00V

CH2 5.0V

CH4 1.0V

4.00µs

1.60ms

A CH2

1.20V

W

B

T

f

_SW= (1.78 × 10¹¹)/R_RT

(1)

Figure 39. Buck Startup

An upper limit prevents out of range frequencies when the RT

pin is shorted to ground or connected with a resistor value less

than 70 kΩ.

Rev. A | Page 16 of 31

Data Sheet

ADP5003

Current-Limit and Short-Circuit Protection

LDO REGULATOR

The buck regulator includes current-limit protection circuitry

to limit the amount of forward current through the field effect

transistor (FET) switches. When the valley inductor current

exceeds the overcurrent limit threshold for a number of clock

cycles during an overload or short-circuit condition, the

regulator enters hiccup mode. The regulator stops switching

and then restarts with a new soft start cycle after the hiccup

time, t_HICCUP, and repeats until the over-current condition is

removed. If the buck regulator output voltage falls below 50%

of the nominal output voltage, the regulator immediately enters

hiccup mode. When the valley inductor current falls below the

negative current-limit threshold, the NFET turns off and the

PFET remains off allowing the inductor current to be discharged

via the PFET body diode. The PFET turns on again with the

next clock edge after the inductor current no longer exceeds

the negative current-limit threshold.

The ADP5003 contains a single low noise, low dropout (LDO)

linear regulator that uses an NFET pass device to provide high

PSRR with low headroom voltage and an output current up to 3 A.

The LDO regulator can operate with an input voltage of 0.65 V

to 5 V while providing excellent line and load transient response

using 10 µF ceramic input and output capacitors.

LDO Startup

The LDO regulator turns on with a controlled soft start ramp to

limit inrush current. This soft start ramp is dictated by t_SSLDO

,

which is typically 400 µs.

4.0

0.1A

3.5

1A

3A

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

V

EN2

2.5

1.5

0.5

–0.5

–1.5

–2.5

–3.5

–4.5

2

3.5A

3

–0.4 –0.2

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4 1.6

TIME (ms)

t_HICCUP

Figure 41. LDO Startup

1

Current Limit

The LDO operates in current limit when the output load exceeds

_LIMIT2. When in current limit operation, the output voltage

I

reduces to maintain a constant output current.

Differential Remote Sensing

V

VOUT1

The LDO can sense at the point of load by using VFB2P and

VFB2N as shown in Figure 42. Differential remote sensing

compensates for both the source drop and the return drop to

provide a more precise supply scheme at the point of load.

2

3.5A

I

L

3

1

PVOUT2

LOW NOISE

PVOUT2

LDO ACTIVE

FILTER

3A

–

+

V

SW1

VFB2P

VFB2N

+

LOAD

–

CH1 10.0V

CH3 2.0A

CH2 2.00V

20.0ms

A CH2

1.08V

B

T

79.7600ms

W

Figure 40. Short-Circuit Response (Current Limit and Hiccup Mode)

AGND1

AGND2

–

+

Figure 42. Differential Remote Sensing

Rev. A | Page 17 of 31

ADP5003

Data Sheet

POWER-GOOD

OUTPUT VOLTAGE OF THE LDO REGULATOR

An external pull-up resistor is necessary to drive the PWRGD

output high (see Figure 43). Through the value of the pull-up

resistor is not critical, it is recommended to use a 10 kΩ to

300 kΩ resistor. The resistor must be pulled to a voltage level

no greater than 5.5 V.

The output voltage on the LDO regulator is adjustable through

an external resistor divider. The LDO adjustable output voltage

configuration is shown in Figure 45.

PVOUT2

PVIN2

REFOUT

VFB2P

VFB2N

V

PULLUP

LDO

R

TOP2

VSET2

R

PULLUP

PWRGD

GPIO

V

R

PWRGD

BOT2

Figure 45. LDO Adjustable Output Voltage Configuration

Figure 43. Power-Good Setup

To calculate the LDO output voltage, use the following

equation:

OUTPUT VOLTAGE OF THE BUCK REGULATOR

The output voltage on the buck regulator is adjustable through

an external resistor divider. When using adaptive mode, the

ADP5003 controls the buck output voltage.













R_{BOT 2}

R_{TOP 2} R_{BOT 2}

(3)

V_{PVOUT 2} V_REFOUTA_LDO

where:

_LDOis the LDO gain.

The adjustable output voltage configuration is shown in Figure 44.

A

SW1

PVOUT1

PVIN1

REFOUT

R

_BOT2is the bottom divider resistor.

_TOP2is the top divider resistor.

VOUT1

BUCK

R

VOLTAGE CONVERSION LIMITATIONS

TOP1

VSET1

For a given input voltage and switching frequency, an upper

and lower limitation on the output voltage exists due to the

minimum on time and minimum off time. The minimum on

time limits the minimum output voltage for a given input

voltage and switching frequency.

R

BOT1

Figure 44. Buck Regulator Adjustable Output Voltage

If the minimum on time is exceeded, the ADP5003 may not

To calculate the buck output voltage, use the following equation:

switch at a fixed frequency because the device can switch at an

effective zero on time, resulting in unpredictable switching

frequencies and unwanted noise.













R_{BOT 1}

_TOP1 R_{BOT 1}

(2)

V_{PVOUT 1} V_REFOUTA_BUCK

R

To calculate the minimum output voltage for a given input

voltage and fixed switching frequency, use the following

equation:

where:

V_REFOUTis the REFOUT output voltage.

_BUCKis the buck regulator gain.

A

R

_BOT1is the bottom divider resistor.

_TOP1is the top divider resistor.

V

_{OUT_MIN}= V_PVIN1× t_{MIN_ON}× f_SW− (R_PFET– R_NFET) ×

_{OUT_MIN}× t_{MIN_ON}× f_SW− (R_NFET+ R_L) × I_{OUT_MIN}(4)

I

where:

V

_{OUT_MIN}is the minimum output voltage.

_PVIN1is the input voltage.

t

_{MIN_ON}is the minimum on time.

f

_SWis the switching frequency.

R

_PFETis the high-side PFET on resistance.

_NFETis the low-side NFET on resistance.

I

_{OUT_MIN}is the minimum output current.

R_Lis the resistance of the output inductor.

Rev. A | Page 18 of 31

Data Sheet

ADP5003

The minimum off time limits the maximum duty cycle which

in turn limits the maximum output voltage for a given input

voltage and switching frequency. Calculate the maximum output

voltage for a given input voltage and switching frequency by

using the following equation:

Use the following equation to calculate the worst case capacitance,

accounting for capacitor variation over temperature, component

tolerance, and voltage:

C

_EFFECTIVE= C_NOMINAL× (1 − TEMPCO) × (1 − DCBIASCO) ×

(1 − Tolerance) (6)

V

_{OUT_MAX}= V_PVIN1× (1 − t_{MIN_OFF}× f_SW) − (R_PFET– R_NFET) × I_{OUT_MAX}

×

where:

C

(1 − t_{MIN_OFF}× f_SW) − (R_NFET+ R_L) × I_{OUT_MAX}

(5)

_EFFECTIVEis the effective capacitance at the operating voltage.

_NOMINALis the nominal data sheet capacitance.

TEMPCO is the worst case capacitor temperature coefficient.

DCBIASCO is the dc bias derating at the output voltage.

Tolerance is the worst case component tolerance.

where:

_{OUT_MAX}is the maximum output voltage.

_{OUT_MAX}is the maximum output current.

_{MIN_OFF}is the minimum off time.

C

V

I

t

As shown in Equation 4 and Equation 5, reducing the switching

frequency eases the minimum on time and minimum off time

limitations.

To guarantee the performance of the device, it is imperative to

evaluate the dc bias effects, temperature, and tolerances on the

behavior of the capacitors for each application.

Capacitors with lower effective series resistance (ESR) and

effective series inductance (ESL) are preferred to minimize

output voltage ripple.

COMPONENT SELECTION

Output Capacitors

Higher output capacitor values reduce the output voltage ripple

and improve the load transient response.

Use the following equation to calculate the minimum

capacitance needed for a specific output voltage ripple:

Ceramic capacitors are manufactured with a variety of dielectrics,

each with a different behavior over temperature and applied

voltage. Capacitors must have a dielectric adequate to ensure

the minimum capacitance over the necessary temperature range

and dc bias conditions. X5R or X7R dielectrics with a voltage

rating of 25 V are recommended for best performance. Y5V

and Z5U dielectrics are not recommended for use with any dc-

to-dc converter because of their poor temperature and dc bias

characteristics.

ΔI_L

(7)

C_{OUT_MIN}

≅

8× f_SW×(V_RIPPLE

—

ΔI_L×R_ESR)

where:

ΔI_Lis the current ripple.

_SWis the switching frequency.

f

V

R

_RIPPLEis the allowed peak-to-peak voltage ripple.

_ESRis the effective series resistance of the capacitor.

The minimum capacitance needed for stability considering

temperature and dc bias effects is 22 µF.

The minimum capacitance recommended for the LDO is 10 µF.

Table 8. Recommended Output Capacitors

Vendor

Wurth

Part No.

Value (µF)

Type

X7R

X5R

X7R

Voltage Rating (V)

Case

0805

1210

0805

1210

885 012 207 026

885 012 209 006

885 012 109 012

885 012 109 004

GRM21BR71A106KE51

GRM32ER71C226KEA8

GRM32ER71A476KE15

10

22

47

100

10

22

47

10

25

6.3

10

16

10

Murata

Rev. A | Page 19 of 31

ADP5003

Data Sheet

To calculate the inductor value, L, use the following equation:

Input Capacitor

The input current to the buck converter steps from zero to a

positive value that is dependent on inductor value, switching

frequency, and load current (typically between 1 Aand 4 A) and

then drops quickly to zero again every switching cycle. Because

these current pulses occur at relatively high frequencies (0.3 MHz

to 2.5 MHz), the input bypass capacitor provides most of the

high frequency current while the input power source supplies

only the average current. Higher value input capacitors reduce

the input voltage ripple and improve transient response.

L = ((V_PVIN1− V_PVOUT1) × D)/(ΔI_L× f_SW

where:

)

(8)

V

_PVIN1is the input voltage.

V_PVOUT1is the output voltage.

D is the duty cycle (D = V_VOUT1/V_PVIN1).

ΔI_Lis the inductor ripple current.

f_SWis the switching frequency.

The minimum dc current rating of the inductor must be greater

than the inductor peak current. Use the following equation to

calculate the inductor peak current:

To minimize supply noise, it is recommended to place a low

ESR capacitor as close as possible to the relevant supply pin.

I

_PEAK= I_LOAD1+ (ΔI_L/2)

where:

_LOAD1is the output current.

ΔI_Lis the inductor ripple current.

(9)

Inductor

The high switching frequency of the ADP5003 buck allows the

selection of small chip inductors. A small inductor leads to larger

inductor current ripple that provides improved transient response

but degrades efficiency. The sizing of the inductor is a trade-off

between efficiency and transient response. As a guideline, the

inductor peak-to-peak current ripple is typically set to 1/3 of

the maximum load current for optimal transient response and

efficiency.

I

Inductor conduction losses are minimized by using larger sized

inductors that have smaller dc resistance; this in turn improves

efficiency at the cost of solution size. Due to the high switching

frequency of the ADP5003, shielded ferrite core material is

recommended for its low core losses and low electromagnetic

interference (EMI).

Table 9. Recommended Inductors

Vendor

Part No.

Value (µH) Saturation Current, I_SAT(A)

RMS Current, I_RMS(A)

DC Resistance (mΩ)

Size (mm)

4 × 4

5 × 5

6 × 6

4 × 4

Coilcraft XAL4020-102

XAL4020-122

XAL4020-152

XAL4020-222

XAL5030-102

XAL5030-122

XAL5030-222

XAL5030-332

XAL5050-562

XAL5050-682

XEL6030-102

XEL6030-152

XEL6030-222

XEL6030-332

XEL6060-472

XAL6060-562

XEL6060-682

XEL6060-822

XAL6060-103

1

8.7

7.9

7.1

5.6

14

6.7

6.6

5.2

4

8.7

7.9

7.2

5.9

5.3

4.7

12

10

7

13.25

17.75

21.45

35.2

8.5

1.2

1.5

2.2

1

1.2

2.2

3.3

5.6

6.8

1

12.5

9.2

8.7

6.3

6

11.4

13.2

21.2

23.45

26.75

6.32

9.57

12.7

19.92

13.65

14.46

20.82

22.71

27

18

1.5

2.2

3.3

4.7

5.6

6.8

8.2

10

1

1.2

1.5

1.8

2.2

15

13

10.5

11.4

9.9

7.9

7.6

9.6

8.8

8.5

8

6

9

7.5

7.3

7

5

Wurth

744 383 570 10

744 383 570 12

744 383 570 15

744 383 570 18

744 383 570 22

7.4

7

6.2

5.8

5.2

11.6

13.4

17.1

18

7

22

Rev. A | Page 20 of 31

Data Sheet

ADP5003

C_CP= (R_ESR× C_PVOUT1)/R_C

(12)

COMPENSATION COMPONENTS DESIGN

For the peak current mode control architecture, the power stage

can be simplified as a voltage controlled current source that

supplies current to the output capacitor and load resistor. The

simplified loop is composed of one dominant pole and a zero

contributed by the output capacitor ESR.

JUNCTION TEMPERATURE

In cases where the ambient temperature (T_A) is known, the

thermal resistance parameter (θ_JA) can estimate the junction

temperature rise (T_J). T_Jis calculated with T_Aand the power

dissipation (P_D) using the following formula:

The ADP5003 uses a transconductance amplifier as the error

amplifier to compensate the system. Figure 46 shows the

simplified peak current mode control, small signal circuit.

T_J= T_A+ (P_D× θ_JA)

(13)

The typical θ_JAvalue for the 32-lead, 5 mm × 5 mm LFCSP is

46.91°C/W. An important factor to consider is that θ_JAis based

on a 4-layer, 4 inches × 3 inches, 2.5 ounces copper PCB, as per

the JEDEC standard, and applications may use different sizes

and layers. It is important to maximize the copper used to

remove the heat from the device. Copper exposed to air

dissipates heat better than copper used in the inner layers.

Connect the exposed pad to the ground plane with several vias.

V

REFOUT

PVOUT1

R

TOP1

C

–

g_m

+

V

PVOUT1

ESR

COMP1

+

–

A

VI

V

A

BUCK

SET1

R

C

CP

R

BOT1

C

If the case temperature can be measured, the junction

temperature is calculated by

Figure 46. Simplified Peak Current Mode Control, Small Signal Circuit

T_J= T_C+ (P_D× θ_JC)

where:

T_Cis the case temperature.

_JCis the junction to case thermal resistance provided in Table 6.

(14)

The compensation components, R_Cand C_C, contribute a zero,

and the optional C_CPand R_Ccontribute an optional pole.

The following procedure shows how to select the compensation

components (R_C, C_C, and C_CP) for ceramic output capacitor

applications:

θ

To achieve reliable operation of the buck converter and LDO

regulator, the estimated die junction temperature of the

ADP5003 must be less than 125°C. Reliability and mean time

between failures (MTBF) is highly affected by increasing the

junction temperature. Additional information about product

reliability can be found in the Analog Devices, Inc., Reliability

Handbook at www.analog.com/reliability_handbook.

1. Determine the cross frequency (f_C). Generally, f_Cis

between f_SW/12 and f_SW/6.

2. Use the following equation to calculate R_C:

2 × π ×C_PVOUT1× A_BUCK

(10)

R_C=

g_m× A_VI

The total power dissipation in the ADP5003 simplifies to

where:

P_D= P_DBUCK+ P_DLDO

where:

(15)

C

A

_PVOUT1is the output capacitance.

_VI= 7 A /V.

P

_DBUCK= (V_PVIN1× I_PVIN1) − (V_PVOUT1× I_LOAD1).

_DLDO= ((V_PVIN2− V_PVOUT2) × I_LOAD2) + (V_PVIN2× I_GND).

3. Place the compensation zero at the domain pole (f_P).

Determine C_Cas follows:

C_C= ((R + R_ESR) × C_PVOUT1)/R_C

(11)

where:

R

_ESRis the equivalent series resistance of the output

capacitor.

_CPis optional. It can cancel the zero caused by the ESR of

the output capacitor. Determine C_CPas follows:

4.

C

Rev. A | Page 21 of 31

ADP5003

Data Sheet

BUCK REGULATOR DESIGN EXAMPLE

This section provides an example of the step by step design

procedures and the external components required for the buck

regulator. Table 10 lists the design requirements for this

example.

SELECTING THE INDUCTOR FOR THE BUCK

REGULATOR

The peak-to-peak inductor ripple current, ΔI_L, is set to 35% of

the maximum output current. Use Equation 8 to estimate the

value of the inductor:

Table 10. Example Design Requirements for the Buck Regulator

Parameter

Specification

V_PVIN1= 12 V

V_PVOUT1= 2.5 V

I_LOAD1= 3 A

ΔV_{OUT1_RIPPLE}= 25 mV

5% at 20% to 80% load transient

L = ((V_PVIN1− V_PVOUT1) × D)/(ΔI_L× f_SW

where:

)

Input Voltage

Output Voltage

Output Current

Output Ripple

Load Transient

V

_PVIN1= 12 V.

V_PVOUT1= 2.5 V.

D is the duty cycle (D = V_PVOUT1/V_PVIN1).

ΔI_L= 35% × 3 A = 1.05 A.

f

_SW= 600 kHz.

SETTING THE SWITCHING FREQUENCY FOR THE

BUCK REGULATOR

The first step is to determine the switching frequency for the

ADP5003 design. In general, higher switching frequencies

produce a smaller solution size due to the lower component

values required, whereas lower switching frequencies result in

higher conversion efficiency due to lower switching losses.

The resulting value for L is 3.14 µH. The selected standard

inductor value is 3.3 µH; therefore, ΔI_Lis 1 A.

To calculate the peak inductor current (I_PEAK), use Equation 9:

I_PEAK= I_LOAD1+ (ΔI_L/2)

The calculated peak current for the inductor is 3.5 A.

SELECTING THE OUTPUT CAPACITOR FOR THE

BUCK REGULATOR

The output capacitor must meet the output voltage ripple, load

transient requirements and stability requirements. To meet the

output voltage ripple requirement, use Equation 7 to calculate

the capacitance:

The switching frequency of the ADP5003 can be set from

0.3 MHz to 2.5 MHz by connecting a resistor from the RT pin

to ground. The selected resistor allows the user to make decisions

based on the trade-off between efficiency and solution size. (For

more information, see the Oscillator Frequency Control section.)

However, the highest supported switching frequency must be

assessed by checking the voltage conversion limitations enforced

by the minimum on time and the minimum off time (see the

Voltage Conversion Limitations section).

ΔI_L

C_{OUT_MIN}

≅

8× f_SW×(V_RIPPLE

—

ΔI_L×R_ESR)

The calculated capacitance, C_{OUT_MIN}, is 8.7 µF.

In this design example, a switching frequency of 600 kHz is

used to achieve an ideal combination of small solution size and

high conversion efficiency. To set the switching frequency to

600 kHz, use Equation 1 to calculate the resistor value, R_RT. This

gives a standard resistor value of R_T= 294 kΩ.

To meet the 5% overshoot and undershoot requirements, use

the following equations to calculate the capacitance:

K_UV× ΔI_STEP²× L

(17)

(18)

C_{OUT_UV}

=

2×

(

V_PVIN1–V_PVOUT1× ΔV_{OUT _UV}

)

K_OV× ΔI_STEP²× L

SETTING THE OUTPUT VOLTAGE FOR THE BUCK

REGULATOR

Select a value for the top resistor (R_TOP1) and then calculate the

bottom feedback (R_BOT1) resistor by using the following

equation:

C_{OUT_OV}

=

2

(

V

_PVOUT1+ ΔV_{OUT _OV}

)

–V_PVOUT1

where:

_UVand K_OVare factors (typically set to 2).

ΔI_STEPis the load step.

K

ΔV_{OUT_UV}is the allowable undershoot on the output voltage.

ΔV_{OUT_OV}is the allowable overshoot on the output voltage.

R

_BOT1= (R_TOP1× V_PVOUT1)/((V_REFOUT× A_BUCK) − V_PVOUT1

) (16)

where:

For estimation purposes, use K_OV= K_UV= 2; therefore,

V

A

_PVOUT1is the buck output voltage.

_REFOUTis 2 V.

_BUCKis the buck regulator gain.

C

_{OUT_OV}= 33.4 µF and C_{OUT_UV}= 9 µF.

It is recommended to use two 22 µF ceramic capacitors.

To set the output voltage to 2.5 V, R_TOP1is set to 100 kΩ, giving

an R_BOT1value of 100 kΩ.

Rev. A | Page 22 of 31

Data Sheet

ADP5003

Figure 47 shows the load transient waveform.

DESIGNING THE COMPENSATION NETWORK FOR

THE BUCK REGULATOR

0.02A/µs

0.015A/µs

For better load transient and stability performance, set the cross

frequency, f_C, to f_SW/10. In this example, f_SWis set to 600 kHz;

therefore, f_Cis set to 60 kHz.

I

LOAD2

2

3

4

2 × π × 44 μF × 60 kHz ×2.5

R_C=

= 9.87 kΩ

= 3.72 nF

600 μS × 7 A/V

V

VOUT1

(

)

0.833 Ω + 0.001 Ω × 44 μF

V

C_C=

PVOUT2

7.18 kΩ

0.001 Ω × 44 μF

= = 4.46 pF

C_CP

7.18 kΩ

B

CH2 1.00A

CH4 20.0mV

CH3 200mV

M200µs

A CH2

1.08A

W

B

T

432.000µs

W

Choose standard components: R_C= 9.76 kΩ, C_C= 4.7 nF,

_CP= 4.7 pF.

Figure 47. 0.6 A to 2.4 A Load Transient for 2.5 V Output, f_SW= 0.6 MHz,

L = 3.3 μH, R_C= 9.76 kΩ, C_C= 4.7 nF, C_CP= 4.7 pF, C_PVOUT1= 44 μF

C

SELECTING THE INPUT CAPACITOR FOR THE BUCK

REGULATOR

For the input capacitor, select a ceramic capacitor with a

minimum capacitance of 10 µF. Place the input capacitor close

to the PVIN1 pin. In this example, one 10 µF, X5R, 25 V

ceramic capacitor is recommended.

Rev. A | Page 23 of 31

ADP5003

Data Sheet

ADAPTIVE HEADROOM CONTROL DESIGN EXAMPLE

This section provides an example of the step by step design

procedures and the external components required for the buck

regulator using adaptive headroom control. Table 11 lists the

design requirements for this example.

SELECTING THE INDUCTOR FOR THE BUCK

REGULATOR USING ADAPTIVE HEADROOM

CONTROL

The peak-to-peak inductor ripple current, ΔI_L, is set to 35% of

the maximum output current. Use the Equation 8 to estimate

the value of the inductor:

Table 11. Example Design Requirements for the Buck

Regulator Using Adaptive Headroom Control

Parameter

Specification

L = ((V_PVIN1– V_PVOUT1) × D)/(ΔI_L× f_SW)

Input Voltage

V_PVIN1= 12 V

V_PVOUT2= 1.3 V

I_LOAD1= I_LOAD2= 3 A

1ꢀꢀ ꢁV at 2ꢀ% to 8ꢀ% load transient

where:

Output Voltage

Output Current

Buck Load Transient

V

_PVIN1= 12 V.

_PVOUT1= V_PVOUT2+ V_HR= 1.7 V.

_PVOUT2= 1.3 V.

_HRis the adaptive headroom voltage at steady state current. See

SETTING THE SWITCHING FREQUENCY FOR THE

BUCK REGULATOR USING ADAPTIVE HEADROOM

CONTROL

Similar to the buck design example, a switching frequency of

600 kHz is used to achieve a good combination of small solution

size and high conversion efficiency. To set the switching frequency

to 600 kHz, use Equation 1 to calculate the resistor value, R_RT:

Table 4 and Figure 25 for the approximate values of V_HRvs. load

current. For this example, use V_HRequal to 0.4 V for steady state

load current of 3 A.

D is the duty cycle (D = V_VOUT1/V_PVIN1).

ΔI_L= 35% × 3 A = 1.05 A.

f

_SW= 600 kHz.

The resulting value for L is 2.32 μH. The selected standard

inductor value is 2.2 μH; therefore, ΔI_Lis 1.1 A.

R

_RT(kΩ) = 1.78 × 10¹¹/f_SW(kHz)

Therefore, select standard resistor R_T= 294 kΩ.

To calculate the peak inductor current (I_PEAK), use Equation 9:

SETTING THE OUTPUT VOLTAGE FOR THE LDO

REGULATOR USING ADAPTIVE HEADROOM

CONTROL

Select a value for the top feedback resistor (R_TOP2) and then

calculate the bottom resistor (R_BOT2) by using the following

equation:

I

_PEAK= I_LOAD1+ (ΔI_L/2)

The calculated peak current for the inductor is 3.55 A.

SELECTING THE OUTPUT CAPACITORS FOR THE

BUCK REGULATOR USING ADAPTIVE HEADROOM

CONTROL

To ensure that the LDO regulator does not track the buck

output, the undershoot voltage must be set to a value less than

the minimum adaptive headroom voltage. Use Equation 17 and

Equation 18 to calculate the capacitance.

R

_BOT2= (R_TOP2× V_PVOUT2)/((V_REFOUT× A_LDO) – V_PVOUT2

)

(19)

where:

V

A

_PVOUT2is the LDO output voltage.

_REFOUTis 2 V.

_LDOis the LDO regulator gain.

For estimation purposes, use K_OV= K_UV= 2; therefore,

C_{OUT_OV}= 40.7 μF and C_{OUT_UV}= 6.92 μF.

To set the output voltage to 1.3 V, R_TOP2is set to 100 kΩ giving

an R_BOT2value of 65 kΩ.

It is recommended to use a single 47 μF ceramic capacitor for the

output of the buck and a single 10 μF for the output of the LDO.

Rev. A | Page 24 of 31

Data Sheet

ADP5003

DESIGNING THE COMPENSATION NETWORK FOR

THE BUCK REGULATOR USING ADAPTIVE

HEADROOM CONTROL

V

PVOUT1

4

Due to the addition of the adaptive headroom scheme in the

feedback loop, a lower bandwidth is required. Set the crossover

frequency, f_C, to f_SW/60. In this example, f_SWis set to 600 kHz;

therefore, f_Cis set to 10 kHz.

0.02A/µs

0.013A/µs

I

LOAD1

1

2 × π × 47 μF ×10 kHz ×2.5

R_C=

C_C=

= 1.76 kΩ

= 15.2 nF

600 μS × 7 A/V

(

)

0.433 Ω + 0.001 Ω × 47 μF

B

CH1 1.00A^BCH4 100mV

200µs

T

A CH3

1.38A

W

1.76 kΩ

508µs

0.001 Ω × 47 μF

Figure 48. 0.6 A to 2.4 A Load Transient for 2.5 V Output, f_SW= 600 kHz,

L = 2.2 μH, R_C= 1.74 kΩ, C_C= 22 nF, C_CP= 22 pF, C_PVOUT1= 47μF

C_CP

= = 26.7 pF

1.76 kΩ

SELECTING THE INPUT CAPACITOR FOR THE BUCK

REGULATOR USING ADAPTIVE HEADROOM

CONTROL

Choose standard components: R_C= 1.74 kΩ, C_C= 22 nF,

_CP= 22 pF.

Figure 48 shows the load transient waveform.

C

For the input capacitor, select a ceramic capacitor with a

minimum value of 10 µF. Place the input capacitor close to the

PVIN1 pin. In this example, one 10 µF, X5R, 25 V ceramic

capacitor is recommended.

Rev. A | Page 25 of 31

ADP5003

Data Sheet

RECOMMENDED EXTERNAL COMPONENTS FOR THE BUCK REGULATOR

Table 12 lists the recommended external components for buck applications up to 3 A operation (±±5 tolerance at an ~605 step transient),

and Table 13 lists the recommended buck external components for adaptive headroom applications up to 3 A operation (V_PVOUT2

100 mV at an ~605 step transient).

±

Table 12. Recommended External Components for Buck Applications up to 3 A Operation ( 5% Tolerance at an ~60% Step Transient)

f_SW(kHz)

300

V_IN(V)

12

5

V_OUT(V)

1

L (μH)

3.3

4.7

5.6

6.8

8.2

10

C_OUT(μF)

210

204.7

147

110

69

R_TOP1(kΩ)

200

150

174

150

100

49.9

0

200

150

174

150

100

49.9

150

100

49.9

0

200

150

174

150

100

49.9

100

49.9

0

200

150

174

150

100

49.9

R_BOT1(kΩ)

49.9

47.5

75

84.5

100

97.6

open

49.9

47.5

75

84.5

100

97.6

84.5

100

97.6

Open

49.9

47.5

75

84.5

100

97.6

100

97.6

Open

49.9

47.5

75

R_C(kΩ)

23.7

23.2

16.5

12.4

7.68

5.23

3.01

23.7

16.5

14.7

10.5

5.23

5.76

15.4

7.15

6.04

4.99

21

C_C(nF)

3.3

4.7

6.8

10

C_CP(pF)

10

1.2

1.5

1.8

2.5

3.3

5

47

26.7

210

147

132

94

47

51.7

69

32

26.7

22

94

147

49.2

47

23

24.2

22

69

47

15

1

3.3

4.7

2.2

3.3

4.7

5.6

1.5

1.8

2.2

3.3

1

3.3

4.7

6.8

10

1.2

1.5

1.8

2.5

3.3

1.5

1.8

2.5

3.3

5

600

12

5

2.2

3.3

4.7

6.8

1.5

2.2

3.3

4.7

2.2

3.3

4.7

1

4.7

2.2

1

1.2

1.5

1.8

2.5

3.3

2.5

3.3

5

33.2

11

10.5

5.11

5.49

8.25

25.5

17.4

12.1

8.66

8.25

5

1000

12

5

1

1.2

1.5

1.8

2.5

3.3

1

1.2

1.5

1.2

32

23

22

1.5

2.2

3.3

84.5

100

97.6

Rev. A | Page 26 of 31

Data Sheet

ADP5003

Table 13. Recommended Buck External Components for Adaptive Headroom Applications up to 3 A Operation (V_PVOUT2100 mV

at an ~60% Step Transient)

f_SW(kHz)

600

V_IN(V)

V_OUT2(V)

3.3

2.5

1.8

1.3

1.1

3.3

2.5

L (µH)

4.7

3.3

2.2

1.8

1.5

1.8

C_OUT1(µF)

R_C(kΩ)

1.74

1.65

2.15

1.74

1.65

1.21

1.65

C_C(nF)

33

22

10

33

22

C_CP(pF)

22

R_TOP2(kΩ)

Short

37.4

100

Short

37.4

100

R_BOT2(kΩ)

Open

118

121

64.9

49.9

Open

118

121

64.9

C_OUT2(µF)

12

5

47

44

57

47

44

32

44

10

1.8

1.3

1.1

1.8

1.5

22

10

22

100

49.9

Rev. A | Page 27 of 31

ADP5003

Data Sheet

BUCK CONFIGURATIONS

80

70

INDEPENDENT

The buck and LDO regulators can operate independently of

each other (see Figure 50) to provide two voltage rails from a

single supply. In this way, the buck regulator can provide an

intermediate supply rail for the LDO regulator with a fixed

headroom voltage between the buck output voltage and the

LDO output voltage. The LDO regulator acts to filter the voltage

ripple and switching noise generated by the buck regulator for

noise sensitive supplies. Where additional filtering is required, a

second stage LC filter can be added between the buck output

and the LDO input. Because the regulators are independently

operated to provide a single voltage rail, the PSRR and efficiency

can be configured as required by the application by either

setting a lower headroom voltage for greater efficiency or a

higher headroom voltage for greater PSRR.

60

50

40

30

20

10

0

ADAPTIVE HEADROOM CONTROL

INDEPENDENT, 150mV HEADROOM

INDEPENDENT, 500mV HEADROOM

0

0.5

1.0

1.5

2.0

2.5

3.0

LOAD CURRENT (A)

Figure 49. Efficiency vs. Load Current for

Different Operating Modes

V_PVIN1: 12V

PVIN1

EN1

C_PVIN1

10µF

VOUT1

SW1

C_C

4.7nF

R_C

9.76kΩ

L1

3.3µH

COMP1

VSET1

BUCK

REGULATOR

3A

V

= 2.5V

PVOUT1

C_PVOUT1

44µF

R_BOT1

100kΩ

PGND1

R_TOP1

100kΩ

C_VREG

1µF

R_RT

294kΩ

VREG

RT

V_PVINSYS: 12V

PVINSYS

C_PVINSYS

PWRGD

SYNC

SYSTEM

ANALOG DEVICES

RF TRANSCEIVER,

HIGH SPEED

ADC/DAC, CLOCK,

ASIC/PROCESSOR

10µF

REFOUT

C_REFOUT

0.22µF

R_TOP2

100kΩ

PVIN2

VSET2

C_PVIN2

10µF

R_BOT2

64.9kΩ

VBUF

LOW NOISE

LDO ACTIVE

FILTER

V

= 1.3V

PVOUT2

C_PVOUT2

C_VBUF

0.1µF

PVOUT2

3A

VREG_LDO

10µF

C_{VREG_LDO}

1µF

VFB2P

VFB2N

EN2

AGND1

AGND2

Figure 50. Independent Configuration (Dual Output)

Rev. A | Page 28 of 31

Data Sheet

ADP5003

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0.2V, 1A

LDO PSRR

= 12V, V

ADAPTIVE HEADROOM

0.28V, 1.5A

0.35V, 2A

0.4V, 2.5A

0.4V, 3A

V

= 0.9V

PVOUT2

PVIN1

The ADP5003 features a scheme to control the buck regulator

output voltage and thus the LDO headroom voltage to provide

better efficiency with the same noise performance of a standalone

LDO regulator. When the buck regulator uses the adaptive

headroom control configuration, the ADP5003 manages the

buck regulator output voltage vs. the LDO load current (see

Figure 25). The adaptive headroom control also optimizes the

LDO headroom when the remote sense feedback corrects any

output voltage drop due to additional filtering or high trace

impedance under high load conditions. The headroom profile

of the adaptive headroom control is set to deliver a consistent

PSRR across the load range while optimizing efficiency of the

overall system (see Figure 51). To enable adaptive headroom

control, connect VSET1 to VREG (see Figure 52).

1

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 51. LDO PSRR vs. Frequency

V_PVIN1: 12V

PVIN1

C_PVIN1

10µF

EN1

VOUT1

SW1

C_C

2.2nF

R_C

1.74kΩ

L1

2.2µH

V

PVOUT1

COMP1

VSET1

BUCK

REGULATOR

3A

(ADAPTIVE)

SW1

C_PVOUT1

47µF

PGND1

C_VREG

1µF

VREG

R_RT

294kΩ

RT

V_PVINSYS: 12V

PVINSYS

PWRGD

SYNC

SYSTEM

C_PVINSYS

10µF

REFOUT

C_REFOUT

0.22µF

R_TOP2

100kΩ

PVIN2

VSET2

VBUF

C_PVIN2

10µF

C_VBUF

0.1µF

R_BOT2

64.9kΩ

PVOUT2

LOW NOISE

LDO ACTIVE

FILTER

V

= 1.3V

VPOUT2

ANALOG DEVICES

RF TRANSCEIVER,

HIGH SPEED ADC/DAC,

CLOCK, ASIC/

C_PVOUT2

10µF

3A

VREG_LDO

C_{VREG_LDO}

1µF

EN2

PROCESSOR

VFB2P

VFB2N

AGND1

AGND2

Figure 52. Adaptive Headroom Configuration

Rev. A | Page 29 of 31

ADP5003

Data Sheet

LAYOUT CONSIDERATIONS

Layout is important for all switching regulators but is

particularly important for regulators with high switching

frequencies. To achieve high efficiency, proper regulation,

stability, and low noise, a well designed PCB layout is required.

Follow these guidelines when designing PCBs:

of load. Keep them as short as possible and away from

noise sources.

•

Place the frequency setting resistor close to the RT pin.

Keep AGND1 and PGND1 separate on the top layer of the

board. This separation avoids pollution of AGND1 with

switching noise. Do not connect PGND1 to the EPAD on

the top layer of the layout. Connect both AGND1 and

PGND1 to the board ground plane with vias. Ideally,

connect PGND1 to the plane at a point between the input

and output capacitors.

•

Keep high current loops as short and wide as possible.

•

Keep the input bypass capacitors close to the PVIN1,

PVIN2, and PVINSYS pins.

•

Keep the inductor and output capacitor close to SW1

and PGND1.

Connect the negative terminal of C_VBUFto the VFB2N pin.

•

Route the VFB2P and VFB2N LDO sense traces side by

side connecting them each as close as possible to the point

13.2mm

L1

PVIN

C

PVINSYS

10µF

C

PVIN1

10µF

50V/X5R

1206

35V/X5R

0805

C

VREG

1µF

C

VOUT1

10V/X5R

0406

22µF

25V/X5R

1206

R

0201

RT

24

1

C

2

3

23

22

21

0402

R

C

4

5

0402

ADP5003

20

19

18

17

R

C

TOP1

BOT1 CP

6

7

8

0201

C

REFOUT

0.22µF

10V/X5R

0402

C

PVIN2

0201

10µF

50V/X5R

1206

R

TOP2

BOT2

C

1µF

PVOUT2

VREG_LDO

10V/X5R

0402

C

PVOUT2

10µF

25V/X5R

0805

C

0.1µF

VBUF

10V/X5R

0402

Figure 53. Example Outline Layout

Rev. A | Page 30 of 31

Data Sheet

ADP5003

OUTLINE DIMENSIONS

DETAIL A

(JEDEC 95)

5.10

5.00 SQ

4.90

0.30

0.25

0.18

PIN 1

INDICATOR

PIN 1

25

32

INDIC ATOR AREA OPTIONS

(SEE DETAIL A)

24

1

0.50

BSC

3.25

3.10 SQ

2.95

EXPOSED

PAD

17

8

9

16

0.50

0.40

0.30

0.20 MIN

BOTTOM VIEW

TOP VIEW

SIDE VIEW

0.80

0.75

0.70

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WHHD

Figure 54. 32-Lead Lead Frame Chip Scale Package [LFCSP]

5 mm × 5 mm Body and 0.75 mm Package Height

(CP-32-7)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

ADP5003ACPZ-R7

ADP5003CP-EVALZ

Temperature Range

−40°C to +125°C

Package Description

32-Lead Lead Frame Chip Scale Package [LFCSP]

Evaluation Board

Package Option

CP-32-7

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D15021-0-3/19(A)

Rev. A | Page 31 of 31


型号：	ADP5003CP-EVALZ
厂家：	ADI
描述：	Low Noise Micro PMU, 3 A Buck Regulator with 3 A LDO
文件：	总31页 (文件大小：1013K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADP5003CP-EVALZ [ADI]

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