ADP3500AST-REEL_技术文档

PRELIMINARY TECHNICAL DATA

a

CDMA Power Management System

Preliminary Technical Data

ADP3500

FEATURES

Handles all CDMA Baseband and RF/IF Power Management

Functions

LDOs Optimized for Specific CDMA Subsystems

Four Backup LDOs for Stand-By mode operation

Four Li-Ion Battery Charge Modes

5mA Pre Charge

Low Current Charge

Full Current Charge

Regulator mode (no current limit)

Ambient Temperature: -30 °C to +85 °C

64pin 7x7 LQFP package

LOGIC

BLOCK

ANALOG

BLOCK

BATTERY

CHARGER

POWER ON

KEYPAD I/F

GPIO

DELAY 10mS

INTERRUPT

CONTROL

REFERENCE

LDO1 to 11

LDO CONTROL

RESET

VOLTAGE

DETECTOR

APPLICATIONS

CDMA/CDMA2000/PCS Handsets

SERIAL I/F

32KHz OUTPUT

CONTROL

RTC COUNTER

ADP3500

GENERAL DESCRIPTION

The ADP3500 is a multifunction power system chip optimized

for CDMA cell phone power management. It contains 15 LDOs.

Sophisticated controls are available for power up during battery

charging, keypad interface, GPIO/INT function and RTC

function. The battery charger has four modes as Pre-charge, Low

Current Charge, Full Current Charge, and Regulator modes, and

is designed for Li-Ion/Li-Polymer batteries.

STAY-ALIVE

TIMER

RESET OUTPUT

Figure 1. Functional Block Diagram

REV. PrP

2/6/02

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or apatent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-87ß3

ANALOG DEVICES, INC., 2002

PRELIMINARY TECHNICAL DATA

ADP3500 - SPECIFICATIONS

MAIN FUNCTIONS

T_A=-30 to +85°C, C_VBAT=1µF MLCC, VBAT=3.6V unless otherwise noted. See Table 2 for C_OUT

.

Parameter

SHUTDOWN GND CURRENT

Power OFF

Symbol

IGND

Conditions

Min

Typ

25

Max

40

Units

LDO3b : ON, connect to RTCV

through Schottky diode.

RTC/32K OSC : Active

All other LDOs: OFF

µA

All logic inputs : VBAT or GND

MVBAT: OFF

OPERATING GND CURRENT

IGND

Stand-by mode operation (light load)

LDO1b, 2b, 3b, 6b: ON

Io=1mA for LDO1b & 3b

Io=300µA for LDO2b & 6b

All other LDOs: OFF

RTC/32K OSC: Active

MVBAT: OFF

60

125

µA

All logic output: no load

Stand-by mode operation (Mid-load)

275

650

LDO1, 2, 3, 6, all Sub-LDO: ON,

Io=70% load

All other LDOs: OFF

RTC/32K OSC: Active

MVBAT: ON

µA

All logic outputs: no load

Active operation

LDO5: OFF

All other LDOs: ON, 70% load

RTC/32K OSC: Active

All logic outputs: no load

MVBAT: ON

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

Operational Temperature range

Adapter Voltage range (recommendation)

VBAT Voltage range

160

35

°C

V

Tope

VADP

VBAT

-30

5.5

3.3

+85

12

5.5

V

LDO SPECIFICATIONS

T_A=25°C, C_VBAT=1µF MLCC, VBAT = Vout+1V, NRCAP=0.1µF. See Table 2 for C_OUT

.

Baseband VDD Main-LDO (LDO #1a)

Parameter

OUTPUT VOLTAGE

Symbol

V_LDO#1

Conditions

Io = 1 to 150 mA

Ta= -30 to +85°C

Min

2.81

Typ

2.90

Max

2.99

Units

V

OUTPUT CAPACITOR REQUIRED FOR

STABILITY

DROPOUT VOLTAGE

Start-up time from shutdown

GND Current

C _LDO#1

V_DO

2.2

µF

Io = 150 mA

200

250

50

mV

µS

µA

I_LDO#1

Baseband VDD Sub-LDO (LDO #1b)

Parameter

OUTPUT VOLTAGE

Symbol

V_LDO#1b

Conditions

Io = 1mA

Min

2.8

Typ

2.87

Max

3.0

Units

V

Ta= -30 to +85°C

GND Current

I_LDO#1b

10

µA

REV.PrP 2/6/02

- 2 -

PRELIMINARY TECHNICAL DATA

ADP3500

Baseband AVDD Main-LDO (LDO #2a)

Parameter

OUTPUT Voltage

Symbol

V_LDO#2

Conditions

16 steps, 20mV/step, Ta= 25C,

Io=50mA

Min

Typ

Max

Units

Code : 1000

Code : 0111

Io = 50 mA, Ta= 25°C

16 steps, 20mV/step, Io=50mA, Ta=

-30 to +85°C

2.30

2.60

2.46

2.36

2.66

2.52

2.43

2.74

2.6

V

OUTPUT default voltage

OUTPUT Voltage

V_LDO#2

2.29

2.57

2.36

2.66

2.47

2.81

V

Code : 1000

Code : 0111

OUTPUT default voltage

OUTPUT CAPACITOR REQUIRED FOR

STABILITY

V_LDO#2

C _LDO#2

2.42

1

2.52

2.66

V

µF

Io = 50 mA, Ta= -30 to +85°C

DROPOUT VOLTAGE

RIPPLE REJECTION

V_DO

Io = 50 mA

f = 1KHz

210

50

mV

dB

OUTPUT NOISE VOLTAGE

Start-up time from shutdown

GND Current

V_NOISE

I_LDO#2

f = 100 Hz to 100 kHz

120

250

50

µV_RMS

µS

µA

Io = 50 mA

Baseband AVDD Sub-LDO (LDO #2b)

Parameter

OUTPUT Voltage

Symbol

V_LDO#2b

Conditions

Io = 300 µA, V_LDO#2a=2.6V

Ta= -30 to +85°C

Min

2.50

Typ

5

Max

2.70

Units

V

GND Current

I_LDO#2b

µA

REFO switch

Parameter

On resistance

Off leak

Symbol

R_ON

I_LEAK

Conditions

Ta= -30~+85°C, Io=500µA

LDO2: ON, Switch: OFF

Min

Typ

50

0.01

Max

130

1

Units

Ω

µA

Coin Cell Main-LDO (LDO #3a)

Parameter

OUTPUT VOLTAGE

Symbol

V_LDO#3

Conditions

Min

2.85

Typ

3.0

Max

3.09

Units

V

Io = 1 to 50 mA

Ta= -30 to +85°C

Io= 50 mA

Dropout Voltage

V_DO

140

mV

OUTPUT CAPACITOR REQUIRED FOR

STABILITY

C _LDO#3

1

µF

Start-up time from shutdown

GND Current

250

50

µS

µA

I_LDO#3

Io = 50 mA

Coin Cell Sub-LDO (LDO #3b)

Parameter

OUTPUT VOLTAGE

Symbol

V_LDO#3b

Conditions

Io=1mA

Min

2.85

Typ

2.97

Max

3.15

Units

V

Ta= -30 to +85°C

GND Current

I_LDO#3b

10

µA

Audio LDO (LDO #4)

Parameter

OUTPUT VOLTAGE

Symbol

V_LDO#4

Conditions

Io = 1 to 180 mA

Ta = -30 to +85°C

Min

2.81

Typ

2.90

Max

2.99

Units

V

OUTPUT CAPACITOR REQUIRED FOR

STABILITY

Dropout Voltage

RIPPLE REJECTION

OUTPUT NOISE VOLTAGE

Start-up time from shutdown

GND Current

C _LDO#4

V_DO

2.2

µF

Io = 180 mA

f = 1KHz

f = 100 Hz to 10 kHz

200

50

250

50

mV

dB

µV_RMS

µS

V_NOISE

I_LDO#4

Io = 180 mA

µA

REV.PrP 2/6/02

- 3 -

PRELIMINARY TECHNICAL DATA

ADP3500

Vibrator LDO (LDO #5)

Parameter

Output Voltage

Symbol

V_LDO#5

Conditions

Min

2.75

Typ

2.9

Max

3.05

Units

V

Io = 1 to 150 mA

Ta= -30 to +85°C

Io = 150mA

Dropout Voltage

Output capacitor required for stability

GND Current

V_DO

C _LDO#5

I_LDO#5

200

50

mV

µF

µA

2.2

Io = 150 mA

Baseband Core Main-LDO (LDO #6a)

Parameter

Output Voltage

Symbol

V_LDO#6

Conditions

Io = 1 to 50 mA

Ta= -30 to +85°C

Min

2.52

Typ

2.60

Max

2.68

Units

V

Output capacitor required for stability

Dropout Voltage

Start-up time from shutdown

GND Current

C _LDO#6

V_DO

1

µF

mV

µS

Io = 50 mA

160

250

50

I_LDO#6

µA

Baseband Core Sub-LDO (LDO #6b)

Parameter

OUTPUT VOLTAGE

Symbol

V_LDO#6b

Conditions

Io = 300 µA

Min

2.5

Typ

2.57

Max

2.7

Units

V

Ta= -30 to +85°C

GND Current

I_LDO#6b

5

µA

RF Rx1 LDO (LDO #7)

Parameter

Output voltage

Symbol

V_LDO#7

Conditions

Io = 1 to 100 mA

Ta= -30 to +85°C

Min

2.81

Typ

2.9

Max

2.99

Units

V

Output capacitor required for stability

Dropout voltage

Ripple rejection

C _LDO#7

V_DO

1.5

µF

mV

dB

Io = 100 mA

f = 1KHz

200

50

Output noise voltage

Start-up time from shutdown

GND Current

V_NOISE

I_LDO#7

f = 100 Hz to 100KHz

40

250

50

µV_RMS

µS

µA

Io=100mA

RF Tx LDO (LDO #8)

Parameter

Output voltage

Symbol

V_LDO#8

Conditions

Io = 1 to 150 mA

Ta= -30 to +85°C

Min

2.81

Typ

2.9

Max

2.99

Units

V

Output capacitor required for stability

Dropout voltage

Ripple Rejection

C _LDO#8

V_DO

2.2

µF

mV

dB

Io = 150mA

f = 1KHz

200

50

Output noise voltage

Start-up time from shutdown

GND Current

V_NOISE

I_LDO#8

f = 100 Hz to 100KHz

40

250

50

µV_RMS

µS

µA

Io=150mA

RF Rx 2 LDO (LDO #9)

Parameter

Output voltage

Symbol

V_LDO#9

Conditions

Io = 1 to 50 mA

Ta= -30 to +85°C

Min

2.81

Typ

2.9

Max

2.99

Units

V

Output capacitor required for stability

Dropout voltage

Ripple Rejection

C _LDO#9

V_DO

1

µF

mV

dB

Io = 50mA

f = 1KHz

150

50

Output noise voltage

Start-up time from shutdown

GND Current

V_NOISE

I_LDO#9

f = 100 Hz to 100KHz

40

250

50

µV_RMS

µS

µA

Io=50mA

RF Optional LDO (LDO #10)

Parameter

Output voltage

Symbol

V_LDO#10

Conditions

Io= 1 to 50 mA

Ta= -30 to +85°C

Min

2.81

Typ

2.9

Max

2.99

Units

V

REV.PrP 2/6/02

- 4 -

PRELIMINARY TECHNICAL DATA

ADP3500

Output capacitor required for stability

Dropout voltage

C _LDO#10

V_DO

1

µF

Io = 50mA

150

50

mV

dB

Ripple rejection

f = 1KHz

Output noise voltage

Start-up Time from Shutdown

GND Current

V_NOISE

I_LDO#10

f = 100 Hz to 100KHz

40

250

50

µV_RMS

µS

µA

Io=50mA

Optional LDO (LDO #11)

Parameter

Output voltage

Symbol

V_LDO#11

Conditions

Io = 1 to 100 mA

Ta= -30 to +85°C

Min

1.42

Typ

1.5

Max

1.58

Units

V

Output capacitor required for stability

Ripple rejection

Output noise voltage

Start-up Time from Shutdown

GND Current

C _LDO#11

V_NOISE

I_LDO#11

2.2

µF

dB

µV_RMS

µS

µA

f = 1KHz

f = 100 Hz to 100KHz

50

250

50

Io=150mA

Voltage Detector for LDO1 and LDO6

Parameter

LDO1 detect voltage

Symbol

V_DET1

Conditions

Ta= -30 to +85°C

Min

2.7

Typ

2.72

2.77

Max

Units

V

LDO1 release voltage

V_LDO1

-NOM

LDO1 Hysteresis

LDO6 detect voltage

LDO6 release voltage

V_HYS1

V_DET6

35

2.3

52

2.33

2.40

85

mV

V

Ta= -30 to +85°C

V_LDO6

-NOM

LDO6 Hysteresis

V_HYS6

40

60

100

mV

Ta= -30 to +85°C

BATTERY VOLTAGE DIVIDER: MVBAT

T_A=-30 to 85°C, C_VBAT=10µF MLCC, C_Adapter=1µF MLCC unless otherwise noted

Parameter

MVBAT Output voltage

Symbol

V_MVBAT

Conditions

VBAT=4.35V, MVEN = 1

code 10000

Min

Typ

Max

Units

5 – bit programmable

2.484 2.508 2.533 V/V

2.673 2.697 2.727 V/V

code 01111

MVBAT Output voltage step

Output drive current capability

MVBAT Load Regulation

MVBAT Output Voltage Step

Operating Battery Current

Shutdown Current

Vstep

Iout

∆ΜVBAT

VBAT=4.35V, MVEN = 1

6

2

3

6

65

mV/lsb

1

mA

mV

µA

5

0 < Iout < 100 µA

VBAT = 4.35 V, MVEN = 1

VBAT = 4.35 V, MVEN = 0

85

1

BATTERY CHARGER

T_A=-30 to 85°C, C_VBAT=10µF MLCC, C_Adapter=1µF MLCC, 4.0V ≤ ADAPTER ≤ 12V unless otherwise noted

Parameter

Charger Control Voltage Range

2 – bit programmable

Symbol

VBAT

SENSE

Conditions

Ta= 25 °C,

V_{R_SENSE}= 6mV & 115mV,

5.5V ≤ ADAPTER ≤ 12V (note 1)

code 00 (default)

code 01

Min

Typ

Max

Units

3.926 3.980 4.034

4.150 4.190 4.230

4.170 4.210 4.250

4.190 4.230 4.270

V

code 10

code 11

Charger Control Voltage Range

2 – bit programmable

VBAT

SENSE

Ta= -20 to 55°C,

V_{R_SENSE}= 6mV & 115mV,

5.5V ≤ ADAPTER ≤ 12V (note 1)

code 00 (default)

code 01

3.905 3.980 4.065

4.130 4.190 4.250

4.146 4.210 4.278

4.166 4.230 4.300

V

code 10

code 11

REV.PrP 2/6/02

- 5 -

PRELIMINARY TECHNICAL DATA

ADP3500

Charger Detect On Threshold

Charger Detect Off Threshold

ADAPT

ER-

110

165

23

225

mV

VBAT

ADAPT

ER-

5

50

mV

VBAT

I_ADAPTER

ADAPT

Charger Supply Current

Current Limit Threshold

High Current Limit

(Full charge current enabled)

Low Current Limit

(Full charge current disabled)

Pre-Charge Current Source

Base Pin Drive Current

ADAPTER=5V, VBAT=4.3V

ADAPTER=5V

2

185

70

7

mA

mV

ER-V_ISNSVBAT=3.6V

135

40

160

55

VBAT=3.0 V

3

15

5

28

2.675

mA

V

VBAT ≤ DDLO

Note 2.

VBAT<DDLO, Ta=25C, 5mA Pre-

Deep Discharge Lock-Out (Releasing voltage)

DDLO

2.78

charge, VBAT ramping up

Deep Discharge Lock-Out Hysteresis

ISENSE Bias Current

BATID pull-up resistor to ADAPTER

Minimum Load for Stability

200

100

mV

µA

KΩ

mA

I_ISNS

R_BATID

I_L

V_ISNS=5V

1

130

10

70

BATID=H. Note 3.

Note 1: Overhead includes external components, including sense resistor, PNP and isolation diode.

2: DDLO hysteresis is dependent upon DDLO threshold value. If DDLO threshold is at maximum, DDLO hysteresis is at

maximum at the same time.

3: Guaranteed but not tested.

REV.PrP 2/6/02

- 6 -

PRELIMINARY TECHNICAL DATA

ADP3500

LOGICS

DC Specifications

T_A=25°C, C_VBAT=1µF MLCC, VBAT = 3.6 V

Parameter

Symbol

Conditions

Min

2.25

Typ

Max

0.5

Units

CS, CLKIN, RESETIN-, TCXO_ON, SLEEP-,

KEYPADROW (Internal 10KΩ pull-up)

Input High Voltage

VIH

VIL

V

Input Low Voltage

470

mV

V

mV

V

Hysteresis

GPIO, DATA

VIH

VIL

2.25

2.69

Input High Voltage

Input Low Voltage

Hysteresis

0.5

VOH

VOL

Output High Voltage

Output Low Voltage

INT-

Output High Voltage

Output Low Voltage

BLIGHT (Open Drain Output)

Output Low Voltage

KEYPADCOL (Open Drain Output)

Output Low Voltage

IOH=400µA

IOL=-1.8mA

0.28

V

VOH

VOL

V

IOH=400µA

IOL=-1.8mA

0.28

0.4

VOL

V

IOL=-100mA

IOL=-1.8mA

0.15

PWRONKEY-, OPT1 (Internal 140KΩ Pull-up)

Input High Voltage

Input Low Voltage

VIH

VIL

Vhys

0.8xVBAT

V

mV

0.2xVBAT

950

Hysteresis

OPT2- (Input/Open Drain Output)

Input High Voltage

Input Low Voltage

Hysteresis

Output Low Voltage

OPT3

VIH

VIL

Vhys

VOL

V

mV

V

0.2xVBAT

0.1xVBAT

IOL=-1.8mA

VIH

VIL

Vhys

0.7xVBAT

0.9xRTCV

V

mV

Input High Voltage

Input Low Voltage

Hysteresis

0.2xVBAT

300

32KOUT

Output High Voltage

Output Low Voltage

RESET+ (Open Drain Output)

Output Low Voltage

OFF Leak

VOH

VOL

V

IOH=400µA

IOL=-1.8mA

0.1xRTCV

VOL

OFF_LEAK

IOL=-1.8mA

0.1xRTCV

1

V

µA

0.005

RSTDELAY-, RESETOUT- (Open Drain Output)

Output Low Voltage

VOL

IOL=-1.8mA

0.1xRTCV

V

BATID (Internal 100KΩ pull-up)

Input High Voltage

Input Low Voltage

Hysteresis

VIH

VIL

VADP=5 to 12V

0.8xVADP

V

0.2xVADP

0.16 x

VADP

1

Supply Current of RTCV

I_OSC

RTCV=3V,

µA

VBAT=0V

All logic: No load.

VADP: Adapter voltage

AC Specifications

All specs include temperature unless otherwise noted

Parameter

Symbol

RTCV

F_CLK

t_START

f_DEV

Conditions

Min

2

Typ

Max

3.1*

Units

V

KHz

mS

Operational Supply Range

Oscillator Frequency

Start-up Time (note)

Frequency deviation

32.768

100

TBD

RTCV=0V to 3V

RTCV=2 to 3V

200

REV.PrP 2/6/02

- 7 -

PRELIMINARY TECHNICAL DATA

ADP3500

Frequency Jitter

Cycle to Cycle

>100cycles

Long term Drift

f_JITTER/S

EC

RTCV=3V, TA=25°C

40*

50*

10*

nS

ppm

RTCV=3V, 3 minutes

SERIAL INTERFACE

Parameter

t_CKS

t_CSS

Min.

50

Typ.

Max

Units

nS

Test Condition/Comments

CLK set-up time

CS set-up time

t_CKH

t_CKL

t_CSH

t_CSR

t_DS

t_DH

t_RD

t_RZ

t_CSZ

100

62

50

40

nS

µS

nS

CLK “High” Duration

CLK “Low” Duration

CS hold time

CS recovery time

Input data set-up time

Input data hold time

Data output delay time

Data output floating time

Data output floating time after CS goes low.

50

nS

Note: These parameters are not tested.

ABSOLUTE MAXIMUM RATINGS

Voltage on ADAPTER pin to GND ……………………………..... -0.3, 15Vmax

Voltage on VBAT pin to GND …………………………………… -0.3, 7Vmax

Voltage on Pin 6-13, 21-28 to GND ……………………………… -0.3, V_LDO1+0.3Vmax

Voltage on Pin 1, 62-64 ………………………………………….. - 0.3, VBAT+0.3V max

Voltage on Pin 20, 32 …………………………………………….. - 0.3, V_RTCV+0.3V max

Voltage on Pin 60, 61 ……………………………………………... - 0.3, V_ADAPTER+0.3V max

Voltage on Pin 2-5, 14, 30, 31, 33 …………………………………. - 0.3, 7V max

Storage Temperature Range ………………………………………. - 65 to +150 °C

Operating Temperature Range ……………………………………. - 30 to +85°C

Maximum Junction Temperature …………………………………. 125°C

θ_JAThermal Impedance (LQFP-64) ………………………………. 2 layer board 76°C/W

θ

_JAThermal Impedance (LQFP-64) ………………………………. 4 layer board 54°C/W

Lead Temperature Range (Soldering, 60sec) ……………………... 300°C

ORDERING GUIDE

Model

Temperature Range

Package

ADP3500AST

-30 C to 85 C

LQFP 64 pins

REV.PrP 2/6/02

- 8 -

PRELIMINARY TECHNICAL DATA

ADP3500

PIN CONFIGURATION

64

49

1

48

VBAT

OPT3

KEYPADCOL0

LDO7 (RF Rx1)

LDO6 (Baseband Core)

VBAT

KEYPADCOL1

KEYPADCOL2

KEYPADCOL3

KEYPADROW0

KEYPADROW1

LDO5 (Vibrator)

LDO4 (Audio)

VBAT

KEYPADROW2

KEYPADROW3

KEYPADROW4

LDO2 (Baseband AVDD)

REFO

AGND

LDO3 (RTC/Coin-cell)

VBAT

KEYPADROW5

TCXO_ON

SLEEP-

BLIGHT

LDO1 (Baseband VDD)

LDO11 (Option)

VBAT

DGND

INT-

RSTDELAY-

16

33

17

32

Figure 2. Pin Configuration

PIN DESCRIPTION

Pin Mnemonic

I/O

I

Supply Function

1

2

3

4

5

6

7

8

9

OPT3

VBAT

LDO1

Optional Power ON input. ADP3500 will keep “power ON” during this pin goes “High”.

Keypad Column Strobe 0 (Open Drain, pull low)

Keypad Column Strobe 1 (Open Drain, pull low)

Keypad Column Strobe 2 (Open Drain, pull low)

Keypad Column Strobe 3 (Open Drain, pull low)

Keypad Row Input 0. Pulled up internally, 10KΩ

Keypad Row Input 1. Pulled up internally, 10KΩ

Keypad Row Input 2. Pulled up internally, 10KΩ

Keypad Row Input 3. Pulled up internally, 10KΩ

Keypad Row Input 4. Pulled up internally, 10KΩ

Keypad Row Input 5. Pulled up internally, 10KΩ

Logic input pin for Main LDOs (LDO1, LDO2, LDO3, LDO6) turning on control. L: OFF, H:

ON

KEYPADCOL0

KEYPADCOL1

KEYPADCOL2

KEYPADCOL3

KEYPADROW0

KEYPADROW1

KEYPADROW2

KEYPADROW3

O

I

10 KEYPADROW4

11 KEYPADROW5

12 TCXO_ON

I

13 SLEEP-

I

LDO1

Logic input pin for RF Rx LDOs (LDO7 and LDO9). Gating register data with this input for

these LDOs. LDO7 and LDO9 are turned OFF when SLEEP- goes Low even if the registers

set to ON.

14 BLIGHT

15 DGND

16 INT-

O

-

O

-

VBAT

LED drive. Open drain output.

Digital Ground

Interrupt signal output

Supply input for RTC, 32KHz OSC, and some other logics. Connects to Coin cell battery in

typical operation.

-

LDO1

-

17 RTCV

18 OSCOUT

19 AGND

20 OSCIN

21 GPIO0

-

RTCV

-

RTCV

LDO1

Connect to 32.768KHz crystal.

Analog Ground

Connect to 32.768KHz crystal.

General Purpose Input and Output port. Integrated Interrupt function. Interrupt occurs both

falling and raising edge.

I/O

22 GPIO1

23 GPIO2

24 GPIO3

I/O

LDO1

General Purpose Input and Output port. Integrated Interrupt function. Interrupt occurs both

falling and raising edge.

General Purpose Input and Output port. Integrated Interrupt function. Interrupt occurs both

falling and raising edge.

General Purpose Input and Output port. Integrated Interrupt function. Interrupt occurs both

falling and raising edge.

25 DATA

26 CS

27 CLKIN

28 RESETIN-

29 32KOUT

I/O

I

O

LDO1

RTCV

Serial Interface data input and output.

Serial Interface Chip Select input. Active High input.

Serial Interface Clock input.

Reset input signal for internal reset signal and starts Stay-Alive timer.

32.768KHz output. Output after 30mS when Reset is released.

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PRELIMINARY TECHNICAL DATA

ADP3500

30 RESET+

31 RESETOUT-

32 TEST

O

I

RTCV

Reset output. Invert signal of RESETOUT-. Open drain and low OFF leak.

Reset output. Follows Voltage Detector operation. Open drain output.

Test pin. If the pin tied to RTCV, test mode runs. Connect to GND for normal operation.

Reset output. 50mS delayed. Connect to baseband’ reset input as typical application. Open

drain output.

33 RSTDELAY-

O

34 VBAT

35 LDO11

36 LDO1

37 VBAT

38 LDO3

39 AGND

40 REFO

41 LDO2

42 VBAT

43 LDO4

44 LDO5

45 VBAT

46 LDO6

47 LDO7

48 VBAT

49 LDO8

50 AGND

51 LDO9

52 VBAT

53 LDO10

54 BVS

-

O

-

O

-

O

-

O

-

O

-

O

-

O

-

O

-

Supply input. Connect to Battery.

VBAT

-

VBAT

-

VBAT

-

VBAT

-

VBAT

-

VBAT

-

VBAT

-

VBAT

-

Regulator #11 output. Use for Optional circuit.

Regulator #1 output. Use for Baseband I/O supply.

Supply input. Connect to Battery.

Regulator #3 output. If VBAT>2.7V, the output is always active. Use for Coin cell supply.

Analog Ground

Output of LDO2 through FET switch.

Regulator #2 output. Use for Baseband analog supply.

Supply input. Connect to Battery.

Regulator #4 output. Use for General analog supplies. Ex. Speaker Amp.

Regulator #5 output. Use for Vibrator.

Supply input. Connect to Battery.

Regulator #6 output. Use for Baseband core supply.

Regulator #7 output. Use for RF Rx IC supply. Gated with SLEEP- signal input.

Supply input. Connect to Battery.

Regulator #8 output. Use for RF Tx IC supply.

Analog Ground

Regulator #9 output. Use for RF Rx IC supply. Gated with SLEEP- input signal.

Supply input. Connect to Battery.

Regulator #10 output. Use for Optional circuit.

Battery Voltage Sense input for Charger. Connect to Battery.

Noise reduction capacitor. 0.1µF MLCC.

55 NRCAP

56 AGND

57 MVBAT

58 BASE

59 ADAPTER

60 BATID

O

-

O

-

VBAT

-

VBAT

Analog Ground

Battery voltage divider output. Buffered internally. Connect to Baseband ADC.

ADAPTER Base drive output for PNP pass transistor

-

AC adapter input. Use to charger supply.

Battery identification. 100KΩ pulled up internally. “L”: Battery exist, “H”: No battery. If

BATID=”H”, Charger operates with “No current Limit”.

I

ADAPTER

61 ISENSE

62 PWRONKEY-

63 OPT1-

I

ADAPTER Charge current sense input

VBAT

Power ON/OFF key input. Pulled up internally (140KΩ).

Optional Power ON input. ADP3500 will keep “power ON” during this pin goes “Low”.

While the part is powered up, the input is pulled to Low (GND) internally. Don’t connect to

any supply or signal source.

64 OPT2-

I/O

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PRELIMINARY TECHNICAL DATA

ADP3500

BLOCK DIAGRAM

VBAT

AGND

BVS

54

ADAPTER ISENSE BASE

56 50 39 19

52 48 45 42 37 34

59

61

58

100KΩ

60

BATID

VBAT

Charger_Detect

Charger Control

Battery Charger

Ω

140K

57

40

55

36

MVBAT (VBAT Measure)

REFO

POWERON_N

OPT1_N

DDLO

LDO_EN

62

63

PWRONKEY-

OPT1-

REF

power_on

OPT2_N

OPT3

OPT2- ⁶⁴

1

OPT3

RTC

Alarm

REF

NRCAP

LPF

LDO1

BATID

Main

Sub

LDO1 (Baseband VDD)

ON/OFF

LOGIC

voltage_detect

PWROFF

CLK

LDO1

Delay

10mS

Main

41

38

ON/OFF

LOGIC

LDO2 (Baseband AVDD)

LDO3 (RTC/Coin-cell)

LDO2

Sub

sync

5

CLK

Main

ON/OFF

LOGIC

LDO3

LDO6

LDO4

LDO5

LDO7

LDO8

LDO9

LDO10

LDO11

Data

In

Main

Sub

46

43

ON/OFF

LOGIC

LDO6 (Baseband Core)

LDO4 (Audio)

INT_N

Level

trans

16

INT-

2

KEYPADCOL0

44

47

49

51

LDO5 (Vibrator)

LDO7 (RF Rx1)

LDO8 (RF Tx)

LDO9 (RF Rx2)

5

3

4

LDO1

KEYPADCOL1

KEYPADCOL2

KEYPADCOL3

KEYPADROW0

KEYPADROW1

KEYPADROW2

KEYPADROW3

KEYPADROW4

KEYPADROW5

Level

trans

INT

5

4

6

KEY

PAD

I/F

7

8

Level

trans

9

6

10

11

14

53

35

LDO10 (RF Option)

LDO11 (Option)

LDO1

GPIO_INT / gpi_intrst

BLIGHT

DGND

15

26

27

CS

CLKIN

DATA

GPIO0

GPIO1

GPIO2

GPIO3

Voltage

Detector

Serial

I/F

DATA

25

21

22

23

13

12

SLEEP-

TCXO_ON

Level

trans

Level

trans

DATA

CLKs

GPIO

+

INT

²⁸RESETIN-

Level Translator

VBAT & RTCV

LDO1

RTCV

24

LDO1

DGND

Level Translator

17

20

18

RTCV

OSC IN

DGND

32KHz

OSC OUT

Delay

30mS

32K OUT 29

32

TEST

Open Drain

RTC

/clock

CLKs

33

Delay

50mS

RSTDELAY-

Data

31

RESETOUT-

Stay/Alive

Timer

0.25-8sec

Data

³⁰RESET+

RESETIN_N

Figure 3. Overall Block Diagram

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PRELIMINARY TECHNICAL DATA

ADP3500

Theory of Operations

As illustrated in Figure 1 at the beginning, ADP3500 can be divided into two high level blocks – Analog and Logic. The Analog

block mainly consists of LDO regulators, battery charger, reference voltage, and voltage detector sub-blocks, all of which are

powered by the main power source(VBAT), namely the main battery or the charging adapter. On the other hand, the Logic block is

more complicated. All the Logic sub-blocks are also powered by VBAT except the RTC counter, 32MHz Output control, RESET

Output, and Stay-Alive Timer. These sub-blocks are powered from RTCV pin, as indicated in Figure 4 in shaded area.

[VBAT]

5

4

3

2

1

6

7

DELAY 10mS

POWER ON

KEYPAD I/F

GPIO

INTERRUPT

CONTROL

SERIAL I/F

RESET

ANALOG

BLOCK

LDO CONTROL

8

[RTCV]- RTC BLOCK

32K OUTPUT

RTC COUNTER

9

CONTROL

10

RESET OUTPUT

11

STAY-ALIVE TIMER

Figure 4. Power partitioning of sub-blocks

1. ANALOG BLOCKS

1.1 LOW DROP-OUT(LDO) REGULATORS

There are total four Sub-LDOs for each LDO1, 2, 3, and 6, in order to meet lower power consumption at light load (stand-by

operation). They are used at low load condition, but they are continuously ON even if the each Main-LDOs are ON. The LDO3 and

3b are used for Coin cell and LDO3b is always ON until Main battery (VBAT) is downed to 2.5V due to DDLO function. LDO7 and

9 are controlled with SLEEP- signal. For detail of LDO ON/OFF control, please refer to Section “2.8 LDO Control”.

Table 1. Ground currents of LDOs with each handset operations.

Baseband Baseband

Baseband

AVDD

RF

Rx1

RF

Tx

RF

Rx2

RF

Option

Main Total LDO

LDO names

Coin Cell Audio Vibrator

Option

VDD

Core

REF

IGND

LDO #

1

6

3

4

5

2

7

8

9

10

11

Power OFF

OFF

OFF OFF OFF

OFF

10µA

20µA

30µA

50µA

Light load

Mid-load

OFF

OFF OFF OFF

OFF

10µA

60µA

5µA

55µA

10µA

60µA

5µA

55µA

Stand-

by

mode

OFF OFF OFF

50µA

20µA 300µA

20µA 450µA

Active load

50µA 50µA 50µA 50µA

Talk

Ring

OFF

50µA

60µA

55µA

60µA 50µA

55µA

50µA 50µA 50µA 50µA

50µA 20µA 550µA

50µA 20µA 600µA

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PRELIMINARY TECHNICAL DATA

ADP3500

Table 2. LDO operation overview

Current

Rating (mA)

Voltage (Typ)

Or Range

2.90V

Step size

(mV)

N/A

20

Regulator

Names

Program steps

Default

Cout

LDO1a

LDO1b

LDO2a

LDO2b

LDO3a

LDO3b

LDO4

Baseband VDD

Baseband VDD sub

Baseband AVDD

Baseband AVDD sub

RTC/Coin Cell

RTC/Coin Cell sub

Audio

150

1

50

0.3

50

1

180

150

50

0.3

100

150

50

N/A

16

-

2.2µF

1µF

2.87V

2.36V~2.66V

2.33V~2.63V

3.0V

2.52V

2.49V

16

20

N/A

-

2.97V

2.9V

2.6V

2.57V

2.9V

1µF

2.2µF

1µF

LDO5

Vibrator

LDO6a

LDO6b

LDO7

LDO8

LDO9

Baseband Core

Baseband Core sub

RF Rx1

1µF

2.2µF

1µF

2.2µF

RF Tx

RF Rx2

RF Option

LDO10

LDO11

50

100

2.9V

1.5V

Option

1.2 BATTERY CHARGER

1.2.1. Block Diagram

Cvbat

RSENSE

ISENSE

AC Adapter

C_ADAPTER

VBAT

ADAPTER

BASE

BVS

Battery

Pre-charge

5m A

+

V(ISENSE)

-

gm

EN

gm

EN

DDLO

EN

MVBAT

EN

MVBAT

REF

100KΩ

BVS

BATID

CHI

CHEN

Charger_

Detect

CHV MVEN

0/1

MV4:0

LDO_

EN

BATID

LOGIC Block

Figure 5. Battery charger block diagram

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PRELIMINARY TECHNICAL DATA

ADP3500

1.2.2. Flow Chart

Battery charger start

N

V_ADAPTER>VBAT

?

Y

Set Charger Detect flag

DDLO comparator will

operate if VBAT>2V.

Even if VBAT<2V, pre-

charge is continuously

applying 5mA.

Pre-charge 5mA

RESETIN- should be

asserted until baseband

chip active.

VBAT>DDLO

?

Then, CHEN=1 as default.

LDO3b: ON

BATID=0: Battery connected

BATID=1: Battery disconnected

BATID=0

?

Set Low Current Charge

I_ADAPTER=250mA

Current Loop Disabled

Voltage Loop Regulates

VBAT to 4.0V

Determined by external

sense resistor

(50mV on Rsense)

Pre-charge: OFF

LDO1, 1b, 2, 2b, 3, 6, 6b

Voltage Detector

all enabled

Voltage Detector

VLDO6>2.5V

AND

VLDO1>2.7V

?

Figure 6. Charger flow chart A

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PRELIMINARY TECHNICAL DATA

ADP3500

A

Reset sequence runs

Baseband sets Charge Voltage

Baseband sets MVBAT gain

Baseband Enables

Full charge current?

(CHI=1?)

CHI=0: Full current charge OFF

CHI=1: Full current charge ON

N

Y

Low Current Charge: OFF

Set Full current charge

I

=750mA

ADAPTER

(150mV on Rsense)

N

Baseband

CHEN=0?

Y

Charging Terminated

Figure 7. Charger flow chart B

1.2.3. Charger Detect function

The ADP3500 will detect that a charging adapter has been applied when the voltage at the ADAPTER pin exceeds the voltage at

BATSNS. The ADAPTER pin voltage must exceed the BVS voltage by a small positive offset. This offset has hysteresis to prevent

jitter at the detection threshold. The charger detection comparator will set the Charger_Detect flag in the 20h register and generate an

interrupt to the system. If the ADAPTER input voltage drops below the detection threshold, charging will stop automatically and the

Charger_Detect flag will be cleared and generate an interrupt also.

1.2.4. DDLO function and operation

The ADP3500 contains a comparator that will lock out system operation if the battery voltage drops to the point of deep discharge.

When the battery voltage exceeds 2.675 V, the reference will start as will the sub-LDO 3b. If the battery voltage drops below the

hysteresis level, the reference and LDO's will be shut down, if for some reason they are still active. Since LDO1 will be in deep

dropout and well below the voltage detector threshold at this point, the reset generator will have already shut down the rest of the

system via RESET+, RESETOUT-, and RSTDELAY-.

If a charging adapter has been applied to the system, the DDLO comparator will force the charging current to trickle charge if the

battery is below the DDLO threshold. During this time, the charging current is limited to 5 mA. When the battery voltage exceeds

the upper threshold, the low current charging is enabled, which allows 55 mV (typical) across the external charge current sense

resistor. See also Figure 6, the Battery Charger Flowchart.

1.3 MVBAT

The ADP3500 provides a scaled buffered output voltage for use in reading the battery voltage with an A/D converter. The battery

voltage is divided down to be nominally 2.600 V at full scale battery of 4.35 V. To assist with calibrating out system errors in the

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PRELIMINARY TECHNICAL DATA

ADP3500

ADP3500 and the external A/D converter, this full scale voltage may be trimmed digitally with 5 bits stored in register 12h. At full

scale input voltage, the output voltage of MVBAT can be scaled in 6 mV steps, allowing a very fine calibration of the battery voltage

measurement. The MVBAT buffer is enabled by the MVEN bit of register 11h, and will consume less than 1 uA of leakage current

when disabled.

1.4 REFERENCE

The ADP3500 has an internal, temperature compensated and trimmed band-gap reference. The battery charger and LDO's all use

this system reference. This reference is not available for use externally. However, to reduce thermal noise in the LDOs, the

reference voltage is brought out to the NRCAP pin through a 50kohm internal resistor. A cap on the NRCAP pin will complete a low

pass filter that will reduce the noise on the reference voltage. All the LDO's, with the exception of LDO3, use the filtered reference.

Since the reference voltage appears at NRCAP through a 50kohm series internal impedance, it is very important to never place any

load current on this pin. Even a volt meter with 10 megohm input impedance will affect the resulting reference voltage by about 6 or

7 mV, affecting the accuracy of the LDO's and charger. If for some reason the reference must be measured, be certain to use a high

impedance range on the volt meter or a discrete high impedance buffer prior to the measurement system.

2. LOGIC BLOCKS

ADP3500 has following logic functions.

•

Three wire Serial Interface (CS, CLK, DATA)

RTC counter section has Year, Month, Day, Week,

Hour, Minute, and Second, and controls Leap year,

and days in month automatically.

Detect Alarms based on RTC counter.

Periodically constant interrupt feature. (2Hz, 1Hz,

1/60Hz, 1/3600Hz, Once a months)

•

GPIO and INT ports control

Key-pad interface

LED light control

LDO functions

Clock and Reset output control

Stay-Alive timer

•

Following is a block diagram based on Logic circuit.

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- 16 -

PRELIMINARY TECHNICAL DATA

ADP3500

[VBAT]

voltage_detect

chager_detect

DELAY

10mS

voltage detect_delay

SYNC.

power_on

PWRONKEY_N

OPT1_N

Interrupt

register

block

OPT2_N

POWER

OFF

OPT3

pwronkey_n_sync,

opt1_n_sync,

opt3_sync

batid

SYNC.

BL

SYNC.

DATA

IN

Analog block

LED control

BLIGHT

DGND

KEY PAD

I/F control

4

6

KEYPADCOL

KEYPADROW

INT

control

register

keypad_int

KEY PAD

I/F

(reset & mask)

4

GPIO

control

GPIO[3:0]

GPIO

INT_N

TCXO_ON

SLEEP_N

LDO control register

Analog

Blocks

write_enable

write_data[7:0]

CS

CLKIN

DATA

Analog

control

registers

Serial

I/F

sp_addr[4:0]

Data

select

resetin_n

(reset for registers)

RESETIN_N

LDO

Control

rtc_resetin_n

analog block

rtc_clk32k

OSCOUT

OSCIN

32K OSC

clk32k

32K CLK

output

control

Output data

select

32K OUT

clk512

Address

decode

RTC

Test mode

register

block

clk1k

Stay-Alive

Timer

test_ldoenable

test_mode

RTC register block

rtc_test

TEST

rtc_voltage_detect

RESETOUT_N

RSTDELAY_N

reset output

control

RESET

[RTCV]

Figure 8. LOGIC block diagram

2.1 RESET

2.1.1 RESETIN- signal

The internal reset function is activated by external reset input, RESETIN-, and this is an asynchronous signal. The internal

reset signal is used in the following blocks.

•

Serial I/F

Interrupt control

Stay-Alive timer

Registers (refer to the Register section for detail).

LDOs, controlled by Serial I/F, are applied “RESET” by RESETIN-. LDO4, LDO5, LDO7, LDO8, LDO9, LDO10, LDO11

and REF0 are set to “0”. In case RESETIN- has noise, the internal circuit may be in reset and cause the system unexpected

result. Please take enough treatment. RESETIN- is level translated from LDO1 to both VBAT and RTCV supplies.

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PRELIMINARY TECHNICAL DATA

ADP3500

2.1.2 RESET output control and 32KHz output control

Using Voltage Detect signal, device generates 32K OUT, RSTDELAY-, RESETOUT-, and RESET signals. About 32mS after

rtc_voltage_detect (Voltage Detect signal in RTCV supply) signal goes from “0” to “1”, 32K OUT signal is generated from

internal RTC_CLK32K signal. RSTDELAY_N (RSTDELAY-) goes to “0” when rtc_voltage_detect is “0”, and it goes to “1”

at 50mS after the “0” to “1” transition of rtc_voltage_detect. RESETOUT_N (RESETOUT-) and RESET toggle their states.

Signal clk512 is a 512Hz, which generated in USEC counter block.

2.2 SERIAL INTERFACE

t^CSR

CS

t^CKSt^CSS

t^CSH

t^CKH

CKL

t

CLKIN

Serial

DATA

CTRL2 (W)

ADDR5

ADDR4 0 CTRL1 (W)

DATA7

1

DATA0

Serial I/F WRITE Timing

t^CSR

CS

t^CKSCSS

t

t^CKH

t^CKL

CLKIN

Serial

DATA

ADDR5 ADDR4

0

CTRL1 (R) CTRL2 (R)

1

DATA0

DATA7

t^RD

t^CSZ

Serial I/F READ Timing Single Mode

CS

t^CKSt^CSS

t^CKH

t^CKL

CLKIN

Serial

DATA

CTRL1 (R) CTRL2 (R) DATA7

ADDR4 0

1

DATA0

ADDR5

ADDR4

ADDR5

t^RD

t^RZ

Serial I/F READ Timing Continuous Mode

Figure 9. Serial Interface signal

Table 3. Set up and Hold Specifications

Parameter Min. Typ. Max

Units

Test Condition/Comments

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PRELIMINARY TECHNICAL DATA

ADP3500

t_CKS

t_CSS

t_CKH

t_CKL

t_CSH

t_CSR

t_DS

t_DH

t_RD

t_RZ

t_CSZ

200

400

500

62

nS

µS

nS

CLK set-up time

CS set-up time

CLK “High” Duration

CLK “Low” Duration

CS hold time

CS recovery time

200

Input data set-up time

Input data hold time

Data output delay time

Data output floating time

Data output floating time after CS goes low.

300

2.2.1. Function block

ADP3500 integrates the serial bus interface for easy communication with the system. The data bus consists of three wires,

CLK, CS, and DATA, and is capable of Serial to Parallel / Parallel to Serial conversion of data, as well as clock transfer.

resetin_n

CS

CLKIN

sp_addr [5:0]

Creation of

DATAIN

write_enable

Serial To Parallel

Conversion

write Data

sp_data [7:0]

RW_SEL

Synchlonization

and Data Selection

ps_data [7:0]

Parallel to Serial

Conversion

DATA

Figure 10. Serial Interface block diagram

Serial interface block works during the time period at CS signal enable. After the falling edge of CLKIN signal right after the

rising edge of CS signal, Address, transfer control signal and write data are held in sequentially. In case DATA READ, each of

data will be prepared by rising edge of CLKIN and baseband chip may want to read or latch the data at falling edge of CLKIN.

While CS is not asserted, CLKIN is ignored. If CS goes “L” while CLKIN is continuously applied or input DATA, all data is

canceled and DATA line would be High impedance. In this case, user needs to input the data again. Please note that CLKIN

should be stayed “L” when CS goes H. RTC counter registers should be accessed at a certain time (>62µS) later after CS

assertion. Asserting RESETIN_N (RESETIN-) signal resets the block..

Notes:

•

CLKIN=10KHz to 1MHz, 20/80% duty cycle.

CLKIN should be “L” when CS goes “H”.

In case of RTC counter access, the access should be approximately 62µS, (2 clock cycles of CLK32K) after the CS signal

is asserted, to hold the RTC value.

•

The CS should not be asserted for 62µS, (2 clock cycles of CLK32K) after the CS is released.

CS signal should never be asserted for 1 sec or longer, otherwise RTC counter makes error.

2.2.2 Data input/output timing

5

4

3

2

1

0

1

0

7

6

5

4

3

2

1

0

Read DATA(8bit)

Address(6bit)

R/W(2bit)

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PRELIMINARY TECHNICAL DATA

ADP3500

Figure 11. Serial I/F Data read/write timing

SP_ADDR[5:0]

SP_CTRL[1:0]

SP_DATA[7:0]

: 6bit address

: 2bit Read/Write control (01: Write, 10: Read)

: 8bit Input/Output Data

* All transfer will be done MSB first.

2.3 GPIO+INT

GPIO block has 4 channel I/O function and interrupt. With GPIO CONTROL register (1Ah), it is possible to control Input or

Output setting of each channel individually. The output data is set in GPIO register (1Ch). When the port is set as input mode,

the input signal transition from “1” to “0” and from “0” to “1”, then generate interrupt signal with Edge detection. The held

interrupt signals are reset by GPIO INT RESET register (1Dh). Setting GPIO MASK register (1Bh) to “1” enables the

interrupt of GPIO. (Not MASKED, “1” at default in reset.)

2.4 INT REGISTER

In case the interrupt event has occurred, “1”, the signal is held in this register. INT detect and Reset are synchronized at the

rising edge of CLK32K. In case the interrupt event and reset signal are occurred at same time, interrupt event has priority.

RESETIN_N signal resets INT register (1Eh) to “0” (No INT detected), except alarm_int and ctfg_int. INT MASK register

(1Fh) to “1” (not masked). This block masks alarm_int and ctfg_int, which generated in RTCV block, but these signals are

reset with ALARM CONTROL register (0Dh) and CTFG CONTROL register (0Eh). The interrupt signal, INT_N, is an

“inverted OR” signal of value in INT register and GPIO register.

DATA-IN register is a port to read an interrupt status. The input data are through SYNC block except Alarm signal. Since this

is for just read back purpose, user cannot write any data.

SYNC block

BATID

Register

RTC Alarm

Charger_Detect

DATA_IN registor (Addr: 20h)

OPT3

OPT1-

PWRONKEY-

Figure 12. DATA-IN block

2.5 KEYPAD CONTROL & LED DRIVE

KEYPADCOL[3:0] are Open Drain output. The KEYPADROW[5:0] are Falling edge trigger input (input state transition from

“1” to “0”) and generate Interrupt signal, and are pulled up to LDO1. By providing 4 keypad-column outputs and 6 keypad-

row inputs the ADP3500 can monitor up to 24 keys with baseband chip. Writing Column outputs and Reading Row inputs are

controlled through serial interface. The address of the KEYPADROW is 19h, and KEYPADCOL is 18h. Initial register value

is “0” that means an output of KEYPADCOL is “High Impedance”.

Back-light drive is an open drain output. Maximum current of internal FET is 100mA. Initial register value is “0” that means

the output of BLIGHT is “High impedance”.

REV.PrP 2/6/02

- 20 -

PRELIMINARY TECHNICAL DATA

ADP3500

2.6 POWER ON INPUT

PWRONKEY and OPT1 have pull-up resistors, and others are not. In addition to these inputs, other internal input signals such

as charger_detect and Alarm signal (alarm_int) from RTC enable Main and Sub LDOs of LDO1, 2, 3 and LDO6. Power ON

status is hold by a latch data in Delay circuit, called voltage_detect_delay (please see 4.8 for more detail). OPT3 has a lower

voltage threshold. OPT2 is different structure to the other inputs, and is pulled down to zero by internal signal when phone is

Power ON status, in order to make sure to have Power ON status even if short-term disconnection is happened. Following is a

block diagram and Power on sequence.

VBAT

140KΩ

voltage_detect_delay

charger_detect

alarm_int

PWRONKEY-

OPT1-

power_on

OPT2-

OPT3

INT

Block

Figure 13. Power ON input block diagram

•

Voltage_detect_delay

charger_detect

alarm_int

PWRONKEY-

OPT1-

: Voltage Detect Signal (10mS delay)

: Charger Detect Signal

: Alarm Detect Signal (Alarm 1 or 2)

: Power On key input

: Power On signal

(1: Assert)

(0: Assert)

(1: Assert)

OPT2-

OPT3

: Power On signal

REV.PrP 2/6/02

- 21 -

PRELIMINARY TECHNICAL DATA

ADP3500

POWER OFF

POWER ON

PowerOnKey

POWERON

LDO1, 2, 3, 6

LDO1b, 2b, 6b

Voltage Detector

voltage_detect_delay

RSTDELAY-

OPT2

10mS

50mS

INT-

Clear INT-

Serial I/F

Clear INT- and set PWROFF(21h)=1

Figure 14. Power ON sequence

2.7 10 MILISECOND DELAY

This block generates a 10mS delayed signal after the reset of the voltage_detect signal is released. After 10mS (11 clocks of

1024Hz) since the voltage_detect signal is asserted, the voltage_detect_delay signal is asserted. If the duration of the

voltage_detect signal is less than 10mS, voltage_detect_delay signal will not be asserted. When the voltage_detect signal is

released, the voltage_detect_delay signal is also released simultaneously. The voltage_detect_delay signal can be reset with

writing “1” in POWER OFF register (21h).

* User just need to write “1” in the POWER OFF register to reset voltage_detect _delay, and not need to over-write it with “0”.

2.8 LDO CONTROL

The LDO control block controls Power ON/OFF of LDO block. The function in this block has:

•

Hardware control using external signals

Software control using serial interface

Mixture of hardware and software above

LDO1, LDO2, LDO3, and LDO6 are structured with Main and Sub LDOs. LDO4, LDO5, LDO7, LDO8, LDO9, LDO10, and

LDO11 are set through serial interface but LDO7 and LDO9 are gated (AND gate) with SLEEP- signal, in order to get into

Sleep mode. If the SLEEP- signal is enabled (goes “Low”), the outputs of LDO7 and LDO9 are turned OFF. Remainder of

LDOs as LDO1, LDO2, and LDO6 is controlled by “Power On Logic”. A Sub LDO called “LDO3b” is independent control

and this LDO control block doesn’t control LDO3b. And Main LDO3 called “LDO3a” is turned on by power_on signal, but

Sub LDO3 called “LDO3b” is always ON while Battery supplies and LDO3b is only controlled by DDLO. A DDLO is control

signal from Battery charger block and is monitoring Battery voltage. When VBAT is under 2.5V (200mV hysteresis from

VBAT=2.7V), DDLO minimizes (DDLO enable) current flow from Li-Ion battery.

Main LDOs

Sub LDOs

: LDO1a, LDO2a, LDO3a, LDO6a

: LDO1b, LDO2b, LDO3b, LDO6b

Table 4a. DDLO status table

Status

LDO1a LDO1b LDO2a LDO2b LDO3a LDO3b LDO4 REFO LDO5 LDO6a LDO6b LDO7 LDO8 LDO9 LDO10 LDO11

Baseband

AVDD

RF

Option

Baseband VDD

Coin cell

Audio REFO Vibrator Baseband Core Rx1

Tx

Rx2

Option

DDLO Enable

DDLO Disable

OFF

X

OFF

X

OFF

ON

OFF

X

OFF

X

OFF

X

OFF

X

OFF

X

OFF

X

OFF

X

OFF

X

OFF

X

OFF

X

Note

REV.PrP 2/6/02

- 22 -

PRELIMINARY TECHNICAL DATA

ADP3500

1. “X” means a status of LDO depends on other conditions.

Table 4b. LDO Control Event Table

Event

LDO1a LDO1b LDO2a LDO2b LDO3a LDO3b LDO4 REFO LDO5 LDO6a LDO6b LDO7 LDO8 LDO9 LDO10 LDO11

Baseband

AVDD

RF

Option

Baseband VDD

Coin cell

ON

Audio REFO Vibrator Baseband Core Rx1

Tx

Rx2

Option

POWER ON

(Note 2)

ON

TCXO_ON

(Note 3)

ON/

OFF

ON/

OFF

ON/

OFF

ON/

OFF

SLEEP-

(Note 4)

ON/

OFF

ON/

OFF

RESETIN-

OFF

“ALLOFF” bit

goes “H”

OFF

“PWROFF” bit

goes “H”

OFF

Notes

1. This table only indicate the change of status caused by an event. Blank cells means “no change” and keep previous status

2. Power ON Event: Indicating a status just after the power ON event. After the event, a status of LDO1a, 2a, 3a, and

LDO6a are changed by TCXO_ON signal.

3. TCXO_ON: Hardware control, change all Main-LDO’ ON/OFF status.

4. SLEEP-: The LDO7 and LDO9 are able to be controlled by software if SLEEP=”H” level. If SLEEP- goes “L”, these

LDOs are turned OFF immediately.

Table 4c. Software Controllability of LDOs

LDO1a LDO1b LDO2a LDO2b LDO3a LDO3b LDO4 REFO LDO5 LDO6a LDO6b LDO7 LDO8 LDO9 LDO10 LDO11

LDO description

Baseband

AVDD

RF

Option

Baseband VDD

Coin cell

Audio REFO Vibrator Baseband Core Rx1

Tx

Rx2

Option

Software Turn

ON

√

(Note1)

Software Turn

OFF

√

Note

1. LDO7 and LDO9 have a gate with SLEEP-. If SLEEP- is in “L” (active) status, user cannot control and both LDOs are kept

to “OFF” status. User may want to use this function as immediate control to get OFF status by using SLEEP- hardware control

while set register “1” to the LDO control register.

2.9 RTC BLOCK

The Calendar registers are set through serial interface.

2.9.1 Function

•

RTC counter using binary

Reading out and writing setting s of Year, Month, Day, Week, Hour, Minute, and second data.

Leap year controls, Number of days in a month control

Alarm function (Weak, Hour, Minute)

Periodic Interrupt function - 2Hz, 1Hz, 1/60Hz, 1/3600Hz, Each month (First day of each month)

Protection of wrong data readout during RTC data update.

REV.PrP 2/6/02

- 23 -

PRELIMINARY TECHNICAL DATA

ADP3500

RTC_CLK32K

RTC_SP_ADDR[5:0]

RTC

Register

block

Loading Alarm times

RTC_WRITE_ENABLE

RTC_WRITE_DATA[7:0]

(from serial I/F)

Alarm

Comparator

rtc_alarm_int

rtc_ctfg_int

Periodic

Interrupt

RTC

Counter

leap year

and Date

Control

Reset will be asserted when

RTC counter is writed.

Data

Select

rtc_data[7:0]

RTC_CS

Sec counter

Increment

control

USEC

Counter

Registers for

Test mode

- Reset to RTC & USEC counters

- Write initial data of USEC counter

Figure 15. RTC counter block

2.9.2 Operation

Synchronizing with RTC_CLK32K clock, USEC counter generates 1sec timing clock and the clock hits RTC counter.

Through the serial interface, CPU can write setting value and read RTC counter value. In case the RTC counter toggles during

the serial interface access to RTC counter, the wrong data can be read/write between RTC counter and interface. CS signal

stops the clocking to RTC counter until CS signal is released. In case CPU writes data into SEC counter, USEC counter is

reset to zero.

Note

•

In case of RTC counter access, the access should be waited approximately 62µS, (2 clock cycles of CLK32K) after the

CS signal is asserted, to hold the RTC value.

•

CS signal should never be asserted 1sec or longer, this affects counter operation.

2.9.3 Operation of USEC counter

USEC counter counts up synchronizing with RTC_CLK32K clock. It generates 1sec timing signal and it is used as an

increment clocking of RTC counter. In case the 1sec signal is generated during CS signal asserted, the increment clock is

delayed until CS signal is released.

2.9.4 Operation of RTC counter

RTC counter uses the increment signal from USEC counter to control counting operation including the leap year control and

numbers of days in a month control.

REV.PrP 2/6/02

- 24 -

PRELIMINARY TECHNICAL DATA

ADP3500

Enabled signals created

by decoding of

RTC_SP_ADDR[5:0]

06h

Year 100 scale

addr06h_write

addr00h_write

Leap year

&

days in month

control

12 scale

31 scale

7 scale

05h Month

Initial data

Date

04h

To following

counters

03h Week

year_count

month_count

day_count

week_count

hour_count

min_count

sec_count

12 scale

60 scale

Hour

02h

01h

00h

Minute

inc_enb

inc_clk

USEC

counter

Second 60 scale

Figure 16. RTC counter block diagram

Definition of Leap year

The definition of a leap year is, “a year which can be divided by 4 and can not be divided by 100” and “a year which can be

divided by 400.” For this device, the following definition is used instead.

“A year which can be divided by 4”

Note

-

Year counter = “00” means year 2000, and is a leap year because it can be divided by 400.

Actual covered year period is from 1901 to 2099.

Number of days of month control

Months 1, 3, 5, 7, 8, 10, 12 have 31days.

Months 4, 6, 9, 11 have 30days.

Month 2 has 28days, but has 29 in leap year.

2.9.5 Alarm Function

Comparing the RTC counter value with the seting value in alarm_setting register (07h-09h), alarm condition is detected.

Setting of week uses 7bits for each day in a week, and works with multiple days setting. There is a delay of 62µS from Alarm

detection to setting up to AOUT/BOUT registers.

ALA_EN flag in ALARM CONTROL register (0Dh) sets Enable/Disable of alarm detection. INT register (1Eh) indicates the

interrupt signals, alarm_int of ALA or/and ALB. INT MASK register (1Fh) do mask of alarm interrupt signal. Alarm

detection state is indicated as AOUT of ALARM CONTROL register (0Dh), and the alarm can be released by writing “1” at

the bit. Alarm B is also controlled as same as Alarm A is.

Note: User just need to write “1” to release the alarm, and not need to write “0” after “1”. User doesn’t need to wait 62µS

from CS assertion.

2.9.6 Periodic Interrupt function

This is a function, which generates interrupt periodically. The timing of cycle can be selected from 2Hz (0.5sec clock pulse),

1Hz (1sec clock pulse), 1/60Hz (minutes), 1/3600Hz (hour), and month (first day of each month).

The cycle is set using CT2-CT0 value in CTFG CONTROL register (0Eh). The state when interrupt is generated is indicated at

INTRA bit of CTFG CONTROL register (0Eh). INT MASK register (1Fh) only does mask of periodic interrupt signal. There

are two kinds of pattern of CTFG Interrupt signal output.

•

Hold the value when the interrupt is occurred (level).

After the interrupt event is happened, assert interrupt signal in certain time period then release it (pulse).

REV.PrP 2/6/02

- 25 -

PRELIMINARY TECHNICAL DATA

ADP3500

In level case, interrupt is occurred at each 0 min (1/60Hz), 0 o’clock (1/3600Hz) or at first day of month. Because they are

happened in long cycle, the value is held at register. After the CPU checks the state, it is released by writing “1” at CTFG bit

of CTFG CONTROL register. In case of 2Hz and 1Hz, the interrupt is not held because the event happens in short cycle.

These event signal output pulse signal of 2Hz or 1Hz in RTC counter directly. Interrupt release operation doesn’t affect on the

interrupt signal in the case.

2.10 STAY-ALIVE TIMER

This is a counter, which increments each 250mS after RTC_RESETIN_N is asserted. It holds its value when the counter

counts full up. Signal clk4 is a 4Hz (250mS) clock which generated in USEC counter. The counter can be reset by writing “1”

at CLR of Stay-Alive TIMER CONTROL register (0Fh). The RTC_RESETIN_N signal is transferred from a logic input

circuit, that is supplied by VBAT, of RESETIN_N.

Note

:

User just need to write “1” to release the interrupt, and not need to write “0” after “1”.

clk4

Stay-Alive Timer

test_reset

SA[4:0]

RTC_RESETIN_N

D

5bit counter

CLRB

Register

Stay-alive Timer Control register (0Fh): CLR

Stay-alive Timer Control register (0Fh): SAx

Figure 17. Stay-Alive Timer block diagram

rtc_voltage_detect

sa_clear

clk4

0

1

2

3

4

5

30

31

0

sa_count[4:0]

Figure 18. Stay-Alive Timer operation timing

REV.PrP 2/6/02

- 26 -

PRELIMINARY TECHNICAL DATA

ADP3500

2.11 REGISTERS

ADDR

Description

Sec. Counter

Min. Counter

Hour Counter

Week Counter

Day Counter

Month Counter

Year Counter

Alarm_A Min Register

Alarm_A Hour Register

Alarm_A Week Register

Alarm_B Min Register

Alarm_B Hour Register

Alarm_B Week Register (Option)

Alarm Control

Periodic Interrupt Control

Stay-Alive Timer Control

Charger Control

Charger MVBAT Control

Charger MVBAT

LDO Control 1

Not available

LDO Control 2

D7 D6

D5

S5

M5

D4

S4

M4

H4

D3

S3

M3

H3

D2

S2

M2

H2

W2

D2

MO2

Y2

AM2

AH2

AW2

BM2

BH2

BW2

D1

S1

M1

H1

W1

D1

MO1

Y1

AM1

AH1

AW1

BM1

BH1

BW1

ALB_EN Bout

CT1

SA1

CHI

D0

S0

M0

H0

W0

D0

MO0

Y0

AM0

AH0

AW0

BM0

BH0

BW0

Comment

Note 1,5

Note 5

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

D4

D3

MO3

Y3

AM3

AH3

AW3

BM3

BH3

BW3

Y6

Y5

AM5

Y4

AM4

AH4

AW4

BM4

BH4

BW4

AW6

AW5

BM5

BW6

BW5

CLR

Note 5

ALA_EN Aout

CTFG

SA3

CT2

SA2

CT0

SA0

CHEN

MVEN

MV0

SA4

Note 4

REF0

MV1

LDO5

Note 4

Note 7

Note 4

CHV1

CHV0

MV4

MV3

MV2

LDO11

LDO4

LDO10

LDO9

LDO8

LDO7

ALLOF

F

16h

LDO Control 3

Note 4

17h

18h

19h

1Ah

LDO2 Gain

Keypad Column/B-light Register

Keypad Row

G23

KO3

KI3

G22

KO2

KI2

G21

KO1

KI1

G20

KO0

KI0

GPC0

GPMSK

0

GPI0

GPO0

GPINT0

GPRST0

Note 4

Note 6

BL

KI4

KI5

GPIO Control Register

GPC3

GPC2

GPC1

1Bh

1Ch

1Dh

GPIO MASK

GPIO Register

GPIO INT

GPMSK3 GPMSK2 GPMSK1

Note 6

Note 2,6

GPI3

GPO3

GPINT3

GPRST3

GPI2

GPO2

GPINT2

GPRST2

GPI1

GPO1

GPINT1

GPRST1

IN

T7

IR

ST

7

INT6

IRST6

INT3

IRST3

INT2

IRST2

INT1

IRST1

INT0

IRST0

1Eh

INT Register

INT5

INT4

Note 2,6

MS

K7

1Fh

20h

21h

3Fh

INT MASK

MSK6

DI6

MSK5

DI5

MSK4

DI4

MSK3

DI3

MSK2

DI2

MSK1

DI1

MSK0

Note 6

Note 3,5

DATA IN

DI0

PWROF

F

Power OFF

TEST register (option)

LDOENB USENB

TEST

Notes:

1. For the RTC counter data protection, the access should be waited for certain time (62µS) period after CS signal assertion.

(Refer to RTC counter section for the wait time).

2. The INT reset operation will be valid at 62µS or later after its setting.

3. This is a set register for internal test, and should not be accessed at normal operation.

4. Analog block control registers. They control LDO etc. They are powered by VBAT.

5. Registers regarding RTC counter. They are powered by RTCV.

6. Registers for INT, GPIO, KEYPAD I/F etc. They are powered by VBAT.

7. Not available.

REV.PrP 2/6/02

- 27 -

PRELIMINARY TECHNICAL DATA

ADP3500

Typical Performance Characteristics

(Vin = 4.2 V, TA = 25 C)

2.879

2.878

2.877

2.876

2.925

2.920

2.915

2.910

2.905

2.900

0

50

100

150

0

0.2

0.4

0.6

0.8

1

Output Current, mA

TPC1, LDO1a load regulation

TPC2, LDO1b load regulation

2.872

2.870

2.868

2.866

2.864

2.862

2.860

2.813

2.812

2.811

0

10

20

30

40

50

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

Output Current, mA

TPC3, LDO6a load regulation

TPC4, LDO6b load regulation

2.920

2.915

2.910

2.905

2.900

2.895

2.890

2.885

2.920

2.915

2.910

2.905

2.900

2.895

2.890

2.885

0

50

100

150

200

0

50

100

150

200

Output Current, mA

TPC5, LDO4 load regulation

TPC6, LDO7 load regulation

REV.PrP 2/6/02

- 28 -

PRELIMINARY TECHNICAL DATA

ADP3500

PACKAGE DIMENSION

ST-64A

64-Lead Thin Plastic Quad Flatpack [LQFP]

7 X 7mm Body, 1.4mm Thick

0.063 (1.60)

MAX

0.354 (9.00) BSC

SQ

0.030 (0.75)

0.024 (0.60)

0.018 (0.45)

49

64

1

48

SEATING

PLANE

0.276

(7.00)

BSC

SQ

TOP VIEW

(PINS DOWN)

16

33

0.003 (0.008)

MAX LEAD

COPLANARITY

32

17

0.016 (0.4) 0.009 (0.23)

BSC

0.007 (0.18)

0.005 (0.13)

0.057

(1.45)

0.055

(1.40)

0.053

(1.35)

7

8

0

8

0.006 (0.15)

0.002 (0.05)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS

REV.PrP 2/6/02

- 29 -


型号：	ADP3500AST-REEL
厂家：	ADI
描述：	IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP64, PLASTIC, LQFP-64, Power Management Circuit
文件：	总29页 (文件大小：256K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADP3500AST-REEL [ADI]

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