ADP3421JRU [ADI]
Geyserville-Enabled DC-DC Converter Controller for Mobile CPUs; 盖瑟维尔启用DC-DC转换器控制器，用于移动处理器
| 型号： | ADP3421JRU |
| 厂家： | 
ADI |
| 描述： | Geyserville-Enabled DC-DC Converter Controller for Mobile CPUs |
| 文件： | 总12页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Geyserville-Enabled DC-DC
Converter Controller for Mobile CPUs
a
ADP3421
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Meets Intel® Mobile Voltage Positioning Requirements
Lowest Processor Dissipation for Longest Battery Life
Best Transient Containment
ADP3421
DACOUT
Minimum Number of Output Capacitors
System Power Management Compliant
Fast, Smooth Output Transition During VID Code
Change
Programmable Current Limit
Power Good
VID4
VID3
CLSET
CS+
CS–
VID DAC
VID2
VID1
CURRENT
LIMIT
COMPARATOR
VID0
Integrated LDO Controllers for Clock and I/O Supplies
Programmable UVLO
VHYS
REG
EN
Soft Start with Restart Lock-In
LTO
LTB
LTI
RAMP
LEVEL
CORE
TRANSLATOR
COMPARATOR
APPLICATIONS
OUT
Geyserville-Enabled Core DC-DC Converters
Fixed Voltage Mobile CPU Core DC-DC Converters
Notebook/Laptop Power Supplies
Programmable Output Power Supplies
CORE CONTROLLER
CLKDRV
CLKFB
IODRV
CLOCK LDO
CONTROLLER
SSC
SSL
SOFT START
TIMER
AND
POWER GOOD
GENERATOR
GENERAL DESCRIPTION
I/O LDO
IOFB
BIAS AND
CORE
CONTROLLER
The ADP3421 is a hysteretic dc-dc buck converter controller
with two auxiliary linear regulator controllers. The ADP3421
provides a total power conversion control solution for a micro-
processor by delivering the core, I/O, and clock voltages. The
optimized low-voltage design is powered from the 3.3 V system
supply and draws only 10 µA maximum in shutdown. The main
output voltage is set by a 5-bit VID code. To accommodate the
transition time required by the newest processors for on-the-
fly VID changes, the ADP3421 features high-speed operation
to allow a minimized inductor size that results in the fastest change
of current to the output. To further allow for the minimum
number of output capacitors to be used, the ADP3421 features
active voltage positioning that can be optimally compensated
to ensure a superior load transient response. The main output
signal interfaces with the ADP3410 dual MOSFET driver,
which is optimized for high speed and high efficiency for driving
both the upper and lower (synchronous) MOSFETs of the
buck converter.
REFERENCE
BIAS EN
VIN/VCC
MONITOR AND
UVLO BIAS
REFERENCE
CONTROLLER
UVLO
VCC
GND
PWRGD
SD
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
(0؇C Յ TA Յ 100؇C, VCC = 3.3 V, VSD = VCC, VULVO = 2.0 V, VCORE = VDAC, ROUT = 100
k⍀, COUT = 10 pF, CSSC = 1.8 nF, CSSL = 1.3 nF, CLTB = 1.5 nF, unless otherwise noted.)
ADP3421–SPECIFICATIONS1
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SUPPLY-UVLO-POWER GOOD
Supply Current
ICC(ON)
ICC(UVLO)
VCCH
7
15
350
10
mA
µA
µA
V
VUVLO = 0.2 V
VSD = 0 V, 3.0 V ≤ VCC ≤ 3.6 V
VCC UVLO Threshold
ICCH
2.9
VCCL
2.7
V
VCC UVLO Hysteresis
Battery UVLO Threshold
Battery UVLO Hysteresis
VCCHYS
VUVLOTH
IUVLO
20
1.175
–0.3
0.6
mV
V
µA
µA
V
V
V
V
V
1.225
1.0
1.275
+0.3
1.4
0.7 × VCC
1.12 × VDAC
1.10 × VDAC
0.92 × VDAC
0.90 × VDAC
VCC
VUVLO = 1.275 V
V
UVLO = 1.175 V
Shutdown Input Threshold
Core Power Good Threshold
VSDTH
VCOREH(UP)
VCOREH(DN)
VCOREL(UP)
3.0 V < VCC < 5.0 V
0.925 V < VDAC < 2.000 V
0.8
1
1.10 × VDAC
1.08 × VDAC
0.90 × VDAC
0.88 × VDAC
0.95 × VCC
0
2
1
2
VCOREL(DN)
3
PWRGD Output Voltage
VPWRGD
VCORE = VDAC
VCORE = 0.8 VDAC
VUVLO = 0.2 V
V
V
V
0.8
0.4
0
CORE CONVERTER SOFT-START TIMER
Timing Charge Current
Discharge Current
Enable Threshold
ISSC(UP)
VSSC = 0 V
VSSC = 1.7 V, VUVLO = 1.1 V
–0.6
0.3
–1.0
1.0
150
1.70
–1.4
µA
mA
mV
V
ISSC(DN)
4
VSSCEN
400
1.87
Termination Threshold
VSSCTH
1.53
VID DAC
VID Input Threshold
VID Input Pull-Up Current
Nominal Output Voltage
Output Voltage Accuracy
Output Voltage Settling Time
VVID0..4
IVID0..4
VDAC
0.8
10
0.925
–0.85
0.7 × VCC
40
2.000
0.85
V
µA
V
%
µs
See VID Code Table I
∆VDAC/VDAC
5
tDACS
35
CORE COMPARATOR
Input Offset Voltage
Input Bias Current
Hysteresis Current
VCOREOS
IREG
IRAMP
VREG = 1.3 V
–3
–2
+3
+2
mV
µA
VREG = VRAMP = 1.3 V
VCORE = VRAMP = 1.3 V
VCS– = 1.30 V, VCS+ = 1.28 V
V
V
REG = 1.28 V
VHYS Open
RVHYS = 170 kΩ
RVHYS = 17 kΩ
REG = 1.32 V
R
–2
–7
–82
+2
–13
–113
µA
µA
µA
–10
–97
RVHYS Open
–2
7
82
1.53
2.5
0
+2
13
113
1.87
3.0
0.4
20
µA
µA
µA
V
V
V
ns
ns
ns
RVHYS = 170 kΩ
10
97
1.70
RVHYS = 17 kΩ
Hysteresis Setting Reference Voltage VVHYS
Output Voltage
VOUTH
VOUTL
tCOREPD
VCC = 3.0 V
VCC = 3.6 V
TA = 25°C
Propagation Delay Time6
Rise and Fall Time6
7
0°C ≤ TA ≤ 100°C
30
10
8
tCORER
,
7
8
tCOREF
–2–
REV. A
ADP3421
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
CURRENT LIMIT COMPARATOR
Input Offset Voltage
Input Bias Current
VCLOS
ICL+
ICL–
VCS– = 1.3 V
VCS+ = 1.3 V
VCORE = VRAMP = 1.3 V
–6
–5
+6
+5
mV
µA
Hysteresis Current
VREG = 1.28 V, VCS– = 1.3 V
V
V
CS+ = 1.28 V
IHYS Open
RIHYS = 170 kΩ
R
–5
–38
–335
µA
µA
µA
–22
–265
–30
–300
RIHYS = 17 kΩ
CS+ = 1.32 V
RIHYS Open
–5
µA
µA
µA
V
ns
ns
R
R
IHYS = 170 kΩ
IHYS = 17 kΩ
–13
–175
1.53
–20
–200
1.70
30
–27
–225
1.87
60
Hysteresis Setting Reference Voltage VVHYS
7
Propagation Delay Time6
tCLPD
TA = 25°C
0°C ≤ TA ≤ 100°C
50
100
LINEAR REGULATOR SOFT-START TIMER
Charge Current
ISSC(UP)
VSSC = 0 V
VSSC = 1.7 V, VUVLO = 1.1 V
–0.6
0.3
–1.0
1.0
150
1.70
–1.4
µA
mA
mV
V
Discharge Current
Enable Threshold
Termination Threshold
ISSC(DN)
4
VSSCEN
400
1.87
VSSCTH
1.53
2.5 V CLK LDO CONTROLLER
Feedback Bias Current
Output Drive Current
ICLKFB
ICLKDRV
VCLKFB = 2.5 V
VCLKDRV = 2.55 V
12.5
25
1
20
µA
µA
V
CLKDRV = 2.45 V
3
mA
mA/V
DC Transconductance
GCLK
∆ICLKDRV = 1 mA
500
7.5
1.5 V I/O LDO CONTROLLER
Feedback Bias Current
Output Drive Current
IIOFB
IIODRV
VIOFB = 1.5 V
VIODRV = 1.53 V
15
1
60
µA
µA
mA
mA/V
V
IODRV = 1.47 V
10
DC Transconductance
GIO
∆ICLKDRV = 1 mA
650
LEVEL TRANSLATOR
Input Clamping Threshold
Output Voltage
VLTIH
VLTOH
VLTOL
tLTPD
ILTI = –10 µA
ILTI = –10 µA9
VLTI = 0.175 V9
0.95
0.9 × VCCLT
1.5
VCCLT
375
V
V
mV
ns
Propagation Delay Time6
10
NOTES
1VCORE ramps up monotonically.
2VCORE ramps down monotonically.
3During latency time of VID code change, the Power Good output signal should not be considered valid.
4Internal bias and soft start are not enabled unless the soft-start pin voltage first drops below the enable threshold.
5Measured from 50% of VID code transient amplitude to the point where VDAC settles within 1% of its steady state value.
6Guaranteed by characterization.
740 mV p-p amplitude impulse with 20 mV overdrive. Measure from the input threshold intercept point to 50% of the output voltage swing.
8Measured between the 30% and 70% points of the output voltage swing.
9The LTO output tied to VCCLT = 2.5 V rail through an RLTO = 150 Ω pull-up resistor.
Specifications subject to change without notice.
REV. A
–3–
ADP3421
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
Input Supply Voltage (VCC) . . . . . . . . . . . . . . –0.3 V to +7 V
UVLO Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
All Other Inputs/Outputs . . . . . . . . . . . . . . . . . . VCC + 0.3 V
Operating Ambient Temperature Range . . . . . . 0°C to 100°C
Junction Temperature Range . . . . . . . . . . . . . . . 0°C to 150°C
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98°C/W
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
VHYS
1
2
28
27
26
25
24
23
22
CS–
CLSET
LTO
CS+
3
REG
RAMP
VCC
OUT
GND
4
LTI
5
LTB
6
VID4
ADP3421
7
VID3
TOP VIEW
(Not to Scale)
8
VID2
21 DACOUT
VID1
9
20
19
18
17
CORE
SSC
10
11
12
13
14
VID0
CLKDRV
CLKFB
IODRV
IOFB
SSL
UVLO
ORDERING GUIDE
16 PWRGD
15
SD
Temperature
Range
Package
Description
Package
Option
Model
ADP3421JRU 0°C to 100°C
Thin Shrink Small RU-28
Outline (TSSOP)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3421 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
Function
1
VHYS
Core Comparator Hysteresis Setting. The voltage at this pin is held at a 1.7 V reference level. A resistor to
ground programs at a 1:1 ratio the current that is alternately switched into and out of the RAMP pin.
2
CLSET
Current Limit Setting. The voltage at this pin is held at a 1.7 V reference level. A resistor to ground programs
a current that is gained up by 3:1 flowing out of the CS– pin, assuming the current limit comparator is not
triggered.
3
4
LTO
LTI
Level Translator Output. This pin must be tied through a pull-up resistor to the voltage level desired for the
output high level. That voltage cannot be less than 1.5 V.
Level Translator Input. This pin should be driven from an open drain/collector signal. The pull-up current is
provided by the pull-up resistor on the LTO pin. However, the pull-up current will be terminated when the
LTI pin reaches 1.5 V.
5
LTB
Level Translator Bypass. For operation of the level translator with high-speed signals, this pin should be by-
passed to ground with a large value capacitor.
6
7
VID4
VID3
VID Input. Most significant bit.
VID Input
8
VID2
VID Input
9
VID1
VID Input
10
11
VID0
CLKDRV
VID Input. Least significant bit.
2.5 V Linear Regulator Driver Output. This pin sinks current from the base of a PNP transistor as needed to
keep the CLKFB node regulated at 2.5 V.
12
13
14
CLKFB
IODRV
IOFB
2.5 V Linear Regulator Output Feedback. This pin is connected to the collector of a PNP transistor whose
base is driven by the CLKDRV pin.
1.5 V Linear Regulator Driver Output. This pin sinks current from the base of a PNP transistor as needed to
keep the IOFB node regulated at 1.5 V.
1.5 V Linear Regulator Output Feedback. This pin is connected to the collector of a PNP transistor whose
base is driven by the IODRV pin.
–4–
REV. A
ADP3421
Pin
Mnemonic
Function
15
16
SD
Shutdown Input. When this pin is pulled low, the IC shuts down and all regulation functions will be disabled.
PWRGD
Power Good Output. This signal will go high only when the SD pin is high to allow IC operation, the UVLO
and VCC pins are above their respective start-up thresholds, the SSC and SSL pins are above a voltage where
soft start is completed, and the voltage at the CORE pin is within the specified limits of the programmed VID
voltage. By choosing the soft-start capacitor for the core larger than that for the linear regulators, at start-up
the core and linear outputs should all be in regulation before PWRGD is asserted.
17
UVLO
Undervoltage Lockout Input. This pin monitors the input voltage through a resistor divider. When the pin
voltage is below a specified threshold, the IC enters into UVLO mode regardless of the status of SD. When
in UVLO mode, a current source is switched on at this pin, which sinks current from the external resistor
divider. The generated UVLO hysteresis is equal to the current sink value times the upper divider resistor.
18
19
SSL
SSC
Linear Regulator Soft Start. During power-up, an external soft-start capacitor is charged by a current source
to control the ramp-up rates of the linear regulators.
Core Voltage Soft Start. During power-up, an external soft-start capacitor is charged by a current source to
control the ramp-up rate of the core voltage.
20
21
CORE
Core Converter Voltage Monitor. This pin is used to monitor the core voltage for power good verification.
DACOUT
VID-Programmed Digital-to-Analog Converter Output. This voltage is the reference voltage for output
voltage regulation.
22
23
GND
OUT
Ground
Logic-Level Drive Signal Output of Core Controller. This pin provides the drive command signal to the IN
pin of the ADP3410 driver. This pin is not capable of directly driving a power MOSFET.
24
25
VCC
RAMP
Power Supply
Current Ramp Input. This pin provides the negative feedback for the core output voltage. The switched sink/
source current from this pin, which is set up at the VHYS pin, works against the terminating resistance at this
pin to set the hysteresis for the hysteretic control.
26
REG
Regulation Voltage Summing Input. In the recommended configuration, the DACOUT voltage and the core
voltage are summed at this pin to establish regulation with output voltage positioning.
27
28
CS+
CS–
Current Limit Positive Sense. This pin senses the positive node of the current sense resistor.
Current Limit Negative Sense. This pin connects through a resistor to the negative node of the current sense
resistor. A current flows out of the pin, as programmed at the CLSET pin. When this pin is more negative
than the CS+ pin, the current limit comparator is triggered and the current flowing out of the pin is reduced
to two-thirds of its previous value, producing a current limit hysteresis.
REV. A
–5–
ADP3421–Typical Performance Characteristics
100m
1000
100
HIGH
NORMAL OPERATING MODE
10m
CORE FULL-SCALE
1m
UVLO MODE
10
1
100
CORE ZERO-SCALE
AND LDOS
SHUTDOWN MODE
10
1
LOW
0.1
0.1
0
20
40
60
80
100
–0.15 –0.1 –0.05
RELATIVE CORE VOLTAGE – ⌬V
0
0.05
0.1
/ V
0.15
1
10
100
TEMPERATURE – ؇C
CORE
CORE
TIMING CAPACITANCE – nF
TPC 1. Supply Current vs.
Temperature
TPC 2. Power Good vs. Relative
CoreVoltageVariation
TPC 3. Soft-Start Time vs. Timing
Capacitance
100
0
–100
–200
OUT = LOW, R
= 170k⍀
2.010
CLSET
+0.85%
OUT = HIGH, RHYS = 17k⍀
OUT = HIGH, R
= 170k⍀
CLSET
FULL-SCALE
2.000
–0.85%
OUT = HIGH, RHYS = 170k⍀
1.990
0.9375
0
OUT = LOW, RHYS = 170k⍀
+0.85%
OUT = LOW, R
= 17k⍀
CLSET
0.925
ZERO-SCALE
OUT = LOW, RHYS = 17k⍀
–100
OUT = HIGH, R
= 17k⍀
–0.85%
CLSET
0.9125
–300
0
0
0
20
40
60
80
100
20
40
60
80
100
20
40
60
80
100
AMBIENT TEMPERATURE – ؇C
AMBIENT TEMPERATURE – ؇C
AMBIENT TEMPERATURE – ؇C
TPC 4. DAC Output Voltage vs.
Temperature
TPC 5. Core Hysteresis Current vs.
Temperature
TPC 6. Current Limit Threshold
Current vs. Temperature
40
2.60
2.55
1.55
30

= 100
1.52
EXT
IO LDO
V
= 1.47V

= 100
IOFB
EXT
20
10
0
1.50
1.48
1.45
2.50
2.45
2.40
CLK LDO
60
V
= 2.45V
CLKFB
0
20
40
80
100
100
1m
0.01
0.1
1
10
100
1m
0.01
0.1
1
AMBIENT TEMPERATURE – ؇C
LOAD CURRENT – A
LOAD CURRENT – A
TPC 7. LDO Drive Current vs.
Temperature
TPC 8. IO LDO DC Load Regulation
TPC 9. CLK LDO DC Load
Regulation
–6–
REV. A
ADP3421
THEORY OF OPERATION
Supply Voltages
applied to the DAC input. The VID code corresponds to that
recommended in guidelines for the mobile Pentium® III published
by Intel (see Table I).
The ADP3421 is optimized for use with, and specified at a
3.3 V supply, but can operate at up to 6 V at the expense of
increased quiescent current and minor tolerance degradation.
The ADP3410 MOSFET driver can accommodate up to 30 V
for driving the upper power MOSFET to 5 V above a 25 V rail.
Table I. VID Code
VID4
VID3
VID2
VID1
VID0
VOUT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2.000
1.950
1.900
1.850
1.800
1.750
1.700
1.650
1.600
1.550
1.500
1.450
1.400
1.350
1.300
Off*
1.275
1.250
1.225
1.200
1.175
1.150
1.125
1.100
1.075
1.050
1.025
1.00
Undervoltage Lockout
The undervoltage lockout (UVLO) circuit comprises the low
V
IN and low VCC detection comparators. UVLO for VIN pro-
vides a system UVLO that monitors the battery voltage and
allows the converter operation to be disabled if the battery falls
below a preset threshold. A resistor divider to the UVLO pin
sets the UVLO-off level for the system comparing to a specified
reference. When VIN goes low enough to activate UVLO, this
triggers a specified current sink into the pin to be switched on.
This raises the UVLO-on threshold above the UVLO-off
threshold by the current sink values times the upper resistor of
the divider. So the resistor divider ratio at the UVLO pin is
used to set the UVLO threshold and the hysteresis.
Hysteresis for the system UVLO is recommended to prevent
oscillation due to nonzero battery impedance. If UVLO is trig-
gered during a condition where the battery is loaded by the
converter operation, the converter will turn off and the battery
voltage will then rise to a slightly higher level. A good design
will ensure that the hysteresis is sufficient to prevent the converter
from turning on again.
UVLO for VCC provides an internally specified UVLO thresh-
old for the ADP3421 to ensure that it only operates when the
applied VCC is sufficient to ensure that it can operate properly.
Activation of either UVLO circuit disables the reference and
bias circuits in the IC except for that which is needed for UVLO
detection.
Power Good
0.975
0.950
0.925
Off*
If the IC is enabled and is not in the UVLO mode and has fin-
ished its soft-start period, and if the core voltage is within 10%
of the VID programmed value, then a high-level signal appears
at the PWRGD pin.
*No CPU shutdown
Power Good During VID Change
Core Comparator
When a VID change occurs, the DAC output responds faster than
the output voltage, which is slew rate limited by the output
filter. In this case, PWRGD may momentarily go low. To avoid
system interruption, the PC power management system should
not respond to this glitch. The PWRGD signal corresponds to
V_GATE as specified in Intel’s Geyserville Voltage Regulator
specification. The glitch can be masked from the system by
using the appropriate system programming settings or by using
a functionally equivalent OR gate, which provides a blanking
signal for the specified latency period where the core voltage is
allowed to settle at its new value. Because of the minimal output
capacitor requirement, the response time of the core voltage is
well within the specified latency period and, when the power
converter is properly compensated, it does not exhibit any
overshoot.
The core comparator is an ultrafast hysteretic comparator with
a typical propagation delay to the OUT pin of 15 ns at a 20 mV
overdrive.
This comparator is used with a switched hysteresis current for
controlling the main feedback loop, as described in the Main
Feedback Loop Operation section. This comparator has no
relation to the CORE pin, which is used only for core voltage
monitoring for the PWRGD function.
Current Limit Comparator
The current limit comparator monitors the voltage across the
current-sense resistor RCS and it overrides the core comparator
and forces the OUT pin to low when the current exceeds the
peak current limit threshold. The current control is hysteretic,
with a valley current threshold equal to two-thirds of the peak
current limit threshold. When the sensed current signal falls to
two-thirds of the peak threshold, the OUT pin is allowed to go
high again, and the control of the main loop reverts back to the
core comparator.
VID-Programmed DAC Reference
This 5-bit digital-to-analog converter (DAC) serves as the
programmable reference source of the dc-dc converter. Pro-
gramming is accomplished by CMOS logic-level VID code
Pentium is a registered trademark of Intel Corp.
REV. A
–7–
ADP3421
A resistor (RCLS) connected between the CLSET and ground
sets a current that is internally multiplied by a factor of three
and flows out of the CS– pin. The resistor RCL connected in
series with the CS– pin to the negative current sense point (i.e.,
the output voltage) sets the voltage that must be developed
across RCS to trip the current limit comparator. Once it is tripped,
the CS– current is scaled down by two-thirds, so the inductor
current must ramp down accordingly to reset the comparator.
time of the linear regulator output voltages. For maximum
flexibility in controlling the start-up sequence, the soft-start
function of the linear regulators was separated from that of the
core converter.
Level Translator
The level translator converts any digital input signal to a user-
programmable voltage level. This can be used to translate an
IO-level signal (i.e., 1.5 V) into a CLK-level or VCC-level or
even 5 V-level signal. For example, the 1.5 V FERR# signal can
be converted to a 3.3 V level for the PII-X4 chipset. The output
signal is in phase with the input, and it is not necessary to have
a pull-up on the input signal. The ADP3421 provides pull-up
for the input signal to 1.5 V. The only practical restriction on
the input signal is that it must not prevent pull-up to 1.5 V. An
external pull-up resistor sets the output signal level. Throughput
time for the signal using a 150 Ω pull-up resistor is 5 ns (typ).
Core Converter Soft-Start Timer
The soft-start function limits the ramp-up time of the core volt-
age in order to reduce the initial in-rush current on the core
input voltage (battery) rail. The soft-start circuit consists of an
internal current source, an external soft-start timing capacitor,
an internal switch across the capacitor, and a comparator
monitoring the capacitor voltage.
The soft-start capacitor is held discharged when either the SD
signal is low or the device is in UVLO mode. As soon as SD is set
to high, and VCC and VIN rise above their respective UVLO
thresholds, the short across the external timing capacitor is removed,
and the internal soft-start current source begins to charge the
timing capacitor. During the charge of the soft-start capacitor, the
Power Good signal is set to low. When the timing capacitor voltage
reaches an internally set soft-start termination threshold, the core
monitor window comparator output is enabled, allowing the
Power Good status to be determined. If the core voltage has
already settled within the specified limits the Power Good signal
goes high, otherwise it stays low. The soft-start capacitor remains
charged until either SD goes low, or VCC or VIN drop below their
respective UVLO thresholds. When this occurs, an internal
switch quickly discharges the soft-start timing capacitor to prepare
the IC for a new start-up sequence.
APPLICATION INFORMATION
Overview—Combined ADP3421 and ADP3410 Power Con-
troller for PC Systems
The ADP3421 is a power controller that can provide a regula-
tion solution for all three power rails of an Intel Pentium II or
III processor. Together with the ADP3410 driver IC, these ICs
form an integral part of a PC system, featuring a high-speed
(<10 ns) level translator, interface with GCL and PII-X4
or other power management signals, and a power sequenced
switched 5 V rail. For high-slew-rate microprocessors, this
minimizes the total solution cost by allowing the quantity of
output capacitors to be minimized to the limit of what the buck
converter topology and the capacitor technology can allow.
Recommended Configuration
The ADP3421 controls the regulation of the core voltage with-
out amplifiers in a unique ripple regulator control topology. In
a proprietary optimized compensation configuration offered
by Analog Devices, Inc., the inductor ripple current is kept at a
fixed programmable value while the output voltage is regulated
with fully programmable voltage positioning parameters, which
can be tuned to optimize the design for any particular CPU
regulation specifications. By fixing the ripple current, the fre-
quency variations associated with changes in output capacitance
and ESR for standard ripple regulators will not appear.
Soft-Start Restart Lock In
In the event that a UVLO event was not long enough to allow
the soft-start capacitors to discharge (e.g., a momentary power
glitch), the UVLO event is captured by a latch. The forced dis-
charge of the soft-start capacitors will continue until a lower
threshold is reached, at which time the converter will restart
with a fully controlled soft start.
1.5 V I/O Voltage Regulator
Two pins control an external PNP, for example, transistor as
a linear regulator for a 1.5 V output. The IODRV pin directly
drives the base of the PNP with ≥10 mA to support an output
current as high as the PNP’s current gain and power dissipation
capability will allow. For example, with a high gain PNP transistor
such as the Zetex ZFT788B (SOT-223), the I/O linear regulator
is capable of delivering peak currents of greater than 2.5 A. The
1.5 V output is connected to the IOFB pin to provide feedback.
Accurate current sensing is needed to accomplish accurate out-
put voltage positioning, which, in turn, is required to allow the
minimum number of output capacitors to be used to contain
transients. A current-sense resistor is used between the inductor
and the output capacitors. To allow the control to operate with-
out amplifiers, the negative feedback signal is taken from the
inductor, or upstream, side of the current-sense resistor, and the
positive feedback signal is taken from the downstream side.
2.5 V CLK LDO Voltage Regulator
Two pins control an external PNP transistor as a linear regulator
for a 2.5 V output. The CLKDRV pin, for example, directly
drives the base of the PNP with ≥3 mA to support an output
current as high as the PNP’s current gain and power dissipation
capability will allow. For example, with a high gain PNP transis-
tor such as the Zetex ZFT788B (SOT-223), the CLK linear
regulator is capable of delivering peak currents of greater than
1.2 A. The 2.5 V output is connected to the CLKFB pin to
provide feedback.
Active voltage positioning, whose advantages are described later,
has two parameters that are separately controlled. The negative
feedback signal uses a resistor divider to ground into the RAMP
pin to create the precise offset voltage needed for voltage position-
ing. The positive feedback signal and the DAC’s VID-controlled
reference are summed into the REG pin through resistors to set
the desired voltage positioning gain. The proprietary optimal com-
pensation is a final parameter that must be tuned to ensure that
the voltage positioning is not bandwidth limited. This is accom-
plished by using the appropriately-sized capacitor in parallel
with the resistor that sums the positive feedback signal. The
Linear Regulator Soft-Start Timer
The soft-start timer circuit of the linear regulators is similar to
that of the core converter, and is used to control the ramp-up
–8–
REV. A
ADP3421
optimal compensation also gives the ripple current control that
adds stability to the switching frequency.
voltage positioning—a tolerance analysis can show the weakness
of this design technique.
Standard Hysteretic Control Configuration
Although additional power is dissipated by the current-sense
resistor, the total power consumption is reduced because of the
squared reduction of current consumption by the CPU. For
example, if the CPU draws 15 A at 1.6 V, the current-sensing
resistor is 3 mΩ, and the supply voltage is reduced by 7%, the
core dissipation can be reduced from 24 W to:
The ADP3421 can also be used as a conventional hysteretic
ripple regulator where the output ripple voltage is directly pro-
grammed. To achieve this conventional operation, the DAC’s
output is connected directly to the REG pin and the output
voltage connects through a resistor to the RAMP pin. This resistor
sets the output ripple voltage, which will be symmetrically centered
around the DAC voltage. If the optimal DAC voltage is not
available, an offset could be summed into the RAMP pin with
another resistor, as was done with the previous configuration.
24 W × 0.932 = 20.76 W,
and the power dissipated in the resistor is only:
[20.76 W/(1.6 V × 0.93)]2 × 3 mΩ = 0.58 W.
Intel Mobile Voltage Positioning Implementation
In the recommended configuration, the ADP3421 uses voltage
Intel Mobile Voltage positioning technology as an inherent part
of its architecture.
The total power savings from the battery is 2.65 W, or 11.1%.
Optimally Compensated for Voltage Positioning
Although voltage positioning helps to control the initial load tran-
sient, high-frequency load repetition rates can cause the voltage to
exceed by double the limits within which the transients can be
contained. For complete transient containment over the bandwidth
of the core’s transient activity, the solution is an enhanced optimally
compensated version of voltage positioning.
No matter how fast the response of the switches, even instanta-
neous, the inductor limits the response speed at the output of
the converter. This places the primary burden of transient
response containment on the output capacitors. The size and
cost of the output capacitors can be minimized by keeping the
output voltage higher at light load in anticipation of a load
increase, and lowering the output voltage at heavier loads in
anticipation of a load decrease. Voltage positioning with the
ADP3421 is active, which means the voltage positioning can be
controlled by loop gain. This increases efficiency compared to
passive voltage positioning that is sometimes used as a supple-
mentary regulation technique with voltage-mode controllers.
Instead of sizing a series resistor to create the entire voltage drop
(often called a “droop” resistor in the passive voltage positioning
implementation), a smaller value current-sensing resistor can be
used and the loop can amplify its voltage drop to position the
voltage as desired without additional power loss.
It prevents the tendency of the core voltage to “bounce” before
settling to its final positioned value after the inductor current
has been ramped to its final value.
Main Feedback Loop Operation
In conjunction with a selected control topology, the ADP3421
regulates a drive control signal at the OUT pin using a comparator.
The two inputs are pins RAMP (–) and REG (+). A bidirectional
switched control current is used at the RAMP input to establish
hysteresis with a chosen termination resistance. Beginning in the
drive high state (OUT pin high), the control current is sinking
current into the RAMP pin, but the output current in the buck
converter is increasing and so VRAMP will eventually exceed VREG
.
When this happens, the control current reverses and sources
current out of the RAMP pin to provide both hysteresis and
overdrive for the comparator. The OUT pin goes low and the
buck converter output current decreases until VRAMP < VREG
at which time the comparator switches, the control current
reverses, and the process repeats.
Voltage Positioning for Power Savings
In addition to the size and cost reduction of the output capacitors,
another advantage of using voltage positioning is a reduction
in the CPU core dissipation. That dissipation is equal to the
product of the applied core voltage and the current drawn by
the CPU. The CPU current is primarily due to the capacitive
switching load of digital circuitry, and it is also proportional to
the applied voltage. The result is that the CPU power dissipation is
approximately proportional to the applied voltage squared.
2
,
How the hysteresis current is used (depending on the control
configuration) will determine which parameter is hysteretically
controlled—presumably either the inductor ripple current or
the output ripple voltage, as in the two suggested configu-
rations, or a weighted combination of the two or another
variable could be introduced.
P
CPU = k × VCPU
This characteristic, combined with the wide tolerance on the
core voltage specification, suggests that the maximum CPU
power dissipation can be substantially reduced by setting the
core voltage near the lower specified voltage limit. For example,
if a 1.6 V processor is operated 7% below its nominal voltage
rating, the CPU power dissipation is reduced by 13.5%. Losses
in the switches and inductor of the power converter are also
reduced due to the decrease in maximum load current.
Core Converter Design Procedure
There are two primary objectives considered in optimizing the
design of a power converter. The first objective is to meet the
specifications; the second objective is to do so at the lowest cost.
Analog Devices, Inc., addresses both of these objectives with the
ADP3421 and its recommended design procedure. The optimized
design yields the additional benefit of reducing the maximum
CPU power consumption by ~10% for typical CPU specifica-
tions, which has created great interest in those using the CPU.
To realize the full cost-reducing benefits of active voltage posi-
tioning, a current-sensing resistor should be used to convey
accurate current information to the control loop. This is needed
to accurately position the core voltage as a function of load cur-
rent. Accurate positioning of the core voltage allows the highest
reduction in output capacitors. It is common to see passive voltage
positioning implemented by sensing voltage drop on a copper trace
or across a power MOSFET. This causes poor control of the
Microprocessors have the distinguishing characteristic of
creating extremely fast load transients from nearly zero to the
maximum load and vice versa. The advent of increasing power
management (used to interrupt the CPU processing) causes
REV. A
–9–
ADP3421
these transients to occur with increasing frequency. Since it takes a
far longer time (typically on the order of several microseconds)
to ramp the inductor current up or down to the correct average
value after a load transient has occurred, the output capacitors
must supply or absorb the extra charge during that period of
time. This causes the output voltage to dip down or peak up.
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
The ADP3421 is a high-speed controller capable of providing
a response time well under 100 ns. To avoid having the ADP3421
respond to noise, the first step in achieving good noise immunity is
to follow the layout considerations.
To contain the output voltage within the specified limits during
load transients, with the minimum quantity of output capacitors,
the output voltage must be positioned as a function of load, and
it must be done so accurately. Therefore, current-sensing with a
discrete resistor (rather than trace resistance) is strongly recom-
mended, because it allows the number of capacitors to be reduced
toward the theoretical minimum— which is nearly half as many
as required for a standard fixed-regulation technique. This is
the key to minimizing the cost (and size) of the power converter.
In some layouts it may be necessary to supplement the ADP3421
control design with additional components designed to minimize
noise problems. For this purpose, some additional hysteresis can
be added around the core and current limit comparators. This
takes the form of adding a small capacitor (~1 pF) from OUT to
REG (for the main loop) and OUT to CS– (for current limit loop),
and providing some resistance for the capacitive hysteresis feed-
back to work against. For the current limit loop, this register is
already in the basic circuit. For the main loop, this resistor must
be added between the REG pin and the standard feedback com-
ponents. This provides a quick dynamic hysteresis with a small
time constant that is chosen only long enough to ensure that the
switching noise ringing through the circuit has decayed by the
time the dynamic hysteresis is substantially lost.
The voltage should be positioned (i.e., regulated) high at no
load and low at maximum load. This means that the power
supply will appear to have an initial offset and reduced load
regulation, because the output voltage will regulate higher than
nominal at no load and below nominal at maximum load. This
regulation technique positions the voltage in anticipation of a
load transient. At no load, the voltage is high, so when the load
transient strikes, the downward dip can be more easily contained
within the limits. Similarly at maximum load, the voltage is low,
so when the load transient strikes, the upward peak can be more
easily contained.
The following guidelines are recommended for optimal perfor-
mance of the ADP3421 and ADP3410 in a power converter.
The circuitry is considered in four parts: the power switching
circuitry, the output filter, the control circuitry, and the LDOs.
Placement Overview
1. For ideal component placement, the output filter capacitors
will divide the power switching circuitry from the control
section. As an approximate guideline, considered on a single-
sided PCB, the best layout would have components aligned
in the following order: ADP3410, MOSFETs and input
capacitor, output inductor, current-sense resistor, output
capacitors, control components, and ADP3421. Note that
the ADP3421 and ADP3410 are completely separated for
an ideal layout, which is only possible with a two-chip solu-
tion. This will minimize jitter in the control caused by having
the driver and MOSFETs close to the control and give
more freedom in the layout of the power switching circuitry.
Multiple MLC capacitors will always be needed on the output across
the CPU power pins to handle the high-frequency component of
the transient with minimized series inductance to and through the
bulk capacitors of the power converter’s output filter. Although there
are numerous trade-offs between size and cost of various com-
binations of capacitor types for meeting a given specification,
the accurate voltage positioning provided by the ADP3421 will
allow the overall combination of capacitors to be minimized.
A key requirement for optimizing the dynamic performance
of a power converter with accurate voltage positioning is to
apply “optimal compensation”—that is, the compensation that
creates a loop response that causes the output voltage to settle
immediately after a load transient, resulting in a “flat” transient
response. The ADP3421’s unique architecture is designed to
accommodate this ADI proprietary optimal compensation
technique in core dc-dc converters for Mobile CPUs. It is imple-
mented by creating the proper frequency response characteristic
at the summing junction of the output voltage and the DAC
voltage, which occurs at the REG pin.
2. Whenever a power dissipating component (e.g., a power
MOSFET) is soldered to a PCB, the liberal use of vias, both
directly on the mounting pad and immediately surrounding
it, is recommended. Two important reasons for this are:
improved current rating through the vias (if it is a current
path) and improved thermal performance—especially if the
vias extend to the opposite side of the PCB where a plane
can more readily transfer heat to air.
The complete design procedure is supplied in a separate appli-
cation note from Analog Devices, Inc., entitled: DC-DC Power
Converter Design using the ADP3421 Controller.
–10–
REV. A
ADP3421
Power Switching Circuitry
Control Circuitry
ADP3410, MOSFETs, Input Capacitors
ADP3421, Control Components
3. Locate the ADP3410 near the MOSFETs so the parasitic
inductance in the gate drive traces and the trace to the SW
pin is small, and so that the ground pins of the ADP3410
are closely connected to the lower MOSFET’s source.
12. If the placement overview cannot be followed, the ground
pin of the ADP3421 should be Kelvin-connected into the
ground plane near the output capacitors to avoid introduc-
ing ground noise from the power switching stage into the
control circuitry. All other control components should be
grounded on that same signal ground.
4. Locate at least one substantial (i.e., > ~1 µF) input bypass
MLC capacitor close to the MOSFETs so that the physical
area of the loop enclosed in the electrical path through the
bypass capacitor and around through the top and bottom
MOSFETs (drain-source) is small. This is the switching
power path loop.
13. If critical signal lines (i.e., signals from the current-sense
resistor leading back to the ADP3421) must cross through
power circuitry, it is best if a signal ground plane can be
interposed between those signal lines and the traces of the
power circuitry. This serves as a shield to minimize noise
injection into the signals at the expense of making signal
ground a bit noisier.
5. Make provisions for thermal management of all the MOSFETs.
Heavy copper and wide traces to ground and power planes will
help to pull out the heat. Heat sinking by a metal tap soldered
in the power plane near the MOSFETs will help. Even just
small airflow can help tremendously. Paralleled MOSFETs will
help spread the heat, even if the on resistance is higher.
14. Absolutely avoid crossing any signal lines over the switching
power path loop, as previously described.
15. Accurate voltage positioning depends on accurate current
sensing, so the control signals that differentially monitor
the voltage across the current-sense resistor should be
Kelvin-connected.
6. An external “antiparallel” Schottky diode (across the bottom
MOSFET) may help efficiency a small amount (< ~1 %); a
MOSFET with a built-in antiparallel Schottky is more
effective. For an external Schottky, it should be placed next
to the bottom MOSFET or it may not be effective at all.
Also, a higher current rating (bigger device with lower voltage
drop) is more effective.
16. The RC filter used for the current-sense signal should be
located near the control components.
LDOs
PNP Transistors
7. Both ground pins of the ADP3410 should be connected into
the same ground plane with the power switching circuitry,
and the VCC bypass capacitor should be close to the VCC
pin and connected into the same ground plane.
17. The maximum steady-state power dissipation expected
for the design should be calculated so that an acceptable
package type PNP for each output is selected and properly
mounted to be able to dissipate the power with acceptable
temperature rise.
Output Filter
Output Inductor and Capacitors, Current-Sense Resistor
8. Locate the current-sense resistor very near to the output
capacitors.
18. Each PNP transistor should be located close to the load that
it sources.
19. The supply voltage to the PNP emitters should be low
impedance to avoid loop instability. It is good design practice
to have at least one MLC capacitor near each of the PNP
emitters to help ensure the impedance is sufficiently low.
9. PCB trace resistances from the current-sense resistor to the
output capacitors, and from the output capacitors to the
load, should be minimized, known (calculated or measured),
and compensated for as part of the design if it is significant.
(Remote sensing is not sufficient for relieving this require-
ment.) A square section of 1 ounce copper trace has a
resistance of ~500 mΩ. Using 2~3 squares of copper can
make a noticeable impact on a 15 A design.
10. Whenever high currents must be routed between PCB layers,
vias should be used liberally to create several parallel current
paths so that the resistance and inductance introduced by
these current paths is minimized and the via current rating
is not exceeded.
11. The ground connection of the output capacitors should be
close to the ground connection of the lower MOSFET and
it should be a ground plane. Current may pulsate in this
path if the power source ground is closer to the output
capacitors than the power switching circuitry, so a close
connection will minimize the voltage drop.
REV. A
–11–
ADP3421
TYPICAL APPLICATION–GEYSERVILLE-ENABLED MOBILE VRM CONVERTER
5V
VIN
3.3V
R22
U1
100k⍀
R15
332
R16
R1
C16
10
C10
10
C15
10
⍀
ADP3421
3.3k⍀
51.1k⍀
F
F
F
U2
28
27
26
25
24
23
22
21
20
19
18
17
16
D2
1
2
VHYS
CS–
R10
10k⍀
22nF
10BQ040
1pF
C25
C31
R2
ADP3410
R19
k⍀
CLSET
LTO
LTI
CS+
2
R21,10k⍀
160k⍀
C32
15nF
1
2
3
4
5
6
7
14
13
12
11
10
9
OVPSET
BST
C17
100nF
R20
10
3
REG
⍀
M1
IRF7811
C2
100nF
DRVH
SW
SD
4
RAMP
VCC
VCC
CPU
CORE
L1
1H
R17
75k⍀
C41
1pF
C1
100nF
RCS
GND
IN
5
LTB
5m
⍀
6
VID4
VID3
VID2
VID1
VID0
OUT
SRMON
PGND
DRVL
VCC
C29
100pF
D1
10BQ040
R18
576
M2
C4–C6,
C11, C12,
C26, C27
M3
7
GND
⍀
DRVLSD
DLY
IRF7811
IRF7811
R9
FROM
CPU
8
DACOUT
CORE
SSC
GND
220F
؋
7 C23
1nF
R8
2.2
9
C18
10pF
⍀
8
VCCGD
2.2
⍀
10
11
12
13
14
C21
1.5nF
R5
10k⍀
R6
7.5k⍀
C22
1nF
C28
10F
Q2
CLKDRV
CLKFB
SSL
2N3906
UVLO
C3
R11
220k⍀
R12
470k⍀
68F
Q1
MJD210
IODRV PWRGD
SD 15
IOFB
C14
100F
VCC ON CORE SENSE
V GATE
VCC CPU IO
VCC CPU CLK
C20
10F
VRON
Figure1. MobileVRMSchematic
OUTLINE DIMENSIONS
Dimensions shown in mm and (inches).
28-Lead Thin Shrink Small Outline Package (TSSOP)
(RU-28)
9.80 (0.386)
9.60 (0.378)
28
15
4.50 (0.177)
4.30 (0.169)
6.50 (0.256)
6.25 (0.246)
1
14
PIN 1
0.15 (0.006)
0.05 (0.002)
1.10 (0.043)
MAX
8؇
0؇
0.65 (0.026)
BSC
0.30 (0.012)
0.19 (0.008)
0.70 (0.028)
0.50 (0.020)
SEATING
PLANE
0.20 (0.008)
0.09 (0.004)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE
ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE
FOR USE IN DESIGN
Revision History
Location
Page
5/02—Data Sheet changed from REV. 0 to REV. A.
Changed Figures to TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Renumbered Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
–12–
REV. A
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