ADP3335ARM-18 [ADI]
High Accuracy Ultralow IQ, 500 mA anyCAP Low Dropout Regulator; 高精度超低IQ ， 500毫安公司的anyCAP低压差稳压器
| 型号： | ADP3335ARM-18 |
| 厂家： | 
ADI |
| 描述： | High Accuracy Ultralow IQ, 500 mA anyCAP Low Dropout Regulator |
| 文件： | 总8页 (文件大小：635K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Accuracy Ultralow IQ, 500 mA
®
a
anyCAP Low Dropout Regulator
ADP3335
FUNCTIONAL BLOCK DIAGRAM
FEATURES
High Accuracy Over Line and Load: ؎0.9% @ 25؇C,
؎1.8% Over Temperature
Ultralow Dropout Voltage: 200 mV (Typ) @ 500 mA
Requires Only CO = 1.0 F for Stability
anyCAP = Stable with Any Type of Capacitor
(Including MLCC)
Current and Thermal Limiting
Low Noise
Low Shutdown Current: < 1.0 A
2.6 V to 12 V Supply Range
Q1
OUT
IN
ADP3335
R1
R2
THERMAL
PROTECTION
CC
NR
g
DRIVER
m
SD
BANDGAP
REF
–40؇C to +85؇C Ambient Temperature Range
Ultrasmall Thermally-Enhanced 8-Lead MSOP Package
GND
APPLICATIONS
PCMCIA Card
Cellular Phones
Camcorders, Cameras
Networking Systems, DSL/Cable Modems
Cable Set-Top Box
MP3/CD Players
NR
ADP3335
OUT
DSP Supply
IN
IN
OUT
OUT
GND
V
V
IN
OUT
GENERAL DESCRIPTION
+
+
C
1F
C
OUT
IN
SD
1F
The ADP3335 is a member of the ADP330x family of precision
low dropout anyCAP voltage regulators. The ADP3335 operates
with an input voltage range of 2.6 V to 12 V and delivers a con-
tinuous load current up to 500 mA. The ADP3335 stands out
from conventional LDOs with the lowest thermal resistance of
any MSOP-8 package and an enhanced process that enables it
to offer performance advantages beyond its competition. Its
patented design requires only a 1.0 µF output capacitor for sta-
bility. This device is insensitive to output capacitor Equivalent
Series Resistance (ESR), and is stable with any good quality
capacitor, including ceramic (MLCC) types for space-restricted
applications. The ADP3335 achieves exceptional accuracy of
0.9% at room temperature and 1.8% over temperature, line,
and load. The dropout voltage of the ADP3335 is only 200 mV
(typical) at 500 mA. This device also includes a safety current
limit, thermal overload protection and a shutdown feature. In
shutdown mode, the ground current is reduced to less than
1 µA. The ADP3335 has ultralow quiescent current 80 µA
(typical) in light load situations.
ON
OFF
Figure 1. Typical Application Circuit
anyCAP is a registered trademark of Analog Devices Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
ADP3335–SPECIFICATIONS1, 2, 3
(VIN = 6.0 V, CIN = COUT = 1.0 F, TA = –40؇C to +85؇C, unless otherwise noted)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
OUTPUT
Voltage Accuracy4
VOUT
VIN = VOUT(NOM) + 0.4 V to 12 V
IL = 0.1 mA to 500 mA
TA = 25°C
VIN = VOUT(NOM) + 0.4 V to 12 V
IL = 0.1 mA to 500 mA
TA = 85°C
VIN = VOUT(NOM) + 0.4 V to 12 V
IL = 0.1 mA to 500 mA
TJ = 150°C
VIN = VOUT(NOM) + 0.4 V to 12 V
IL = 0.1 mA
–0.9
+0.9
%
–1.8
–2.3
+1.8
+2.3
%
%
Line Regulation4
0.04
0.04
mV/V
mV/mA
TA = 25°C
Load Regulation
Dropout Voltage
IL = 0.1 mA to 500 mA
TA = 25°C
VDROP
VOUT = 98% of VOUT(NOM)
IL = 500 mA
200
140
30
370
230
110
40
mV
mV
mV
mV
IL = 300 mA
IL = 50 mA
IL = 0.1 mA
10
Peak Load Current
Output Noise
ILDPK
VNOISE
VIN = VOUT(NOM) + 1 V
f = 10 Hz–100 kHz, CL = 10 µF
IL = 500 mA, CNR = 10 nF
f = 10 Hz–100 kHz, CL = 10 µF
IL = 500 mA, CNR = 0 nF
800
47
mA
µV rms
95
µV rms
GROUND CURRENT
In Regulation
IGND
IL = 500 mA
IL = 300 mA
IL = 50 mA
IL = 0.1 mA
VIN = VOUT(NOM) – 100 mV
IL = 0.1 mA
4.5
2.6
0.5
80
10
6
2.5
110
400
mA
mA
mA
µA
In Dropout
IGND
120
µA
In Shutdown
IGNDSD
SD = 0 V, VIN = 12 V
0.01
1
µA
SHUTDOWN
Threshold Voltage
VTHSD
ON
2.0
V
OFF
0.4
3
5
V
SD Input Current
Output Current In Shutdown
ISD
IOSD
0 ≤ SD ≤ 5 V
TA = 25°C, VIN = 12 V
TA = 85°C, VIN = 12 V
1.2
1.2
1.2
µA
µA
µA
5
NOTES
1All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
2Ambient temperature of 85°C corresponds to a junction temperature of 125°C under pulsed full load test conditions.
3Application stable with no load.
4VIN = 2.6 V to 12 V for models with VOUT(NOM) ≤ 2.2 V.
Specifications subject to change without notice.
REV. 0
–2–
ADP3335
ABSOLUTE MAXIMUM RATINGS*
PIN FUNCTION DESCRIPTIONS
Input Supply Voltage . . . . . . . . . . . . . . . . . . . –0.3 V to +16 V
Shutdown Input Voltage . . . . . . . . . . . . . . . . –0.3 V to +16 V
Power Dissipation . . . . . . . . . . . . . . . . . . . Internally Limited
Operating Ambient Temperature Range . . . . –40°C to +85°C
Operating Junction Temperature Range . . . –40°C to +150°C
Pin
No.
Mnemonic Function
1, 2, 3 OUT
Output of the Regulator. Bypass to
ground with a 1.0 µF or larger capacitor.
All pins must be connected together for
proper operation.
θ
θ
JA 2-layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153°C/W
JA 4-layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110°C/W
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
4
5
GND
NR
Ground Pin.
Noise Reduction Pin. Used for further
reduction of output noise (see text for
detail).
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged.
Capacitor required if COUT > 3.3 µF.
6
SD
Active Low Shutdown Pin. Connect to
ground to disable the regulator output.
When shutdown is not used, this pin
should be connected to the input pin.
7, 8
IN
Regulator Input. All pins must be con-
nected together for proper operation.
PIN CONFIGURATION
8
7
6
5
1
2
3
4
IN
OUT
OUT
OUT
GND
ADP3335
IN
TOP VIEW
(Not to Scale)
SD
NR
ORDERING GUIDE
Output
Voltage*
Package
Option
Branding
Information
Model
ADP3335ARM-1.8
ADP3335ARM-2.5
ADP3335ARM-2.85
ADP3335ARM-3.3
ADP3335ARM-5
1.8 V
2.5 V
2.85 V
3.3 V
5 V
RM-8 (MSOP-8)
RM-8 (MSOP-8)
RM-8 (MSOP-8)
RM-8 (MSOP-8)
RM-8 (MSOP-8)
LFA
LFC
LFD
LFE
LFF
*Contact the factory for other output voltage options.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3335 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
–Typical Performance Characteristics (T = 25؇C unless otherwise noted.)
ADP3335
A
2.201
2.200
2.199
2.198
2.197
2.196
2.202
140
120
100
80
V
= 2.2V
V
V
= 2.2V
I
= 100A
OUT
OUT
= 6V
V
= 2.2V
L
OUT
I
= 0
2.201
2.200
2.199
2.198
2.197
2.196
L
IN
150mA
300mA
I
= 0
L
60
40
2.195
2.194
2.193
20
0
2.195
2.194
500mA
0
100
200
300
400
500
2
4
6
8
10
12
0
2
4
6
8
10
12
INPUT VOLTAGE – Volts
OUTPUT LOAD – mA
INPUT VOLTAGE – Volts
Figure 2. Line Regulation Output
Voltage vs. Supply Voltage
Figure 3. Output Voltage vs. Load
Current
Figure 4. Ground Current vs. Supply
Voltage
1
5.0
4.0
3.0
2.0
1.0
8
0
I
= 500mA
0.9
L
7
0.8
300mA
0.7
6
5
4
3
0.6
0.5
0.4
0.3
0.2
300mA
500mA
0.1
0
100mA
50mA
2
1
–0.1
500mA
–0.2
–0.3
0
0
0
0
0
–0.4
–40 –15
5
25
45
65
85 105 125
100
200
300
400
500
–40 –15
5
25
45
65
85
105 125
OUTPUT LOAD – mA
JUNCTION TEMPERATURE – ؇C
JUNCTION TEMPERATURE – ؇C
Figure 7. Ground Current vs. Junction
Temperature
Figure 5. Ground Current vs. Load
Current
Figure 6. Output Voltage Variation %
vs. Junction Temperature
250
200
150
100
50
V
= 2.2V
OUT
SD = V
3.0
2.5
2.0
1.5
1.0
0.5
0
3
IN
= 4.4⍀
C
= 1F
R
OUT
L
2
1
0
4
2
0
C
= 10F
OUT
V
= 2.2V
OUT
SD = V
R
IN
= 4.4⍀
L
1
2
3
4
200
400
TIME – s
600
800
0
TIME – Sec
0
100
200
300
400
500
OUTPUT LOAD – mA
Figure 8. Dropout Voltage vs.
Output Current
Figure 10. Power–Up Response
Figure 9. Power-Up/Power-Down
REV. 0
–4–
ADP3335
2.210
2.200
2.190
2.189
2.179
3.500
3.000
2.3
2.2
2.1
2.210
2.200
2.190
2.189
2.179
3.500
3.000
V
V
C
= 4V
= 2.2⍀
V
R
C
= 2.2V
= 4.4⍀
= 10F
V
R
C
= 2.2V
= 4.4⍀
= 1F
IN
OUT
= 1F
OUT
OUT
L
L
L
L
L
400
200
0
40
80
140
180
200
400
TIME – s
600
800
40
80
140
180
TIME – s
TIME – s
Figure 13. Load Transient Response
Figure 11. Line Transient Response
Figure 12. Line Transient Response
V
V
R
= 6V
IN
2.3
2.2
2.1
2.2
0
3
2
= 2.2V
= 4.4⍀
OUT
1F
L
1
0
10F
V
R
C
= 2.2V
= 4.4⍀
= 10F
OUT
FULL SHORT
10F
800m⍀
SHORT
3
L
L
1F
400
200
0
2
2
0
V
= 4V
1
0
IN
200
400
TIME – s
600
800
200
400
TIME – s
600
800
200
400
TIME – s
600
800
Figure 16. Turn On–Turn Off Response
Figure 14. Load Transient Response
Figure 15. Short Circuit Current
–20
100
160
V
= 2.2V
V
= 2.2V
= 1mA
OUT
OUT
C
= 10nF
NR
C
= 10F
= 500mA
L
I
L
140
–30
–40
–50
–60
–70
–80
–90
I
L
C
C
= 10F
C
= 1F
= 500mA
L
L
10
1
C
C
= 10F
L
= 0
I
NR
L
120
100
80
60
40
20
0
= 10nF
NR
IL = 500mA WITHOUT
NOISE REDUCTION
C
= 1F
= 0
L
C
NR
C
L
= 1F
= 50A
IL = 500mA WITH
NOISE REDUCTION
I
L
0.1
0.01
IL = 0mA WITHOUT
NOISE REDUCTION
C
C
= 1F
= 10nF
L
NR
C
= 10F
= 50A
L
I
L
IL = 0mA WITH NOISE REDUCTION
0.001
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
0
10
20
C
30
– F
40
50
FREQUENCY – Hz
L
Figure 19. Output Noise Density
Figure 17. Power Supply Ripple
Rejection
Figure 18. RMS Noise vs. CL
(10 Hz–100 kHz)
REV. 0
–5–
ADP3335
THEORY OF OPERATION
With the ADP3335 anyCAP LDO, this is no longer true. It can
be used with virtually any good quality capacitor, with no con-
straint on the minimum ESR. This innovative design allows the
circuit to be stable with just a small 1 µF capacitor on the out-
put. Additional advantages of the pole-splitting scheme include
superior line noise rejection and very high regulator gain, which
leads to excellent line and load regulation. An impressive 1.8%
accuracy is guaranteed over line, load, and temperature.
The new anyCAP LDO ADP3335 uses a single control loop for
regulation and reference functions. The output voltage is sensed
by a resistive voltage divider consisting of R1 and R2 which is
varied to provide the available output voltage option. Feedback
is taken from this network by way of a series diode (D1) and a
second resistor divider (R3 and R4) to the input of an amplifier.
INPUT
Q1
OUTPUT
Additional features of the circuit include current limit and ther-
mal shutdown and noise reduction.
COMPENSATION
CAPACITOR
ATTENUATION
R1
(V
/V
)
BANDGAP OUT
APPLICATION INFORMATION
Capacitor Selection
R3 D1
C
PTAT
OS
LOAD
(a)
R2
NONINVERTING
WIDEBAND
DRIVER
V
g
m
PTAT
CURRENT
Output Capacitors: as with any micropower device, output
transient response is a function of the output capacitance. The
ADP3335 is stable with a wide range of capacitor values, types
and ESR (anyCAP). A capacitor as low as 1 µF is all that is
needed for stability; larger capacitors can be used if high output
current surges are anticipated. The ADP3335 is stable with
extremely low ESR capacitors (ESR ≈ 0), such as multilayer
ceramic capacitors (MLCC) or OSCON. Note that the effective
capacitance of some capacitor types may fall below the mini-
mum at cold temperature. Ensure that the capacitor provides
more than 1 µF at minimum temperature.
R
LOAD
R4
ADP3335
GND
Figure 20. Functional Block Diagram
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that equilibrium pro-
duces a large, temperature-proportional input ,“offset voltage”
that is repeatable and very well controlled. The temperature-
proportional offset voltage is combined with the complementary
diode voltage to form a “virtual bandgap” voltage, implicit in
the network, although it never appears explicitly in the circuit.
Ultimately, this patented design makes it possible to control
the loop with only one amplifier. This technique also improves
the noise characteristics of the amplifier by providing more flex-
ibility on the trade-off of noise sources that leads to a low noise
design.
Input Bypass Capacitor
An input bypass capacitor is not strictly required but is advisable
in any application involving long input wires or high source
impedance. Connecting a 1 µF capacitor from IN to ground
reduces the circuit's sensitivity to PC board layout. If a larger
value output capacitor is used, then a larger value input capaci-
tor is also recommended.
Noise Reduction
The R1, R2 divider is chosen in the same ratio as the bandgap
voltage to the output voltage. Although the R1, R2 resistor divider
is loaded by the diode D1 and a second divider consisting of R3
and R4, the values can be chosen to produce a temperature stable
output. This unique arrangement specifically corrects for the load-
ing of the divider thus avoiding the error resulting from base
current loading in conventional circuits.
A noise reduction capacitor (CNR) can be used to further reduce
the noise by 6 dB–10 dB (Figure 18) low leakage capacitors in
10 pF–500 pF range provide the best performance. Since the
noise reduction pin (NR) is internally connected to a high imped-
ance node, any connection to this node should be carefully done
to avoid noise pickup from external sources. The pad connected
to this pin should be as small as possible and long PC board
traces are not recommended.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this spe-
cial noninverting driver enables the frequency compensation
to include the load capacitor in a pole-splitting arrangement
to achieve reduced sensitivity to the value, type, and ESR of
the load capacitance.
When adding a noise reduction capacitor, maintain a mini-
mum load current of 1 mA when not in shutdown.
Most LDOs place very strict requirements on the range of ESR
values for the output capacitor because they are difficult to stabilize
due to the uncertainty of load capacitance and resistance. More-
over, the ESR value, required to keep conventional LDOs stable,
changes depending on load and temperature. These ESR limita-
tions make designing with LDOs more difficult because of their
unclear specifications and extreme variations over temperature.
REV. 0
–6–
ADP3335
It is important to note that as CNR increases, the turn-on time
will be delayed. With NR values greater than 1 nF, this delay
may be on the order of several milliseconds.
Calculating Junction Temperature
Device power dissipation is calculated as follows:
PD = VIN −VOUT ILOAD + VIN IGND
(
)
(
)
C
NR
Where ILOAD and IGND are load current and ground current, VIN
and VOUT are input and output voltages respectively.
NR
OUT
Assuming ILOAD = 400 mA, IGND = 4 mA, VIN = 5.0 V and
ADP3335
VOUT = 3.3 V, device power dissipation is:
IN
OUT
PD = (5 – 3.3) 400 mA + 5.0(4 mA) = 700 mW
V
OUT
GND
V
IN
OUT
IN
+
+
The proprietary package used in the ADP3335 has a thermal
resistance of 110°C/W, significantly lower than a standard
MSOP-8 package. Assuming a 4-layer board, the junction tem-
perature rise above ambient temperature will be approximately
equal to:
C
1F
C
IN
OUT
1F
SD
ON
OFF
Figure 21. Typical Application Circuit
Paddle-Under-Lead Package
∆TJA = 0.700W × 110°C/W = 77.0°C
To limit the maximum junction temperature to 150°C, maxi-
mum allowable ambient temperature will be:
The ADP3335 uses a patented paddle-under-lead package
design to ensure the best thermal performance in an MSOP-8
footprint. This new package uses an electrically isolated die
attach that allows all pins to contribute to heat conduction.
This technique reduces the thermal resistance to 110°C/W on a
4-layer board as compared to >160°C/W for a standard MSOP-8
leadframe. Figure 22 shows the standard physical construc-
tion of the MSOP-8 and the paddle-under-lead leadframe.
T
AMAX = 150°C – 77.0°C = 73.0°C
Printed Circuit Board Layout Consideration
All surface mount packages rely on the traces of the PC board to
conduct heat away from the package.
In standard packages the dominant component of the heat resis-
tance path is the plastic between the die attach pad and the
individual leads. In typical thermally enhanced packages one or
more of the leads are fused to the die attach pad, significantly
decreasing this component. To make the improvement mean-
ingful, however, a significant copper area on the PCB must be
attached to these fused pins.
The patented paddle-under-lead frame design of the ADP3335
uniformly minimizes the value of the dominant portion of the
thermal resistance. It ensures that heat is conducted away by all
pins of the package. This yields a very low 110°C/W thermal
resistance for an MSOP-8 package, without any special board
layout requirements, relying only on the normal traces connected
to the leads. This yields a 33% improvement in heat dissipation
capability as compared to a standard MSOP-8 package. The
thermal resistance can be decreased by, approximately, an addi-
tional 10% by attaching a few square cm of copper area to the
IN pin of the ADP3335 package.
DIE
Figure 22. Thermally Enhanced Paddle-Under-Lead Package
Thermal Overload Protection
The ADP3335 is protected against damage from excessive power
dissipation by its thermal overload protection circuit which limits
the die temperature to a maximum of 165°C. Under extreme
conditions (i.e., high ambient temperature and power dissipation)
where die temperature starts to rise above 165°C, the output
current is reduced until the die temperature has dropped to a
safe level. The output current is restored when the die tempera-
ture is reduced.
It is not recommended to use solder mask or silkscreen on the
PCB traces adjacent to the ADP3335’s pins since it will increase
the junction-to-ambient thermal resistance of the package.
Shutdown Mode
Applying a TTL high signal to the shutdown (SD) pin or tying
it to the input pin, will turn the output ON. Pulling SD down to
0.4 V or below, or tying it to ground will turn the output OFF.
In shutdown mode, quiescent current is reduced to much less
than 1 µA.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, device power dissipation should be externally limited
so that junction temperatures will not exceed 150°C.
REV. 0
–7–
ADP3335
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead mini_SO
(RM-8)
0.122 (3.10)
0.114 (2.90)
8
5
4
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
1
PIN 1
0.0256 (0.65) BSC
0.120 (3.05)
0.112 (2.84)
0.120 (3.05)
0.112 (2.84)
0.043 (1.09)
0.037 (0.94)
0.006 (0.15)
0.002 (0.05)
33؇
0.018 (0.46)
0.008 (0.20)
27؇
0.028 (0.71)
0.016 (0.41)
0.011 (0.28)
0.003 (0.08)
SEATING
PLANE
REV. 0
–8–
相关型号：
ADP3335ARM-2.5
IC VREG 2.5 V FIXED POSITIVE LDO REGULATOR, 0.37 V DROPOUT, PDSO8, ULTRA SMALL, THERMALLY ENHANCED, MINI, MSOP-8, Fixed Positive Single Output LDO Regulator
ADI
ADP3335ARM-2.5-RL
IC VREG 2.5 V FIXED POSITIVE LDO REGULATOR, 0.37 V DROPOUT, PDSO8, MO-187AA, MSOP-8, Fixed Positive Single Output LDO Regulator
ADI
ADP3335ARM-2.5-RL7
2.5 V FIXED POSITIVE LDO REGULATOR, 0.37 V DROPOUT, PDSO8, MO-187AA, MSOP-8
ROCHESTER
ADP3335ARM-2.85-R7
2.85 V FIXED POSITIVE LDO REGULATOR, 0.37 V DROPOUT, PDSO8, MO-187AA, MSOP-8
ROCHESTER
ADP3335ARM-2.85-RL
IC VREG 2.85 V FIXED POSITIVE LDO REGULATOR, 0.37 V DROPOUT, PDSO8, MO-187AA, MSOP-8, Fixed Positive Single Output LDO Regulator
ADI
ADP3335ARM-2.85-RL
2.85 V FIXED POSITIVE LDO REGULATOR, 0.37 V DROPOUT, PDSO8, MO-187AA, MSOP-8
ROCHESTER
ADP3335ARM-2.85-RL7
IC VREG 2.85 V FIXED POSITIVE LDO REGULATOR, 0.37 V DROPOUT, PDSO8, MSOP-8, Fixed Positive Single Output LDO Regulator
ADI
ADP3335ARM-3.3-RL7
IC VREG 3.3 V FIXED POSITIVE LDO REGULATOR, 0.37 V DROPOUT, PDSO8, MO-187AA, MSOP-8, Fixed Positive Single Output LDO Regulator
ADI
©2020 ICPDF网 联系我们和版权申明