ADP3166 [ADI]
5-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller; 5位可编程2-， 3-， 4相同步降压控制器
| 型号： | ADP3166 |
| 厂家： | 
ADI |
| 描述： | 5-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller |
| 文件： | 总20页 (文件大小：346K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
5-Bit Programmable 2-, 3-, 4-Phase
Synchronous Buck Controller
ADP3166*
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Selectable 2-, 3- or 4-Phase Operation at up to
1 MHz per Phase
VCC
28
RAMPADJ RT
14
13
Differential Sensing Error 1% over Temperature
Logic-Level PWM Outputs for Interface to
External High Power Drivers
Active Current Balancing between All Output Phases
Built-in Power Good Blanking Supports On-the-Fly
VID Code Changes
5-Bit Digitally Programmable 0.8 V to 1.55 V Output
Short-Circuit Protection with Programmable
Latch-Off Delay
ADP3166
UVLO
SHUTDOWN
AND BIAS
EN
11
OSCILLATOR
SET
RESET
EN
+
27 PWM1
26 PWM2
25 PWM3
CMP
–
GND
19
6
+
CROWBAR
RESET
2-, 3-, 4-PHASE
DRIVER LOGIC
CMP
–
CURRENT
BALANCING
CIRCUIT
CSREF
2.1V
+
–
+
RESET
CMP
–
+
+
–
DAC + 300mV
CSREF
RESET
PWM4
24
CURRENT
CMP
Overvoltage Protection Crowbar Logic Output
–
CROWBAR
+
–
LIMIT
APPLICATIONS
DAC – 300mV
Desktop PC Power Supplies
Next-Generation AMD Processors
VRM Modules
23
22
21
20
SW1
SW2
SW3
SW4
PWRGD 10
DELAY
GENERAL DESCRIPTION
ILIMIT
15
The ADP3166 is a highly efficient, multiphase, synchronous
buck switching regulator controller optimized for converting a
12 V main supply into the core supply voltage required by high
performance AMD processors. It uses an internal 5-bit DAC to
read a voltage identification (VID) code directly from the pro-
cessor, which is used to set the output voltage between 0.8 V
and 1.55 V. The ADP3166 also uses a multimode PWM
architecture to drive the logic-level outputs at a programmable
switching frequency that can be optimized for VRM size and
efficiency. The phase relationship of the output signals can be
programmed to provide 2-, 3-, or 4-phase operation, allowing
for the construction of up to four complementary buck switch-
ing stages.
–
+
17
16
CSSUM
CSREF
CURRENT
LIMIT
CIRCUIT
EN
DELAY
COMP
12
9
18
CSCOMP
SOFT
START
–
+
FB
8
+
–
PRECISION
REFERENCE
VID
DAC
7
1
2
3
4
5
FBRTN
VID4 VID3 VID2 VID1 VID0
The ADP3166 includes programmable no-load offset and slope
functions to adjust the output voltage as a function of the load
current so that it is always optimally positioned for a system
transient. The ADP3166 also provides accurate and reliable
short-circuit protection, adjustable current limiting, and a delayed
power good output that accommodates on-the-fly output volt-
age changes requested by the CPU.
ADP3166 is specified over the commercial temperature range of
0°C to 85°C and is available in a 28-lead TSSOP package.
*Patent pending
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
ADP3166–SPECIFICATIONS1
(VCC = 12 V, FBRTN = GND, TA = 0؇C to 85؇C, unless otherwise noted.)
Parameter
Symbol
Conditions
Min Typ Max
Unit
ERROR AMPLIFIER
Accuracy
VFB
0.8 V Output
Referenced to FBRTN, CSSUM = CSCOMP, 0.792 0.800 0.808
See Test Circuit 1
Referenced to FBRTN, CSSUM = CSCOMP, 1.163 1.175 1.187
See Test Circuit 1
Referenced to FBRTN, CSSUM = CSCOMP, 1.535 1.55 1.566
See Test Circuit 1
V
V
V
1.175 V Output
1.55 V Output
Line Regulation
Input Bias Current
FBRTN Current
Output Current
Gain Bandwidth Product
Slew Rate
∆VFB
IFB
IFBRTN
VCC = 10 V to 14 V
0.05
–15.5 –17
100
500
20
%
–13
µA
200
µA
IO(ERR)
FB forced to VOUT – 3%
µA
GBW(ERR) COMP = FB
CCOMP = 10 pF
MHz
V/µs
50
VID INPUTS
Input Low Voltage
Input High Voltage
Input Current
Pull-Up Resistance
Internal Pull-Up Voltage
VID Transition Delay Time2
No CPU Detection Turn-Off
Delay Time2
VIL(VID)
VIH(VID)
IVID
0.8
26
V
V
µA
kΩ
V
ns
ns
2
VID(X) = 0 V
20
120
2.4
RVID
100
2.0
400
400
2.65
VID code change to FB change
VID code change to 11111 to
PWM going low
OSCILLATOR
Frequency Range2
Frequency Variation
fOSC
fPHASE
0.25
160
4
240
MHz
kHz
kHz
kHz
V
kΩ
mV
µA
TA = 25°C, RT = 250 kΩ, 4-phase
TA = 25°C, RT = 115 kΩ, 4-phase2
TA = 25°C, RT = 75 kΩ, 4-phase2
RT = 100 kΩ to GND
200
400
600
2.0
Output Voltage
Timing Resistor Value
RAMPADJ Voltage
RAMPADJ Input Current Range IRAMPADJ
VRT
1.9
2.1
500
+50
50
VRAMPADJ
RAMPADJ – FB
–50
0
CURRENT SENSE AMPLIFIER
Offset Voltage
VOS(CSA)
IBIAS(CSA)
GBWCSA
CSSUM – CSREF, see Test Circuit 2
–3
+3
100
mV
nA
MHz
V/µs
V
mV
V
Input Bias Current
Gain Bandwidth Product
Slew Rate
Input Common-Mode Range
Positioning Accuracy
Output Voltage Range
Output Current
20
20
50
C
CSCOMP = 10 pF
CSSUM and CSREF
See Test Circuit 3
0
–76
0.05
3
–84
3.3
∆VFB
–80
500
ICSCOMP
= 100 µA
ICSCOMP
µA
CURRENT BALANCE CIRCUIT
Common-Mode Range
Input Resistance
Input Current
Input Current Matching
VSW(X)CM
RSW(X)
ISW(X)
–600
24
5
+200
36
9
mV
kΩ
µA
%
SW(X) = 0 V
SW(X) = 0 V
SW(X) = 0 V
30
7
∆ISW(X)
–5
+5
CURRENT LIMIT COMPARATOR
Output Voltage
Normal Mode
VILIMIT(NM) EN > 2 V
2.9
3
3.1
V
In Shutdown
Output Current, Normal Mode
Maximum Output Current
Current Limit Threshold Voltage VCL
Current Limit Setting Ratio
Latch-Off Delay Threshold
Latch-Off Delay Time
VILIMIT(SD) EN < 0.8 V, IILIMIT = –100 µA
IILIMIT(NM) EN > 2 V, RILIMIT = 250 kΩ
EN > 2 V
400
mV
µA
µA
mV
mV/µA
V
12
60
105
VCSREF – VCSCOMP, RILIMIT = 250 kΩ
VCL/IILIMIT
125
10.4
1.8
145
1.9
VSET(DLY)
tSET(DLY)
In current limit
RDELAY = 250 kΩ, CDELAY = 4.7 nF
1.7
600
µs
–2–
REV. 0
ADP3166
Parameter
Symbol
Conditions
Min Typ Max
Unit
SOFT START
Output Current, Soft Start Mode IDELAY(SS)
During start-up, DELAY < 2.8 V
RDELAY = 250 kΩ, CDELAY = 4.7 nF
VID Code = 01111
15
20
350
25
µA
µs
Soft Start Delay Time
tDELAY(SS)
ENABLE INPUT
Input Low Voltage
Input High Voltage
Input Current
VIL(EN)
VIH(EN)
0.8
+1
V
V
µA
2
–1
POWER GOOD COMPARATOR
Undervoltage Threshold
Overvoltage Threshold
Output Low Voltage
Off-State Leakage Current
Delay Time
VPWRGD(UV)
VPWRGD(OV)
VOL(PWRGD)
Relative to nominal DAC output
Relative to nominal DAC output
IPWRGD(SINK) = 4 mA
–200 –300 –400
mV
mV
mV
µA
200
300
150
400
400
50
VCSREF = VDAC
VID Code Changing
VID Code Static
100
250
400
µs
ns
CROWBAR COMPARATOR
Crowbar Trip Point
Crowbar Reset Point
Crowbar Response Time
Overvoltage to PWM Low
Overvoltage to CRWBR High
Output Voltage Low
VCROWBAR
tCROWBAR
2.0
300
2.1
400
2.2
500
V
mV
400
400
100
5.0
ns
ns
mV
V
VOL(CROWBAR) ICROWBAR(SINK) = 100 µA
VOH(CROWBAR) ICROWBAR(SOURCE) = 100 µA
500
500
Output Voltage High
4.0
4.0
PWM OUTPUTS
Output Voltage Low
Output Voltage High
VOL(PWM)
VOH(PWM)
IPWM(SINK) = 400 µA
160
5.0
mV
V
IPWM(SOURCE) = 400 µA
SUPPLY
DC Supply Current
UVLO Threshold Voltage
UVLO Hysteresis
ICC
VUVLO
7
6.9
0.9
10
7.3
1.1
mA
V
V
VCC rising
6.5
0.7
NOTES
1All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2Guaranteed by design, not tested in production.
Specifications subject to change without notice.
REV. 0
–3–
ADP3166
ABSOLUTE MAXIMUM RATINGS*
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V
FBRTN . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
VID0 to VID4, EN, DELAY, ILIMIT, CSCOMP, RT, COMP,
CROWBAR, PWM1 to PWM4 . . . . . . . . . –0.3 V to +5.5 V
SW1 to SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to +25 V
All Other Inputs and Outputs . . . . . . . –0.3 V to VCC + 0.3 V
Operating Ambient Temperature Range . . . . . . . 0°C to 85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . 125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only. Functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Absolute maximum
ratings apply individually only, not in combination. Unless otherwise specified, all
other voltages are referenced to GND.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100°C/W
JA
ORDERING GUIDE
Temperature
Range
Package
Options
Quantity
per Reel
Model
ADP3166JRU-REEL7
ADP3166JRU-REEL
0°C to 85°C
0°C to 85°C
RU-28 (TSSOP-28) 1000
RU-28 (TSSOP-28) 2500
4
3
2
1
0
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
T
= 25؇C
A
4-PHASE OPERATION
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
50
100
150
200
250
300
R
VALUE – kΩ
MASTER CLOCK FREQUENCY – MHz
T
TPC 1. Supply Current vs. Master Clock Frequency
TPC 2. Master Clock Frequency vs. RT
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADP3166 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–4–
REV. 0
ADP3166
ADP3166
ADP3166
VCC
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VID4
VCC
PWM1
PWM2
PWM3
PWM4
SW1
12V
+
1F
100nF
28
VID3
12V
3
VID2
FB
5-BIT CODE
8
9
4
VID1
10k⍀
5
VID0
COMP
CSCOMP
CSSUM
CSREF
6
CROWBAR
FBRTN
FB
7
200k⍀
SW2
18
17
16
19
8
SW3
200k⍀
9
–
+
COMP
PWRGD
EN
SW4
1k⍀
+
–
10
11
12
13
14
80mV
1V
GND
1.25V
CSCOMP
CSSUM
CSREF
ILIMIT
20k⍀
100nF
+
–
DELAY
RT
GND
⌬V = FB – V
FB
VID
4.7nF
250k⍀
RAMPADJ
250k⍀
Test Circuit 3. Positioning Voltage Test Circuit
Test Circuit 1. Closed-Loop Output Voltage Accuracy
ADP3166
VCC
28
18
17
16
19
12V
CSCOMP
CSSUM
CSREF
GND
100nF
39k⍀
–
+
1k⍀
+
–
1V
CSCOMP – 1V
40
V
=
OS
Test Circuit 2. Positioning Amplifier VOS Test Circuit
REV. 0
–5–
ADP3166
PIN CONFIGURATION
RU-28
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VID4
VID3
VCC
PWM1
PWM2
PWM3
PWM4
SW1
3
VID2
ADP3166
TOP VIEW
(Not to Scale)
4
VID1
5
VID0
6
CROWBAR
FBRTN
FB
7
SW2
8
SW3
9
COMP
PWRGD
EN
SW4
10
11
12
13
14
GND
CSCOMP
CSSUM
CSREF
ILIMIT
DELAY
RT
RAMPADJ
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic
Function
1–5
VID4–VID0
Voltage Identification DAC Inputs. These five pins are pulled up to an internal reference, providing a
logic 1 if left open. When in normal operation mode, the DAC output programs the FB regulation voltage
from 0.8 V to 1.55 V. Leaving VID4 through VID0 open results in the ADP3166 going into a “No CPU”
mode, shutting off its PWM outputs.
6
CROWBAR
Crowbar Output. This logic-level output can be used to control an external device to short the 12 V supply
to ground to protect the CPU from overvoltage if CSREF exceeds 2.1 V.
7
8
FBRTN
FB
Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.
Feedback Input. Error amplifier input for remote sensing of the output voltage. A resistor between this pin
and the output voltage sets the no-load offset point.
9
COMP
Error Amplifier Output and Compensation Point.
10
PWRGD
Power Good Output. Open-drain output that pulls to GND when the output voltage is outside of the
proper operating range.
11
12
EN
Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs.
DELAY
Soft Start Delay and Current Limit Latch-Off Delay Setting Input. A resistor and capacitor connected
between this pin and GND sets the soft start ramp-up time and the overcurrent latch-off delay time.
13
RT
Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscil-
lator frequency of the device.
14
15
RAMPADJ
ILIMIT
PWM Ramp Current Input. A resistor from the converter input voltage to this pin sets the internal PWM ramp.
Current Limit Set Point/Enable Output. A resistor from this pin to GND sets the current limit threshold of
the converter. This pin is actively pulled low when the ADP3166 EN input is low, or when VCC is below
its UVLO threshold to signal to the driver IC that the driver high-side and low-side outputs should go low.
16
CSREF
Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current
sense amplifiers and the Power Good and Crowbar functions. This pin should be connected to the com-
mon point of the output inductors.
17
18
CSSUM
Current Sense Summing Node. Resistors from each switch node to this pin sum the average inductor cur-
rents together to measure the total output current.
CSCOMP
Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the slope
of the load line and the positioning loop response time.
19
GND
Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
20–23
SW4–SW1
Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused
phases should be grounded.
24–27
28
PWM4–PWM1 Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such
as the ADP3413 or ADP3418. Connecting the PWM3 and/or PWM 4 outputs to GND will cause that
phase to turn off, allowing the ADP3166 to operate as a 2-, 3-, or 4-phase controller.
VCC
Supply Voltage for the Device.
–6–
REV. 0
ADP3166
THEORY OF OPERATION
Table I. VID Code vs. Output Voltage
The ADP3166 combines a multimode, fixed frequency PWM
control with multiphase logic outputs for use in 2-, 3-, and 4-phase
synchronous buck CPU core supply power converters. The
internal 5-bit VID DAC conforms to AMD’s Hammer family
power specifications. Multiphase operation is important for
producing the high currents and low voltages demanded by
today’s microprocessors. Handling the high currents in a single-
phase converter would place high thermal demands on the
components in the system such as the inductors and MOSFETs.
VID4
VID3
VID2
VID1
VID0
VOUT(NOM) (V)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
No CPU
0.800
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
1.525
1.550
The multimode control of the ADP3166 ensures a stable, high
performance topology for
•
•
Balancing currents and thermals between phases.
High speed response at the lowest possible switching frequency
and output decoupling.
•
Minimizing thermal switching losses due to lower frequency
operation.
•
•
•
•
•
Tight load line regulation and accuracy.
High current output from having up to 4-phase operation.
Reduced output ripple utilizing multiphase cancellation.
Immunity to board layout.
Ease of use and design due to independent component
selection.
•
Flexibility in operation for tailoring design to low cost or
high performance.
Number of Phases
The number of operational phases and their phase relationship
are determined by internal circuitry that monitors the PWM
outputs. Normally, the ADP3166 operates as a 4-phase PWM
controller. Grounding the PWM 4 pin programs 3-phase opera-
tion, and grounding the PWM3 and PWM4 pins programs
2-phase operation.
Output Voltage Differential Sensing
When the ADP3166 is enabled, the controller outputs a voltage
on PWM3 and PWM4 that is approximately 550 mV. An inter-
nal comparator checks each pin’s voltage versus a threshold of
400 mV. If the pin is grounded, it will be below the threshold
and the phase will be disabled. The output impedance of the
PWM pin is approximately 5 kΩ. Any external pull-down resis-
tance connected to the PWM pin should not be less than 25 kΩ
to ensure proper operation. The phase detection is made during
the first two clock cycles of the internal oscillator. After this
time, if the PWM output was not grounded, it will switch between
0 V and 5 V. If the PWM output was grounded, it will remain off.
The ADP3166 combines differential sensing with a high accu-
racy VID DAC and reference and a low offset error amplifier to
maintain a worst-case specification of 1% differential sensing
error over its full operating output voltage and temperature
range. The output voltage is sensed between the FB and
FBRTN pins. FB should be connected through a resistor to the
regulation point, usually the remote sense pin of the micropro-
cessor. FBRTN should be connected directly to the remote
sense ground point. The internal VID DAC and precision refer-
ence are referenced to FBRTN, which has a minimal current of
100 µA to allow accurate remote sensing. The internal error
amplifier compares the output of the DAC to the FB pin to
regulate the output voltage.
The PWM outputs are logic-level devices intended for driving
external gate drivers such as the ADP3418. Since each phase is
monitored independently, operation approaching 100% duty
cycle is possible. Also, more than one output can be on at a time
for overlapping phases.
Output Current Sensing
The ADP3166 provides a dedicated current sense amplifier
(CSA) to monitor the total output current for proper voltage
positioning versus load current, and for current limit detection.
Sensing the load current at the output gives the total average
current being delivered to the load, which is an inherently more
accurate method than peak current detection or sampling the
current across a sense element such as the low-side MOSFET.
Master Clock Frequency
The clock frequency of the ADP3166 is set with an external
resistor connected from the RT pin to ground. The frequency
follows the graph in TPC 1. To determine the frequency per
phase, the clock is divided by the number of phases in use. If
PWM4 is grounded, divide the master clock by 3 for the frequency
of the remaining phases. If PWM3 and PWM4 are grounded,
divide by 2. If all phases are in use, divide by 4.
REV. 0
–7–
ADP3166
This amplifier can be configured several ways depending on the
objectives of the system:
EN is a logic low, the DELAY pin is held at ground. After the
UVLO threshold is reached and EN is a logic high, the DELAY
capacitor is charged up with an internal 20 µA current source.
The output voltage follows the ramping voltage on the DELAY
pin, limiting the inrush current. The soft start time depends on
the value of VID DAC and CDLY, with a secondary effect from
RDLY. Refer to the Applications section for detailed information
•
•
•
Output inductor ESR sensing without thermistor for
lowest cost
Output inductor ESR sensing with thermistor for improved
accuracy with tracking of inductor temperature
on setting CDLY
.
Sense resistors for highest accuracy measurements
When the PWRGD threshold is reached, the soft start cycle is
stopped and the DELAY pin is pulled up to 3 V. This ensures
that the output voltage is at the VID voltage when the PWRGD
signals to the system that the output voltage is good. If EN is
taken low or if VCC drops below UVLO, the DELAY capacitor
is reset to ground to be ready for another soft start cycle.
The positive input of the CSA is connected to the CSREF pin,
which is connected to the output voltage. The inputs to the
amplifier are summed together through resistors from the sensing
element (such as the switch node side of the output inductors) to
the inverting input, CSSUM. The feedback resistor between
CSCOMP and CSSUM sets the gain of the amplifier, and a filter
capacitor is placed in parallel with this resistor. The gain of the
amplifier is programmable by adjusting the feedback resistor to
set the load line required by the microprocessor. The current
information is then given as the difference of CSREF – CSCOMP.
This difference signal is used internally to offset the VID DAC
for voltage positioning, and as a differential input for the current
limit comparator.
Current Limit and Short-Circuit Protection
The ADP3166 compares a programmable current limit set point
to the voltage on the output of the current sense amplifier at the
CSCOMP pin. The level of current limit is set with the resistor
from the ILIMIT pin to ground. During normal operation, the
voltage on ILIMIT is 3 V. The current through the external
resistor is internally scaled to give a current limit threshold of
10.4 mV/µA. If the difference in voltage between CSREF and
CSCOMP drops below the current limit threshold, the internal
current limit amplifier will control the internal COMP voltage
to maintain the average output current at the limit.
To provide the best accuracy for the sensing of current, the
CSA has been designed to have a low offset input voltage. Also,
the sensing gain is determined by external resistors so that it can
be made extremely accurate.
After the limit is reached, the 3 V pull-up on the DELAY pin is
disconnected, and the external delay capacitor is discharged
through the external resistor. A comparator monitors the DELAY
voltage and shuts off the controller when the voltage drops
below 1.8 V. The current limit latch-off delay time is therefore
set by the RC time constant discharging from 3 V to 1.8 V. The
Applications section discusses the selection of RDLY based on
the CDLY that has been chosen.
Active Impedance Control Mode
For controlling the dynamic output voltage droop as a function
of output current, a signal proportional to the total output cur-
rent at the CSCOMP pin can be scaled to be equal to the droop
impedance of the regulator times the output current. This droop
voltage is then used to set the input control voltage to the sys-
tem. The droop voltage is subtracted from the DAC reference
input voltage directly to tell the error amplifier where the output
voltage should be. This differs from previous implementations
and allows enhanced feed-forward response.
Because the controller continues to cycle the phases during the
latch-off delay time, if the short is removed before the 1.8 V
threshold is reached, the controller will return to normal operation.
The recovery characteristic depends on the state of PWRGD. If
the output voltage is within the PWRGD window, the controller
resumes normal operation. However, if short circuit has caused
the output voltage to drop below the PWRGD threshold, then a
soft start cycle is initiated.
Voltage Control Mode
A high gain-bandwidth voltage mode error amplifier is used for
the voltage mode control loop. The control input voltage to the
positive input is set via the VID 5-bit logic code according to
the voltages listed in Table I. This voltage is also offset by the
droop voltage for active positioning of the output voltage as a
function of current, commonly known as active voltage position-
ing. The output of the amplifier is the COMP pin, which sets
the termination voltage for the internal PWM ramps.
The latch-off function can be reset by either removing and
reapplying VCC to the ADP3166, or by pulling the EN pin low
for a short time. To disable the short-circuit latch-off function,
the external resistor to ground should be left open, and a large
(greater than 1 MΩ) resistor should be connected from VCC to
DELAY. This prevents the DELAY capacitor from discharging
so the 1.8 V threshold is never reached. The resistor will have
an impact on the soft start time because the current through it
will add to the internal 20 µA current source.
The negative input (FB) is tied to the output sense location with
a resistor, RB, and is used for sensing and controlling the output
voltage at this point. A current source from the FB pin flowing
through RB is used for setting the no-load offset voltage from
the VID voltage. The no-load voltage will be positive with respect
to the VID DAC. The main loop compensation is incorporated
in the feedback network between FB and COMP.
During startup when the output voltage is below 200 mV, a
secondary current limit is active. This is necessary because the
voltage swing of CSCOMP cannot go below ground. This sec-
ondary current limit controls the internal COMP voltage to the
PWM comparators to 2 V. This will limit the voltage drop across
the low-side MOSFETs through the current balance circuitry.
Soft Start
The power-on ramp-up time of the output voltage is set with a
capacitor and resistor in parallel from the DELAY pin to ground.
The RC time constant also determines the current limit latch-off
time, as explained in the following section. In UVLO or when
–8–
REV. 0
ADP3166
Dynamic VID
APPLICATION INFORMATION
The ADP3166 incorporates the ability to dynamically change
the VID input while the controller is running. This allows the
output voltage to change while the supply is running and sup-
plying current to the load. This is commonly referred to as
VID on-the-fly (OTF). A VID-OTF can occur under either
light load or heavy load conditions. The processor signals the
controller by changing the VID inputs in multiple steps from
the start code to the finish code. This change can be either
positive or negative.
The design parameters for a typical AMD K8 compliant CPU
application are as follows:
•
•
•
•
•
•
Input voltage (VIN) = 12 V
VID setting voltage (VVID) = 1.500 V
Duty cycle (D) = 0.125
Maximum static output voltage error ( VSERR) = 50 mV
Maximum dynamic output voltage error ( VDERR) = 70 mV
Error voltage allowed for controller and ripple ( VRERR) =
20 mV
When a VID input changes state, the ADP3166 detects the
change and blanks the DAC for a minimum of 400 ns. This
time is to prevent a false code due to logic skew while the six
VID inputs are changing. Additionally, the first VID change
initiates the PWRGD blanking function for a minimum of
100 µs to prevent a false PWRGD event. Each VID change will
reset the internal timer.
•
•
•
Maximum output current (IO) = 56 A
Maximum output current step (⌬IO) = 24 A
Static output droop resistance (RO) based on:
a) No load output voltage set at upper output
voltage limit.
Power Good Monitoring
The power good comparator monitors the output voltage via the
CSREF pin. The PWRGD pin is an open-drain output whose
high level (when connected to a pull-up resistor) indicates that
the output voltage is within the nominal limits specified previ-
ously, based on the VID voltage setting. PWRGD will go low if
the output voltage is outside of this specified range. PWRGD is
blanked during a VID-OTF event for a period of 100 µs to
prevent false signals during the time the output is changing.
V
ONL = VVID + VSERR – VRERR = 1.530 V
b) Full load output voltage set at lower output
voltage limit.
•
•
VOFL = VVID – VSERR + VRERR = 1.470 V
RO = (VONL – VOFL)/ (IO) = (1.530 V – 1.470 V)/(56A) =
1.1 mΩ
•
Dynamic output droop resistance (ROD) based on:
Output Crowbar
a) Output current step to no load with output voltage
set at upper output dynamic voltage limit.
As part of the protection for the load and output components of
the supply, the PWM outputs are driven low (turning on the
low-side MOSFETs) and the CROWBAR logic output goes
high when the output voltage exceeds the upper power good
threshold. This crowbar action releases once the output volt-
age has fallen back within specifications if no other faults are
present. The release threshold is approximately 400 mV.
VONLD = VVID + VDERR – VRERR = 1.550 V
b) Output voltage prior to load change
(at IOUT = ⌬IO).
•
•
VOL = VONL – (⌬IO
؋
RO)= 1.504 V ROD = (VONLD – VOL)/ (⌬IO) = (1.550 V – 1.504 V)/(24A) =
1.9 mΩ
Turning on the low-side MOSFETs pulls down the output as
the reverse current builds up in the inductors. If the output
overvoltage is due to a short of the high-side MOSFET, this
action current limits the input supply or blow its fuse, protect-
ing the microprocessor from destruction.
•
•
Number of phases (n) = 3
Switching frequency per phase (fSW) = 330 kHz
Setting the Clock Frequency
The CROWBAR output can be used to signal an external input
crowbar or other protection circuit.
The ADP3166 uses a fixed-frequency control architecture. The
frequency is set by an external timing resistor (RT). The clock
frequency and the number of phases determine the switching
frequency per phase, which relates directly to switching losses
and the sizes of the inductors and input and output capacitors.
With n = 3 for three phases, a clock frequency of 990 kHz sets
the switching frequency of each phase, fSW, to 330 kHz, which
represents a practical trade-off between the switching losses and
the sizes of the output filter components. Figure 1 shows that to
achieve a 990 kHz oscillator frequency, the correct value for RT
is 200 kΩ. Alternatively, the value for RT can be calculated using
Output Enable and UVLO
The input VCC must be higher than the UVLO threshold and the
EN pin must be higher than its logic threshold for the ADP3166 to
begin switching. IF UVLO is less than the threshold or the EN pin
is a logic low, the ADP3166 is disabled. This holds the PWM
outputs at ground, shorts the DELAY capacitor to ground, and
holds the ILIMIT pin at ground.
In the application circuit, the ILIMIT pin should be connected
to the OD pins of the ADP3418 drivers. Because ILIMIT is
grounded, this disables the drivers such that both DRVH and
DRVL are grounded. This feature is important to prevent dis-
charging of the output capacitors when the controller is shut off.
If the driver outputs were not disabled, a negative voltage could
be generated on the output due to the high current discharge of
the output capacitors through the inductors.
1
RT =
(1)
1
n × f × 5.83 pF –
(
)
SW
1.5 MΩ
where 5.83 pF and 1.5 MΩ are internal IC component values.
For good initial accuracy and frequency stability, it is recom-
mended to use a 1% resistor.
REV. 0
–9–
ADP3166
L1
1.6H
2200F/16V
؋
3 NICHICON PW SERIES
V
12V
IN
RTN
+
+
C9
4.7F
C1
C6
V
IN
U2
C8
ADP3418 100nF
D1
1N4148WS
D2
Q1
IPD12N03L
1
2
3
4
BST
IN
DRVH
SW
8
7
6
5
820F/2.5V
؋
8 OSCON SERIES
12m⍀ ESR (EACH)
1N4148WS
L2
600nH/1.6m⍀
V
CC(CORE)
0.8V–1.55V
56A
OD
PGND
DRVL
+
+
C10
4.7nF
R1
VCC
C28
C21
C7
V
CC(CORE) RTN
2.2⍀
4.7F
Q3
IPD06N03L
Q2
IPD06N03L
10F
؋
5MLCC AROUND
SOCKET
D3
C13
4.7F
C12
U3
1N4148WS
ADP3418100nF
Q4
IPD12N03L
1
2
3
4
BST
DRVH
8
7
6
5
L3
IN
SW
600nH/1.6m⍀
OD
PGND
DRVL
C14
4.7nF
VCC
C11
4.7F
R2
2.2⍀
Q6
IPD06N03L
Q5
IPD06N03L
D4
C17
4.7F
U4
ADP3418
1N4148WS
C16
100nF
Q7
IPD12N03L
BST
DRVH
1
2
3
4
8
7
6
5
L4
IN
SW
PGND
DRVL
600nH/1.6m⍀
OD
C18
4.7nF
VCC
R3
2.2⍀
C15
R
TH
100k⍀, 5%
4.7F
Q9
IPD06N03L
Q8
IPD06N03L
+
R4
10⍀
C19
1F
C20
33F
U1
ADP3166
R
R
383k⍀
VID4
VCC
PWM1
PWM2
1
2
3
4
5
6
7
8
9
28
VID3
27
26
VID2
FROM CPU
VID1
PWM3 25
PWM4 24
VID0
R
*
SW1
CROWBAR
FBRTN
FB
SW1
23
R
*
SW2
SW2 22
SW3 21
C
B
R
*
SW3
680pF
C
FB
18pF
R
PH1
147k⍀
R
PH3
147k⍀
COMP
SW4 20
C
R
R
A
7.32k⍀
A
B
POWER
GOOD
680pF
2.00k⍀
R
10 PWRGD
11 EN
GND 19
PH2
147k⍀
R
R
CS2
C
1.5nF
CS1
35.7k⍀ 73.2k⍀
CS2
ENABLE
CSCOMP 18
CSSUM 17
CSREF 16
ILIMIT 15
12 DELAY
13 RT
C
CS1
2.2nF
C
39nF
DLY
R
DLY
390k⍀
R
T
200k⍀
14 RAMPADJ
*SEE THEORY OF
OPERATION
R
LIM
200k⍀
SECTION FOR
DESCRIPTION
OF OPTIONAL
R
RESISTORS
SW
Figure 1. 56 AMD K8 CPU Supply Circuit
–10–
REV. 0
ADP3166
Soft Start and Current Limit Latch-Off Delay Times
If the ripple voltage is less than that designed for, the inductor can
be made smaller until the ripple value is met. This will allow opti-
mal transient response and minimum output decoupling.
Because the soft start and current limit latch-off delay functions
share the DELAY pin, these two parameters must be considered
together. The first step is to set CDLY for the soft start ramp.
This ramp is generated with a 20 µA internal current source.
The value of RDLY will have a second order impact on the soft-
start time because it sinks part of the current source to ground.
However, as long as RDLY is kept greater than 200 kΩ, this effect
is minor. The value for CDLY can be approximated using
The smallest possible inductor should be used to minimize the
number of output capacitors. A 600 nH inductor is a good
choice for a starting point, and it gives a calculated ripple cur-
rent of 6.6 A. The inductor should not saturate at the peak
current of 22 A, and should be able to handle the sum of the
power dissipation caused by the average current of 18.7 A in the
winding and the core loss.
VVID
2 × RDLY
tSS
VVID
CDLY = 20µA –
×
(2)
Another important factor in the inductor design is the DCR,
which is used for measuring the phase currents. A large DCR
will cause excessive power losses, while too small a value will
lead to increased measurement error. A good rule is to have the
DCR be about 1 to 1 1/2 times the static droop resistance (RO).
For our example, we are using an inductor with a DCR of 1.6 mΩ.
where tSS is the desired soft start time. Assuming an RDLY of 390
kΩ and a desired a soft start time of 3 ms, CDLY is 36 nF.
The closest standard value for CCS is 39 nF. Once CDLY has
been chosen, RDLY can be calculated for the current limit latch
off time using
Designing an Inductor
Once the inductance and DCR are known, the next step is either
to design an inductor or to find a standard inductor that comes as
close as possible to meeting the overall design goals. It is also
important to have the inductance and DCR tolerance specified to
keep the accuracy of the system controlled. Using 20% for the
inductance and 8% for the DCR (at room temperature) are rea-
sonable tolerances that most manufacturers can meet.
1.96 × tDLY
RDLY
=
(3)
CDLY
If the result for RDLY is less than 200 kΩ , then a smaller soft start
time should be considered by recalculating the equation for CDLY
or a longer latch-off time should be used. In no case should RDLY
be less than 200 kΩ. In this example, a delay time of 8 ms makes
R
DLY = 402 kΩ. The closest standard 5% value is 390 kΩ.
The first decision in designing the inductor is to choose the core
material. There are several possibilities for providing low core
loss at high frequencies. Two examples are the powder cores
Inductor Selection
The choice of inductance for the inductor determines the ripple
current in the inductor. Less inductance leads to more ripple
current, which increases the output ripple voltage and conduc-
tion losses in the MOSFETs but allows using smaller-size
inductors and, for a specified peak-to-peak transient deviation,
less total output capacitance. Conversely, a higher inductance
means lower ripple current and reduced conduction losses, but
requires larger-size inductors and more output capacitance for
the same peak-to-peak transient deviation. In any multiphase
converter, a practical value for the peak-to-peak inductor ripple
current is less than 50% of the maximum dc current in the same
inductor. Equation 4 shows the relationship between the induc-
tance, oscillator frequency, and peak-to-peak ripple current in
the inductor. Equation 5 can be used to determine the mini-
mum inductance based on a given output ripple voltage:
®
(e.g., Kool-Mµ from Magnetics, Inc. or Micrometals) and the
gapped soft ferrite cores (e.g., 3F3 or 3F4 from Philips). Low
frequency powdered iron cores should be avoided due to their
high core loss, especially when the inductor value is relatively
low and the ripple current is high.
The best choices for a core geometry are closed-loop types, such
as pot cores, PQ, U, and E cores, or toroids. A good compromise
between price and performance are cores with a toroidal shape.
There are many useful references for quickly designing a power
inductor, such as
•
Magnetic Designer Software
Intusoft (http://www.intusoft.com)
•
Designing Magnetic Components for High-Frequency
DC-DC Converters
VVID × 1– D
(
)
McLyman, Kg Magnetics
ISBN 1-883107-00-8
IR =
(4)
(5)
fSW ×L
VVID × ROD × 1– n × D
(
)
(
)
L ≥
fSW ×VRIPPLE
Solving Equation 5 for a 10 mV p-p output ripple voltage yields
1.5V ×1.9mΩ × 1– 0.375
(
)
L ≥
= 540nH
330kHz ×10mV
REV. 0
–11–
ADP3166
Selecting a Standard Inductor
It is best to have a dual location for CCS in the layout so stan-
dard values can be used in parallel to get as close to the value
desired. For this example, choosing CCS to be a 1.5 nF and 2.2 nF
in parallel is a good choice. For best accuracy, CCS should be
a 10% capacitor. The closest standard 1% value for RPH(X) is
147 kΩ .
The following companies can provide design consultation and
deliver power inductors optimized for high power applications
upon request.
•
•
•
•
Coilcraft
(847)639-6400
http://www.coilcraft.com
Inductor DCR Temperature Correction
With the inductor’s DCR being used as the sense element and
copper wire being the source of the DCR, one needs to com-
pensate for temperature changes of the inductor’s winding.
Fortunately, copper has a well known temperature coefficient
(TC) of 0.39%/°C.
Coiltronics
(561)752-5000
http://www.coiltronics.com
Sumida Electric Company
(510) 668-0660
http://www.sumida.com
If RCS is designed to have an opposite and equal percentage
change in resistance to that of the wire, it will cancel the tem-
perature variation of the inductor’s DCR. Due to the nonlinear
nature of NTC thermistors, resistors RCS1 and RCS2 (see Figure 2)
are needed to linearize the NTC and produce the desired tem-
perature tracking.
Vishay Intertechnology
(402) 563-6866
http://www.vishay.com
Output Droop Resistance
The design requires that the regulator output voltage measured
at the CPU pins drops when the output current increases. The
specified voltage drop corresponds to the static output droop
resistance (RO).
PLACE AS CLOSE AS POSSIBLE
TO NEAREST INDUCTOR
TO
SWITCH
NODES
TO
OR LOW SIDE MOSFET
V
OUT
R
SENSE
TH
The output current is measured by summing together the voltage
across each inductor and then passing the signal through a low-
pass filter. This summer-filter is the CS amplifier configured with
resistors RPH(X) (summers) and RCS, and CCS (filter). The output
resistance of the regulator is set by the following equations, where
RL is the DCR of the output inductors:
R
R
R
PH3
PH1
PH2
ADP3166
R
R
CS2
CS1
CSCOMP
CSSUM
CSREF
18
17
16
KEEP THIS PATH
RCS
C
CS
RO =
× RL
AS SHORT AS POSSIBLE
AND WELL AWAY FROM
SWITCH NODE LINES
(6)
(7)
RPH(X)
L
RL × RCS
CCS
=
One has the flexibility of choosing either RCS or RPH(X). It is best
to select RCS equal to 100 kΩ, and then solve for RPH(X) by
rearranging Equation 6.
Figure 2. Temperature Compensation Circuit Values
The following procedure and expressions will yield values to use
for RCS1, RCS2, and RTH (the thermistor value at 25°C) for a
given RCS value.
RL
RO
RPH(X)
=
× RCS
1.6mΩ
1.1mΩ
1. Select an NTC based on type and value. Since we do not
have a value yet, start with a thermistor with a value close to
RPH(X)
=
×100kΩ= 145.5kΩ
R
CS. The NTC should also have an initial tolerance of better
Next, use Equation 6 to solve for CCS
:
than 5%.
2. Based on the type of NTC, find its relative resistance value at
two temperatures. The temperatures to use that work well are
50°C and 90°C. We will call these resistance values A (A is
600nH
1.6mΩ ×100kΩ
CCS
=
= 3.75nF
RTH(50°C)/RTH(25°C)) and B (B is RTH(90°C)/RTH(25°C)). Note that
the NTC’s relative value is always 1 at 25°C.
3. Next, find the relative value of RCS required for each of these
temperatures. This is based on the percentage change needed,
which we will initially make 0.39%/°C. We will call these r1
(r1 is 1/(1 + TC ϫ (T1 – 25))) and r2 (r2 is 1/(1 + TC ϫ (T2 – 25)))
,
where TC = 0.0039, T1 = 50°C and T2 = 90°C.
–12–
REV. 0
ADP3166
4. Compute the relative values for RCS1, RCS2, and RTH using
A – B × r × r – A × 1– B × r +B × 1– A × r
Combined ceramic values of 30 µF to 100 µF are recommended,
usually made up of multiple ceramic capacitors. Select the num-
ber of ceramics and find the total ceramic capacitance (CZ).
(
)
(
)
(
)
)
1
2
2
1
RCS2
=
A × 1– B × r – B × 1– A × r – A – B
(
)
(
)
(
Next, there is an upper limit imposed on the total amount of
bulk capacitance (CX) when one considers the VID on-the-fly
voltage stepping of the output (voltage step VV in time tV with
error of VERR) and a lower limit based on meeting the critical
capacitance for load release for a given maximum load step ∆IO:
1
2
1– A
(
)
RCS1
=
1
A
–
1– RCS2 r – RCS2
1
(8)
1
RTH
=
L × ∆IO
1
1
CX (MIN )
≥
– C
Z
(12)
–
n × R ×VVID
OD
1– RCS2 RCS1
5. Calculate RTH = rTH RCS, then select the closest value of
ϫ
L
thermistor available. Also compute a scaling factor k based on
the ratio of the actual thermistor value used relative to the
computed one:
CX (
≤
×
MAX
)
n × K2 × RO2
(13)
2
VV
VVID
VVID n × K × R
VV
RTH ACTUAL
V
O
(
)
1+ t ×
×
– 1 – C
Z
k=
L
(9)
RTH CALCULATED
(
)
6. Finally, calculate values for RCS1 and RCS2 using the following:
RCS1 = RCS × k × RCS1
V
VV
ERR
(10)
where K –In
RCS2 = RCS × 1- k + k × R
(
(
)
(
)
)
CS2
For this example, RCS has been chosen to be 100 kΩ, so we start
with a thermistor value of 100 kΩ. Looking through available 0603
size thermistors, we find a Vishay NTHS0603N01N1003JR NTC
thermistor with A = 0.3602 and B = 0.09174. From these we
compute RCS1 = 0.3796, RCS2 = 0.7195 and RTH = 1.0751.
Solving for RTH yields 107.51 kΩ, so we choose 100 kΩ, mak-
ing k = 0.9302. Finally, we find RCS1 and RCS2 to be 35.3 kΩ
and 73.9 kΩ. Choosing the closest 1% resistor values yields a
choice of 35.7 kΩ and 73.2 kΩ.
To meet the conditions of these expressions and transient
response, the ESR of the bulk capacitor bank (RX) should be
less than or equal to the dynamic droop resistance, ROD. If the
C
X(MIN) is larger than CX(MAX), the system will not meet the VID
on-the-fly specification and may require the use of a smaller
inductor or more phases (and may have to increase the switch-
ing frequency to keep the output ripple the same).
For our example, a combination of MLCC capacitors (CZ = 50 µF)
was used. The VID on-the-fly step change is from 1.5 V to 0.8 V
(making VV = 700 mV) in 100 µs with a setting error of 3%.
Solving for the bulk capacitance yields
Output Offset
AMD’s specification requires that at no load, the nominal output
voltage of the regulator be offset to a higher value than the nominal
voltage corresponding to the VID code. The offset is set by a con-
stant current source flowing out of the FB pin (IFB) and flowing
through RB. The value of RB can be found using Equation 11:
600 nH × 24 A
3×1.9 mΩ ×1.5V
CX (MIN )
≥
– 50 µF = 1.63 mF
VONL – VVID
RB =
IFB
600nH × 700mV
3× 3.52 ×1.5V
CX (
≤
×
MAX
)
(11)
1.53V –1.5 V
15 µA
RB =
= 2.00kΩ
100ms ×1.5V × 3× 3.5×1.1mΩ2
The closest standard 1% resistor value is 2.00 kΩ.
1+
–1 – 50mF = 20.4mF
700mV × 600nH
COUT Selection
The required output decoupling for the regulator is typically
recommended by AMD for various processors and platforms.
One can also use some simple design guidelines to determine
what is required. These guidelines are based on having both
bulk and ceramic capacitors in the system.
where K = 3.5.
Using eight 820 µF OSCONs with a typical ESR of 12 mΩ each
yields CX = 6.56 mF with an RX = 1.5 mΩ.
One last check should be made to ensure that the ESL of the
bulk capacitors (LX) is low enough to limit the initial high fre-
quency transient spike. This is tested using
The first thing is to select the total amount of ceramic capaci-
tance, which is based on the number and type of capacitor to be
used. The best location for ceramics is inside the socket. Others
can be placed along the outer edge of the socket as well.
2
LX ≥ 2 ×CZ × ROD
LX ≥ 2 × 50mF ×1.9mW 2 = 361pH
(14)
REV. 0
–13–
ADP3166
In this example, LX is 375 pH for the eight OSCON capacitors,
which basically satisfies this limitation. If the LX of the chosen
bulk capacitor bank is too large, the number of capacitors must
be increased.
takes for the main MOSFET to turn on and off, and to the
current and voltage that are being switched. Basing the switch-
ing speed on the rise and fall time of the gate driver impedance
and MOSFET input capacitance, the following expression pro-
vides an approximate value for the switching loss per main
MOSFET, where nMF is the total number of main MOSFETs:
One should note for this multimode control technique, all-
ceramic designs can be used as long as the conditions of
Equations 12, 13, and 14 are satisfied.
VCC × IO
nMF
n
PS(MF = 2 × fSW
×
× RG
×
×CISS
(16)
Power MOSFETs
)
nMF
For this example, the N-channel power MOSFETs have been
selected for one high-side switch and two low-side switches per
phase. The main selection parameters for the power MOSFETs
are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate
Here, RG is the total gate resistance (2 Ω for the ADP3418 and
about 1 Ω for typical high speed switching MOSFETs, making
RG = 3 Ω) and CISS is the input capacitance of the main
MOSFET. It is interesting to note that adding more main
MOSFETs (nMF) does not really help the switching loss per
MOSFET since the additional gate capacitance slows down
switching. The best thing to reduce switching loss is to use
lower gate capacitance devices.
d
rive voltage (the supply voltage to the ADP3418) dictates
whether standard threshold or logic-level threshold MOSFETs
must be used. With VGATE ~10 V, logic-level threshold MOSFETs
(VGS(TH) < 2.5 V) are recommended.
The maximum output current, IO, determines the RDS(ON)
requirement for the low-side (synchronous) MOSFETs. With
the ADP3166, currents are balanced between phases, thus the
current in each low-side MOSFET is the output current divided
by the total number of MOSFETs (nSF). With conduction losses
being dominant, the following expression shows the total power
being dissipated in each synchronous MOSFET in terms of the
ripple current per phase (IR) and average total output current (IO):
The conduction loss of the main MOSFET is given by the fol-
lowing, where RDS(MF) is the on resistance of the MOSFET:
2
2
IO
1
12
n × I
nMF
PC(MF) = D ×
+
×
× RDS MF
R
(
)
(17)
n
MF
Typically, for main MOSFETs, one wants the highest speed
(low CISS) device, but these usually have higher on resistance.
One must select a device that meets the total power dissipation
(about 1.5 W for a single D-PAK) when combining the switch-
ing and conduction losses.
2
2
IO
1
12
n × I
nSF
R
PSF = 1– D ×
+
×
× RDS SF
(
)
(
)
(15)
n
SF
Knowing the maximum output current being designed for and
the maximum allowed power dissipation, one can find the required
RDS(ON) for the MOSFET. For D-PAK MOSFETs up to an
ambient temperature of 50ºC, a safe limit for PSF is 1 W to 1.5 W
at 120ºC junction temperature. Thus, for our example (56 A
maximum), we find RDS(SF) (per MOSFET) < 10 mΩ. This
For our example, we have selected an Infineon IPD12N03L as the
main MOSFET (three total; nMF = 3), with a CISS = 1460 pF (max)
and RDS(MF) = 14 mΩ (max at TJ = 120ºC) and an Infineon
IPD06N03L as the synchronous MOSFET (six total; nSF = 6),
with CISS = 2370 pF (max) and RDS(SF) = 8.4 mΩ (max at TJ = 120ºC).
The synchronous MOSFET CISS is less than 3000 pF, satisfy-
ing that requirement. Solving for the power dissipation per
MOSFET at IO = 56 A and IR = 6.6 A yields 647 mW for each
synchronous MOSFET and 1.26 W for each main MOSFET.
These numbers work well considering there is usually more
PCB area available for each main MOSFET versus each syn-
chronous MOSFET.
RDS(SF) is also at a junction temperature of about 120ºC, so we
need to make sure we account for this when making this selection.
For our example, we selected two lower-side MOSFETs at 7 mΩ
each at room temperature, which gives 8.4 mΩ at high temperature.
Another important factor for the synchronous MOSFET is the
input capacitance and the feedback capacitance. The ratio of
the feedback to input needs to be small (less than 10% is recom-
mended) to prevent accidental turn-on of the synchronous
MOSFETs when the switch node goes high.
One last thing to look at is the power dissipation in the driver
for each phase. This is best described in terms of the QG for the
MOSFETs and is given by the following, where QGMF is the
total gate charge for each main MOSFET and QGSF is the total
gate charge for each synchronous MOSFET:
Also, the time to switch off the synchronous MOSFETs should
not exceed the nonoverlap dead time of the MOSFET driver
(40 ns typical for the ADP3418). The output impedance of the
driver is about 2 Ω and the typical MOSFET input gate resistances
are about 1 Ω to 2 Ω, so a total gate capacitance of less than
6000 pF should be adhered to. Since there are two MOSFETs in
parallel, we should limit the input capacitance for each synchro-
nous MOSFET to 3000 pF.
fSW
PDRV
=
× n
(
×QGMF + nSF ×QGSF + I
×VCC
(18)
)
MF
CC
2 × n
Also shown is the standby dissipation factor (ICC ϫ VCC) for the
driver. For the ADP3418, the maximum dissipation should be
less than 400 mW. For our example, with ICC = 7 mA, QGMF
=
The high-side (main) MOSFET must be able to handle two
main power dissipation components: conduction and switching
losses. The switching loss is related to the amount of time it
22.8 nC and QGSF = 34.3 nC, we find 265 mW in each driver,
which is below the 400 mW dissipation limit. See the ADP3418
data sheet for more details.
–14–
REV. 0
ADP3166
For values of RLIM greater than 500 kΩ, the current limit may be
lower than expected, so some adjustment of RLIM may be needed.
Here, ILIM is the average current limit for the output of the sup-
ply. For our example, choosing 75 A for ILIM, we find RLIM to be
378 kΩ, for which we choose 374 kΩ as the nearest 1% value.
The per phase current limit described earlier has its limit deter-
mined by the following:
Ramp Resistor Selection
The ramp resistor (RR) is used for setting the size of the internal
PWM ramp. The value of this resistor is chosen to provide the
best combination of thermal balance, stability, and transient
response. The following expression is used for determining the
optimum value:
AR × L
RR =
VCOMP(MAX) –VR –VBIAS IR
3 × AD × RDS ×CR
IPHLIM
≅
–
(23)
AD × RDS(MAX)
2
(19)
0.2 ×600nH
3 × 5 × 4.2mW × 5pF
RR =
= 381kΩ
For the ADP3166, the maximum COMP voltage (VCOMP(MAX))
is 3.3 V, the COMP pin bias voltage (VBIAS) is 1.2 V, and the
current balancing amplifier gain (AD) is 5. Using VR of 0.48 V,
and RDS(MAX) of 4.2 mΩ (low-side on resistance at 150°C), we
find a per phase limit of 74 A.
where AR is the internal ramp amplifier gain, AD is the current
balancing amplifier gain, RDS is the total low-side MOSFET on
resistance, and CR is the internal ramp capacitor value. The
closest standard 1% resistor value is 383 kΩ.
This limit can be adjusted by changing the ramp voltage VR. But
make sure not to set the per phase limit lower than the average
per phase current (ILIM/n).
The internal ramp voltage magnitude can be calculated using
A × 1– D ×V
RR ×CR × fSW
There is also a per phase initial duty cycle limit determined by:
(
)
R
VID
VR =
VR =
VCOMP MAX –VBIAS
(
)
(20)
0.2 × 1– 0.125 ×1.5 V
DMAX = D ×
(
)
(24)
= 0.41 V
VRT
383kΩ × 5 pF × 330kHz
For this example, the maximum duty cycle is found to be 0.55.
The size of the internal ramp can be made larger or smaller. If it
is made larger, stability and transient response will improve, but
thermal balance will degrade. Conversely, if the ramp is made
smaller, thermal balance will improve at the sacrifice of transient
response and stability. The factor of three in the denominator of
Equation 19 sets a ramp size that gives an optimal balance for
good stability, transient response, and thermal balance.
Feedback Loop Compensation Design
Optimized compensation of the ADP3166 allows the best pos-
sible response of the regulator’s output to a load change. The
basis for determining the optimum compensation is to make the
regulator and output decoupling appear as an output impedance
that is optimized over the widest possible frequency range,
including dc, and equal to the droop resistances (RO and
ROD). With the output impedance, the output voltage will respond
in proportion with the load current; this ensures the optimal
output positioning and allows the minimization of the output
decoupling.
COMP Pin Ramp
There is a ramp signal on the COMP pin due to the droop
voltage and output voltage ramps. This ramp amplitude adds to
the internal ramp to produce the following overall ramp signal
at the PWM input.
With the multimode feedback structure of the ADP3166, one
needs to set the feedback compensation to make the converter’s
output impedance work in parallel with the output decoupling to
meet this goal. There are several poles and zeros created by the
output inductor and decoupling capacitors (output filter) that
need to be compensated for.
VR
VRT
=
R + R
× 1– nD
(
)
(
)
O
OD
(21)
1–
n × fSW × CX × RO × ROD
For this example, the overall ramp signal is found to be 0.48 V.
Current Limit Set Point
To select the current limit set point, we need to find the resistor
value for RLIM. The current limit threshold for the ADP3166 is
set with a 3 V source (VLIM) across RLIM with a gain of 10.4 mV/µA
(ALIM). RLIM can be found using the following:
ALIM ×VLIM
ILIM × RO
RLIM
=
(22)
REV. 0
–15–
ADP3166
The first step is to compute the time constants for all of the poles and zeros in the system:
R + R
× L × 1– n × D ×V
RL ×VR
VVID
(
+
)
(
)
O
OD
RT
T
Re = n × ROD + AD × RDS
+
n × CX × RO × ROD ×VVID
1.1mΩ+1.9 mΩ ×600 nH × 1– 0.375 × 0.48V
1.6 mΩ × 0.48 V
1.5 V
(
)
(
)
Re = 3×1.9 mΩ + 5× 4.2 mΩ +
Re = 36.0 mΩ
+
(25)
3×6.56 mF ×1.1mΩ ×1.9 mΩ ×1.5V
'
LX
ROD
ROD – R
'
Ta = CX × R
– R
+
×
(
)
OD
RX
375 pH 1.9 mΩ– 0.6 mΩ
T = 6.56 mF × 1.9 mΩ– 0.6 mΩ +
×
(
)
a
1.5 mΩ
1.5 mΩ
(26)
(27)
Ta = 8.70 µs
Tb = RX + R' – ROD × CX
(
)
T = 1.5 mΩ+ 0.6 mΩ –1.9 mΩ ×6.56 mF =1.31µs
(
)
b
AD × R
2 × fSW
DS
VRT × L –
Tc =
Tc =
VVID × Re
5× 4.2 mΩ
2× 330kHz
(28)
0.48V × 600nH –
= 5.05µs
1.5 V × 36.0 mΩ
2
CX ×CZ × ROD
Td =
Td =
CX × R – R +C × ROD
(
)
O
Z
6.56mF × 50mF ×1.9 mΩ2
= 137 ns
6.56 mF × 1.9 mΩ – 0.6 mΩ + 50 mF ×1.9 mΩ
(
)
(29)
(33)
where, for the ADP3166, R' is the PCB resistance from the bulk
capacitors to the ceramics and where RDS is the total low-side
MOSFET on resistance per phase. For this example, AD is 5, VRT
equals 0.48 V, R' is approximately 0.6 mΩ (assuming a 4-layer
motherboard), and LX is 375 pH for the eight OSCON capacitors.
Td
137ns
CFB
=
=
= 18.7 pF
RA 7.33kΩ
Choosing the closest standard values for these components yields:
CA = 680 pF, RA = 7.32 kΩ, CB = 680 pF, and CFB = 18 pF.
A type-three compensator on the voltage feedback is adequate for
proper compensation of the output filter. The expressions that
follow are intended to yield an optimal starting point for the design;
some adjustments may be necessary to account for PCB and com-
ponent parasitic effects (see the Tuning Procedure section).
Figure 3 shows the typical transient response using the compen-
sation values.
CIN Selection and Input Current di/dt Reduction
In continuous inductor-current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to n ϫ VOUT/VIN and an amplitude one-nth of the
maximum output current. To prevent large voltage transients, a
low ESR input capacitor sized for the maximum rms current
must be used. The maximum rms capacitor current is given by
The compensation values can then be solved using the following:
n × ROD ×Ta
CA =
Re × RB
(30)
(31)
(32)
3×1.9mΩ × 8.70µs
36.0mΩ × 2.00kΩ
CA =
= 689 pF
1
ICRMS = D × IO
×
– 1
n × D
Tb
1.31µs
(34)
CB
CB
=
=
=
= 655 pF
1
ICRMS = 0.125 × 56A ×
– 1 = 9.05A
RB 2.00kΩ
3 × .125
Note that the capacitor manufacturer’s ripple current ratings are
often based on only 2,000 hours of life. This makes it advisable
Tb
1.31µs
=
= 655 pF
RB 2.00kΩ
–16–
REV. 0
ADP3166
AC Loadline Setting
to further derate the capacitor, or to choose a capacitor rated at
a higher temperature than required. Several capacitors may be
placed in parallel to meet size or height requirements in the
design. In this example, the input capacitor bank is formed by
three 2200 µF, 16 V Nichicon capacitors with a ripple current
rating of 3.5 A each.
11. Remove the dc load from the circuit and hook up the
dynamic load.
12. Hook up the scope to the output voltage and set it to dc
coupling with the time scale at 100 µs/div.
13. Set the dynamic load for a transient step of about 24 A at 1
kHz with 50% duty cycle.
To reduce the input-current di/dt to below the recommended
maximum of 0.1 A/µs, an additional small inductor (L > 1 µH
@ 15 A) should be inserted between the converter and the sup-
ply bus. That inductor also acts as a filter between the converter
and the primary power source.
14. Measure the output waveform (it might be necessary to
use a dc offset on scope to see the waveform). Try to use a
vertical scale of 100 mV/div or finer.
15. The waveform should look something like Figure 3. Use
the horizontal cursors to measure VACDRP and VDCDRP
as shown. DO NOT MEASURE THE UNDERSHOOT
OR OVERSHOOT THAT HAPPENS IMMEDI-
ATELY AFTER THE STEP.
V
–VFLCOLD
–VFLHOT
(
)
NL
NL
RCS2 NEW = RCS2 OLD
×
(35)
(
)
(
)
V
(
)
TUNING PROCEDURE FOR ADP3166
1.
Build a circuit based on compensation values computed
from the design spreadsheet.
2.
Hook up the dc load to the circuit, turn it on, and verify its
operation. Also check for jitter at no load and full load.
DC Loadline Setting
3.
Measure the output voltage at no load (VNL). Verify that
it is within tolerance.
V
ACDRP
V
DCDRP
4.
Measure the output voltage at full load cold (VFLCOLD). Let
the board set for a ~10 minutes at full load and measure
output (VFLHOT). If there is a change of more than a few
millivolts, adjust RCS1 and RCS2 using Equations 35 and 37.
5.
6.
Repeat Step 4 until the cold and hot voltage measurements
remain the same.
Figure 3. AC Loadline Waveform
Measure the output voltage from no load to full load using 5
A steps. Compute the loadline slope for each change and
then average them to get the overall loadline slope (ROMEAS).
16. If the VACDRP and VDCDRP are different by more than a few
millivolts, use the following to adjust CCS. It might be
necessary to parallel different values to get the right one
since there are limited standard capacitor values available.
(It is a good idea to have locations for two capacitors in
the layout for this.)
7.
If ROMEAS is off by more than 0.05 mΩ from RO, use Equa-
tion 36 to adjust the RPH values:
) ROMEAS
RPH NEW = RPH OLD
(36)
(
)
(
RO
17. Repeat Steps 11 to 13 and repeat adjustments if neces-
sary. Once complete, do not change CCS for the rest of
the procedure.
8.
9.
Repeat Steps 6 and 7 to check the loadline and repeat the
adjustments if necessary.
Once finished with dc loadline adjustment, do not change
18. Set the dynamic load step to maximum step size (do not
use a step size larger than needed), and verify that the
output waveform is square (meaning VACDRP and VDCDRP
are equal).
RPH, RCS1, RCS2, or RTH for the rest of the procedure.
10. Measure the output ripple at no load and at full load with
a scope and make sure that it is within spec.
1
RCS2 NEW
=
)
(
RCS1 OLD) +R
TH 25o C
(
1
(
)
–
(37)
) RTH 25o C
RCS1 OLD) × R
+ R
(
– RCS2 NEW × R
) – R
(
)
TH 25oC
TH 25o C
)
CS2 OLD
CS1 OLD
(
(
)
(
)
(
(
)
(
VACDRP
CCS NEW = CCS OLD
(38)
(
)
(
) VDCDRP
REV. 0
–17–
ADP3166
SWITCH NODE
PLANES
Initial Transient Setting
12V CONNECTOR
INPUT POWER PLANE
19. With dynamic load still set at maximum step size, expand
scope time scale to see 2 µs/div to 5 µs/div. The waveform
may have two overshoots and one minor undershoot (see
Figure 5). Here, VDROOP is the final desired static value.
THERMISTOR
V
DROOP
KEEP-OUT
AREA
OUTPUT
POWER
PLANE
KEEP-OUT
AREA
KEEP-OUT
AREA
V
TRAN1
V
TRAN2
CPU
SOCKET
KEEP-OUT
AREA
Figure 4. Transient Setting Waveform
20. If the overshoots are larger than desired, try making the
following adjustments in this order (Note: if these adjust-
ments do not change the response, you are limited by the
output decoupling). Check the output response each time
a change is made as well as the switching nodes (to make
sure it is still stable).
Figure 6. Layout Recommendations
General Recommendations
•
For good results, at least a four-layer PCB is recommended.
This should allow the needed versatility for control circuitry
interconnections with optimal placement, power planes for
ground, input and output power, and wide interconnection
traces in the rest of the power delivery current paths. Keep
in mind that each square unit of 1 ounce copper trace has a
resistance of ~0.53 mΩ at room temperature.
a. Make the ramp resistor larger by 25% (RRAMP).
b. For VTRAN1, increase CB or switching frequency.
c. For VTRAN2, increase RA and decrease CA by 25%.
•
•
Whenever high currents must be routed between PCB lay-
ers, vias should be used liberally to create several parallel
current paths so that the resistance and inductance intro-
duced by these current paths is minimized and the via current
rating is not exceeded.
V
TRANREL
V
DROOP
If critical signal lines (including the output voltage sense
lines of the ADP3166) must cross through power circuitry,
it is best if a signal ground plane can be interposed between
those signal lines and the traces of the power circuitry. This
serves as a shield to minimize noise injection into the signals
at the expense of making signal ground a bit noisier.
•
An analog ground plane should be used around and under
the ADP3166 for referencing the components associated
with the controller. This plane should be tied to the nearest
output decoupling capacitor ground and should not be tied
to any other power circuitry to prevent power currents from
flowing in it.
Figure 5. Transient Setting Waveform
21. For load release (see Figure 5), if VTRANREL is larger
than VTRAN1 (refer to Figure 4), there is not enough
output capacitance. Either more capacitance is needed or
it is necessary to make the inductor values smaller (if
inductors are changed, it is necessary to start design over
using the spreadsheet and this tuning guide).
•
•
•
The components around the ADP3166 should be located
close to the controller with short traces. The most important
traces to keep short and away from other traces are the FB
and CSSUM pins. Refer to Figure 6 for more details on
layout for the CSSUM node.
LAYOUT AND COMPONENT PLACEMENT
The following guidelines are recommended for optimal performance
of a switching regulator in a PC system. Key layout issues are
illustrated in Figure 6.
The output capacitors should be connected as close as
possible to the load (or connector) that receives the power
(e.g., a microprocessor core). If the load is distributed, the
capacitors should also be distributed, and generally in pro-
portion to where the load tends to be more dynamic.
Avoid crossing any signal lines over the switching power
path loop, described below.
–18–
REV. 0
ADP3166
Power Circuitry
•
The switching power path should be routed on the PCB to
encompass the shortest possible length to minimize radiated
switching noise energy (i.e., EMI) and conduction losses in
the board. Failure to take proper precautions often results in
EMI problems for the entire PC system as well as noise-
related operational problems in the power converter control
circuitry. The switching power path is the loop formed by
the current path through the input capacitors and the power
MOSFETs including all interconnecting PCB traces and
planes. The use of short and wide interconnection traces is
especially critical in this path for two reasons: it minimizes
the inductance in the switching loop, which can cause high
energy ringing, and it accommodates the high current
demand with minimal voltage loss.
•
Whenever a power dissipating component (e.g., a power
MOSFET) is soldered to a PCB, the liberal use of vias, both
directly on the mounting pad and immediately surrounding
it, is recommended. Two important reasons for this are
improved current rating through the vias, and improved
thermal performance from vias extended to the opposite side
of the PCB where a plane can more readily transfer the heat
to the air. Make a mirror image of any pad being used to
heatsink the MOSFETs on the opposite side of the PCB to
achieve the best thermal dissipation to the air around the
board. To further improve thermal performance, the largest
possible pad area should be used.
•
•
The output power path should also be routed to encompass
a short distance. The output power path is formed by the
current path through the inductor, the output capacitors,
and the load.
For best EMI containment, a solid power ground plane
should be used as one of the inner layers extending fully
under all the power components.
Signal Circuitry
•
The output voltage is sensed and regulated between the
FB pin and the FBRTN pin, which connects to the signal
ground at the load. To avoid differential mode noise pickup
in the sensed signal, the loop area should be small. Therefore
the FB and FBRTN traces should be routed adjacent to each
other on top of the power ground plane back to the controller.
•
The feedback traces from the switch nodes should be con-
nected as close as possible to the inductor. The CSREF
signal should be connected to the output voltage at the
inductor nearest to the controller.
REV. 0
–19–
ADP3166
OUTLINE DIMENSIONS
28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
9.80
9.70
9.60
28
15
14
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20
MAX
0.15
0.05
0.75
0.60
0.45
8؇
0؇
0.30
0.19
0.20
0.09
COPLANARITY
0.10
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153AE
–20–
REV. 0
相关型号：
ADP3166JRUZ-REEL
IC SWITCHING CONTROLLER, 4000 kHz SWITCHING FREQ-MAX, PDSO28, TSSOP-28, Switching Regulator or Controller
ADI
ADP3167
ADP3160/ADP3167: 5-Bit Programmable 2-Phase Synchronous Buck Controller Data Sheet (Rev. B. 5/02)
ETC
ADP3167JR-REEL
IC DUAL SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, PDSO16, SOIC-16, Switching Regulator or Controller
ADI
©2020 ICPDF网 联系我们和版权申明