ADP3088ARM-REEL7 [ADI]
1 MHz, 750 mA Buck Regulator; 1兆赫， 750毫安降压稳压器
| 型号： | ADP3088ARM-REEL7 |
| 厂家： | 
ADI |
| 描述： | 1 MHz, 750 mA Buck Regulator |
| 文件： | 总16页 (文件大小：759K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
1 MHz, 750 mA Buck Regulator
ADP3088
FUNCTIONALBLOCKDIAGRAM
FEATURES
1 MHz PWM Frequency
Automatic PWM to Power Saving Mode at Light Load
Fully Integrated 1 A Power Switch
3% Output Regulation Accuracy over Temperature,
Line, and Load
100% Duty Cycle Operation
Simple Compensation
SW
IN
IN
CURRENT
SENSE
AMP
DRV
PWM
COMPATOR
1MHz
S
Q
R
Output Voltage: 1.25 V to 10.5 V
Small Inductor and MLC Capacitors
Low Quiescent Current while Pulse Skipping
Thermal Shutdown
ROTEC
UN/STOP
OMPARATORS
LOGIC
(ILIM, OT)
Fully Integrated Soft Start
Cycle-by-Cycle Current Limit
RROR
P
FB
g
COMP
GND
m
APPLICATIONS
SOFT START
TIMER
REF
1.245V
+
PDAs and Palmtop Computers
Notebook Computers
PCMCIA Cards
GN
ADP3088
Bus Products
Portable Instruments
GENERALDESCRIPTION
ADP3088
3.3ꢀH
V
IN
V
1.8V
SW
DRV
GND
IN
OUT
The ADP3088 is a high frequency, nonsynchronous
down dc-to-dc regulator with an integrated 1 A pow
in a space-saving MSOP-8 package. It providehigh eff
and excellent dynamic response and is verimple to use.
3.3V
0.1ꢀF
10ꢀF
IN
10.0kꢁ
1N5817
GND
COMP
10ꢀF
FB
The ADP3088’s 1 MHz switching freqncy ws r small,
inexpensive external components, and the current modcontrol
loop is simple to compensate and noise filtering. he device
operates in PWM current modeavy loads and saves
energy at lighter loads by swally into power
saving mode. Soft start is intetely on-chip, as is
the cycle-by-cycle current limit.
22.4kꢁ
4.7pF
220pF
20kꢁ
Figure 1. Typical Application
Capable of operatV to 1input, the ADP3088 is
ideal for many ading portable, battery-powered
applications whe-use power regulation is
required. Supportoltages down to 1.25 V, the
ADP3088 is ideal for ating low voltage rails, providing
the optimal solution in its class for delivering power efficiently,
responsively, and simply with a minimal printed circuit board area.
The device is specified over the industrial temperature range of
–40∞C to +85∞C.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
ADP3088–SPECIFICATIONS1 (VIN = 3.3 V, TA = –40ꢂC to +85ꢂC, unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SUPPLY
Input Voltage Range
Ground Current, Operating
VIN
IGND
DRV = GND
VIN = 10 V, IL = 500 mA,
DRV = GND
DRV = 2 V
No Load
VCOMP = 0 V
2.5
11
V
2
6
mA
mA
mA
mA
∞C
2.5
150
15
3.6
250
40
Quiescent Current, Operating
Shutdown
Thermal Shutdown Threshold
IQ
ISD
TSD
160
OSCILLATOR
Oscillator Frequency
Minimum Sleep Duty Cycle
Maximum Duty Cycle
Wake-Up Hysteresis
fSW
0.75
1
14
1.25
40
MHz
%
%
DPSM
DMAX
VHYST
IL = 500 mA
100
20
FB Voltage Drops below VREF
mV
OUTPUT SWITCH
Switch-On Voltage
3
VIO
IL = 500 mA, FB = GND, and
DRV = GND
0.25
0
1.4
V
Current Limit Threshold
Leakage Current
ILIM
1.0
1.2
5
A
mA
VIN = 12 V
ERROR AMPLIFIER
Reference Voltage Accuracy
Reference Voltage Line
Regulation
Feedback Input Bias Current
Sink/Source Current
Short Circuit Current
VREF
FB = COMP
FB = COMP,
VIN = 3 V to 12 V
Soft Start Exed
1.222
1.245
0.02
1.265
V
%/V
IFB
ICOMP
ICOMP
–50
35
+1
60
20
+50
85
40
nA
mA
mA
,
VCOMP = 0 V, Acting
Shu
SD
Transconductance
gm, EA
FB
480
mA/V
MODULATOR
Transconductance
Control Offset Voltage
Soft Start Time
Shutdown Threshold Voltage
Slope Compensation
gm, MOD
VCOM
1
0.90
250
A/V
V
ms
mV
A/ms
VPWM
tSS
,
OS
600
750
VCOMP
m
,
340
SD
Effively Summed to ISW
0.7
NOTES
1All limits at temperature extremes are gon using standard Statistical Quality Control (SQC).
2For higher efficiency operation, tie the DRor IL < 250 mA and VIN > 3 V.
3VIN – VSW includes voltage drop across intern.
Specifications subject to changtice.
–2–
REV. C
ADP3088
ABSOLUTEMAXIMUMRATINGS
*
PINCONFIGURATION
Input Supply Voltage . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V
Voltage on Any Pin with Respect to GND . . . –0.3 V to +12 V
(Voltage on Any Pin May Not Exceed VIN)
Operating Ambient Temperature Range . . . . –40∞C to +85∞C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . 125∞C
1
2
3
4
8
7
6
5
SW
IN
IN
DRV
GND
FB
ADP3088
TOP VIEW
(Not to Scale)
GND
COMP
q
q
JA (4-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . . . . 116∞C/W
JA (2-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . . . . 159∞C/W
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300∞C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215∞C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability. Only one absolute maximum
rating may be applied at any one time.
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1, 2
IN
PoweSupply Input. Both pins must
be nnected.
3, 6
4
GND
roundoth pins must be
ned.
COMP
Feedck Lp Compensation and
Shutdonput. An open drain or
collector used to pull the pin to
round will shut down the device.
ORDERING GUIDE
Temperature
Range
Package
Option
5
7
8
FB
Feedback Voltage Sense Input. This
pin senses the voltage via an external
resistor divider.
Model
Branding
ADP3088ARM-REEL –40∞C to +85∞C MSOP-8 P0A
ADP3088ARM-REEL7 –40∞C to +85∞C MSOP-8 P0A
RV
SW
This pin provides a separate path for
the drive current to be connected to
ground.
Switching Output.
CAUTION
ESD (electrostatic discharge) sensitive device. Electres as high as 4000 V readily
accumulate on the human body and test equient and can de without detection. Although the
ADP3088 features proprietary ESD proteion cir, permanent damage may occur on devices
subjected to high energy electrostatic dischaerefoproper ESD precautions are recommended
to avoid performance degradation or loss of functionali
–3–
REV. C
ADP3088–Typical Performance Characteristics
100
200.00
V
= 3.3V
OUT
90
80
180.00
70
V
= 2.5V
OUT
60
50
40
30
20
160.00
140.00
120.00
V
= 1.5V
OUT
V
= 5V, C = C
= 10ꢀF, L = 10ꢀH
OUT
IN
IN
T
= 25ꢂC
A
10
0
100.00
0
100
200
300
400
500
–40
–15
10
35
60
85
LOAD CURRENT (mA)
TEMATURE
TPC 1. Efficiency vs. Load Current and Output Voltage
TPC 4. Standby Quiecent Cnt vs. mperature
100
5.00
V
= 5V
OUT
90
80
4.00
70
60
V
= 3.3V
OUT
I
mA
LO
V
= 2.5V
3.00
2.
1.00
50
40
30
20
10
0
OUT
V
= 2V
DRV
V
= 1.5V
OUT
V
= 10V, C = C
= 10ꢀF, L = 10ꢀH
OUT
IN
IN
T
= 25ꢂC
A
0
100
200
300
500
–40
–15
10
35
60
85
TEMPERATURE (ꢂC)
LOAD CURRENT (mA)
TPC 2. Efficiency vs. Load Current and OVolta
TPC 5. Ground Current vs. Temperature
100
1.2438
I
1.2433
1.2428
1.2423
1.2418
10
V
= 1.5V, C = C
ꢀF, DRV = GND
OUT
IN
OUT
T
= 25ꢂC
1
A
I
= 0mA
8
L
0
0
2
4
6
10
12
–40
–15
10
35
60
85
INPUT VOLTAGE (V)
TEMPERATURE (ꢂC)
TPC 3. Quiescent Current vs. Input Voltage
TPC 6. Feedback Voltage vs. Temperature
–4–
REV. C
ADP3088
1.515
1.505
1.495
1.485
20.00
18.00
16.00
14.00
V
= 5V, C = C
= 10ꢀF, L = 10ꢀH
OUT
IN
IN
T
= 25ꢂC
A
12.00
10.00
0
100
200
300
400
500
–40
–15
0
5
60
85
OUTPUT CURRENT (mA)
MPERARE (ꢂC)
TPC 7. Load Regulation
TPC 10. Shutdon Suppurrens. Temperature
0.300
280
1.10
1.05
1.00
0.95
0.90
0.260
= 500mA
D
0.240
0.220
0.200
–40
–15
10
35
60
85
–40
–15
10
35
TEMPERATURE (ꢂC)
TEMPERATURE (ꢂC
TPC 8. Oscillator Frequency vs. peratu
TPC 11. Switch-Sense Resistor Voltage vs. Temperature
1.000
T
= 25ꢂC
A
1.20
1.15
1.10
1.05
1.00
0.900
0.800
0.700
0.600
0.500
0.400
V
= 12V
IN
V
= 5V
IN
0.300
0.200
0.100
V
= 3.3V
IN
V
= 2.5V
IN
0.00
0.25
0.50
OUTPUT CURRENT (A)
0.75
1.00
–40
–15
10
35
60
85
TEMPERATURE (ꢂC)
TPC 12. Switch Saturation Voltage vs. Load
Current and Input Voltage
TPC 9. Current Limit vs. Temperature
–5–
REV. C
ADP3088
CH 1: INPUT VOLTAGE, 2V/DIV
CH 1: INPUT VOLTAGE, 10mv/DIV,
AC-COUPLED
CH 2: OUTPUT VOLTAGE, 500mV/DIV
V
= 5V, V
= 1.5V, LOAD CURRENT = 0mA,
V
= 5V, V
= 1.5V, LOAD CURRENT = 500mA,
= 10ꢀF, L = 10ꢀH
IN
OUT
= 10ꢀF, L = 10ꢀH
IN
OUT
C
T
= C
C
T
= C
IN
OUT
IN
OUT
= 25ꢂC
= 25ꢂC
A
A
TPC 13. Start-Up Waveform
TPC 1. VOple
CH 1: INPUT VOLTAGE, 2V/DIV
CH 2: OUTPUT VOLTAGE, 500mV/DIV
V
= 5V, V
= 1.5V, LOAD CURRENT = 500mA,
IN
OUT
C
= C
= 10ꢀF, L = 10ꢀH
IN
OUT
T
= 25ꢂC
A
T
= 25ꢂC
A
V
= 5V, V
= 1.5V, LOAD CURRENT = 10mA,C = C
IN
= 10ꢀF, L = 10ꢀH
OUT
IN
OUT
TPC 14. Start-Up Wavefor
TPC 17. Power-Saving Mode Waveforms*
CH 1: INPUT VOL
CH 2: OUTPUT VOLTAGE
500mV/DIV
V
C
= 2.5V, V
= 1.25V, LOAD CURRENT = 250mA,
IN
OUT
T
= 25ꢂC
V
= 5V, V
= 1.5V, LOAD CURRENT= 25mA,
OUT
A
IN
= C
= 10ꢀF, L = 10ꢀH, T = 25ꢂC
IN
OUT A
C
= C
= 10ꢀF, L = 10ꢀH
OUT
IN
TPC 15. Start-Up Waveform
TPC 18. Steady-State Waveforms*
*NOTES FOR TPCs 17 AND 18
CH 1: Output Voltage, 20mV/DIV, AC-Coupled
CH 2: Switch Node Voltage, 2V/DIV
CH 3: Inductor Current, 100mA/DIV
–6–
REV. C
ADP3088
CH 1: LOAD CURRENT STEP, 167mA/DIV
CH 2: OUTPUT VOLTAGE, 100mV/DIV
V
= 5V, V
= 1.5V, LOAD CURRENT = 100mA,
IN
OUT
25ꢂC, C = C
V
= 5V, V
OUT
= 1.5V, LOAD CRENT = 50mA TO 550mA TO 50mA,
0ꢀF, L = 10ꢀH
IN
T
=
= 10ꢀF, L = 10ꢀH
OUT
A
IN
T
= 25ꢂC, C = 10ꢀF, C
A
IN
OU
TPC 19. Steady-State Waveforms*
TPC 2Load Tsient esponse
CINVOLTAGE, 2V/DIV
CH 1: LOAD CURRENT STEP, 167mA/DIV
CH 2: OUTPUT VOLTAGE, 100mV/DIV
H 2: OUTPUT VOLTAGE, 20mV/DIV
V
= 5V, V
OUT
= 1.5V, LOAD CURRENT = 50mA TO 550mA
= 10ꢀF, C = 20ꢀF, L = 10ꢀH
V
= 3V TO 5V, V
= 1.5V, LOAD CURRENT = 500mA,
= 10ꢀF, L = 10ꢀH
OUT
IN
IN
OUT
T
= 25ꢂC, C
A
IN
OUT
T
= 25ꢂC, C = 10ꢀF, C
A
IN
TPC 20. Load Transient spo
TPC 23. Line Transient Response
CH 1: LOAD CURRE
CH 2AGE, 100mV/DIV
V
C
= 5V, V
= 1.5V, LOAD CURRENT = 550mA TO 50mA,
= 10ꢀF, L = 10ꢀH
IN
OUT
= C
OUT
IN
= 25ꢂC
T
A
TPC 21. Load Transient Response
*NOTES FOR TPC 19
CH 1: Output Voltage, 20mV/DIV, AC-Coupled
CH 2: Switch Node Voltage, 2V/DIV
CH 3: Inductor Current, 100mA/DIV
–7–
REV. C
ADP3088
THEORYOFOPERATION
The ADP3088 is a fixed frequency buck switching regulator in
an MSOP-8 package using an external Schottky rectifier. It
features an integrated 1 A power switch and switches at 1 MHz.
The ADP3088 uses PWM operation and incorporates soft start
for controlled start-up sequence and overtemperature switch
protection. The ADP3088 draws low current while running
in power saving mode and even lower current in shutdown.
The current limit protection overrides the PWM comparator; if
this occurs, then the switch pulse will be terminated and the soft
start mode will be reset.
Current Sense Amplifier
The voltage on the internal current sense resistor is sensed and
passed to the ramp input of the PWM comparator. This current
sense signal is also passed to the current limit comparator for
peak current limit shutdown. At the current limit, the soft start
capacitor is reset and soft start is reinitiated. The current limit is
nominally 1.2 A. Slope compensation is added to the ADP3088
to stabilize the loop. A generated ramped signal is summed with
the current sense signal to provide spe compensation. Slope
compensation is needed to close e inner oop so subharmonic
oscillation is avoided. The ramreseith each clock cycle so
that the ADP3088 is capabof tr0% dutycle.
The system shown in the Functional Block Diagram is config-
ured for a 1.8 V output using a 10 mH inductor. At the beginning
of a cycle, the 1 MHz oscillator enables an SR latch, enabling the
internal 1 A power switch. The current sense amplifier and the
protection logic block monitor the current flowing between the
IN and SW pins. The switch is turned off when the current
reaches a level determined by the protection logic block or
PWM comparator, whichever is lower. The error amplifier
measures the output voltage through an external resistor divider
tied to the FB pin. This amplifier servos the switch current to
regulate the FB pin voltage to 1.245 V. An internal regulator
provides power to the control circuitry. The COMP pin can be
used to shut down the ADP3088. When pulled low, it turns off
the internal regulator, thus biasing down the chip, reducing the
input current, and disconnecting the output from the input.
Antisaturation circuitry is used to drive the switch to the edge of
saturation. This allows the driver to quickly switch at 1 MHz
and maintain good efficiency. For improved efficiency, the DRV
pin may be connected to the output provided that the input
voltage is at least 1 V greater than the output.
Run/Stop Comparator
This block creates th1 Mz signal sent o the SR latch that is
used for the switching frequey. It also takes the FB voltage
and decides whn to go into waup mode from power saving
mode. The cision to induce the power saving mode is based
on the duatio. ring steady-state continuous operation, the
duty ratio of M buck egulator is simply a function of the
input/output voge ra, with second-order effects including
the voltage drop ointernal switch and the external diode.
ce the load drops to a certain point, discontinuous operation
occ, and thduty ratio begins to modulate to maintain
regulan. Ithe ADP3088, the regulator goes to sleep when
integed duty ratio measurements drop to less than half of
minimum expected integrated duty ratio. The minimum
cted duty ratio occurs at the maximum input voltage and
minimum output voltage in continuous mode operation.
If the output load increases, the error amplifier will dete
lower voltage on the FB pin via the resistor divider on the
and send a signal to the PWM comparator to increase the on
of the switch. This in effect increases the duty cycle d prov
more current to drive the increased load durithe transient
event until a new operating point is establishe
PWM Comparator
The PWM comparator looks at the signal from the current
sense amplifier and the error amplifier to determine the correct
switch-on time to regulate the output voltage under a given load.
Reference
The ADP3088 incorporates an internd gap referee,
including curvature correction for ay low temperature
coefficient. The reference can be nding the
COMP pin, which also turns off the t of the chip.
Soft Start Timer
The soft start will prevent saturating the inductor, which could
cause uncontrolled overshoot of the output voltage and electrical
stress to the system at startup. When first powered up, an internal
soft start capacitor is discharged and the soft start circuitry
provides a gradually decaying offset to the error amplifier to
prevent it from saturating and from commanding the maximum
switch current to charge the output capacitor. The output
voltage approaches the final regulation voltage with a smooth
exponential decay. This will reduce electrical stress to the system.
Error Amplifier
The error amplifier prol volte to the PWM stage
to set the peak inductets the output current of
the regulator. It is a gat its output is a current to
the COMP pin.
Protection Logic
The protection logic block provides current limit and
overtemperature protection. The overtemperature protection is
enabled when the temperature of the chip exceeds a specified
preset temperature; the switch will be disabled until the tempera-
ture drops below a specified level, then normal operation will
resume. The thermal shutdown only stops switching, but it does
not put the chip into power saving mode, nor does it reinitiate soft
start. As the chip cools slightly, it will rapidly cycle in and out of
thermal shutdown, maintaining the die temperature at 160∞C but
allowing the output voltage and current to swing up and down.
Output
The output stage contains the bipolar power switch and the
circuits necessary to switch it on and off quickly. The pass
switch is driven to the edge of saturation, and the result is a fast
switching response and low switch resistance. For improved
efficiency, the DRV pin may be connected to the output, provided
that the input voltage is at least 1 V higher than the output.
This will send the current needed to drive the bipolar switch to
the output load instead of routing it to ground. For some VIN
and ILOAD configurations, the DRV pin must be grounded for
reliable operation.
–8–
REV. C
ADP3088
APPLICATIONINFORMATION
Output Voltage Setting
junction to case or ambient, as desired, to determine the internal
temperature rise.
In its standard usage, the output voltage of the ADP3088 is
programmed to a desired fixed value by a resistor divider from
the output voltage into the feedback node, the FB pin, at which
node the control loop ensures regulation at the reference level,
If the input voltage were so much higher than the output voltage
that it required an average duty ratio less than an internally
preset threshold, then power savings mode (PSM)—which is
characterized by periodic shutdown and wake-up of the device
that reduces average quiescent current—would be active for all
load conditions rather than only at lighter loads, for which it is
intended. PSM operation is characterized by low frequency
ripple on the output that appears similar to the behavior of a
hysteretic regulator. This is usually not a factor for consider-
ation and may be ignored if PSM operation is acceptable for all
load conditions. But in case it irelevant, the following recom-
mendation is offered:
V
REF. The divider should be designed to satisfy the formula
Ê
Ë
ˆ
RA
RB
VOUT = VREF ¥ 1+
Á
˜
¯
(1)
where RA is the upper divider resistor (between the output and FB)
and RB is the lower one (between FB and ground). RA and RB
are recommended to have values in the range of 2 kW~200 kW and
are likely to require a 1% tolerance or better to attain acceptable
output voltage tolerance.
VO +VF
V
IN
<
(3)
In less conventional applications described separately, the resistor
feedback configuration can be modified or tapped with other
resistors to affect current flow into the FB node that, in turn,
influences the output voltage. Even a switched voltage can be
summed into the FB node as long as it is sufficiently integrated
and does not intolerably compromise the transient response. This
latter application is considered further below, for an application for
powering a DSP.
D
PSM(MA
It is not possible o pret the duty raio from tending toward
zero in nonsynchronous bk converters below a certain minimum
load currelevel called “borline current” or “critical current”
for the ower cnverter. That corresponds to the inductor
ripple rrent aching zero at its bottom peak, sometimes called
the “vallrrent.” ISM activation strains the lower regulation
limit due to e hyretic ripple, the output voltage can be offset
slightly upwary readjusting the nominal voltage setpoint with
the resistor divider.
Input Voltage, Power Dissipation Considerations, and
Power Savings Mode
The input voltage range is not typically considered a critical
parameter for electrical functionality, but there are several
considerations, upon which there is further elaboration
n thoh a buck converter may have a low dropout voltage
thaws the static regulation to be maintained as the input
voltage drops near the output voltage, in buck converters, the
slew rate limitation of the inductor current can compromise the
dynamic regulation in response to the load current step increases.
That is because the maximum rate the current can be increased
to in the inductor is proportional to the voltage available to
impress across it, which is compromised as the input voltage
reduces toward the output voltage. This is not a limitation of
the device but of buck converters in general. The limitation is
considered part of the output filter design, although it could
also be considered in terms of a minimum acceptable input
voltage for a given output filter that will ensure that the dynamic
response is acceptably maintained.
1. VIN must never exceed the maximum rated voltag
2. VIN must be within the specified operating range wh
operation is expected.
3. VIN must be greater than VOUT by at let the speied head-
room when dc regulation is expected.
4. VIN, if not sufficiently greater thVOUT, may limit e large
signal transient response of a nverter
5. VIN, if much greater than ise to such a low
duty ratio that it activates pode even at static
higher load conditions or upon load changes when
it is not desired
Output Filter Components
6. VIN affects thissipation (a lower value causes
higher dissipaurn affects die temperature
that must be keaximum rating.
In most applications, it is desirable to use the smallest inductor
value that does not introduce practical problems, since this tends
to yield the lowest cost inductor. One reason for using an even
larger inductor than the minimum tolerable might be to reduce
the output ripple voltage further. But cost being equal, this is
generally better accomplished with a better quality or propor-
tionally larger output capacitor instead, since a larger inductor
degrades the large signal transient performance capability.
The lowest input voltage together with the maximum output
voltage and maximum current create the conditions for the
maximum power dissipation in the device, which determine the
maximum temperature rise that should be checked against the
maximum junction temperature rating. The formula for maximum
power dissipation in the device is given by
A conservative nominal design target value for the inductor of a
typical application circuit is that which creates a peak-to-peak
ripple current, DIL, for the nominal input voltage that is approxi-
mately a third of the nominal 500 mA rating of the ADP3088.
The reason for not basing the ripple current on the maximum
load current is concern about the protection. Scaling the ripple
currents with lower load currents would yield higher inductor
values that might give satisfactory operation. However, in order for
overload operation up to the current limit level of the ADP3088
to be satisfactory, it would be necessary to choose an inductor
VO +VF @ IO, MAX
PDMAX
=
¥ IO, MAX ¥VSW @ IO, MAX
(2)
V
IN
where VF is the diode forward voltage drop and VSW is the drop
across the internal switch and current sensing resistor that
appears between the VIN and SW pins of the ADP3088 during the
on state of the switch. Both of these variables can be approximated
from a combination of worst-case specifications and typical graphs.
Multiply the power dissipation by the thermal resistance from
–9–
REV. C
ADP3088
rated up to that higher current, which would likely yield an
unsatisfactory inductor size and cost. In any case, having chosen
a target level for DIL, the recommended inductor value is
given by
For a given inductor selection, the earlier formula is rearranged
for convenience and skewed to the worst-case input voltage to
determine the maximum inductor ripple current, DIL.
V
-VO –VSW VO +VF
IN(MAX)
DIL(MAX)
=
¥
(7)
(1- D)¥ (VO +VF )
V
+VF –VSW
fSW ¥ L
IN(MAX)
L =
(4)
fSW ¥ DIL
Performance degradation of the inductor, consisting of some
where D is the duty ratio, the suffix indicating continuous
inductor current, and is given by
loss of inductance or excessive power loss, may be encountered
at higher ripple currents, so the ripple current figure, together
with the knowledge of the expected dc current, should be
checked against the specifications of the inductor.
VO +VF
D =
(5)
V
+VF -VSW
IN
If the ESR of the output capacitor is bstantial, as it is likely to
be if an MLC capacitor is not usethen the ripple voltage on
the output, dominated by the E, may substantial and of
concern for regulation specificati. he resistie component
of the output voltage rippis simple rippcurrent multi-
plied by the ESR, and is more thafmillivolts, it will
dominate the outpuapance in contrbuting to the output
ripple voltage.
V
SW and VF are assessed at full load, and fSW is the fixed
switching frequency of the ADP3088. The formula suggests the
calculation of L using a nominal input voltage; for applications
requiring a large range of VIN, the limitations of transient
response at VIN(MIN) versus the higher ripple at VIN(MAX) may
warrant deeper consideration of how to optimize the design. In
applications where load transients are not severe, this conservative
design for L is recommended. A more aggressive minimization of
L is outlined below, but a few restrictions are noted.
The boundarcondition of the inuctor reaching the borderline
current, IL), can determined by the formula
As inductance becomes smaller, the ripple current becomes
larger. If the ripple becomes particularly large or, as an addi-
tional factor, if the load is particularly dynamic, then there is
an increasing possibility that the peak inductor current will
reach the current limit shutdown threshold, ICL, which is not
desirable. This should be avoided by restricting the minimum
inductor value to keep the ripple current moderated. An
alternative way to prevent excessive dynamic overshoot
inductor current during a load transient is to reduce th
gain of the error amplifier by adding resistive feedback;
idea is discussed below.
VF
V
-VO -VSW
+VF -VSW
IO(BL)
=
¥
(8)
2fS
L
IN
ow this output current level, the inductor current will be
disctinuousnd the duty ratio will be modulated to lower
values fars substantially more than the losses that cause
y a smamount of the modulation in the continuous inductor
nt operation. PSM is initiated automatically by a propri-
technique consisting of a duty ratio amplifier with an
rnal time constant. As the load current drops well into the
low current region and the duty ratio passes below the threshold
of DPSM for a sufficient time, PSM is activated. The correspond-
ing level of output current is given by
Another important restriction of the minimum uctor may
apply. The design should ensure against possiharmo
oscillation that can occur in all fixed frequency, current-contred
switching power supplies when swit high dtios.
The subharmonic oscillation phet be explained
here (there are many papers writteexcept to
say that it is characterized by alternnd low duty
ratios, i.e., every other cyh prodditional ripple
on the output. To prenic osllation, the follow-
ing restriction for the tor value is recommended:
1
2
VIN +VF -VSW VIN -VO -VSW
IO(PSM)
=
¥ DP2SM
¥
(9)
VO +VF
fSW ¥ L
It can be seen in the formula that this current threshold is inversely
proportional to inductance, so although it is usually not a relevant
concern, it is noted that an aggressively low output inductance
should be avoided to keep the PSM threshold current at a desir-
ably low level.
2mH
V
IN(MIN )
For the user’s reference, when current is below the borderline
level, the duty ratio is modulated according to the formula
L >
¥ V + V
– 0.35
(
)
O
F
(6)
The value used for VIN(MIN) should be only the minimum input
voltage for which normal high performance operation must be
ensured. Note that the value returned for L may be negative, in
which case the restriction does not apply. If the preceding formula
yields a lower inductor value than the conservative recommen-
dation given previously, as is likely for most applications, then
one should consider further limitations to see how low the value
can be minimized.
VO +VF
+VF -VSW
fSW ¥ L
-VO -VSW
DD = 2 ¥ IO ¥
¥
IN
(10)
V
IN
V
where the suffix indicates that the inductor current is discontinuous.
For controlling the capacitive component of the output ripple
voltage, the following constraint on the minimum output
capacitance should be applied:
DIL
8fSW DVR
CO >
(11)
–10–
REV. C
ADP3088
where ⌬VR is the tolerable ripple voltage. However, this constraint
is rarely relevant, since the typical capacitance requirement is
driven more by dynamic response requirements than by ripple
concerns. In a typical application circuit, a 10 mF capacitor
produces a capacitive output voltage ripple component of only
about 2 mV. 10 mF is usually sufficient for applications that do not
impose particularly high frequency load transients, and imposes
additional constraints that are elaborated upon in the next section.
Returning to constraints for choosing the output capacitor for
digital loads, another criterion for ensuring sufficient output
capacitance applies.
2
DIO
CO >
ÈdIL
˘
˙
(13)
2DVO
MIN
Í
dt
Í
Î
˙
˚
Load Characterization
where DIO is the maximum high frequency load step. It should
be noted that the formula results strictly from the physical
limitation of the output filter; the compensation must also be
optimized to maximize the response of the control loop to avoid
substantial additional output ltage deviation. The formula
might also be written to desbe a mimum inductance for a
given capacitance, but it is neralbetter practice to choose
the inductor first and ad capnce as nded.
Optimization of the compensation, as well as the output filter,
requires some knowledge of a fundamental characteristic of the
load. Qualitatively, there are two types of loads with which we
are concerned: fast slew rate and slow slew rate. These slew
rates are assessed with respect to the minimum (absolute)
inductor (current) slew rate, as given by
È
Í
˘
Ê dIL ˆ
ÏVIN(MIN ) - VSW - VO
VO + VF ¸
, MIN = <
and
(12)
The impedance of output captoogether with a digital
load also createommiting conserations. Series resistance
(ESR) rather than capaance can be a dominant design
consideratn with non-MLcapacitors. If the load is essentially
digital, en the dynamic deviation of the output voltage cannot
be lied to y better than the dynamic load current step
times thR. In a fmula,
˙
Ì
˝
LMAX
˛
Á
˜
dt
LMAX
Ë
Í
Î
¯
˙
˚
Ó
where the < sign indicates a selection of whichever bracket term
is lower.
If the slew rate of the load is fast compared to the minimum
inductor slew rate, then the ability of the power converter to
contain the output voltage deviation following a load change is
limited not only by the response of the control loop, i.e., by its
speed to demand zero or maximum duty ratio from the modulator,
but by the power stage as well. In such a case, beginning with
the recognition that output voltage deviation would be substantial
even if the loop response were instantaneous, it can be s
that one can achieve better overall voltage containm
degenerating the dc loop gain. As a technical matter, i
noted that there will always be some minimum output v
deviation downward due to a load step even if ductor
as fast as the load slew rate. During a switcg cycle, the modula-
tor latches its “decision” to turn off the stch. nrescind
that decision, but must instead wait for the next clock le to
turn on the switch again and begiing the induccurrent
upward. This is only a second-sideration.
(14)
DVO ≥ ¥ SR
In such a case, it is often important to choose a capacitor that
ntrols thESR to a sufficiently small value. MLC capacitors are
ofcsen to practically eliminate the consideration of ESR
entir.
Closing the Loop—Compensation
The factors determining the response of the power converter
include the feedback input resistor divider, a lead network if
applicable, the transconductance of the error amplifier, its
frequency response limitation (i.e., as adequately modeled by a
capacitance from output to ground), its external termination
impedance (i.e., the compensation that may or may not include
dc feedback), the modulator transconductance, and the power
converter’s termination impedance (i.e., the output capacitor
and load resistance).
Slow slew rate loads may be as conventional
loads, since these have been the nt type of load.
Optimally compensaonvenad is synonymous
with small signal ans; thbjective is to maximize
the ac gain up to equency, ensure sufficient
phase margin at tossover frequency, and keep
the gain rolling off uencies to avoid gain margin
problems.
Since the ADP3088 has a current-controlled loop, the particular
inductor value does not by first-order consideration affect small
signal stability. However, slew rate limitations, as discussed
earlier, a large signal limitation consideration, set boundaries
that are often relevant for optimizing compensation of the feed-
back loop. If the compensation of the current control signal, i.e.,
the COMP pin, is designed to promote a current response that is
faster than the inductor current can slew, then when a step load is
applied, the control signal will tend to initially respond in excess
(of the actual current change that is occurring) and then allow an
overshoot of the current and output voltage since it is delayed in
correcting its excess.
Fast slew rate loads may be referred to as digital loads since,
from the perspective of the power converter, they have a digital
characteristic when changing between two extremes, and also
because such fast slew rates tend to characterize modern digital
circuits, which often feature power management interrupts, i.e.,
interrupt signals used to turn circuitry on and off as needed during
normal system operation. Optimally compensating a digital load
is more a task of impedance matching and dc gain determina-
tion than a task of ac loop optimization.
For conventional loads, the following describes how the fre-
quency corners (poles and zeros) are positioned or should be
chosen to optimize the loop gain, beginning in the low
frequency spectrum:
–11–
REV. C
ADP3088
1. The dc loop gain is limited by the applied load resistance and
the output resistance of the error amplifier, but it is not important
to determine how high the dc gain is.
where VOUT is the nominal dc level. This equation together with
the preceding recommendations should suffice to determine
compensation component selection for users familiar with loop
design. This begins with deciding the crossover frequency, fC,
evaluating the impedances at that frequency, and setting the open-
loop gain, AOL, to unity. By example, fC = 125 kHz is chosen.
2. Two poles in the low frequency spectrum begin to roll off the
gain, one determined by the load resistance and output
capacitor, CO, and the other by the error amplifier’s output
resistance and its termination capacitance, the equivalent
feedback capacitance, and the added compensation capaci-
tance CHF. Determining the location of these poles is not
relevant to the compensation design. It suffices to know that
both are decades below the crossover frequency.
Assuming a well chosen CHF as described previously, in other
words, such that it creates a pole well above crossover or approxi-
mately matches the zero of the output capacitor, the following
equation approximates the calculation of the crossover frequency:
1+ 50k WA ¥ f ¥ k
(
)
Z
1
3. A lead network is especially desirable for a variable output
voltage application in order to keep a fairly constant crossover
frequency and phase margin for all output voltages. If used,
this lead network simply consists of a capacitor, CFF, in parallel
with the upper feedback divider resistor, RA; this creates a
closely spaced zero/pole pair that provides a gain boost before
crossover so that, above the pole frequency, the loop gain and
phase are similar for all output voltages. If the lead network is
used for a fixed voltage application, the pole should be chosen
to align with the following described zero; for variable voltage
applications, the maximum frequency of the pole should be
placed as high as is comfortable without substantially degrad-
ing the phase margin, e.g., not within an octave or, more
conservatively, a half-decade of the crossover frequency.
(16)
fC
=
21k WA ¥ k
1
where k1 = CO ¥ VOUT/RC and fZ 1/2p CC, the zero frequency
set by the compensation, ad ths are shwn with the
constants in the equatioor clarificn.
The preceding equaticaot readily be lved in terms of k1,
but it can be solved closely engh by a few iterations beginning
with values for around 1 ¥ 10A). For the example below, set
the zero aboa half-decade below C as previously advised, that is,
choose fZ /÷10 0 kHz. Using the previously stated values for
fZ and fC, the lof k1 = 80 p (FA) satisfies the equation. RA
and RB are presed to already chosen per earlier guidelines to
set the output volts an example, RA = RB = 10 kW (implying
output voltage of 2.5 V). Similarly, it is presumed that CO was
cho; let CO 5 mF. Then, finally, RC and then also CC can be
determed brearranging the simple formulas previously given.
e exame yields RC ~ 47 kW and CC ~ 82 pF. Assuming an
C output capacitor of reasonable quality, the pole setting
citor could be chosen to be CHF = 4.7 pF.
4. A zero turns the gain roll-off back to one-pole sufficiently in
advance of the crossover frequency to create ample phase
margin, e.g., half a decade; the zero could feasibly be that
the output capacitor itself, i.e., the zero formed by the E
and the capacitance, CO, but that is both unlikely (sinc
zero frequency will likely be higher than where the loop z
desired) and generally imprudent (since the lorforma
would depend on the stability of the ESR, hich often is
poor or unknown). As recommended, the zo, f, red
by an RC circuit terminating the COMP pin (a resistor, Rin
series with a capacitor, CC), while tacitance termting
the error amplifier, CHF, forms a with RC to ancel
the zero of the output capacitos well above
the crossover frequency, as may n using an
MLC output capacitor, that pole is ough above
the crossover frequefor exle, half a decade,
so that it doesn’t cinto the phase margin at
crossover but still engain roll-off so that the gain
margin is acceptably t the previous guidelines
6.8ꢀH
ADP3088
V
1.5V
OUT
V
5V
IN
SW
IN
1A
10ꢀF
MLCC
SCHOTTKY
IN
DRV
1ꢀF
MLCC
R
A
GND
GND
COMP
10kꢁ
FB
C
4.7pF
HF
R
B
C
C
48.7kꢁ
470pF
R
C
10kꢁ
Figure 2. 5 V to 1.5 V, General-Purpose Application
Another application circuit features a voltage inversion and
regulation design such that the output voltage is negative (see
Figure 3). Negative output voltages are allowed when the input
plus the output voltage does not exceed the rating of the device.
In the voltage inverting configuration, the ground reference of
the ADP3088 is the negative output voltage, and the conventional
output voltage point is tied to ground. Operation is bootstrapped;
the power converter behaves as if the input voltage were equal to
the actual input voltage plus the magnitude of the output voltage
and as if the output voltage were not inverted. This implies that
it is possible to have the input voltage be less than the magnitude
of the output voltage, provided that the input voltage alone is
sufficient to start the operation of the IC, i.e., before the negative
suggest that CC ≥ 10 ¥
5. The gain crosses 0 dB (unity) at a crossover frequency that is
typically a tenth and advisably not greater than a fourth of the
switching frequency; one primary reason for this approximate
upper limit being the extra phase margin loss due to the
switching interval that is not predicted by the linear model.
Assuming no lead network is used, the open-loop gain is given by
Ê V ˆ
600m
¥ ZCOMP ¥ ZO
Á
˜
W2
Ë
¯
(15)
AOL
ª
VOUT
–12–
REV. C
ADP3088
output voltage has been developed. (The circuit in Figure 3
with a –3.3 V output works well over an input range from 2.5 V
to 7.5 V.) Since the ADP3088 features a current-controlled
loop, the feedback effect of essentially boosting the input voltage
atop the output (with respect to the ground connection of the
ADP3088) is reduced to a negligible second-order effect.
higher than VREF, which would result in a slight downward shift
of the nominal output voltage.
Having chosen this design approach, the series RC of the com-
pensation network can be removed, and the single remaining
capacitor, CHF, should be increased to approximately
CO ¥ ESR
CHF
=
(18)
RFB
4.7ꢀH
ADP3088
V
IN
5V
SW
IN
1A
10ꢀF
If an MLC capacitor is used for CO, the value of CHF might be
calculated to be less than a few picofarads, in which case it is
SCHOTTKY
MLCC
IN
+
DRV
R
1ꢀF
MLCC
A
GND
GND
COMP
10kꢁ
recommended to use a 4.7 pF~10 pF capacitor. The formula is
®
FB
+
derived from a patented design echnique called ADOPT
,
C
HF
4.7pF
R
B
Analog Devices’ Optimal Posoning Technology. This creates
ac and dc impedance matcg, and e increased complexity of
the dc regulation design is mered by thsimplicity of the
frequency compensatn.
C
C
6.04kꢁ
220pF
R
20kꢁ
C
V
OUT
–3.3V
In this design apph, at higher nts the output voltage
will be appreciaby lowean at the lower currents. This is equiva-
lent to sayithat the loregulation appears to be poor.
But, paroxically perhapo the user unfamiliar with volt-
age potioninghe overall containment of the voltage within a
given dowill be improved, and that tends to be of particu-
lar impore in my highly dynamic loads.
Figure 3. +5 V to –3.3 V, General-Purpose
Inverting Application
Voltage Positioning Designs
For digital loads, a different compensation technique is recom-
mended that involves implementing “voltage positioning,”
which is now commonly used on CPUs but is equally applicable
to any dynamic device. Voltage positioning is the intentional
and controlled variation of the output voltage with the load
current, such that the power supply appears to have a sub-
stantial output resistance. The key to voltage positioning
optimization for a digital load is to degenerate the loop
just enough so that the static load regulation allows
voltage deviation with the current as would be the
age deviation, ⌬VO, that could not be avoided in th
that a step change of the current were to occur even
loop response were instantaneous. The ron for even a
instantaneous response in the control loallowioutput
voltage deviation is that the slew rate of tent in e
output is limited by the inductor, and a corresponding ynamic
burden is placed on the output r to maihe output
voltage. Therefore, inductor ion is desired both
for concern over its size and caximize the slew
rate of the current to the output aller output capaci-
tor is needed.
The applicaticuit in Figure 4 features a 3.3 V input and a
2.5 V output at 100 mA~400 mA, which constrains the output
oltage witn a ~100 mV range with only a 4.7 mF output
ccitoeven when the load slew rate is extremely fast. This
doet include the initial tolerance of the voltage setting
that is separately accounted with voltage positioning designs.
Note that the lower resistor, RB, of the feedback divider is
reduced from the 10 kW value that one would use for a standard
(nonvoltage-positioned) design that had no voltage positioning
resistor RVP
.
3.3ꢀH
V
OUT
ADP3088
V
IN
2.5V
SW
IN
3.3V
1A
SCHOTTKY
4.7ꢀF
100 mA–400 mA
MLCC
IN
DRV
R
1ꢀF
MLCC
A
GND
GND
COMP
10kꢁ
FB
C
4.7pF
HF
R
B
8.75kꢁ
To implement vola resistor, RVP, should be placed
between the COMccording to the formula
R
VP
51kꢁ
DIOR
gMOD ¥ DVO
Figure 4. Application Circuit Using Voltage Posi-
tioning, Allowing Small Output Capacitance
RVP
=
(17)
Extra-Low Voltage Outputs
where gMOD is the modulator gain and ⌬IO must be assessed
over the entire operating load range as the difference between
the maximum and minimum load. CO must be chosen at least
large enough to support the targeted ⌬VO according to the previous
formula governing the relationship among the minimum output
capacitance, voltage deviation, and load current. In order to ensure
that the output voltage will be constrained within the limitations
of ⌬VO, the limitations noted earlier for PSM hysteretic ripple are
applicable in the operating load range and ESR. Also, an experi-
mental adjustment downward to the value of RB may be needed,
since the dc bias point of the COMP node is usually a little
Some newer power management applications require voltage levels
below the normal adjustable voltage range of the ADP3088, i.e.,
below 1.25 V. Such applications can be accommodated using
the ADP3088 by modifying the application circuit to sum in a
resistor-weighted portion of another regulated system voltage,
e.g., 3.3 V, to the feedback node (FB). The tolerance of the
ADP3088’s output voltage will increase by an amount propor-
tional to the tolerance of the summed in-system voltage times
the ratio of the conductance from that node to that of the output
voltage. The example in Figure 5 shows an implementation
of this technique together with another special implementation
described in the following section. The resistor RTT sums from a
–13–
REV. C
ADP3088
2.5 V system voltage to the FB node that will reduce the out-
put voltage according to the formula
The design of either parallel bit or PWM type of voltage control
must consider whether the interface node(s), from parallel
switched bits or a single PWM signal, has an active pull-up state
(in which case it must be to a known voltage) or a passive pull-up
(open drain) that floats up to the FB node voltage, 1.25 V, in its
high state. If at least the lower extreme of the desired output
voltage range must be lower than 1.25 V, either technique can
be combined with the technique for lowering the output voltage
below 1.25 V. Such an example of an application having this
RA
DVOUT = V
-VTT
(
)
RTT
(19)
REF
Dynamic Voltage Control
Some newer power management applications also require an
ability to adjust the voltage being delivered to a load during
operation. Although there is no integration of this feature in the
ADP3088, it can readily be accommodated with a few compo-
nents. Dynamic voltage control can be implemented either by
parallel bus control or by PWM. In both cases, the output voltage
is modified by summing either switched bits with, presumably
binary, weighting resistors or a switched PWM node via a single
resistor into the FB pin. (The switched PWM node refers to an
external PWM control signal, not the switched node of the power
converter itself.) Since the PWM technique modulates a current
into the FB node, it is necessary both to integrate that signal
and to avoid slowing down the response of the power converter
to the output voltage transitions. This can be accomplished by
placing a capacitor between the output voltage and the feedback
node, which serves to provide a zero/pole pair in the main regu-
lation loop and appears as an integration pole to the PWM signal.
®
requirement is the Blackfin DSP. Figure 5 shows an implementa-
tion of this technique.
Input Voltage: 4.75 V ~ 7.5 V
Output Voltage: 0.9 V ~ 1.5 V
Dynamic voltage control intce tecique: PWM, active
high to VIO
System voltage used flowering out tage below
1.25 V: VTT = VIO 2
Maximum output current: 0 mA
ADP3088
IN
0ꢀH@1A
V
OUT
V
IN
3ꢃ10ꢀF
MLCC
0.9V TO 1.5V
@700 mA
1
~5V TO 8V
2.2ꢀF
MLCC
R
A
C
FF
10.0kꢁ
C
C
2.2nF
HF
C
10pF
V
2.5V
0pF
TT
R
TT
R
C
287kꢁ
PWM 0V TO 2.5V
2
R
PWM
41.2kꢁ
gure 5. Blackfin DSP Application
–14–
REV. C
ADP3088
OUTLINE DIMENSIONS
8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
3.00
BSC
8
5
4
4.90
BSC
3.00
BSC
1
PIN 1
0.65 BSC
1.10 MAX
0.15
0.00
0
0.
8ꢂ
0ꢂ
0.38
0.22
0.23
0.08
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS M87AA
–15–
REV. C
ADP3088
Revision History
Location
Page
1/04—Data Sheet changed from REV. B to REV. C.
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to TPC 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to Equation 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Changes to Equation 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Changes to Equation 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4/03—Data Sheet changed from REV. A to REV. B.
Equation 1 edited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
10/02—Data Sheet changed from REV. 0 to REV. A.
Equation 6 edited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Equation 16 edited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
–16–
REV. C
相关型号：
ADP3088ARMZ
IC 1.4 A SWITCHING REGULATOR, 1250 kHz SWITCHING FREQ-MAX, PDSO8, MSOP-8, Switching Regulator or Controller
ADI
ADP3089ACP-REEL
IC 2 A SWITCHING REGULATOR, 1250 kHz SWITCHING FREQ-MAX, DSO8, 3 X 3 MM, LEAD FRAME, CSP-8, Switching Regulator or Controller
ADI
ADP3089ACP-REEL7
IC 2 A SWITCHING REGULATOR, 1250 kHz SWITCHING FREQ-MAX, DSO8, 3 X 3 MM, LEAD FRAME, CSP-8, Switching Regulator or Controller
ADI
ADP3110AKCPZ-RL
HALF BRDG BASED MOSFET DRIVER, PDSO8, 3 X 3 MM, 0.50 PITCH, LEAD FREE, DFN-8
ROCHESTER
©2020 ICPDF网 联系我们和版权申明