ADP2443ACPZN-R7_技术文档

3 A, 36 V, Synchronous Step-Down

DC-to-DC Regulator

ADP2443

Data Sheet

FEATURES

TYPICAL APPLICATION CIRCUIT

Continuous output current: 3 A

ADP2443

Input voltage: 4.5 V to 36 V

Integrated MOSFETs: 98 mΩ/35 mΩ

Reference voltage: 0.6 V 1%

V

PVIN

EN

BST

SW

IN

C

L

BST

V

C

OUT

IN

C

R

OUT

RAMP

TOP

RAMP

Fast minimum on time: 50 ns

PGOOD

FB

Programmable switching frequency: 200 kHz to 1.8 MHz

Synchronizes to external clock: 200 kHz to 1.8 MHz

Precision enable and power good

Cycle-by-cycle current limit with hiccup protection

External compensation

RT/SYNC COMP

R

C

R

VREG

SS

T

BOT

C

VREG

SS

C

GND

PGND

Programmable soft start time

Startup into a precharged output

Supported by ADIsimPower design tool

Figure 1.

APPLICATIONS

Intermediate power rail conversion

Multicell battery powered systems

Process control and industrial automation

Healthcare and medical

Networking and servers

GENERAL DESCRIPTION

The ADP2443 is synchronous step-down, dc-to-dc regulator

with an integrated 98 mΩ, high-side power metal oxide semicon-

ductor field effect transistor (MOSFET) and a 35 mΩ, synchronous

rectifier MOSFET to provide a high efficiency solution in a

compact 4 mm × 4 mm LFCSP package. The regulators operate

from an input voltage range of 4.5 V to 36 V. The output voltage

can be adjusted down to 0.6 V and deliver up to 3 A of

continuous current. The fast 50 ns minimum on time allows the

regulators convert high input voltage to low output voltage at high

frequency.

Other key features include undervoltage lockout (UVLO),

overvoltage protection (OVP), overcurrent protection (OCP),

short-circuit protection (SCP), and thermal shutdown (TSD).

The ADP2443 operates over the −40°C to +125°C operating

junction temperature range and is available in a 24-lead, 4 mm ×

4 mm LFCSP package.

100

95

90

85

80

75

70

The ADP2443 uses an emulated current mode, constant frequency

pulse-width modulation (PWM) control scheme for excellent

stability and transient response. The switching frequency of the

ADP2443 can be programmed from 200 kHz to 1.8 MHz. The

synchronization function allows the switching frequency be syn-

chronized with an external clock to minimize the system noise.

V

= 5V

= 3.3V

OUT

65

60

55

50

The ADP2443 targets high performance applications that require

high efficiency and design flexibility. External compensation

and an adjustable soft start function provide design flexibility.

The power-good output and precision enable input provide

simple and reliable power sequencing.

0

0.5

1.0

1.5

2.0

2.5

3.0

OUTPUT CURRENT (A)

Figure 2. Efficiency vs. Output Current, V_IN= 24 V, f_SW= 300 kHz

Rev. 0

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADP2443* PRODUCT PAGE QUICK LINKS

Last Content Update: 11/29/2017

COMPARABLE PARTS

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DESIGN RESOURCES

• ADP2443 Material Declaration

• PCN-PDN Information

EVALUATION KITS

• ADP2443 Evaluation Board

• Quality And Reliability

• Symbols and Footprints

DOCUMENTATION

Data Sheet

DISCUSSIONS

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• ADP2443: 3 A, 36 V, Synchronous Step-Down DC-to-DC

Regulator Data Sheet

SAMPLE AND BUY

Visit the product page to see pricing options.

User Guides

• UG-1029: Evaluation Board for the ADP2443 3 A, 36 V,

Synchronous Step-Down DC-to-DC Regulator

TECHNICAL SUPPORT

Submit a technical question or find your regional support

number.

TOOLS AND SIMULATIONS

• ADIsimPower™ Voltage Regulator Design Tool

• ADP244x Buck Regulator Design Tool

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Submit feedback for this data sheet.

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ADP2443

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications Information .............................................................. 15

Input Capacitor Selection.......................................................... 15

Output Voltage Setting .............................................................. 15

Voltage Conversion Limitations............................................... 15

Inductor Selection ...................................................................... 15

Output Capacitor Selection....................................................... 17

Programming Input Voltage UVLO ........................................ 17

Slope Compensation Setting..................................................... 17

Compensation Design ............................................................... 17

ADIsimPower Design Tool ....................................................... 18

Design Example.............................................................................. 19

Output Voltage Setting .............................................................. 19

Frequency Setting....................................................................... 19

Inductor Selection...................................................................... 19

Output Capacitor Selection....................................................... 20

Slope Compensation Setting..................................................... 20

Compensation Components..................................................... 20

Soft Start Time Program ........................................................... 20

Input Capacitor Selection.......................................................... 20

Recommended External Components .................................... 21

Printed Circuit Board Layout Recommendations ..................... 22

Typical Applications Circuits........................................................ 23

Outline Dimensions....................................................................... 24

Ordering Guide .......................................................................... 24

Applications....................................................................................... 1

Typical Application Circuit ............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications..................................................................................... 4

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Theory of Operation ...................................................................... 13

Control Scheme .......................................................................... 13

Precision Enable/Shutdown ...................................................... 13

Internal Regulator (VREG)....................................................... 13

Bootstrap Circuitry .................................................................... 13

Oscillator ..................................................................................... 13

Synchronization.......................................................................... 13

Soft Start ...................................................................................... 14

Power Good................................................................................. 14

Peak Current-Limit and Short-Circuit Protection................. 14

Overvoltage Protection (OVP)................................................. 14

Undervoltage Lockout (UVLO) ............................................... 14

Thermal Shutdown..................................................................... 14

REVISION HISTORY

9/2016—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

Data Sheet

ADP2443

FUNCTIONAL BLOCK DIAGRAM

VREG

4µA

ADP2443

EN

EN_BUF

5V

PVIN

REGULATOR

0.13µA

1.2V

PGOOD

GND

UVLO

DEGLITCH

0.66V

BOOST

REGULATOR

0.54V

0.7V

BST

SW

OVP

NFET

DRIVER

CONTROL

LOGIC AND

MOSFET

DRIVER

WITH

ANTICROSS

PROTECTION

VREG

DRIVER

FB

0.6V

AMP

I

NFET

SS

CMP

SS

PGND

COMP

SLOPE

COMPENSATION

AND RAMP

GENERATOR

RAMP

A

CS

HICCUP

MODE

OSC

RT/SYNC

OCP

I

MAX

CLK

NEG

NEGATIVE CURRENT CMP

Figure 3.

Rev. 0 | Page 3 of 24

ADP2443

Data Sheet

SPECIFICATIONS

V_PVIN= 12 V, T_J= −40°C to +125°C for minimum/maximum specifications, T_A= 25°C for typical specifications, unless otherwise noted.

Table 1.

Parameters

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

PVIN

PVIN Voltage Range

Quiescent Current

V_PVIN

I_Q

4.5

36

V

mA

No switching, RAMP connected to PVIN

through a resistor

0.868 1.1

Shutdown Current

PVIN Undervoltage Lockout Threshold

I_SHDN

EN = GND

PVIN rising

PVIN falling

28

4.3

3.9

57

4.45

µA

V

3.8

FB

Regulation Voltage

Bias Current

V_FB

I_FB

−40°C < T_J< +125°C

0.594 0.6

0.05

0.606

0.2

V

µA

ERROR AMPLIFIER (EA)

Transconductance

Source Current

g_m

I_SOURCE

I_SINK

485

515

50

545

µS

µA

V_FB= 0.45 V

V_FB= 0.75 V

Sink Current

INTERNAL REGULATOR (VREG)

VREG Voltage

Dropout Voltage

V_VREG

V_PVIN= 12 V, I_VREG= 10 mA

V_PVIN= 12 V, I_VREG= 30 mA

4.9

5

320

100

5.1

V

mV

mA

Regulator Current Limit

SW

High-Side On Resistance¹

Low-Side On Resistance¹

Low-Side Valley Current Limit

Low-Side Negative Current Limit

Leakage Current

R_{DSON_HS}

R_{DSON_LS}

BST pin voltage (V_BST) − V_SW= 5 V

V_VREG= 5 V

98

35

4.7

2.5

1.5

50

147

58

5.1

3

7.9

65

235

mΩ

A

µA

ns

3.9

2

V_SW= 0 V, EN = GND

SW Minimum On Time

SW Minimum Off Time

BST

t_{MIN_ON}

t_{MIN_OFF}

200

ns

Bootstrap Voltage

OSCILLATOR (RT/SYNC)

Switching Frequency

Switching Frequency Range

Synchronization Range

SYNC Minimum Pulse Width

SYNC Minimum Off Time

SYNC Input Voltage

High

V_BOOT

f_SW

4.65

5

5.2

V

R_T= 280 kΩ

540

200

100

600

660

1800 kHz

kHz

ns

1.3

3.0

V

Low

0.4

3.8

SS

SS Pin Pull-Up Current

PGOOD

I_SS

3.4

µA

Power-Good Range

FB Rising Threshold

FB Rising Hysteresis

FB Falling Threshold

FB Falling Hysteresis

Power-Good Deglitch Time

Power-Good Leakage Current

Power-Good Output Low Voltage

108

88

110

5

90

5

16

0.1

220

112

92

%

Both rising and falling

V_PGOOD= 5 V

I_PGOOD= 1 mA

Clock cycles

µA

mV

1

300

Rev. 0 | Page 4 of 24

Data Sheet

ADP2443

Parameters

EN

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

EN Rising Threshold

EN Input Hysteresis

EN Current

1.16

1.2

100

0.13

4

1.24

V

mV

µA

EN voltage < 1.1 V, sink current

EN voltage > 1.2 V, source current

THERMAL SHUTDOWN

Threshold

Hysteresis

150

25

°C

¹Pin to pin measurement.

Rev. 0 | Page 5 of 24

ADP2443

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 2.

THERMAL RESISTANCE

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Careful attention to

PCB thermal design is required.

Parameter

Rating

PVIN, EN, PGOOD, RAMP

SW

BST

FB, SS, CO M P, RT/SYNC

VREG

PGND to GND

Operating Junction Temperature Range

Storage Temperature Range

Soldering Conditions

−0.3 V to +40 V

−1 V to +40 V

V_SW+ 6 V

−0.3 V to +6 V

−0.3 V to +0.3 V

−40°C to +125°C

−65°C to +150°C

JEDEC J-STD-020

Table 3. Thermal Resistance

Package Type

CP-24-12¹

θ_JA

θ_JC

Unit

42.6

6.8

°C/W

¹Thermal impedance simulated value is based on a 4-layer, JEDEC standard board.

ESD CAUTION

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Rev. 0 | Page 6 of 24

Data Sheet

ADP2443

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADP2443

TOP VIEW

(Not to Scale)

1

2

3

18

17

16

15

14

13

COMP

FB

PVIN

BST

25

GND

VREG

GND 4

26

SW

5

6

SW

PGND

NOTES

1. EXPOSED GND PAD. THE EXPOSED GND PAD MUST

BE SOLDERED TO A LARGE, EXTERNAL, COPPER

GND PLANE TO REDUCE THERMAL RESISTANCE.

2. EXPOSED SW PAD. THE EXPOSED SW PAD MUST

BE CONNECTED TO THE SW PINS OF THE ADP2443

BY USING SHORT, WIDE TRACES, OR SOLDERED

TO A LARGE EXTERNAL SW COPPER PLANE TO

REDUCE THERMAL RESISTANCE.

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic Description

1

2

3

COMP

FB

VREG

Error Amplifier Output. Connect an RC network from COMP to GND.

Feedback Voltage Sense Input. Connect this pin to a resistor divider from the output voltage (V_OUT).

Output of the Internal 5 V Regulator. The control circuits are powered from the voltage on this pin. Place a 1 µF,

X7R or X5R ceramic capacitor between this pin and GND.

4

GND

Analog Ground. Return of internal control circuit.

5, 6, 7, 14 SW

Switch Node Output. Connect these pins to the output inductor.

Power Ground. Return of low-side power MOSFET.

Supply Rail for the High-Side Gate Drive. Place a 0.1 µF, X7R or X5R capacitor between SW and BST.

8 to 13

15

PGND

BST

16 to 19

PVIN

Power Input. Connect these pins to the input power source and connect a bypass capacitor between these pins and

PGND.

20

EN

Precision Enable Pin. An external resistor divider can be used to set the turn-on threshold. To enable the device

automatically, connect the EN pin to the PVIN pin.

21

22

PGOOD

RT/SYNC

Power-Good Output (Open-Drain). A pull-up resistor of 10 kΩ to 100 kΩ is recommended.

Frequency Setting (RT). Connect a resistor between RT and GND to program the switching frequency between

200 kHz to 1.8 MHz.

Synchronization Input (SYNC). Connect this pin to an external clock to synchronize the switching frequency

between 200 kHz and 1.8 MHz. See the Oscillator section and the Synchronization section for more information.

23

24

25

RAMP

SS

E P, G N D

Slope Compensation Setting. Connect a resistor from RAMP to PVIN to set the slope compensation.

Soft Start Control. Connect a capacitor from SS to GND to program the soft start time.

Exposed GND Pad. The exposed GND pad must be soldered to a large, external, copper GND plane to reduce

thermal resistance.

26

E P, S W

Exposed SW Pad. The exposed SW pad must be connected to the SW pins of the ADP2443 by using short, wide

traces, or soldered to a large external SW copper plane to reduce thermal resistance.

Rev. 0 | Page 7 of 24

ADP2443

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 25^oC, V_IN= 24 V, V_OUT= 5 V, L = 6.8 µH, C_OUT= 47 µF × 2, f_SW= 600 kHz, unless otherwise noted.

100

90

80

70

60

50

40

30

100

90

80

70

60

50

40

30

V

= 5V, L = 6.8µH

= 3.3V, L = 4.7µH

= 1.2V, L = 2.2µH

V

= 5V, L = 6.8µH

= 3.3V, L = 4.7µH

= 1.2V, L = 2.2µH

OUT

0

0.5

1.0

1.5

2.0

2.5

3.0

0

0.5

1.0

1.5

2.0

2.5

3.0

OUTPUT CURRENT (A)

Figure 5. Efficiency at V_IN= 24 V, f_SW= 600 kHz

Figure 8. Efficiency at V_IN= 12 V, f_SW= 600 kHz

100

90

80

70

60

50

40

30

100

90

80

70

60

50

40

30

V

= 5V, L = 10µH

= 3.3V, L = 10µH

= 1.2V, L = 4.7µH

V

= 5V, L = 10µH

= 3.3V, L = 10µH

= 1.2V, L = 4.7µH

OUT

0.5

1.0

1.5

2.0

2.5

0.5

1.0

1.5

2.0

2.5

OUTPUT CURRENT (A)

Figure 6. Efficiency at V_IN= 24 V, f_SW= 300 kHz

Figure 9. Efficiency at V_IN= 12 V, f_SW= 300 kHz

100

90

80

70

60

50

40

30

100

90

80

70

60

50

40

30

V

= 5V, L = 3.3µH

= 3.3V, L = 2.2µH

V

= 5V, L = 3.3µH

= 3.3V, L = 2.2µH

= 1.2V, L = 1µH

OUT

0.5

1.0

1.5

2.0

2.5

0.5

1.0

1.5

2.0

2.5

OUTPUT CURRENT (A)

Figure 7. Efficiency at V_IN= 24 V, f_SW= 1.2 MHz

Figure 10. Efficiency at V_IN= 12 V, f_SW= 1.2 MHz

Rev. 0 | Page 8 of 24

Data Sheet

ADP2443

60

50

40

30

20

10

0

1000

950

900

850

800

750

700

T

= +125°C

= +25°C

= –40°C

T

= +125°C

= +25°C

= –40°C

J

12

16

20

24

28

32

36

12

16

20

24

28

32

36

INPUT VOLTAGE (V)

Figure 11. Shutdown Current vs. Input Voltage (V_PVIN

)

Figure 14. Quiescent Current vs. Input Voltage (V_PVIN)

4.5

4.4

4.3

4.2

4.1

4.0

3.9

3.8

3.7

1.25

1.20

1.15

1.10

1.05

1.00

0.95

RISING

FALLING

RISING

FALLING

–40

–20

0

20

40

60

80

100

120

–40

–20

0

20

40

60

80

100

120

TEMPERATURE (°C)

Figure 12. PVIN UVLO Threshold vs. Temperature

Figure 15. EN Threshold vs. Temperature

606

604

602

600

598

596

594

3.60

3.55

3.50

3.45

3.40

3.35

3.30

3.25

3.20

–40

–20

0

20

40

60

80

100

120

–40

–20

0

20

40

60

80

100

120

TEMPERATURE (°C)

Figure 13. Feedback Voltage vs. Temperature

Figure 16. SS Pin Pull-Up Current vs. Temperature

Rev. 0 | Page 9 of 24

ADP2443

Data Sheet

5.10

5.05

5.00

4.95

4.90

4.85

620

610

600

590

580

570

R

= 280kꢀ

T

4.80

–40

–20

0

20

40

60

80

100

120

–40

–20

0

20

40

60

80

100

120

TEMPERATURE (°C)

Figure 17. VREG Voltage vs. Temperature

Figure 20. Frequency vs. Temperature

140

120

100

80

6.0

5.5

5.0

4.5

4.0

3.5

3.0

60

40

20

R

DSON_HS

R

DSON_LS

0

–40

–20

0

20

40

60

80

100

120

–40

–20

0

20

40

60

80

100

120

TEMPERATURE (°C)

Figure 21. Current-Limit Threshold vs. Temperature

Figure 18. MOSFET On Resistor vs. Temperature

T

V

(AC)

OUT

1

EN

3

I

L

V

OUT

SW

1

2

4

PGOOD

4

2

I

L

B

CH1 2.00V

CH3 20.0V

CH2 5.00V

CH4 1.00A

M2.00ms

25.30%

A CH3

11.2V

CH1 10.0mV

CH2 10.0V

CH4 1.0A

M2.00µs

50.00%

A CH2

10.0V

W

B

T

W

Figure 22. Voltage Precharged Output

Figure 19. Working Mode Waveform

Rev. 0 | Page 10 of 24

Data Sheet

ADP2443

T

EN

3

EN

3

V

OUT

V

OUT

1

2

PGOOD

I

OUT

1

4

2

PGOOD

I

OUT

4

B

CH1 2.00V

CH3 20.0V

CH2 5.00V

CH4 2.00A

M2.00ms

27.20%

A CH3

11.2V

CH1 2.00V

CH3 5.00V

CH2 5.00V

CH4 2.00A

M1.00ms

30.00%

A CH3

2.60V

W

B

T

W

Figure 23. Soft Start with Full Load

Figure 26. Shutdown with Full Load

T

V

(AC)

V

(AC)

OUT

1

PVIN

SW

3

2

I

OUT

4

B

CH2 20.0V

CH1 100mV

M200µs

20.00%

A CH4

1.44A

CH1 20.0mV

CH3 10.0V

M2.00ms A CH3

W

21.0V

W

B

CH4 1.00A

T

20.10%

W

Figure 24. Load Transient Response, 0.3 A to 2.7 A

Figure 27. Line Transient Response, V_IN= 12 V to 30 V, I_OUT= 3 A

T

V

OUT

1

2

4

SW

2

4

I

L

B

CH1 2.00V

CH2 20.0V

CH4 5.00A

M10.0ms

20.00%

A CH1

3.04V

CH1 2.00V

CH2 20.0V

CH4 5.00A

M10.0ms

W

A CH1

3.04V

W

B

T

80.10%

W

Figure 25. Output Short Entry

Figure 28. Output Short Recovery

Rev. 0 | Page 11 of 24

ADP2443

Data Sheet

4

3

2

1

0

3

2

1

0

V

= 12V

= 9V

= 5V

V

= 12V

= 9V

= 5V

OUT

= 1.2V

= 2.5V

65

70

75

80

85

90

95

100

105

65

70

75

80

85

90

95

100

105

AMBIENT TEMPERATURE (°C)

Figure 29. Load Current vs. Ambient Temperature at V_IN= 24 V, f_SW= 600 kHz,

Measured on ADP2443-EVALZ

Figure 31. Load Current vs. Ambient Temperature at V_IN= 36 V, f_SW= 600 kHz,

Measured on ADP2443-EVALZ

4

3

2

V

= 5V

= 3.3V

= 1.2V

OUT

1

0

70

75

80

85

90

95

100

105

110

AMBIENT TEMPERATURE (°C)

Figure 30. Load Current vs. Ambient Temperature at V_IN= 12 V, f_SW= 600 kHz,

Measured on ADP2443-EVALZ

Rev. 0 | Page 12 of 24

Data Sheet

ADP2443

THEORY OF OPERATION

The ADP2443 is synchronous step-down, dc-to-dc regulator that

uses an emulated current-mode architecture with an integrated

high-side power switch and a low-side synchronous rectifier.

The regulator targets high performance applications that require

high efficiency and design flexibility.

INTERNAL REGULATOR (VREG)

The on-board 5 V regulator provides a stable supply for the

internal circuits. It is recommended that a 1 µF ceramic capacitor

be placed between the VREG pin and GND. The internal regulator

includes a current-limit circuit to protect the output if the

maximum external load current is exceeded.

The ADP2443 operates with an input voltage from 4.5 V to 36 V

and regulates the output voltage down to 0.6 V. Additional features

that maximize design flexibility include programmable switching

frequency, programmable soft start, external compensation,

precision enable, and a power-good output.

BOOTSTRAP CIRCUITRY

The ADP2443 includes a regulator to provide the gate drive

voltage for the high-side N-MOSFET. It uses differential sensing

to generate a 5 V bootstrap voltage between the BST and SW pins.

CONTROL SCHEME

It is recommended that a 0.1 µF, X7R or X5R ceramic capacitor

be placed between the BST pin and the SW pin.

The ADP2443 uses a fixed frequency, current mode PWM control

architecture to achieve high efficiency and low noise operation.

OSCILLATOR

The ADP2443 operates at a fixed frequency set by an external

resistor from RT/SYNC to GND. It uses the low side NFET current

for the PWM control as shown in Figure 32. The valley current

information is captured at the end of the off period and combines

with the slope ramp to form the emulated current ramp voltage.

The slope ramp voltage is controlled by the resistor between

RAMP and PVIN. At the start of each oscillator cycle, the high-

side NFET turns on and the inductor current increases until the

emulated current ramp voltage crosses the COMP voltage, which

turns off the high-side NFET and turns on the low-side NFET,

which in turn places a negative voltage across the inductor,

causing a reduction in the inductor current. The low-side NFET

stays on for the remainder of the cycle.

The switching frequency of ADP2443 is controlled by the

RT/SYNC pin. A resistor from RT/SYNC to GND programs the

switching frequency according to the following equation:

168,000

f_SW(kHz) =

R_T(kΩ)

A 280 kΩ resistor sets the frequency to 600 kHz, and a 560 kΩ

resistor sets the frequency to 300 kHz. Figure 33 shows the

typical relationship between f_SWand R_T.

2200

2000

1800

1600

1400

1200

1000

800

PVIN

I

RAMP

V

CLK

PWM

L

RAMP

S

R

Q

IN DH

DL

V

C

OUT

SW

OUT

600

– A

CS

400

R

TOP

200

V

COMP

0

g

m

BOT

0

100

200

300

400

500

(kΩ)

600

700

800

900

R

C

0.6V

R

T

C

Figure 33. Switching Frequency vs. R_T

Figure 32. PWM Control Scheme

SYNCHRONIZATION

PRECISION ENABLE/SHUTDOWN

To synchronize the ADP2443, connect an external clock to the

RT/SYNC pin. The frequency of the external clock can be in the

range of 200 kHz to 1.8 MHz. During synchronization, the reg-

ulator operates in continuous conduction mode (CCM) and the

rising edge of the switching waveform runs 180° out of phase to

the rising edge of the external clock.

The EN input pin has a precision analog threshold of 1.2 V

(typical) with 100 mV of hysteresis. When the enable voltage

exceeds 1.2 V, the regulator turns on; when it falls below 1.1 V

(typical), the regulator turns off. To force the regulator to start

automatically when input power is applied, connect EN to PVIN.

The precision EN pin has an internal pull-down current source

(0.13 µA) that provides a default turn-off when the EN pin is open.

When the ADP2443 is operating in synchronization mode,

a resistor must be connected from the RT/SYNC pin to GND

to program the internal oscillator to run at 80% to 120% of the

external synchronization clock.

When the EN pin voltage exceeds 1.2 V (typical), the ADP2443

is enabled and the internal pull-up current increases to 4 µA, which

allows users to program the PVIN UVLO and hysteresis.

Rev. 0 | Page 13 of 24

ADP2443

Data Sheet

The overcurrent counter increments during this process; otherwise

the overcurrent counter decreases. If the overcurrent counter reaches

10 or the FB voltage drops below 0.2 V after the soft start, the

device enters hiccup mode. During hiccup mode, the high-side

NFET and low-side NFET are both turned off. The device remains

in this mode for seven soft start cycles and then attempts to restart

with soft start. If the current-limit fault is cleared, the device

resumes normal operation; otherwise, it reenters hiccup mode.

SOFT START

The ADP2443 uses the SS pin to program the soft start time.

Place a capacitor between SS and GND; an internal current

charges this capacitor to establish the soft start ramp. Calculate

the soft start time (t_SS) using the following equation:

0.6 V ×C_SS

t_SS

=

I_SS

CYCLE-BY-CYCLE

THRESHOLD

where:

_SSis the soft start capacitance.

_SSis the typical soft start pull-up current (3.4 µA).

PVIN

CURRENT-LIMIT

COMPARATOR

C

I

RAMP

V

RAMP

HICCUP

CONTROL

BLOCK

If the output voltage is precharged before power up, the ADP2443

prevents the low-side MOSFET from turning on until the soft

start voltage exceeds the voltage on the FB pin.

R

C

RAMP

V

FB

PWM

SW

POWER GOOD

– A

CS

The power-good pin (PGOOD) is an active high, open-drain

output that requires an external resistor to pull it up to a

voltage. A logic high on the PGOOD pin indicates that the

voltage on the FB pin (and therefore the output voltage) is

within regulation.

Figure 35. Current-Limit Circuit

CYCLE-BY-CYCLE PEAK

CURRENT-LIMIT THRESHOLD

V

RAMP

The power-good circuitry monitors the output voltage on the

FB pin and compares it to the rising and falling thresholds that

are specified in Table 1. If the rising output voltage exceeds the

target value, the PGOOD pin is held low. The PGOOD pin

continues to be held low until the falling output voltage returns

to the target value.

PWM

VALLEY

CURRENT-LIMIT

THRESHOLD

Figure 36. Cycle-By-Cycle Current-Limit Waveform

If the output voltage falls below the target output voltage, the

PGOOD pin is held low. The PGOOD pin continues to be held

low until the rising output voltage returns to the target value.

OVERVOLTAGE PROTECTION (OVP)

The ADP2443 includes an OVP feature to protect the regulator

against an output short to a higher voltage supply or when a strong

load disconnect transient occurs. If the feedback voltage increases

to 0.7 V, the internal high-side MOSFET and low-side MOSFET

are turned off until the voltage at the FB pin decreases to 0.63 V.

At that time, the ADP2443 resumes normal operation.

The power-good rising and falling thresholds are shown in

Figure 34. There is always a 16-cycle waiting period (deglitch)

before the PGOOD pin is pulled from low to high or from high

to low.

V

RISING

V

FALLING

OUT

UNDERVOLTAGE LOCKOUT (UVLO)

110%

105%

100%

95%

UVLO circuitry is integrated in the ADP2443 to prevent the

occurrence of power-on glitches. If the V_PVINvoltage drops below

3.9 V typical, the device shuts down and both the power switch

and synchronous rectifier turn off. When the V_PVINvoltage rises

again above 4.3 V typical, the soft start period is initiated and

the device is enabled.

90%

PGOOD

16-CYCLE

THERMAL SHUTDOWN

DEGLITCH DEGLITCH

Figure 34. PGOOD Rising and Falling Thresholds

If the ADP2443 junction temperature rises above 150°C, the

internal thermal shutdown circuit turns off the regulator for self

protection. Extreme junction temperatures can be the result of high

current operation, poor PCB layout thermal design, and/or high

ambient temperature. A 25°C hysteresis is included in the thermal

shutdown circuit so that, if an overtemperature event occurs, the

ADP2443 does not return to normal operation until the on-chip

temperature drops below 125°C. Upon recovery, a soft start is

initiated before normal operation begins.

PEAK CURRENT-LIMIT AND SHORT-CIRCUIT

PROTECTION

The ADP2443 uses the emulated current ramp voltage for cycle-

by-cycle current limit protection to prevent current runaway. When

the emulated current ramp voltage reaches the valley current

limit threshold plus the ramp voltage, the high-side MOSFET

turns off and the low-side MOSFET turns on until the next cycle.

Rev. 0 | Page 14 of 24

Data Sheet

ADP2443

APPLICATIONS INFORMATION

R

I

_{DSON_LS}is the low-side MOSFET on resistance.

_{OUT_MIN}is the minimum output current.

R_Lis the series resistance of output inductor.

INPUT CAPACITOR SELECTION

The input capacitor reduces the input voltage ripple caused by

the switch current on PVIN. Place the input capacitor as close

as possible to the PVIN pin. A ceramic capacitor in the 10 μF to

47 μF range is recommended. The loop that is composed of this

input capacitor, the high-side N-MOSFET, and the low-side N-

MOSFET must be kept as small as possible.

The maximum output voltage for a given input voltage and

switching frequency is constrained by the minimum off time

and the maximum duty cycle. The minimum off time is typically

200 ns.

Calculate the maximum output voltage, limited by the minimum

off time at a given input voltage and frequency, using the

following equation:

The voltage rating of the input capacitor must be greater than

the maximum input voltage. The rms current rating of the input

capacitor must be larger than the value calculated from the

following equation:

V

_{OUT_MAX}= V_IN× (1 − t_{MIN_OFF}× f_SW) − (R_{DSON_HS}− R_{DSON_LS}) ×

_{OUT_MAX}× (1 − t_{MIN_OFF}× f_SW) − (R_{DSON_LS}+ R_L) × I_{OUT_MAX}

where:

_{OUT_MAX}is the maximum output voltage.

_{MIN_OFF}is the minimum off time.

I

(2)

I

_{CIN_RMS}= I_OUT×

D × (1 − D)

OUTPUT VOLTAGE SETTING

V

The output voltage of the ADP2443 is set by an external resistor

divider. The resistor values are calculated using

t

I

_{OUT_MAX}is the maximum output current.





R_TOP

R_BOT

As Equation 1 and Equation 2 show, reducing the switching

frequency alleviates the minimum on time and minimum off

time limitations.

V_OUT= 0.6 ×





1 +





To limit output voltage accuracy degradation due to FB bias

current (0.1 µA maximum) to less than 0.5% (maximum),

ensure that R_BOT< 30 kΩ.

INDUCTOR SELECTION

The inductor value is determined by the operating frequency,

input voltage, output voltage, and inductor ripple current. Using

a small inductor results in a faster transient response but degrades

efficiency, due to a larger inductor ripple current; whereas using

a large inductor value results in s smaller ripple current and

better efficiency, but also results in a slower transient response.

Table 5 lists the recommended resistor divider values for

various output voltages.

Table 5. Resistor Divider Values for Various Output Voltages

V_OUT(V)

R_TOP1% (kΩ)

R_BOT1% (kΩ)

1.0

10

15

As a guideline, the inductor ripple current, ΔI_L, is typically set

to one-third of the maximum load current. Calculate the

inductor value using the following equation:

1.2

10

1.5

15

10

1.8

20

10

(V_IN− V_OUT) × D

L =

2.5

3.3

5.0

8.0

10.0

12.0

47.5

10

22

44.2

39.2

52.3

15

2.21

3

3.57

2.49

2.74

∆I_L× f_SW

where:

_INis the input voltage.

_OUTis the output voltage.

D is the duty cycle.

V

ΔI_Lis the inductor current ripple.

VOLTAGE CONVERSION LIMITATIONS

f_SWis the switching frequency.

The minimum output voltage for a given input voltage and

switching frequency is constrained by the minimum on time.

The minimum on time of the ADP2443 is typically 50 ns.

Calculate the minimum output voltage at a given input voltage

and frequency using the following equation:

V_OUT

D =

V_IN

Calculate the peak inductor current using

∆I_L

2

I

_PEAK= I_OUT+

V

_{OUT_MIN}= V_IN× t_{MIN_ON}× f_SW− (R_{DSON_HS}− R_{DSON_LS}) ×

_{OUT_MIN}× t_{MIN_ON}× f_SW− (R_{DSON_LS}+ R_L) × I_{OUT_MIN}

where:

_{OUT_MIN}is the minimum output voltage.

_{MIN_ON}is the minimum on time.

_SWis the switching frequency.

I

(1)

The saturation current (I_SAT) of the inductor must be larger than the

peak inductor current. For ferrite core inductors with a quick

saturation characteristic, the saturation current rating of the

inductor must be greater than the current limit threshold of the

switch, which prevents the inductor from reaching saturation.

V

t

f

R_{DSON_HS}is the high-side MOSFET on resistance.

Rev. 0 | Page 15 of 24

ADP2443

Data Sheet

Calculate the rms current of the inductor from the following

equation:

Shielded ferrite core materials are recommended for low core

loss and low EMI. Table 6 lists recommended inductors.

2

∆I_L

2

I_RMS

=

I_OUT

+

12

Table 6. Recommended Inductors

Vendor

Part Number

Value (µH)

0.75

1.0

1.5

2.2

3.3

4.7

5.6

6.8

10

I_SAT(A)

10.9

9.5

13.7

11.4

9.8

8.2

7.9

7.1

6.1

19.8

18.5

23

I_RMS(A)

10.7

9.5

14.6

11.6

9.0

8.0

7.3

7.1

5.2

17.7

13

18

16

14

10

8

11

10

9

DC Resistance (DCR) (mΩ)

Toko

FDVE0630-R75M

FDVE0630-1R0M

FDVE1040-1R5M

FDVE1040-2R2M

FDVE1040-3R3M

FDVE1040-4R7M

FDVE1040-5R6M

FDVE1040-6R8M

FDVE1040-100M

XAL5030-601ME

XAL5030-801ME

XAL6030-102ME

XAL6030-122ME

XAL6030-182ME

XAL6030-222ME

XAL6030-332ME

XAL6060-472ME

XAL6060-562ME

XAL6060-682ME

XAL6060-822ME

XAL6060-103ME

XAL6060-153ME

XAL6060-223ME

744 333 0068

6.2

8.5

4.6

6.8

10.1

13.8

18.0

20.2

34.1

4.52

5.65

6.18

7.5

10.5

14.0

20.8

16.4

17.8

20.8

26.4

29.8

43.8

60.6

1.35

2.5

3.7

5.4

8.2

13.2

20.7

4.5

4.9

6.5

9

12

20.9

30.8

51.5

63

CoilCraft

0.6

0.8

1.0

1.2

1.8

2.2

3.3

4.7

5.6

6.8

8.2

10

22

18.2

15.9

12.2

10.5

9.9

9.2

8.4

7.6

5.8

5.6

38

36

27.5

27

22

15.5

15

8

7

6

5

15

22

Würth Elektronik

0.68

0.82

1.0

1.5

2.2

3.3

4.7

6.8

8.2

10

0.68

0.82

1.0

1.5

2.2

3.3

4.7

6.8

8.2

10

20

18

16.5

14

13

11.5

9

12

11.3

10

8

7.5

6

744 333 0082

744 333 0100

744 333 0150

744 333 0220

744 333 0330

744 333 0470

744 333 0680

744 333 0820

11

8

26

744 333 100 0

744 373 490 068

744 373 490 082

744 373 490 10

744 373 490 15

744 373 490 22

744 373 490 33

744 373 490 47

744 373 490 68

744 373 490 82

744 373 491 00

744 373 492 20

25

19.5

14.5

14

12

11

9.5

9

8

5

3.5

3.3

3.2

2.1

69

170

22

6.5

Rev. 0 | Page 16 of 24

Data Sheet

ADP2443

OUTPUT CAPACITOR SELECTION

PROGRAMMING INPUT VOLTAGE UVLO

The output capacitor selection affects the output ripple voltage

load step transient and the loop stability of the regulator.

The ADP2443 has a precision enable input to program the

UVLO threshold of the input voltage (see Figure 37).

For example, during a load step transient where the load is

suddenly increased, the output capacitor supplies the load until

the control loop can ramp up the inductor current. The delay

caused by the control loop causes the output to undershoot.

Calculate the output capacitance that is required to satisfy the

voltage droop requirement using the following equation:

ADP2443

PVIN

4µA

R

TOP_EN

EN

1.2V

0.13µA

BOT_EN

EN CMP

2

K_UV× ∆I_STEP× L

2 ×(V_IN−V_OUT)× ∆V_{OUT _UV}

Figure 37. Programming the Input Voltage UVLO

Use the following equation to calculate R_{TOP_EN}and R_{BOT_EN}

1.1V ×V_{IN _ RISING}−1.2 V ×V_{IN _ FALLING}

C_{OUT_UV}

where:

_UVis a factor, with a typical setting of K_UV= 2.

=

:

K

R_{TOP _ EN}

=

ΔI_STEPis the load step.

ΔV_{OUT_UV}is the allowable undershoot on the output voltage.

1.1 V ×0.13µA +1.2 V ×3.87 µA

where:

Another example occurs when a load is suddenly removed from

the output, and the energy stored in the inductor rushes into

the output capacitor, causing the output to overshoot.

V_{IN_RISING}is the V_INrising threshold.

V_{IN_FALLING}is the V_INfalling threshold.

1.2 V × R_{TOP _ EN}

Calculate the output capacitance that is required to meet the

overshoot requirement using the following equation:

R_{BOT _ EN}

=

V_{IN _ RISING}− R_{TOP _ EN}×0.13µA −1.2 V

2

K_OV× ∆I_STEP× L

SLOPE COMPENSATION SETTING

C_{OUT_OV}

=

2

The slope compensation is necessary in a current mode control

architecture to prevent subharmonic oscillation and to maintain a

stable output. The ADP2443 uses the emulated current mode

and the slope compensation is implemented by connecting a

resistor (R_RAMP) between the RAMP pin and PVIN pin.

(V_OUT+ ∆V_{OUT _ OV}) − V_OUT

where:

_OVis a factor, with a typical setting of K_OV= 2.

ΔV_{OUT_OV}is the allowable overshoot on the output voltage.

K

The output ripple is determined by the effective series resistance

(ESR) and the value of the capacitance. Use the following equation

to select a capacitor that can meet the output ripple requirements:

Theoretically, an extra slope of V_OUT/(2 × L) is enough to

stabilize the system. To guarantee that any noise is decimated in

one cycle and the system is stable from subharmonic oscillation,

the ADP2443 uses an extra slope of V_OUT/L.

∆I_L

C_{OUT_RIPPLE}

=

8 × f_SW× ∆V_{OUT _ RIPPLE}

Calculate the ramp resistor value, R_RAMP, using the following

equation:

where ΔV_{OUT_RIPPLE}is the allowable output ripple voltage.

∆V_{OUT _ RIPPLE}

L ×10¹²

3.9

R_RAMP

=

R_ESR

=

∆I_L

where L is the inductor value.

where R_ESRis the equivalent series resistance of the output

capacitor in ohms (Ω).

COMPENSATION DESIGN

The ADP2443 uses an emulated current mode control

architecture that combines the fast line transient response of

traditional peak current mode with the capability to convert a

high input voltage to a very low output voltage. Furthermore,

the small signal characteristics of the emulated current mode

are almost identical to those of traditional peak current mode.

Therefore, the compensation network design method used in

traditional peak current mode can also be applied to the

emulated current mode control.

Select the largest output capacitance given by C_{OUT_UV}, C_{OUT_OV}

and C_{OUT_RIPPLE}to meet both load transient and output ripple

performance.

,

The selected output capacitor voltage rating must be greater

than the output voltage. The rms current rating of the output

capacitor must be greater than the value that is calculated by

using the following equation:

∆I_L

12

I_{COUT_RMS}

=

The power stage can be simplified as a voltage controlled current

source supplying current to the output capacitor and load resistor.

It is composed of one domain pole and a zero.

Rev. 0 | Page 17 of 24

ADP2443

Data Sheet

The control to output transfer function is based on the following

equations:

1  R_C C_C s

R_C C_C C_CP

 G_VD(s)

s  (1 

 s)

C_C C_CP

























s

1

The following design guideline shows how to select the R_C, C_C,

and C_CPcompensation components for ceramic output

capacitor applications:

2π  f_Z

V

_OUT(s)

G_VD(s) 

 A_VI R 

V_COMP(s)

s

2π  f_P

1. Determine the cross frequency, f_C. Generally, f_Cis between

f_SW/12 and f_SW/6.

2. Calculate R_Cusing the following equation:

where:

A_VI= 10 A/V.

R is the load resistance.

2   V_OUT C_OUT f_C

R_C



1

0.6 V  g_m A_VI

f_Z



2π  R_ESRC_OUT

3. Place the compensation zero at the domain pole, f_P; then

determine C_Cusing the following equation:

where:

_ESRis the ESR of the output capacitor.

R

(R  R_ESR)C_OUT

C_OUTis the output capacitance.

C_C



R_C

1

f_P

4. C_CPis optional. It can be used to cancel the zero caused by

the ESR of the output capacitor.

2π(R  R_ESR)C_OUT

The ADP2443 uses a transconductance amplifier for the error

amplifier and to compensate the system. Figure 38 shows the

simplified, peak current mode control, small signal circuit.

R_ESRC_OUT

C_CP



R_C

V

OUT

ADIsimPOWER DESIGN TOOL

V

OUT

R

The ADP2443 is supported by the ADIsimPower™ design tool

set. ADIsimPower is a collection of tools that produce complete

power designs that are optimized for a specific design goal. The

tools enable the user to generate a full schematic and bill of

materials and calculate performance in minutes. ADIsimPower

can optimize designs for cost, area, efficiency, and component

count, while taking into consideration the operating conditions

and limitations of the IC and all real external components. For

more information about the ADIsimPower design tools, refer to

www.analog.com/ADIsimPower. The tool set is available from

this website, and users can request an unpopulated board.

TOP

C

OUT

ESR

A

V

VI

COMP

g

m

R

C

BOT

CP

R

C

Figure 38. Simplified Peak Current Mode Control, Small Signal Circuit

The compensation components, R_Cand C_C, contribute a zero,

and the optional C_CPand R_Ccontribute an optional pole.

The closed-loop transfer equation is as follows:

R_BOT

R_BOT R_TOPC_C C_CP

g_m

T_V(s) 



Rev. 0 | Page 18 of 24

Data Sheet

ADP2443

DESIGN EXAMPLE

ADP2443

V

= 24V

IN

L

PVIN

EN

BST

SW

C

BST

0.1µF

6.8µH

C

10µF

50V

IN

V

= 5V

OUT

R

RAMP

1.5MΩ

C

OUT

R

TOP

47µF

16V

RAMP

PGOOD

RT/SYNC

VREG

SS

22kΩ

1%

R

T

280kΩ

FB

COMP

R

BOT

3kΩ

1%

C

VREG

R

C

20kΩ

C

1µF

SS

C

CP

22nF

3.3pF

C

GND PGND

2.7nF

Figure 39. Schematic for Design Example

This section describes the procedures for selecting the external

components based on the example specifications that are listed

in Table 7. See Figure 39 for the schematic of this design example.

This calculation results in L = 7.33 μH. Choose the standard

inductor value of 6.8 μH.

The peak-to-peak inductor ripple current can be calculated by

using the following equation:

Table 7. Step-Down DC-to-DC Regulator Requirements

Parameter

Symbol

Specification

V_IN= 24.0 V 10%

V_OUT= 5 V

(V_INV_OUT) D

I_L

Input Voltage

Output Voltage

Output Current

V_IN

V_OUT

I_OUT

L f_SW

This calculation results in ΔI_L= 0.97 A.

I_OUT= 3 A

Output Voltage Ripple ∆V_{OUT_RIPPLE}

Load Transient I_LOAD

Switching Frequency f_SW

∆V_{OUT_RIPPLE}= 50 mV

5%ꢀ 0.5 A to 2.5 Aꢀ 2 A/μs

f_SW= 600 kHz

Use the following equation to calculate the peak inductor current:

I_L

I_PEAK I_OUT



2

OUTPUT VOLTAGE SETTING

This calculation results in I_PEAK= 3.49 A.

Choose a 22 kΩ resistor as the top feedback resistor (R_TOP),

and calculate the bottom feedback resistor (R_BOT) by using the

following equation:

Use the following equation to calculate the rms current flowing

through the inductor:

2

I_L

2

I_RMS



I_OUT











0.6

V_OUT 0.6

12

R_BOT R_TOP











This calculation results in I_RMS= 3.013 A.

To set the output voltage to 5 V, the resistors values are as

follows: R_TOP= 22 kΩ and R_BOT= 3 kΩ.

Based on the calculated current value, select an inductor with

a minimum rms current rating of 3.013 A and a minimum

saturation current rating of 3.49 A.

FREQUENCY SETTING

However, to protect the inductor from reaching its saturation

point under the current-limit condition, the inductor must be

rated for at least a 5.1 A saturation current for reliable operation.

To set the switching frequency to 600 kHz, connect a 280 kΩ

resistor from the RT/SYNC pin to GND.

INDUCTOR SELECTION

Based on the requirements described previously, select a 6.8 μH

inductor, such as the FDVE1040-6R8M from Toko, which has

a 20.2 mΩ DCR and an 7.1 A saturation current.

The peak-to-peak inductor ripple current, ΔI_L, is set to 30% of

the maximum output current. Use the following equation to

estimate the inductor value:

(V_INV_OUT) D

L 

I_L f_SW

where:

V

_IN= 24 V.

_OUT= 5 V.

D = 0.208.

ΔI_L= 0.9 A.

f

_SW= 600 kHz.

Rev. 0 | Page 19 of 24

ADP2443

Data Sheet

OUTPUT CAPACITOR SELECTION

COMPENSATION COMPONENTS

The output capacitor is required to meet both the output voltage

ripple and load transient response requirements.

For better load transient and stability performance, set the cross

frequency, f_C, to f_SW/10. In this case, f_SWis running at 600 kHz;

therefore, the f_Cis set to 60 kHz.

To meet the output voltage ripple requirement, use the following

equation to calculate the ESR and capacitance value of the output

capacitor:

The 47 µF ceramic output capacitor has a derated value of 32 µF.

2 × π × 5 V × 32 µF × 60 kHz

R_C=

= 19.5 kΩ

∆I_L

0.6 V × 515 µs ×10 A/V

C_{OUT _ RIPPLE}

=

8 × f_SW× ∆V_{OUT _ RIPPLE}

∆V_{OUT _ RIPPLE}

1.667 Ω + 0.002 Ω × 32 µF

C_C

=

= 2739 pF

19.5 kΩ

R_ESR

=

∆I_L

0.002 Ω × 32 µF

C_CP

=

= 3.3 pF

This calculation results in C_{OUT_RIPPLE}= 4.04 μF, and R_ESR= 51.5 mΩ.

19.5 kΩ

To meet the 5% overshoot and undershoot transient

requirements, use the following equations to calculate the

capacitance:

Choose standard components, as follows: R_C= 20 kΩ,

C_C= 2700 pF, and C_CP= 3.3 pF.

Figure 40 shows the Bode plot at a 3 A load current. The cross

frequency is 59 kHz, and the phase margin is 66°.

K_OV× ∆I_STEP²× L

C_{OUT _OV}

=

2

(V_OUT+ ∆V_{OUT _OV}) −V_OUT

60

180

144

108

72

48

where:

_OV= K_UV= 2 are the coefficients for estimation purposes.

K

36

∆I_STEP= 2 A is the load transient step.

∆V_{OUT_OV}= 5% V_OUTis the overshoot voltage.

24

PHASE

12

36

K_UV× ∆I_STEP²× L

0

C_{OUT _UV}

=

MAGNITUDE

2×(V_IN−V_OUT)× ∆V_{OUT _UV}

–12

–24

–36

–48

–60

–36

–72

–108

–144

–180

where ∆V_{OUT_UV}= 5% V_OUTis the undershoot voltage.

This calculation results in C_{OUT_OV}= 21.2 μF, and C_{OUT_UV}= 5.7 μF.

According to the calculation, the output capacitance must be

greater than 21.2 μF, and the ESR of the output capacitor must be

smaller than 51.5 mΩ. It is recommended that one 47 μF/X5R/16 V

ceramic capacitor be used, such as the GRM32ER61C476KE15K

from Murata, with an ESR of 2 mΩ.

1k

10k

100k

FREQUENCY (Hz)

1M

Figure 40. Bode Plot at 3 A

SOFT START TIME PROGRAM

SLOPE COMPENSATION SETTING

The soft start feature allows the output voltage to ramp up in a

controlled manner, eliminating output voltage overshoot during

soft start and limiting the inrush current. Set the soft start time

to 4 ms.

The ramp resistor, R_RAMP, determines the slope compensation.

Use the following equation to calculate the R_RAMPvalue:

6.8 μH ×10¹²

L ×10¹²

R_RAMP

=

= 1.74 MΩ

t_{SS _ EXT}× I_SS4 ms × 3.4 µA

3.9

C_SS

=

= 22.7 nF

0.6 V

Choose a standard component value, as follows: R_RAMP= 1.5 MΩ.

Choose a standard component value, as follows: C_SS= 22 nF.

INPUT CAPACITOR SELECTION

A minimum 10 μF ceramic capacitor must be placed near the

PVIN pin. In this application, it is recommended that one 10 μF,

X5R, 50 V ceramic capacitor be used.

Rev. 0 | Page 20 of 24

Data Sheet

ADP2443

RECOMMENDED EXTERNAL COMPONENTS

Table 8. Recommended External Components for Typical Applications with a 3 A Output Current

f_SW(kHz) V_IN(V) V_OUT(V)

L (µH) C_OUT(µF)¹

R_TOP(kΩ)

R_BOT(kΩ)

R_RAMP(kΩ) R_C(kΩ)

C_C(pF)

5600

2700

1200

C_CP(pF)

120

100

82

300

12

1

3.3

4.7

6.8

8.2

10

470 + 100

330 + 100

330

10

15

845

33.2

29.4

30.9

24.9

28

1.2

1.5

1.8

2.5

3.3

5

10

845

15

10

1000

1500

2700

845

220

20

10

3 × 100

2 × 100

2 × 47

470 + 100

330

47.5

10

15

12

2.21

3

24.9

18.7

33.2

40.2

30.9

37.4

34.8

37.4

28

10

22

6.8

120

100

82

24

1

3.3

4.7

6.8

8.2

10

15

1.2

1.5

1.8

2.5

3.3

5

10

1000

1500

2700

3300

5600

383

15

10

330

20

10

220

47.5

10

15

68

3 × 100

2 × 100

2 × 47

47

2.21

3

10

15

22

6.8

3.9

2.7

56

47

10

8

22

44.2

52.3

10

15

3.57

2.74

15

10

22.1

10.5

31.6

37.4

34

12

1

22

600

12

24

1.5

2.2

3.3

4.7

2.2

3.3

4.7

6.8

10

220 + 47

3 × 100

100 + 47

2 × 47

47

1.2

1.5

1.8

2.5

3.3

5

562

20

47.5

10

15

2.21

3

845

41.2

28

8.2

6.8

4.7

3.3

47

1000

562

24.9

18.7

37.4

34

22

1.2

1.5

1.8

2.5

3.3

5

220 + 47

3 × 100

2 × 100

2 × 47

100

10

15

20

47.5

10

15

2.21

3

3.57

2.74

10

562

10

845

41.2

37.4

24.9

28

22.1

21

8.2

6.8

4.7

3.3

1.8

1.2

6.8

5.6

4.7

3.3

2.2

1.5

3.3

2.2

1.5

1

1000

1500

2700

255

22

8

47

44.2

52.3

10

12

1.2

1.5

1.8

2.5

3.3

5

10

47

1200

12

24

1

2 × 100

2 × 47

100 + 47

100

36.5

22.6

41.2

37.4

24.9

37.4

24.9

37.4

44.2

42.2

1

15

10

255

1.5

2.2

3.3

4.7

20

10

383

47.5

10

15

383

47

2.21

3

562

47

22

562

2.5

3.3

5

100

47.5

10

15

562

47

2.21

3

562

47

22

845

8

47

44.2

52.3

3.57

2.74

1000

12

47

0.5

¹680 μF: 4 V, KEMET T520Y687M004ATE010; 470 μF: 6.3 V, KEMET T520X477M006ATE010; 330 μF: 6.3 V, KEMET T520D337M006ATE009; 220 μF: 6.3 V, KEMET

T520D227M006ATE009; 100 μF: 6.3 V, X5R, Murata GRM32ER60J107ME20; 47 μF: 16 V, X5R, Murata GRM32ER61C476KE15K.

Rev. 0 | Page 21 of 24

ADP2443

Data Sheet

PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS

Good PCB layout is essential for obtaining the best performance

from the ADP2443. Poor PCB layout can degrade the output

regulation, as well as the electromagnetic interface (EMI) and

electromagnetic compatibility (EMC) performance. Figure 42

shows an example of a good PCB layout for the ADP2443. For

optimum layout, refer to the following guidelines:



Connect the exposed GND pad of the ADP2443 to a large,

external copper ground plane to maximize its power

dissipation capability and minimize junction temperature.

In addition, connect the exposed SW pad to the SW pins

of the ADP2443, using short, wide traces; or connect the

exposed SW pad to a large copper plane of the switching

node for high current flow.

Place the feedback resistor divider as close as possible to

the FB pin to prevent noise pickup. Minimize the length of

the trace that connects the top of the feedback resistor divider

to the output while keeping the trace away from the high

current traces and the switching node to avoid noise

pickup. To reduce noise pickup further, place an analog

ground plane on either side of the FB trace and ensure that

the trace is as short as possible to reduce the parasitic

capacitance pickup.



Use separate analog ground planes and power ground planes.

Connect the ground reference of sensitive analog circuitry,

such as output voltage divider components, compensation

components, frequency setting components, and soft start

capacitor, to analog ground (GND). In addition, connect the

ground reference of the power components, such as input

and output capacitors, to power ground (PGND). Connect

both ground planes to the exposed GND pad of the

ADP2443.



Place the input capacitor, inductor, and output capacitor as

close as possible to the IC, and use short traces.

ADP2443

Ensure that the high current loop traces are as short and as

wide as possible. Make the high current path from the input

capacitor through the inductor, the output capacitor, and the

power ground plane back to the input capacitor as short as

possible. To accomplish this, ensure that the input and output

capacitors share a common power ground plane.

V

IN

PVIN

BST

SW

C

L

BST

C

IN

V

EN

OUT

R

C

RAMP

OUT

R

TOP

RAMP

FB

COMP

SS

PGOOD

RT/SYNC

VREG

R

C

R

C

R

BOT

T

C

VREG

SS

C

In addition, ensure that the high current path from the power

ground plane through the inductor and output capacitor

back to the power ground plane is as short as possible by

tying the PGND pins of the ADP2443 to the PGND plane

as close as possible to the input and output capacitors.

GND PGND

Figure 41. High Current Path in the PCB Circuit

ANALOG GROUND PLANE

VIA

BOTTOM LAYER TRACE

COPPER PLANE

R

RAMP

PVIN

COMP

PVIN

R

TOP

GND

FB

INPUT

BYPASS CAP BULK CAP

VREG

PVIN

BST

C

VREG

GND

SW

C

BST

SW

PGND

SW

INDUCTOR

OUTPUT

CAPACITOR

POWER GROUND PLANE

VOUT

Figure 42. Recommended PCB Layout

Rev. 0 | Page 22 of 24

Data Sheet

ADP2443

TYPICAL APPLICATIONS CIRCUITS

ADP2443

V

= 24V

IN

L

C

BST

0.1µF

PVIN

EN

BST

SW

4.7µH

V

= 3.3V

OUT

C

IN

10µF

50V

C

47µF

6.3V

C

R

OUT1

OUT2

47µF

6.3V

RAMP

1MΩ

R

10kΩ

TOP

RAMP

1%

PGOOD

R

PGOOD

100kΩ

FB

VREG

RT/SYNC

COMP

SS

R

C

R

BOT

C

4.7pF

CP

26.7kΩ

C

2.7nF

2.21kΩ

1%

C

22nF

C

R

T

280kΩ

SS

VREG

1µF

C

GND PGND

Figure 43. Typical Application Circuit, V_IN= 24 V, V_OUT= 3.3 V, I_OUT= 3A, f_SW= 600 kHz

ADP2443

V

= 24V

IN

L

C

BST

0.1µF

PVIN

EN

BST

SW

2.2µH

V

= 1.2V

R

C

OUT

C

TOP_EN

84.5kΩ

IN

R

RAMP

10µF

50V

C

220µF

6.3V

499kΩ

OUT1

OUT2

R

10kΩ

R

TOP

BOT_EN

100µF

6.3V

5.36kΩ

1%

PGOOD

RAMP

FB

VREG

COMP

SS

R

C

R

RT/SYNC

C

BOT

CP

56pF

34.8kΩ

10kΩ

1%

C

47nF

C

3.3nF

R

SS

VREG

1µF

T

GND PGND

340kΩ

Figure 44. Programming Input Voltage UVLO Rising Threshold at 20 V, Falling Threshold at 18 V, V_IN= 24 V, V_OUT= 1.2 V, I_OUT= 3 A, f_SW= 500 kHz

ADP2443

V

= 24V

IN

L

C

0.1µF

PVIN

EN

BST

SW

BST

3.3µH

V

= 5V

C

OUT

IN

10µF

50V

C

47µF

16V

OUT

R

22kΩ

R

TOP

RAMP

845kΩ

RAMP

PGOOD

1%

C

1µF

R

VREG

PGOOD

FB

100kΩ

VREG

RT/SYNC

SS

COMP

R

C

R

3kΩ

1%

C

1.5pF

BOT

CP

40.2kΩ

R

T

140kΩ

C

1.2nF

C

GND PGND

C

22nF

SS

Figure 45. Typical Application Circuit, V_IN= 24 V, V_OUT= 5 V, I_OUT= 3 A, f_SW= 1.2 MHz

Rev. 0 | Page 23 of 24

ADP2443

Data Sheet

OUTLINE DIMENSIONS

4.10

4.00 SQ

3.90

2.80

2.70

2.60

0.20

MIN

0.20 MIN

PIN 1

INDICATOR

1.50

PIN 1

INDICATOR

0.20

MIN

19

24

18

1.40

1

1.30

0.45

EXPOSED

PAD

0.35

0.25

0.50

BSC

EXPOSED

PAD

1.05

0.95

0.85

6

13

7

12

0.50

0.40

0.30

TOP VIEW

BOTTOM VIEW

0.20

MIN

0.80

0.75

0.70

FOR PROPER CONNECTION OF

THE EXPOSED PADS, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.30

0.25

0.20

0.203 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WGGD .

Figure 46. 24-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm × 4 mm Body and 0.75 mm Package Height

(CP-24-12)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

−40°C to +125°C

Output Voltage

Package Description

Package Option

CP-24-12

ADP2443ACPZN-R7

ADP2443-EVALZ

Adjustable

24-Lead LFCSP

Evaluation Board

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D14794-0-9/16(0)

Rev. 0 | Page 24 of 24


型号：	ADP2443ACPZN-R7
厂家：	ADI
描述：	3 A, 36 V, Synchronous Step-Down DC-to-DC Regulator 开关输出元件
文件：	总25页 (文件大小：734K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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