ADP2140ACPZ1233R7 [ADI]
3 MHz, 600 mA, Low Quiescent Current Buck with 300 mA LDO Regulator;
| 型号： | ADP2140ACPZ1233R7 |
| 厂家： | 
ADI |
| 描述： | 3 MHz, 600 mA, Low Quiescent Current Buck with 300 mA LDO Regulator 开关 光电二极管 |
| 文件： | 总32页 (文件大小：2811K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3 MHz, 600 mA, Low Quiescent Current
Buck with 300 mA LDO Regulator
Data Sheet
ADP2140
FEATURES
TYPICAL APPLICATION CIRCUITS
V
= 3.6V
Input voltage range: 2.3 V to 5.5 V
LDO input (VIN2) 1.65 V to 5.5 V
Buck output voltage range: 1.0 V to 3.3 V
LDO output voltage range: 0.8 V to 3.3 V
Buck output current: 600 mA
IN1
+
C
10µF
IN
ADP2140
100kΩ
PG
10
9
1
2
3
4
5
VIN1
PGND
1µH
V
= 1.2V
OUT
PG
SW
8
+
C
EN1
EN2
EN1
AGND
FB
OUT
10µF
LDO output current: 300 mA
7
EN2
V
= 1.8V
OUT2
6
LDO quiescent current: 22 μA with zero load
Buck quiescent current: 20 μA in PSM mode
Low shutdown current: <0.3 μA
Low LDO dropout 110 mV @ 300 mA load
High LDO PSRR
VOUT2
VIN2
+
C
OUT2
1µF
Figure 1. ADP2140 with LDO Connected to VIN1
V
= 3.3V
IN1
65 dB @ 10 kHz at VOUT2 = 1.2 V
+
C
IN
10µF
ADP2140
55 dB @ 100 kHz at VOUT2 = 1.2 V
Low noise LDO: 40 μV rms at VOUT2 = 1.2 V
Initial accuracy: 1ꢀ
Current-limit and thermal overload protection
Power-good indicator
100kΩ
PG
10
9
1
2
3
4
5
VIN1
PGND
1µH
V
= 1.8V
OUT
PG
SW
8
+
C
EN1
EN2
EN1
AGND
FB
OUT
10µF
7
EN2
V
= 1.2V
OUT2
6
VOUT2
VIN2
+
Optional enable sequencing
10-lead 0.75 mm × 3 mm × 3 mm LFCSP package
C
OUT2
1µF
Figure 2. ADP2140 with LDO Connected to Buck Output
APPLICATIONS
Mobile phones
Personal media players
Digital camera and audio devices
Portable and battery-powered equipment
GENERAL DESCRIPTION
The ADP2140 includes a high efficiency, low quiescent 600 mA
stepdown dc-to-dc converter and a 300 mA LDO packaged in a
small 10-lead 3 mm × 3 mm LFCSP. The total solution requires
only four tiny external components.
ADP2140 includes a power-good pin, soft start, and internal
compensation. Numerous power sequencing options are user-
selectable through two enable inputs. In autosequencing mode,
the highest voltage output enables on the rising edge of EN1.
During logic controlled shutdown, the input disconnects from
the output and draws less than 300 nA from the input source.
Other key features include: undervoltage lockout to prevent deep
battery discharge, soft start to prevent input current overshoot
at startup, and both short-circuit protection and thermal overload
protection circuits to prevent damage in adverse conditions.
The buck regulator uses a proprietary high speed current-
mode, constant frequency, pulse-width modulation (PWM)
control scheme for excellent stability and transient response. To
ensure the longest battery life in portable applications, the
ADP2140 has a power saving variable frequency mode to reduce
switching frequency under light loads.
When the ADP2140 is used with two 0603 capacitors, one 0402
capacitor, one 0402 resistor, and one 0805 chip inductor, the
total solution size is approximately 90 mm2 resulting in the smallest
footprint solution to meet a variety of portable applications.
The LDO is a low quiescent current, low dropout linear regulator
designed to operate in a split supply mode with VIN2 as low as
1.65 V. The low input voltage minimum allows the LDO to be
powered from the output of the buck regulator increasing effi-
ciency and reducing power dissipation. The ADP2140 runs from
input voltages of 2.3 V to 5.5 V allowing single Li+/Li− polymer
cell, multiple alkaline/NiMH cell, PCMCIA, and other standard
power sources.
Rev. B
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ADP2140
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Short-Circuit Protection............................................................ 20
Undervoltage Lockout ............................................................... 20
Thermal Protection.................................................................... 20
Soft Start ...................................................................................... 20
Current Limit.............................................................................. 20
Power-Good Pin......................................................................... 20
LDO Section ............................................................................... 20
Applications Information.............................................................. 21
Power Sequencing ...................................................................... 21
Power-Good Function............................................................... 24
External Component Selection ................................................ 24
Selecting the Inductor................................................................ 24
Output Capacitor........................................................................ 24
Input Capacitor........................................................................... 24
Efficiency..................................................................................... 25
Recommended Buck External Components .......................... 25
LDO Capacitor Selection .......................................................... 26
LDO as a Postregulator to Reduce Buck Output Noise ........ 26
Thermal Considerations................................................................ 28
PCB Layout Considerations...................................................... 29
Outline Dimensions....................................................................... 30
Ordering Guide .......................................................................... 30
Applications....................................................................................... 1
Typical Application Circuits............................................................ 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Recommended Specifications: Capacitors and Inductor........ 4
Absolute Maximum Ratings............................................................ 5
Thermal Data................................................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Buck Output.................................................................................. 7
LDO Output................................................................................ 14
Theory of Operation ...................................................................... 19
Buck Section................................................................................ 19
Control Scheme .......................................................................... 19
PWM Operation......................................................................... 19
PSM Operation ........................................................................... 19
Pulse Skipping Threshold.......................................................... 19
Selected Features............................................................................. 20
REVISION HISTORY
10/2019—Rev. A to Rev. B
Changes to Output Capacitor Section ......................................... 24
Updated Outline Dimensions....................................................... 30
Changes to Ordering Guide .......................................................... 30
9/2012—Rev. 0 to Rev. A
Updated Outline Dimensions....................................................... 30
Changes to Ordering Guide .......................................................... 30
6/2010—Revision 0: Initial Version
Rev. B | Page 2 of 32
Data Sheet
ADP2140
SPECIFICATIONS
VIN1 = 3.6 V, VIN2 = VOUT2 + 0.3 V or 1.65 V, whichever is greater; 5 V EN1 = EN2 = VIN1; IOUT = 200 mA, IOUT2 = 10 mA, CIN = 10 μF,
C
OUT = 10 µF, COUT2 = 1 µF, LOUT = 1 μH; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical
specifications, unless otherwise noted.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
BUCK SECTION
Input Voltage Range
Buck Output Accuracy
VIN1
VOUT
2.3
−1.5
−2.5
5.5
+1.5
+2.5
V
%
%
IOUT = 10 mA
VIN1 = 2.3V or (VOUT + 0.5V) to 5.5 V, IOUT = 1 mA to
600 mA
Transient Load Regulation
Transient Line Regulation
VTR-LOAD
VOUT = 1.8 V
Load = 50 mA to 250 mA, rise/fall time = 200 ns
Load = 200 mA to 600 mA, rise/fall time = 200 ns
Line transient = 4 V to 5 V, 4 μs rise time
VOUT = 1.0 V
VOUT = 1.8 V
VOUT = 3.3 V
75
75
mV
mV
VTR-LINE
40
25
25
100
mV
mV
mV
mA
mA
mA
PWM To PSM Threshold
Output Current
Current Limit
VIN1 = 2.3 V or (VOUT + 0.5 V) to 5.5 V
IOUT
ILIM
600
VIN1 = 2.3 V or (VOUT + 0.5 V) to 5.5 V
1100 1300
Switch On Resistance
PFET
NFET
Switch Leakage Current
Quiescent Current
Minimum On Time
Oscillator Frequency
Frequency Foldback Threshold VFOLD
Start-Up Time1
Soft Start Time2
RPFET
RNFET
ILEAK-SW
IQ
ON-TIMEMIN
FREQ
VIN1 = 2.3 V to 5.5 V
VIN1 = 2.3 V to 5.5 V
EN1 = GND, VIN1 = 5.5 V, and SW = 0 V
No load, device not switching
250
250
−1
mΩ
mΩ
μA
μA
ns
MHz
%
µs
20
30
70
2.55
3.0
50
3.15
Output voltage where fSW ≤ 50% of nominal frequency
VOUT = 1.8 V, 600 mA load
VOUT = 1.8 V, 600 mA load
tSTART-UP
SSTIME
70
150
μs
LDO SECTION
Input Voltage Range
LDO Output Accuracy
VIN2
VOUT2
1.65
−1
5.5
+1
+1.5
V
%
%
IOUT2 = 10 mA, TJ = 25°C
1 mA < IOUT2 < 300 mA, VIN2 = (VOUT2 + 0.3 V) to 5.5 V, TJ −1.5
= 25°C
1 mA < IOUT2 < 300 mA, VIN2 = (VOUT2 + 0.3 V) to 5.5 V
−3
+3
%
Line Regulation
Load Regulation3
Dropout Voltage4
∆VOUT2/∆VIN2 VIN2 = (VOUT2 + 0.3 V) to 5.5 V, IOUT2 = 10 mA
∆VOUT2/∆IOUT2 IOUT2 = 1 mA to 300 mA
−0.05
+0.05 %/V
0.001 0.005 %/mA
VDROPOUT
IOUT2 = 10 mA, VOUT2 = 1.8 V
IOUT2 = 300 mA, VOUT2 = 1.8 V
No load, buck disabled
IOUT2 = 10 mA
4
7
mV
mV
μA
μA
μA
110
22
65
150
200
35
90
220
Ground Current
IAGND
IOUT2 = 300 mA
Power Supply Rejection Ratio
PSRR on VIN2
PSRR
VIN2 = VOUT2 + 1 V, VIN1 = 5 V, IOUT2 = 10 mA
10 kHz, VOUT2 = 1.2 V, 1.8 V, 3.3 V
100 kHz, VOUT2 = 3.3 V
100 kHz, VOUT2 = 1.8 V
100 kHz, VOUT2 = 1.2 V
65
53
54
55
dB
dB
dB
dB
Rev. B | Page 3 of 32
ADP2140
Data Sheet
Parameter
Symbol
Test Conditions/Comments
VIN2 = VIN1 = 5 V, IOUT2 = 10 mA
10 Hz to 100 kHz, VOUT2 = 0.8 V
10 Hz to 100 kHz, VOUT2 = 1.2 V
10 Hz to 100 kHz, VOUT2 = 1.8 V
10 Hz to 100 kHz, VOUT2 = 2.5 V
10 Hz to 100 kHz, VOUT2 = 3.3 V
TJ = 25°C
Min
Typ
Max
Unit
Output Noise
OUTNOISE
29
40
50
66
88
500
µV rms
µV rms
µV rms
µV rms
µV rms
mA
μA
µs
μs
Current Limit
ILIM
360
760
1
Input Leakage Current
Start-Up Time1
Soft Start Time2
ILEAK-LDO
tSTART-UP
SSTIME
EN2 = GND, VIN2 = 5.5 V and VOUT2 = 0 V
VOUT2 = 3.3 V, 300 mA load
VOUT2 = 3.3 V, 300 mA load
70
130
ADDITIONAL FUNCTIONS
Undervoltage Lockout
Input Voltage Rising
Input Voltage Falling
EN Input
UVLO
UVLORISE
UVLOFALL
2.23
2.16
2.3
V
V
2.05
1.0
EN1, EN2 Input Logic High
EN1, EN2 Input Logic Low
EN1, EN2 Input Leakage
VIH
VIL
IEN-LKG
2.3 V ≤ VIN1 ≤ 5.5 V
2.3 V ≤ VIN1 ≤ 5.5 V
EN1, EN2 = VIN1 or GND
EN1, EN2 = VIN1 or GND
V
V
µA
µA
μA
0.27
0.05
0.3
1
1.2
Shutdown Current
Thermal Shutdown
Threshold
ISHUT
VIN1 = 5.5 V, EN1, EN2 = GND, TJ = −40°C to +85°C
TSSD
TJ rising
150
20
°C
°C
Hysteresis
TSSD-HYS
Power Good
Rising Threshold
Falling Threshold
Power-Good Hysteresis
Output Low
Leakage Current
Buck to LDO Delay
Power-Good Delay
PGRISE
PGFALL
PGHYS
VOL
IOH
tDELAY
tRESET
92
86
6
%VOUT
%VOUT
%VOUT
V
μA
ms
ISINK = 4 mA
Power-good pin pull-up voltage = 5.5 V
PWM mode only
0.2
1
5
5
PWM mode only
ms
1 Start-up time is defined as the time between the rising edge of ENx to VOUTx being at 10% of the VOUTx nominal value.
2 Soft start time is defined as the time between VOUTx being at 10% to VOUTx being at 90% of the VOUTx nominal value.
3 Based on an endpoint calculation using 1 mA and 300 mA loads.
4 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 2.3 V.
RECOMMENDED SPECIFICATIONS: CAPACITORS AND INDUCTOR
Table 2.
Parameter
Symbol
Test Conditions/Comments
TA = −40°C to +125°C
Min
Typ
Max
Unit
MINIMUM INPUT AND OUTPUT CAPACITANCE1
Buck
LDO
CMIN
CMIN
7.5
0.7
10
1.0
µF
µF
Ω
Ω
Ω
TA = −40°C to +125°C
CAPACITOR ESR
Buck
LDO
RESR
RESR
0.001
0.001
0.7
0.01
1
MINIMUM INDUCTOR
INDMIN
1
μH
1 The minimum input and output capacitance should be greater than 0.70 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are recommended,
Y5V and Z5U capacitors are not recommended for use with any LDO.
Rev. B | Page 4 of 32
Data Sheet
ADP2140
ABSOLUTE MAXIMUM RATINGS
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of θJA are based on a 4-layer, 4 in. × 3 in. circuit
board. Refer to JESD 51-7 for detailed information on the board
construction.
Table 3.
Parameter
Rating
VIN1, VIN2 to PGND, AGND
VOUT2 to PGND, AGND
SW to PGND, AGND
−0.3 V to +6.5 V
−0.3 V to VIN2
−0.3 V to VIN1
FB to PGND, AGND
PG to PGND, AGND
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−65°C to +150°C
−40°C to +85°C
−40°C to +125°C
JEDEC J-STD-020
EN1, EN2 to PGND, AGND
Storage Temperature Range
Operating Ambient Temperature Range
Operating Junction Temperature Range
Soldering Conditions
For more information, see AN-772 Application Note, A Design
and Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP).
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a 4-layer board. The JESD51-12, Guidelines for
Reporting and Using Package Thermal Information, states that
thermal characterization parameters are not the same as thermal
resistances. ΨJB measures the component power flowing through
multiple thermal paths rather than a single path, as in thermal
resistance, θJB. Therefore, ΨJB thermal paths include convection
from the top of the package as well as radiation from the package,
factors that make ΨJB more useful in real-world applications.
Maximum junction temperature (TJ) is calculated from the
board temperature (TB) and power dissipation (PD) using the
formula
THERMAL DATA
Absolute maximum ratings apply individually only, not in com-
bination. The ADP2140 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that TJ is within the specified temperature
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
need to be derated.
TJ = TB + (PD × ΨJB)
Refer to JESD51-8 and JESD51-12 for more detailed
information about ΨJB.
In applications with moderate power dissipation and low
printed circuit board (PCB) thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long as
the junction temperature is within specification limits. The
junction temperature (TJ) of the device is dependent on the
ambient temperature (TA), the power dissipation of the device
(PD), and the junction-to-ambient thermal resistance of the
package (θJA).
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
θJA
ΨJB
Unit
Maximum junction temperature (TJ) is calculated from the
ambient temperature (TA) and power dissipation (PD) using the
formula
10-Lead 3 mm × 3 mm LFCSP
35.3
16.9
°C/W
ESD CAUTION
TJ = TA + (PD × θJA)
Rev. B | Page 5 of 32
ADP2140
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PGND
1
2
3
4
5
10
VIN1
SW
9
PG
ADP2140
TOP VIEW
AGND
FB
8
EN1
(Not to Scale)
7
EN2
VIN2
6
VOUT2
NOTES
1. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP PACKAGE ENHANCES
THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GROUND
INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD BE
CONNECTED TO THE GROUND PLANE ON THE CIRCUIT BOARD.
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin
Mnemonic
PGND
SW
AGND
FB
Description
1
2
3
4
Power Ground.
Connection from Power MOSFETs to Inductor.
Analog Ground.
Feedback from Buck Output.
LDO Input Voltage.
5
VIN2
6
7
VOUT2
EN2
LDO Output Voltage.
Logic 1 to Enable LDO or No Connect for Autosequencing.
8
EN1
Logic 1 to Enable Buck or Initiate Sequencing. This is a dual function pin and the state of EN2 determines
which function is operational.
9
PG
Power Good. Open-drain output. PG is held low until both output voltages (which includes the external
inductor and capacitor sensed by the FB pin) rise above 92% of nominal value. PG is held high until both
outputs fall below 85% of nominal value.
10
VIN1
EP
Analog Power Input.
Exposed Pad. The exposed pad on the bottom of the LFCSP package enhances thermal performance and is
electrically connected to ground inside the package. It is recommended that the exposed pad be connected
to the ground plane on the circuit board.
Rev. B | Page 6 of 32
Data Sheet
ADP2140
TYPICAL PERFORMANCE CHARACTERISTICS
BUCK OUTPUT
VIN1 = 4 V, V OUT = 1.8 V, IOUT = 10 mA, CIN = COUT = 10 µF, TA = 25°C, unless otherwise noted.
30
25
20
15
10
5
1.82
1.81
1.80
1.79
1.78
1.77
1.76
LOAD CURRENT = 1mA
LOAD CURRENT = 10mA
LOAD CURRENT = 50mA
LOAD CURRENT = 100mA
LOAD CURRENT = 300mA
LOAD CURRENT = 600mA
–40°C
–5°C
+25°C
+85°C
+125°C
0
2.3
2.8
3.3
3.8
4.3
4.8
5.3
–40
–5
25
85
125
INPUT VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
Figure 4. Quiescent Supply Current vs. Input Voltage, Different Temperatures
Figure 7. Output Voltage vs. Temperature, VIN1 = 2.3 V, Different Loads
3.1
3.0
2.9
2.8
1200
1150
1100
1050
2.3V
3.0V
4.0V
5.0V
5.5V
1000
950
900
850
800
750
700
2.7
+25°C
–40°C
–5°C
+85°C
2.6
+125°C
2.5
2.3
2.8
3.3
3.8
4.3
4.8
5.3
–60 –40 –20
0
20
40
60
80
100 120 140
INPUT VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
Figure 5. Switching Frequency vs. Input Voltage, Different Temperatures
Figure 8. Current Limit vs. Temperature, Different Input Voltages
3.10
3.05
140
120
100
80
5.5V
4.6V
3.1V
2.3V
3.00
2.95
2.90
2.85
2.80
2.75
2.70
2.65
2.60
60
40
–40°C
–5°C
+25°C
+85°C
+125°C
20
0
–60 –40 –20
0
20
40
60
80
100 120 140
3.50
3.75
4.00
4.25
4.50
4.75
5.00
5.25
5.50
TEMPERATURE (°C)
INPUT VOLTAGE (V)
Figure 6. Switching Frequency vs. Temperature, Different Input Voltages
Figure 9. PSM to PWM Mode Transition vs. Input Voltage, Different
Temperatures
Rev. B | Page 7 of 32
ADP2140
Data Sheet
VIN1 = 4 V, V OUT = 1.8 V, IOUT = 10 mA, CIN = COUT = 10 µF, TA = 25°C, unless otherwise noted.
1.82
1.81
1.80
1.79
1.78
1.77
1.76
3.350
3.325
3.300
3.275
3.250
LOAD CURRENT = 1mA
LOAD CURRENT = 10mA
LOAD CURRENT = 50mA
LOAD CURRENT = 100mA
LOAD CURRENT = 300mA
LOAD CURRENT = 600mA
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
1000
1000
1
10
100
1000
INPUT VOLTAGE (V)
LOAD CURRENT (mA)
Figure 10. Line Regulation, VOUT = 1.8 V, Different Loads
Figure 13. Load Regulation, VOUT = 3.3 V
1.82
1.81
1.80
1.79
1.78
1.77
1.76
100
90
80
70
60
50
40
30
20
10
0
2.5V
3.0V
4.0V
5.0V
5.5V
1
10
100
1
10
100
1000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 11. Load Regulation, VOUT = 1.8 V, VIN1 = 2.3 V
Figure 14. Efficiency vs. Load Current, VOUT = 1.8 V, Different Input Voltages
1.22
1.21
1.20
1.19
1.18
1.17
100
90
80
70
60
50
40
30
–40°C
20
–5°C
+25°C
+85°C
+125°C
10
0
1
10
100
1
10
100
1000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 12. Load Regulation, VOUT = 1.2 V, VIN1 = 2.3 V
Figure 15. Efficiency vs. Load Current, VOUT = 1.8 V, Different Temperatures
Rev. B | Page 8 of 32
Data Sheet
ADP2140
VIN1 = 4 V, V OUT = 1.8 V, IOUT = 10 mA, CIN = COUT = 10 µF, TA = 25°C, unless otherwise noted.
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
2.5V
3.0V
4.0V
5.0V
5.5V
–40°C
–5°C
+25°C
+85°C
+125°C
1
10
100
1000
1
10
100
1000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 16. Efficiency vs. Load Current, VOUT = 1.2 V, Different Input Voltages
Figure 19. Efficiency vs. Load Current, VOUT = 3.3 V, Different Temperatures
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
–40°C
–5°C
20
20
4.0V
5.0V
+25°C
+85°C
10
10
5.5V
+125°C
0
0
1
10
100
1000
1
10
100
1000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 17. Efficiency vs. Load Current, VOUT = 1.2 V, Different Temperatures
Figure 20. Efficiency vs. Load Current, VOUT = 3.3 V, Different Input Voltages
T
T
INPUT VOLTAGE
INPUT VOLTAGE
OUTPUT VOLTAGE
OUTPUT VOLTAGE
2
2
1
1
SWITCH NODE
SWITCH NODE
3
3
CH1 1.00V
CH3 5.00V
CH2 50.0mV M20.0µs
11.60%
A
CH1
4.68V
CH1 1.00V
CH3 5.00V
CH2 20.0mV M20.0µs
11.60%
A
CH1
4.68V
T
T
Figure 18. Line Transient, VOUT = 1.8 V, Power Save Mode, 50 mA,
IN1 = 4 V to 5 V, 4 μs Rise Time
Figure 21. Line Transient, VOUT = 1.8 V, PWM Mode, 600 mA, VIN1 = 4 V to 5 V,
4 μs Rise Time
V
Rev. B | Page 9 of 32
ADP2140
Data Sheet
VIN1 = 4 V, V OUT = 1.8 V, IOUT = 10 mA, CIN = COUT = 10 µF, TA = 25°C, unless otherwise noted.
T
T
INPUT VOLTAGE
INPUT VOLTAGE
OUTPUT VOLTAGE
OUTPUT VOLTAGE
2
1
2
1
SWITCH NODE
SWITCH NODE
3
3
CH1 1.00V
CH3 5.00V
CH2 50.0mV M20.0µs
A
CH1
4.68V
CH1 1.00V
CH3 5.00V
CH2 20.0mV M20.0µs
A
CH1
4.68V
T
11.60%
T 11.60%
Figure 22. Line Transient, VOUT = 1.2 V, PSM Mode, 50 mA, VIN1 = 4 V to 5 V,
4 μs Rise Time
Figure 25. Line Transient, VOUT = 3.3 V, PWM Mode, 600 mA, VIN1 = 4 V to 5 V,
4 μs Rise Time
T
T
INPUT VOLTAGE
SWITCH NODE
3
LOAD CURRENT
2
OUTPUT VOLTAGE
1
1
2
SWITCH NODE
OUTPUT VOLTAGE
3
CH1 1.00V
CH3 5.00V
CH2 20.0mV M20.0µs
10.80%
A
CH1
4.32V
CH1 200mA
CH3 5.00V
CH2 50.0mV M20.0µs
10.40%
A
CH1
288mA
T
T
Figure 23. Line Transient, VOUT = 1.2 V, PWM Mode, 600 mA, VIN1 = 4 V to 5 V,
4 μs Rise Time
Figure 26. Load Transient, VOUT = 1.8 V, 200 mA to 600 mA, Load Current Rise
Time = 200 ns
T
T
INPUT VOLTAGE
SWITCH NODE
3
OUTPUT VOLTAGE
LOAD OUTPUT
2
1
1
2
SWITCH NODE
OUTPUT VOLTAGE
3
CH1 1.00V
CH3 5.00V
CH2 50.0mV M20.0µs
11.60%
A
CH1
4.68V
CH1 100mA
CH3 5.00V
CH2 50.0mV M20.0µs
10.40%
A
CH1
136mA
T
T
Figure 24. Line Transient, VOUT = 3.3 V, PSM Mode, 50 mA, VIN1 = 4 V to 5 V,
4 μs Rise Time
Figure 27. Load Transient, VOUT = 1.8 V, 50 mA to 250 mA, Load Current Rise
Time = 200 ns
Rev. B | Page 10 of 32
Data Sheet
ADP2140
VIN1 = 4 V, V OUT = 1.8 V, IOUT = 10 mA, CIN = COUT = 10 µF, TA = 25°C, unless otherwise noted.
T
T
SWITCH NODE
SWITCH NODE
3
3
LOAD CURRENT
LOAD CURRENT
1
2
1
2
OUTPUT VOLTAGE
OUTPUT VOLTAGE
CH1 50.0mA CH2 50.0mV M20.0µs
CH3 5.00V 10.40%
A
CH1
51.0mA
CH1 50.0mA CH2 100.0mV M20.0µs
CH3 5.00V 10.40%
A
CH1
50.0mA
T
T
Figure 28. Load Transient, VOUT = 1.8 V,10 mA to 110 mA, Load Current Rise
Time = 200 ns
Figure 31. Load Transient, VOUT = 3.3 V,10 mA to 110 mA, Load Current Rise
Time = 200 ns
T
T
SWITCH NODE
SWITCH NODE
3
3
LOAD CURRENT
LOAD CURRENT
1
1
2
2
OUTPUT VOLTAGE
OUTPUT VOLTAGE
CH1 200mA
CH3 5.00V
CH2 100.0mV M20.0µs
10.40%
A
CH1
292mA
CH1 200.0mA CH2 50.0mV M20.0µs
CH3 5.00V 10.40%
A
CH1
376mA
T
T
Figure 29. Load Transient, VOUT = 3.3 V, 200 mA to 600 mA, Load Current Rise
Time = 200 ns
Figure 32. Load Transient, VOUT = 1.2 V, 200 mA to 600 mA, Load Current Rise
Time = 200 ns
T
T
SWITCH NODE
3
SWITCH NODE
3
LOAD CURRENT
LOAD CURRENT
1
1
2
2
OUTPUT VOLTAGE
OUTPUT VOLTAGE
CH1 100mA
CH3 5.00V
CH2 100.0mV M20.0µs
10.40%
A
CH1
80.0mA
CH1 100.0mA CH2 50.0mV M20.0µs
CH3 5.00V 10.40%
A
CH1
154mA
T
T
Figure 30. Load Transient, VOUT = 3.3 V, 50 mA to 250 mA, Load Current Rise
Time = 200 ns
Figure 33. Load Transient, VOUT = 1.2 V, 50 mA to 250 mA, Load Current Rise
Time = 200 ns
Rev. B | Page 11 of 32
ADP2140
Data Sheet
VIN1 = 4 V, V OUT = 1.8 V, IOUT = 10 mA, CIN = COUT = 10 µF, TA = 25°C, unless otherwise noted.
T
T
3
3
SWITCH NODE
SWITCH NODE
INDUCTOR CURRENT
LOAD CURRENT
1
1
2
OUTPUT VOLTAGE
ENABLE 1
OUTPUT VOLTAGE
2
4
CH1 50.0mA CH2 50.0mV M20.0µs
CH3 5.00V 10.40%
A
CH1
48.0mA
CH1 500mA
CH3 5.00V
CH2 2.00V
CH4 5.00V
M40.0µs
10.40%
A
CH4
2.70V
T
T
Figure 34. Load Transient, VOUT = 1.2 V,10 mA to 110 mA, Load Current Rise
Time = 200 ns
Figure 37. Startup, VOUT = 3.3 V, 10 mA
T
T
SWITCH NODE
3
SWITCH NODE
3
INDUCTOR CURRENT
INDUCTOR CURRENT
1
1
OUTPUT VOLTAGE
OUTPUT VOLTAGE
ENABLE 1
ENABLE 1
2
4
2
4
CH1 500mA
CH3 5.00V
CH2 1.00V
CH4 5.00V
M100µs
10.40%
A
CH4
2.70V
CH1 500mA
CH3 5.00V
CH2 2.00V
CH4 5.00V
M40.0µs
10.40%
A
CH4
2.70V
T
T
Figure 35. Startup, VOUT = 1.8 V, 10 mA
Figure 38. Startup, VOUT = 3.3 V, 600 mA
T
T
SWITCH NODE
3
SWITCH NODE
3
1
INDUCTOR CURRENT
INDUCTOR CURRENT
1
OUTPUT VOLTAGE
OUTPUT VOLTAGE
ENABLE 1
ENABLE 1
2
4
2
4
CH1 500mA
CH3 5.00V
CH2 1.00V
CH4 5.00V
M40.0µs
10.40%
A
CH4
2.70V
CH1 200mA
CH3 5.00V
CH2 1.00V
CH4 5.00V
M100µs
10.40%
A
CH4
2.30V
T
T
Figure 36. Startup, VOUT = 1.8 V, 600 mA
Figure 39. Startup, VOUT = 1.2 V, 10 mA
Rev. B | Page 12 of 32
Data Sheet
ADP2140
VIN1 = 4 V, V OUT = 1.8 V, IOUT = 10 mA, CIN = COUT = 10 µF, TA = 25°C, unless otherwise noted.
T
T
BUCK OUTPUT
LDO OUTPUT
3
SWITCH NODE
1
2
1
INDUCTOR CURRENT
OUTPUT VOLTAGE
PG SIGNAL
ENABLE 1
3
4
2
4
ENABLE 1
CH1 500mA
CH3 5.00V
CH2 1.00V
CH4 5.00V
M40.0µs
10.00%
A
CH4
2.30V
CH1 1.00V
CH3 5.00V
CH2 1.00V
CH4 5.00V
M2.00ms
10.00%
A
CH4
2.30V
T
T
Figure 40. Startup, VOUT = 1.2 V, 600 mA
Figure 41. Startup, Autosequence Mode, VOUT = 1.8 V, VOUT2 = 1.2 V
Rev. B | Page 13 of 32
ADP2140
Data Sheet
LDO OUTPUT
VIN1 = 5 V, VIN2 = 2.3 V, VOUT2 = 1.8 V, IOUT2 = 10 mA, CIN2 = COUT2 = 1 µF, TA = 25°C, unless otherwise noted.
1.83
1.82
1.81
1.80
1.79
1.78
1.77
180
160
140
120
100
80
LOAD CURRENT = 1mA
LOAD CURRENT = 5mA
LOAD CURRENT = 10mA
60
LOAD CURRENT = 1mA
LOAD CURRENT = 5mA
LOAD CURRENT = 10mA
LOAD CURRENT = 50mA
LOAD CURRENT = 100mA
LOAD CURRENT = 300mA
40
LOAD CURRENT = 50mA
LOAD CURRENT = 100mA
LOAD CURRENT = 300mA
20
0
–40
–5
25
85
125
–40
–5
25
85
125
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure 42. Output Voltage vs. Junction Temperature, Different Loads
Figure 45. Ground Current vs. Junction Temperature, Different Loads
1.820
1.815
1.810
1.805
1.800
1.795
1.790
1.785
1.780
160
140
120
100
80
60
40
20
0
1
10
100
1000
1
10
100
1000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 43. Output Voltage vs. Load Current
Figure 46. Ground Current vs. Load Current
1.820
160
1.815
1.810
1.805
1.800
1.795
1.790
1.785
1.780
140
120
100
80
60
LOAD CURRENT = 1mA
LOAD CURRENT = 5mA
LOAD CURRENT = 10mA
LOAD CURRENT = 50mA
LOAD CURRENT = 100mA
LOAD CURRENT = 300mA
40
LOAD CURRENT = 1mA
LOAD CURRENT = 5mA
LOAD CURRENT = 10mA
LOAD CURRENT = 50mA
LOAD CURRENT = 100mA
LOAD CURRENT = 300mA
20
0
2.2
2.2
2.6
3.0
3.4
3.8
4.2
4.6
5.0
5.4
2.6
3.0
3.4
3.8
4.2
4.6
5.0
5.4
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 44. Output Voltage vs. Input Voltage, Different Loads
Figure 47. Ground Current vs. Input Voltage, Different Loads
Rev. B | Page 14 of 32
Data Sheet
ADP2140
VIN1 = 5 V, V IN2 = 2.3 V, VOUT2 = 1.8 V, IOUT2 = 10 mA, CIN2 = COUT2 = 1 µF, TA = 25°C, unless otherwise noted.
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
200
180
160
140
120
100
80
2.2V
2.6V
3.4V
3.8V
4.6V
5.5V
60
I
I
I
I
I
I
= 1mA
= 5mA
= 10mA
= 50mA
= 100mA
= 300mA
GND
GND
GND
GND
GND
GND
40
20
0
–50
–25
0
25
50
75
100
125
1.6
1.7
1.8
1.9
2.0
TEMPERATURE (°C)
INPUT VOLTAGE (V)
Figure 48. Shutdown Current vs. Temperature at Various Input Voltages
Figure 51. Ground Current vs. Input Voltage (in Dropout)
150
125
100
75
0
300mA
100mA
10mA
1mA
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
50
25
0
1
10
100
1000
10
100
1k
10k
100k
1M
10M
LOAD CURRENT (mA)
FREQUENCY (Hz)
Figure 49. Dropout Voltage vs. Load Current
Figure 52. Power Supply Rejection Ratio vs. Frequency VOUT2 = 1.2 V, VIN1 = 5 V,
VIN2 = 2.2 V
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
1.85
1.80
1.75
1.70
1.65
1.60
1.55
1.50
1.45
300mA
200mA
100mA
10mA
1mA
V
V
V
V
V
V
= 1mA
= 5mA
= 10mA
= 50mA
DROP
DROP
DROP
DROP
DROP
DROP
= 100mA
= 300mA
10
100
1k
10k
100k
1M
10M
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
FREQUENCY (Hz)
INPUT VOLTAGE (V)
Figure 53. Power Supply Rejection Ratio vs. Frequency VOUT2 = 1.2 V, VIN1 = 5 V,
IN2 = 1.7 V
Figure 50. Output Voltage vs. Input Voltage (in Dropout)
V
Rev. B | Page 15 of 32
ADP2140
Data Sheet
VIN1 = 5 V, V IN2 = 2.3 V, VOUT2 = 1.8 V, IOUT2 = 10 mA, CIN2 = COUT2 = 1 µF, TA = 25°C, unless otherwise noted.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
300mA
100mA
10mA
1mA
300mA
200mA
100mA
10mA
1mA
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 54. Power Supply Rejection Ratio vs. Frequency, VOUT2 = 3.3 V,
IN1 = 5 V, VIN2 = 4.3 V
Figure 57. Power Supply Rejection Ratio vs. Frequency, VOUT2 = 3.3 V,
IN1 = 5 V, VIN2 = 3.8 V
V
V
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
300mA
100mA
10mA
1mA
300mA
200mA
100mA
10mA
1mA
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 55. Power Supply Rejection Ratio vs. Frequency, VOUT2 = 1.8 V,
Figure 58. Power Supply Rejection Ratio vs. Frequency VOUT2 = 1.8 V,
IN1 = 5 V, VIN2 = 2.3 V
VIN1 = 5 V, VIN2 = 2.8 V
V
10
100
90
80
70
60
50
40
30
20
10
0
1.2V
1.8V
2.5V
3.3V
1.2V
1.8V
2.5V
3.3V
1
0.1
0.01
10
100
1k
10k
100k
100n
1µ
10µ
100µ
1m
10m
100m
1
FREQUENCY (Hz)
LOAD CURRENT (A)
Figure 56. Output Noise Spectrum, VIN2 = 5 V, Load Current = 10 mA
Figure 59. Output Noise vs. Load Current and Output Voltage
IN2 = 5 V
V
Rev. B | Page 16 of 32
Data Sheet
ADP2140
VIN1 = 5 V, V IN2 = 2.3 V, VOUT2 = 1.8 V, IOUT2 = 10 mA, CIN2 = COUT2 = 1 µF, TA = 25°C, unless otherwise noted.
T
T
V
LOAD CURRENT
IN2
1
2
V
OUT2
2
1
V
OUT2
CH1 100mA
CH2 100mV
M40.0µs
10.40%
A
CH1
68mA
CH1 1.00V
CH2 5.00mV M2.00µs
10.20%
A
CH4
12mV
T
T
Figure 60. Load Transient Response, VIN2 = 4 V, VOUT2 = 1.2 V,
1 mA to 300 mA, Load Current Rise Time = 200 ns
Figure 63. Line Transient Response, VOUT2 = 1.8 V, Load Current = 1 mA,
IN2 = 4 V to 5 V, 1 μs Rise Time
V
T
T
LOAD CURRENT
V
IN2
1
2
V
2
1
OUT2
V
OUT2
CH1 100mA
CH2 100mV
M40.0µs
A
CH1
68mA
CH1 1.00V
CH2 5.00mV M2.00µs
10.20%
A
CH4
12mV
T
10.40%
T
Figure 61. Load Transient Response, VIN2 = 4 V, VOUT2 = 1.8 V,
1 mA to 300 mA, Load Current Rise Time = 200 ns
Figure 64. Line Transient Response, VOUT2 = 1.2 V, Load Current = 1 mA,
IN2 = 4 V to 5 V, 1 μs Rise Time
V
T
T
LOAD CURRENT
V
IN2
1
2
V
2
1
OUT2
V
OUT2
CH1 100mA
CH2 100mV
M40.0µs
10.40%
A
CH1
68mA
CH1 1.00V
CH2 5.00mV M2.00µs
10.20%
A
CH4
12mV
T
T
Figure 62. Load Transient Response, VIN2 = 4 V, VOUT2 = 3.3 V,
1 mA to 300 mA, Load Current Rise Time = 200 ns
Figure 65. Line Transient Response, VOUT2 = 3.3 V, Load Current = 1 mA,
IN2 = 4 V to 5 V, 1 μs Rise Time
V
Rev. B | Page 17 of 32
ADP2140
Data Sheet
VIN1 = 5 V, V IN2 = 2.3 V, VOUT2 = 1.8 V, IOUT2 = 10 mA, CIN2 = COUT2 = 1 µF, TA = 25°C, unless otherwise noted.
T
T
V
V
IN2
IN2
V
V
OUT2
OUT2
2
1
2
1
CH1 1.00V
CH2 5.00mV M2.00µs
10.20%
A
CH4
12mV
CH1 1.00V
CH2 5.00mV M2.00µs
10.20%
A
CH4
12mV
T
T
Figure 66. Line Transient Response, VOUT2 = 1.8 V, Load Current = 300 mA,
IN2 = 4 V to 5 V, 1 μs Rise Time
Figure 68. Line Transient Response, VOUT2 = 3.3 V, Load Current = 300 mA,
IN2 = 4 V to 5 V, 1 μs Rise Time
V
V
T
V
IN2
V
OUT2
2
1
CH1 1.00V
CH2 5.00mV M2.00µs
10.20%
A
CH4
12mV
T
Figure 67. Line Transient Response, VOUT2 = 1.2 V, Load Current = 300 mA,
IN2 = 4 V to 5 V, 1 μs Rise Time
V
Rev. B | Page 18 of 32
Data Sheet
ADP2140
THEORY OF OPERATION
SOFT
START
UVLO
VIN1
CURRENT
SENSE AMP
FB
Gm ERROR
AMP
CURRENT
LIMIT
PWM/
PSM
CONTROL
REFERENCE
3MHz
OSCILLATOR
0.5V
DRIVER
AND
THERMAL
SHUTDOWN
ANTISHOOT
THROUGH
VIN2
SW
R1
R2
ZERO-CROSS
COMPARATOR
PGND
PG
FB
AGND
POWER
GOOD
EPAD
EN1
EN2
ENABLE/
SEQUENCING
Figure 69. Internal Block Diagram
positive voltage across the inductor. Current in the inductor
increases until the current sense signal crosses the peak inductor
current level that turns off the P-channel MOSFET switch and
turns on the N-channel MOSFET synchronous rectifier. This
puts a negative voltage across the inductor, causing the inductor
current to decrease. The synchronous rectifier stays on for the
remainder of the cycle, unless the inductor current reaches zero,
which causes the zero-crossing comparator to turn off the
N-channel MOSFET.
BUCK SECTION
The ADP2140 contains a step-down dc-to-dc converter that
uses a fixed frequency, high speed current-mode architecture. The
high 3 MHz switching frequency and tiny 10-lead, 3 mm × 3 mm
LFCSP package allow for a small step-down dc-to-dc converter
solution.
The ADP2140 operates with an input voltage from 2.3 V to 5.5 V.
Output voltage options are 1 . 0 V, 1.1 V, 1.2 V, 1.5 V, 1.8 V, 1.875 V,
2.5 V, and 3.3 V.
PSM OPERATION
CONTROL SCHEME
The ADP2140 has a smooth transition to the variable frequency
PSM mode of operation when the load current decreases below
the pulse skipping threshold current, switching only as necessary to
maintain the output voltage within regulation. When the output
voltage dips below regulation, the ADP2140 enters PWM mode
for a few oscillator cycles to increase the output voltage back to
regulation. During the wait time between bursts, both power
switches are off, and the output capacitor supplies the entire
load current. Because the output voltage occasionally dips and
recovers, the output voltage ripple in this mode is larger than the
ripple in the PWM mode of operation.
The ADP2140 operates with a fixed frequency, current-mode
PWM control architecture at medium to high loads for high
efficiency, but shifts to a variable frequency control scheme at
light loads for lower quiescent current. When operating in fixed
frequency PWM mode, the duty cycle of the integrated switches
adjust to regulate the output voltage, but when operating in power
saving mode (PSM) at light loads, the switching frequency adjusts
to regulate the output voltage.
The ADP2140 operates in the PWM mode only when the load
current is greater than the pulse skipping threshold current. At
load currents below this value, the converter smoothly transitions
to the PSM mode of operation.
PULSE SKIPPING THRESHOLD
The output current at which the ADP2140 transitions from
variable frequency PSM control to fixed frequency PWM control
is called the pulse skipping threshold. The pulse skipping threshold
has been optimized for excellent efficiency over all load currents.
PWM OPERATION
In PWM mode, the ADP2140 operates at a fixed frequency of
3 MHz set by an internal oscillator. At the start of each oscillator
cycle, the P-channel MOSFET switch is turned on, putting a
Rev. B | Page 19 of 32
ADP2140
Data Sheet
SELECTED FEATURES
The ADP2140 also provides a negative current limit to prevent
an excessive reverse inductor current when the switching section
sinks current from the load in forced continuous conduction
mode. Under negative current limit conditions, both the high-
side and low-side switches are disabled.
SHORT-CIRCUIT PROTECTION
The ADP2140 includes frequency foldback to prevent output
current runaway on a hard short. When the voltage at the feed-
back pin falls below 50% of the nominal output voltage, indicating
the possibility of a hard short at the output, the switching frequency
is reduced to 1/2 of the internal oscillator frequency. The reduc-
tion in the switching frequency gives more time for the inductor
to discharge, preventing a runaway of output current.
POWER-GOOD PIN
The ADP2140 has a dedicated pin (PG) to signal the state of the
monitored output voltages. The voltage monitor circuit has an
active high, open-drain output requiring an external pull-up
resistor typically supplied from the I/O supply rail, as shown
in . The voltage monitor circuit has a small amount
UNDERVOLTAGE LOCKOUT
To protect against battery discharge, undervoltage lockout
circuitry is integrated on the ADP2140. If the input voltage
drops below the 2.15 V UVLO threshold, the ADP2140 shuts
down and both the power switch and synchronous rectifier turn
off. When the voltage rises again above the UVLO threshold,
the soft start period initiates and the part is enabled.
of hysteresis and is deglitched to ensure that noise or external
perturbations do not trigger the PG line.
LDO SECTION
The ADP2140 low dropout linear regulator uses an advanced
proprietary architecture to achieve low quiescent current, and
high efficiency regulation. It also provides high power supply
rejection ratio (PSRR), low output noise, and excellent line and
load transient response with just a small 1 μF ceramic output capa-
citor. The wide input voltage range of 1.65 V to 5.5 V allows it to
operate from either the input or output of the buck. Supply current
in shutdown mode is typically 0.3 µA.
THERMAL PROTECTION
In the event that the ADP2140 junction temperatures rises above
150°C, the thermal shutdown circuit turns off the converter.
Extreme junction temperatures can be the result of high current
operation, poor circuit board design, and/or high ambient tem-
perature. A 20°C hysteresis is included; thus, when thermal
shutdown occurs, the ADP2140 does not return to operation
until the on-chip temperature drops below 130°C. When
emerging from a thermal shutdown, soft start initiates.
Internally, the LDO consists of a reference, an error amplifier, a
feedback voltage divider, and a pass device. The output current
is delivered via the pass device, which is controlled by the error
amplifier, forming a negative feedback system ideally driving
the feedback voltage to be equal to the reference voltage. If the
feedback voltage is lower than the reference voltage, the negative
feedback drives more current, increasing the output voltage. If
the feedback voltage is higher than the reference voltage, the
negative feedback drives less current, decreasing the output
voltage. The positive supply for all circuitry, except the pass
device, is the VIN1 pin.
SOFT START
The ADP2140 has an internal soft start function that ramps the
output voltage in a controlled manner upon startup, thereby
limiting the inrush current. This prevents possible input voltage
drops when a battery or a high impedance power source is con-
nected to the input of the converter.
CURRENT LIMIT
The ADP2140 has protection circuitry to limit the direction and
amount of current to 1000 mA flowing through the power switch
and synchronous rectifier. The positive current limit on the power
switch limits the amount of current that can flow from the input
to the output, and the negative current limit on the synchronous
rectifier prevents the inductor current from reversing direction
and flowing out of the load.
The LDO has an internal soft start that limits the output voltage
ramp period to approximately 130 µs.
The LDO is available in 0.8 V, 1.0 V, 1.1 V, 1.2 V, 1.3 V, 1.5 V, 2.5 V,
2.8 V, 3.0 V, and 3.3 V output voltage options.
Rev. B | Page 20 of 32
Data Sheet
ADP2140
APPLICATIONS INFORMATION
POWER SEQUENCING
Table 6. Power Sequencing Modes
EN21 EN1
Description
The ADP2140 has a flexible power sequencing system
supporting two distinct activation modes:
0
0
1
1
0
1
0
1
Individual mode: both regulators are off.
Individual mode: buck regulator is on.
Individual mode: LDO regulator is on.
Individual mode: both regulators are on.
Individual activation control is where EN1 controls only
the buck regulator and EN2 controls only the LDO. A high
level on Pin EN1 turns on the buck and a high level on
Pin EN2 turns on the LDO. A logic low level turns off the
respective regulator.
NC
Rising edge Autosequence: Buck regulator turns on,
then the LDO regulator turns on. The LDO
voltage is less than the buck voltage.
Autosequencing is where the two regulators turn on in a
specified order and delay after a low-to-high transition on
the EN1 pin.
NC
Rising edge Autosequence: LDO regulator turns on,
then the buck regulator turns on. The LDO
voltage is greater than the buck voltage.
NC
NC
Rising edge Autosequence: If the buck voltage is 1.875 V,
then the LDO regulator always turns on first.
Falling edge Autosequence: The LDO and buck regula-
tors turn off at the same time.
Select the activation mode (individual or autosequence) by
decoding the state of Pin EN2. The individual activation mode
is selected when the EN2 pin is driven externally or hardwired
to a voltage level (VIN1 or PGND). The autosequencing mode
is selected when the EN2 pin remains unconnected (floating).
1 NC means not connected.
Figure 70 to Figure 75 use the following symbols, as described in
Table 7.
To minimize quiescent current consumption, the mode selection
executes one time only during the rising edge of VIN1. The
detection circuit then activates for the time needed to assess the
EN2 state, after which time the circuit is disabled until VIN1 falls
below 0.5 V.
Table 7. Timing Symbols
Typical
Value
Symbol
Description
tSTART
Time needed for the internal circuitry 60 μs
to activate the first regulator
When EN2 is unconnected, the internal control circuit provides
a termination resistance to ground. The 100 kΩ termination
resistance is low enough to guarantee insensitivity to noise and
transients. The termination resistor is disabled in the event that
the EN2 pin is driven externally to a logic level high (individual
activation mode assumed) to reduce the quiescent current con-
sumption.
tSS
tRESET
Regulator soft start time
Time delay from power-good
condition to the release of PG
330 μs
5 ms
tREG12
Delay time between buck and LDO
activation
5 ms
When the autosequencing mode is selected, the EN1 pin is used to
start the on/off sequence of the regulators. A logic high sequences
the regulators on whereas a logic low sequences the regulators
off. The regulator activation order is associated with the voltage
selected for the buck regulator and the LDO.
V
EN1
92% V
BUCK
V
BUCK
tSS
When the turn on or turn off autosequence starts, the start-up
delay between the first and the second regulator is fixed to 5 ms
in PWM mode (tREG12, as shown in Figure 71 and Figure 72).
EN2
92% V
LDO
85% V
LDO
When the application requires activating and deactivating the
regulators at the same time, use the individual activation mode,
which connects the EN1 and EN2 pins together, as shown in
Figure 75.
V
LDO
tSS
PG
tRESET
Figure 70. Individual Activation Mode
TIME
Rev. B | Page 21 of 32
ADP2140
Data Sheet
V
EN1
92% V
BUCK
EN2 = UNCONNECTED
85% V
85% V
BUCK
V
BUCK
EN1
EN2
92% V
92% V
LDO
BUCK
LDO
V
LDO
V
V
BUCK
LDO
tSTART
92% V
LDO
tSS
PG
85% V
LDO
tRESET
tREG12
tSS
Figure 74. Individual Activation Mode, One Regulator Only (Buck) Sensed
PG
tRESET
TIME
EN1
EN2
Figure 71. Autosequencing Mode, Buck First Then LDO
V
92% V
92% V
BUCK
85% V
BUCK
V
BUCK
LDO
EN2 = UNCONNECTED
EN1
85% V
LDO
LDO
V
92% V
PG
LDO
V
V
LDO
tRESET
tSTART
92% V
BUCK
85% V
tSS
Figure 75. Individual Activation Mode, No Activation/Deactivation Delay
Between Regulators, EN1 and EN2 Pins Tied Together
BUCK
BUCK
tREG12
T
tSS
BUCK OUTPUT
PG
tRESET
TIME
Figure 72. Autosequencing Mode, LDO First Then Buck
The PG responds to the last activated regulator. As described in
the Power Sequencing section, the regulator order in the auto-
sequencing mode is defined by the voltage option combination.
Therefore, if the sequence is buck first, the LDO and the PG
signal are active low for tRESET after VLDO reaches 92% of the rated
output voltage, at which time PG goes high and remains high
for as long as VLDO is above 86% of the rated output voltage.
When the sequencing is LDO first then buck, VBUCK controls
PG. This control scheme also applies when the individual
activation mode is selected.
1
LDO OUTPUT
2
EN1
3
CH1 500mV
CH3 2.00V
CH2 500mV
M1.00ms
10.00%
A
CH3
1.16V
T
Figure 76. Autosequence Mode Turn On Behavior, Buck Voltage = 1.8 V,
LDO Voltage = 1.2 V, Buck Load = 500 mA, LDO Load = 100 mA
As soon as either regulator output voltage drops below 86% of
the respective nominal level, the PG pin is forced low.
T
BUCK OUTPUT
EN1
92% V
95%
BUCK
85%
BUCK
BUCK
85% V
BUCK
V
V
V
BUCK
1
EN2
LDO OUTPUT
2
92% V
85% V
LDO
LDO
V
LDO
EN1
PG
3
tRESET
tRESET
CH1 500mV
CH3 2.00V
CH2 500mV
M40.0µs
10.00%
A
CH3
1.16V
Figure 73. Individual Activation Mode, Both Regulators Sensed
T
Figure 77. Autosequence Mode Turn On Behavior, Buck Voltage = 1.8 V,
LDO Voltage = 1.2 V, Buck Load = 500 mA, LDO Load = 100 mA
Rev. B | Page 22 of 32
Data Sheet
ADP2140
T
T
LDO OUTPUT
BUCK OUTPUT
LDO OUTPUT
1
2
2
1
BUCK OUTPUT
EN1
EN1
3
3
CH1 500mV
CH3 2.00V
CH2 500mV
M40.0µs
10.00%
A
CH3
1.16V
CH1 500mV
CH3 2.00V
CH2 1.00V
M40.0µs
10.00%
A
CH3
2.04V
T
T
Figure 78. Autosequence Mode Turn On Behavior, Buck Voltage = 1.8 V,
LDO Voltage = 1.2 V, Buck Load = 500 mA, LDO Load = 100 mA
Figure 81. Autosequence Mode Turn On Behavior, Buck Voltage = 1.0 V,
LDO Voltage = 3.3 V, Buck Load = 500 mA, LDO Load = 100 mA
(Expanded Version of Figure 80)
T
BUCK OUTPUT
LDO OUTPUT
1
2
BUCK OUTPUT
LDO OUTPUT
1
2
EN1
EN1
3
3
CH1 1.00V
CH3 2.00V
CH2 1.00V
M100ms
A
CH3
3.04V
CH1 500mV
CH3 2.00V
CH2 1.00V
M40.0µs
10.00%
A
CH3
2.04V
T
Figure 79. Autosequence Mode Turn On Behavior, Buck Voltage =1.8 V,
LDO Voltage = 1.2 V, Buck Load = 1 mA, LDO Load = 100 mA
Figure 82. Autosequence Mode Turn Off Behavior, Buck Voltage = 1.0 V,
LDO Voltage = 3.3 V, Buck Load = 500 mA, LDO Load = 100 mA
LDO OUTPUT
T
LDO OUTPUT
T
2
1
2
1
BUCK OUTPUT
EN1
BUCK OUTPUT
EN1
3
3
CH1 500mV
CH3 2.00V
CH2 1.00V
M2.00ms
10.00%
A
CH3
2.04V
CH1 500mV
CH3 2.00V
CH2 1.00V
M2.00ms
10.00%
A
CH3
3.04V
T
T
Figure 80. Autosequence Mode Turn On Behavior, Buck Voltage = 1.0 V,
LDO Voltage = 3.3 V, Buck Load = 500 mA, LDO Load = 100 mA
Figure 83. Autosequence Mode Turn On Behavior, Buck Voltage = 1.0 V,
LDO Voltage = 3.3 V, Buck Load = 1 mA, LDO Load = 100 mA
Rev. B | Page 23 of 32
ADP2140
Data Sheet
T
BUCK OUTPUT
SELECTING THE INDUCTOR
The high frequency switching of the ADP2140 allows the selection
of small chip inductors. The inductor value affects the transition
between CFM to PSM, efficiency, output ripple, and current limit
values. Use the following equation to calculate the inductor ripple
current:
LDO OUTPUT
1
2
VOUT ×(VIN −VOUT
VIN × fsw × L
)
ΔIL =
EN1
where:
SW is the switching frequency (3 MHz typical).
L is the inductor value.
f
3
CH1 500mV
CH3 2.00V
CH2 500mV
M40.0µs
10.00%
A
CH3
1.16V
T
The dc resistance (DCR) value of the selected inductor affects
efficiency, but a decrease in this value typically means an increase
in root mean square (rms) losses in the core and skin. As a
minimum requirement, the dc current rating of the inductor
should be equal to the maximum load current plus half of the
inductor current ripple, as shown by the following equation:
Figure 84. Individual Activation Mode, EN1 and EN2 Pins Tied Together
POWER-GOOD FUNCTION
The ADP2140 power-good (PG) pin indicates the state of the
monitored output voltages. The PG function is the logical AND
of the state of both outputs. The PG function is an active high,
open-drain output, requiring an external pull-up resistor typically
supplied from the I/O supply rail, as shown in . When the sensed
output voltages are below 92% of their nominal value, the PG pin is
held low. When the sensed output voltages rise above 92% of
the nominal levels, the PG line is pulled high after tRESET. The
PG pin remains high as long as the sensed output voltages are
above 86% of the nominal output voltage levels.
ΔIL
2
IPK = ILOAD(MAX) +(
)
OUTPUT CAPACITOR
Output capacitance is required to minimize the voltage over-
shoot and ripple present on the output. Capacitors with low
equivalent series resistance (ESR) values are recommended to
produce low output ripple. For good stability over temperature,
use capacitors such as the X5R or X7R dielectric. Do not use the
Y5V and Z5U capacitors; they are not suitable for this application
because of their large variation in capacitance over temperature
The typical PG delay when the buck is in PWM mode is 5 ms.
When the part is in PSM mode, the PG delay is load dependent
because the internal clock is disabled to reduce quiescent current
during the sleep stage. PG delay varies from hundreds of micro-
seconds at 10 mA, up to seconds at current loads of less than 10 μA.
and dc bias voltage. The minimum output capacitance (COUT_MIN
is determined by the following VRIPPLE and COUT_MIN equations.
)
T
For acceptable maximum output voltage ripple,
EN1
VRIPPLE = ΔIL × (ESRCOUT + 1/(8 × fSW × COUT_MIN))
1
Therefore,
BUCK
2
COUT_MIN = ΔIL/(8 × fSW × (VRIPPLE − ΔIL × ESRCOUT))
LDO
where:
VRIPPLE is allowable peak-to-peak output voltage ripple in V.
3
ΔIL is the inductor ripple current in A.
ESRCOUT is the equivalent series resistance of the capacitor in Ω.
SW is the converter switching frequency in Hz.
PG
f
4
Increasing the output capacitor has no effect on stability and
increasing the output capacitance may further reduce output
ripple and enhance load transient response. When choosing this
value, it is also important to account for the loss of capacitance
due to output voltage dc bias. For recommended 10 μF
capacitors, please refer to Table 9.
CH1 2.00V
CH3 2.00V
CH2 2.00V
CH4 2.00V
M2.00ms
10.20%
A
CH1
2.20V
T
Figure 85. Typical PG Timing
EXTERNAL COMPONENT SELECTION
The external component selection for the ADP2140 application
circuit that is shown in Table 8, Table 9, and Figure 86 is
dependent on input voltage, output voltage, and load current
requirements. Additionally, trade-offs between performance
parameters such as efficiency and transient response can be
made by varying the choice of external components.
INPUT CAPACITOR
Input capacitance is required to reduce input voltage ripple; there-
fore, place the input capacitor as close as possible to the VINx pins.
As with the output capacitor, a low ESR X7R- or X5R-type
capacitor is recommended to help minimize the input voltage
Rev. B | Page 24 of 32
Data Sheet
ADP2140
ripple. Use the following equation to determine the minimum
input capacitance:
Switching Losses
Switching losses are associated with the current drawn by the
driver to turn on and turn off the power devices at the switching
frequency. Each time a power device gate is turned on and
turned off, the driver transfers a charge, ΔQ, from the input
supply to the gate, and then from the gate to ground.
VOUT (VIN VOUT
)
ICIN ILOAD(MAX)
VIN
EFFICIENCY
Estimate switching losses using the following equation:
Efficiency is defined as the ratio of output power to input power.
The high efficiency of the ADP2140 has two distinct advantages.
First, only a small amount of power is lost in the dc-to-dc con-
verter package, which in turn, reduces thermal constraints. In
addition, high efficiency delivers the maximum output power
for the given input power, thereby extending battery life in
portable applications.
PSW = (CGATE_P + CGATE_N) × VIN2 × fSW
where:
CGATE_P is the gate capacitance of the internal high-side switch.
CGATE_N is the gate capacitance of the internal low-side switch.
fSW is the switching frequency.
Transition Losses
Power Switch Conduction Losses
Transition losses occur because the P-channel switch cannot
turn on or turn off instantaneously. In the middle of an SW
node transition, the power switch provides all of the inductor
current. The source-to-drain voltage of the power switch is half
the input voltage, resulting in power loss. Transition losses
increase with both load current and input voltage and occur
twice for each switching cycle.
Power switch dc conduction losses are caused by the flow of
output current through the P-channel power switch and the
N-channel synchronous rectifier, which have internal resis-
tances (RDS(ON)) associated with them. The amount of power
loss can be approximated by
2
PSW _COND (RDS(ON)_ P D RDS(ON)_ N (1 D))IOUT
Use the following equation to estimate transition losses:
VOUT
where D
VIN
PTRAN = VIN/2 × IOUT × (tr + tf) × fSW
The internal resistance of the power switches increases with
temperature but decreases with higher input voltage.
where:
tr is the rise time of the SW node.
tf is the fall time of the SW node.
Inductor Losses
RECOMMENDED BUCK EXTERNAL COMPONENTS
Inductor conduction losses are caused by the flow of current
through the inductor, which has an internal resistance (DCR)
associated with it. Larger size inductors have smaller DCR, which
can decrease inductor conduction losses. Inductor core losses
relate to the magnetic permeability of the core material. Because
the ADP2140 is a high switching frequency dc-to-dc converter,
shielded ferrite core material is recommended for its low core
losses and low EMI.
The recommended buck external components for use with the
ADP2140 are listed in Table 8 (inductors) and Table 9 (capacitors).
V
= 3.6V
IN1
+
CIN
10µF
ADP2140
100kΩ
PG
10
9
1
2
3
4
5
VIN1
PGND
1µH
V
= 1.2V
OUT
PG
SW
8
+
COUT
10µF
EN1
EN2
EN1
AGND
FB
To estimate the total amount of power lost in the inductor, use
the following equation:
7
EN2
V
= 1.8V
OUT2
6
VOUT2
VIN2
+
COUT2
1µF
PL = DCR × IOUT2 + Core Losses
Figure 86. Typical Application Circuit with LDO Connected to Input Voltage
Table 8. 1.0 μH Inductors
Vendor
Murata
Murata
Murata
FDK
Model
Case Size
0805
1206
Dimensions
ISAT (mA)
DCR (mΩ)
LQM21PN1R0MC0D
LQM31PN1R0M00L
LQM2HPN1R0MJ0
MIPSA2520D1R0
2.0 mm × 1.25 mm × 0.5 mm 800
3.2 mm × 1.6 mm × 0.95 mm 1200
2.5 mm × 2.0 mm × 0.95 mm 1500
190
120
90
1008
2.5 mm × 2.0 mm × 1.0 mm
1200
90
Table 9. 10 μF Capacitors
Vendor
Murata
Taiyo Yuden
TDK
Type
X5R
X5R
X5R
Model
Case Size
0805
0805
Voltage Rating
6.3 V
6.3 V
GRM219R60J106
JMK212BJ106
C1608X5R0J106
0603
6.3 V
Rev. B | Page 25 of 32
ADP2140
Data Sheet
1.2
1.0
0.8
0.6
LDO CAPACITOR SELECTION
Output Capacitor
MURATA PART NUMBER:
GRM155R61A105KE15
The ADP2140 LDO is designed for operation with small, space-
saving ceramic capacitors, but functions with most commonly
used capacitors as long as care is taken about the effective series
resistance (ESR) value. The ESR of the output capacitor affects
stability of the LDO control loop. A minimum of 0.70 µF capa-
citance with an ESR of 1 Ω or less is recommended to ensure
stability of the ADP2140. Transient response to changes in load
current is also affected by output capacitance. Using a larger
value of output capacitance improves the transient response of
the ADP2140 to large changes in load current. Figure 87 shows
the transient response for an output capacitance value of 1 µF.
0.4
0.2
0
0
2
4
6
8
10
VOLTAGE (V)
Figure 88. Capacitance vs. Voltage Characteristic
T
LOAD CURRENT
Use Equation 1 to determine the worst-case capacitance accounting
for capacitor variation over temperature, component tolerance, and
voltage.
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL)
(1)
1
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
V
OUT2
2
In this example, the worst-case temperature coefficient
(TEMPCO) over −40°C to +85°C is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10%, and CBIAS is 0.94 μF at 1.8 V as shown in Figure 88.
CH1 100mA
CH2 100mV
M40.0µs
10.40%
A
CH1
68mA
T
Figure 87. Output Transient Response, VOUT2 = 1.8 V, COUT = 1 µF,
1 mA to 300 mA, Load Current Rise Time = 200 ns
Substituting these values in Equation 1 yields
Input Bypass Capacitor
CEFF = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF
Connecting a 1 µF capacitor from VIN to GND reduces the cir-
cuit sensitivity to the PCB layout, especially when long input
traces or high source impedance are encountered. If greater than
1 µF of output capacitance is required, increase the input
capacitor to match it.
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temper-
ature and tolerance at the chosen output voltage.
To guarantee the performance of the ADP2140, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors are evaluated for each application.
Input and Output Capacitor Properties
Use any good quality ceramic capacitors with the ADP2140, as
long as they meet the minimum capacitance and maximum ESR
requirements. Ceramic capacitors are manufactured with a variety
of dielectrics, each with different behavior over temperature and
applied voltage. Capacitors must have a dielectric adequate to
ensure the minimum capacitance over the necessary temperature
range and dc bias conditions. X5R or X7R dielectrics with a voltage
rating of 6.3 V or 10 V are recommended for best performance.
Y5V and Z5U dielectrics are not recommended for use with any
LDO because of their poor temperature and dc bias characteristics.
LDO AS A POSTREGULATOR TO REDUCE BUCK
OUTPUT NOISE
The output of the buck regulator may not be suitable for many
noise sensitive applications because of its inherent switching
noise. This is particularly true when the buck is operating in
PSM mode because the switching noise may be in the audio
range. The ADP2140 LDO can greatly reduce the noise at the
output of the buck at high efficiency because of the load dropout
voltage of the LDO and the high PSRR of the LDO. Figure 89
and Figure 90 show the noise reduction that is possible when
the LDO is used as a post regulator.
Figure 88 depicts the capacitance vs. voltage bias characteristic
of a 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is about 15% over the −40°C to +85°C tempera-
ture range and is not a function of package or voltage rating.
Rev. B | Page 26 of 32
Data Sheet
ADP2140
T
T
BUCK OUTPUT VOLTAGE
BUCK OUTPUT VOLTAGE
1
2
1
2
LDO OUTPUT VOLTAGE
LDO OUTPUT VOLTAGE
CH1 50.0mV CH2 10.0mV M40.0µs
48.00%
A
CH1
–27.0mV
CH1 10.0mV CH2 10.0mV M2.00µs
A
CH1
800µV
T
T 48.00%
Figure 89. LDO as a Postregulator (see Figure 2), VOUT = 1.8 V,
Load Current = 50 mA, VOUT2 = 1.2 V, Load Current = 50 mA
Figure 90. LDO as a Postregulator (see Figure 2), VOUT = 1.8 V,
Load Current = 500 mA, VOUT2 = 1.2 V, Load Current = 50 mA
Rev. B | Page 27 of 32
ADP2140
Data Sheet
THERMAL CONSIDERATIONS
In most applications, the ADP2140 does not dissipate much
heat due to its high efficiency. However, in applications with
high ambient temperature and high supply voltage-to-output
voltage differential, the heat dissipated in the package is large
enough that it can cause the junction temperature of the die to
exceed the maximum junction temperature of 125°C.
where:
I
I
LOAD is the LDO load current.
AGND is the analog ground current.
VIN and VOUT are the LDO input and output voltages,
respectively.
PSW, PTRAN, and PSW_COND are defined in the Efficiency section.
When the junction temperature exceeds 150°C, the converter
enters thermal shutdown. It recovers only after the junction
temperature has decreased below 130°C to prevent any permanent
damage. Therefore, thermal analysis for the chosen application
is very important to guarantee reliable performance over all
conditions. The junction temperature of the die is the sum of
the ambient temperature of the environment and the tempera-
ture rise of the package due to the power dissipation, as shown
in Equation 2.
For a given ambient temperature and total power dissipation,
there exists a minimum copper size requirement for the PCB to
ensure the junction temperature does not rise above 125°C. The
following figures show junction temperature calculations for
different ambient temperatures, total power dissipation, and
areas of PCB copper.
145
135
125
115
105
95
To guarantee reliable operation, the junction temperature of the
ADP2140 must not exceed 125°C. To ensure the junction temper-
ature stays below this maximum value, the user needs to be aware
of the parameters that contribute to junction temperature changes.
These parameters include ambient temperature, power dissipa-
tion in the power device, and thermal resistances between the
junction and ambient air (θJA). The θJA number is dependent on
the package assembly compounds that are used and the amount of
copper used to solder the package GND pins to the PCB. Table 10
shows typical θJA values of the 10-lead, 3 mm × 3 mm LFCSP for
various PCB copper sizes.
85
75
65
55
2
500mm
45
35
25
2
50mm
2
0mm
T
J MAX
0
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00
TOTAL POWER DISSIPATION (W)
Figure 91. Junction Temperature vs. Power Dissipation, TA = 25°C
Table 10. Typical θJA Values
140
Copper Size (mm2)
01
θJA (°C/W)
42.5
130
120
110
100
90
50
40.0
100
300
500
38.8
37.2
36.2
1 The device is soldered to minimum size pin traces.
The junction temperature of the ADP2140 can be calculated
from the following equation:
80
70
60
50
2
500mm
2
50mm
TJ = TA + (PD × θJA)
(2)
2
0mm
T
J MAX
where:
0
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50
TOTAL POWER DISSIPATION (W)
TA is the ambient temperature.
PD is the total power dissipation in the die, given by
Figure 92. Junction Temperature vs. Power Dissipation, TA = 50°C
PD = PLDO + PBUCK
where:
P
P
LDO = [(VIN − VOUT) × ILOAD] + (VIN × IAGND
BUCK = PSW + PTRAN + PSW_COND
)
(3)
(4)
Rev. B | Page 28 of 32
Data Sheet
ADP2140
145
135
125
115
105
95
PCB LAYOUT CONSIDERATIONS
Improve heat dissipation from the package by increasing
the amount of copper attached to the pins of the ADP2140.
However, as listed in Table 10, a point of diminishing returns
is eventually reached, beyond which an increase in the copper
size does not yield significant heat dissipation benefits.
Poor layout can affect the ADP2140 buck performance causing
electromagnetic interference (EMI) and electromagnetic compa-
tibility (EMC) performance, ground bounce, and voltage losses;
thus, regulation and stability can be affected. Implement a good
layout using the following rules:
85
2
500mm
2
50mm
75
2
0mm
T
J MAX
65
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
•
Place the inductor, input capacitor, and output capacitor
close to the IC using short tracks. These components carry
high switching frequencies and long, large tracks act like
antennas.
TOTAL POWER DISSIPATION (W)
Figure 93. Junction Temperature vs. Power Dissipation, TA = 65°C
135
•
•
Route the output voltage path away from the inductor and
SW node to minimize noise and magnetic interference.
Use a ground plane with several vias connected to the
component-side ground to reduce noise interference on
sensitive circuit nodes.
125
115
•
Use of 0402- or 0603-size capacitors achieves the smallest
possible footprint solution on boards where area is limited.
105
2
500mm
95
85
2
50mm
2
0mm
T
J MAX
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
TOTAL POWER DISSIPATION (W)
Figure 94. Junction Temperature vs. Power Dissipation, TA = 85°C
In cases where the board temperature is known, use the thermal
characterization parameter, ΨJB, to estimate the junction temper-
ature rise. Maximum junction temperature (TJ) is calculated
from the board temperature (TB) and power dissipation (PD)
using the formula
TJ = TB + (PD × ΨJB)
(5)
Figure 96. PCB Layout, Top
The typical ΨJB value for the 10-lead, 3 mm × 3 mm LFCSP is
16.9°C /W.
140
120
100
80
60
T
T
T
T
T
= 25°C
= 50°C
= 65°C
= 85°C
B
B
B
B
40
20
Figure 97. PCB Layout, Bottom
J MAX
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
TOTAL POWER DISSIPATION (W)
Figure 95. Junction Temperature vs. Power Dissipation
Rev. B | Page 29 of 32
ADP2140
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
2.48
2.38
2.23
3.10
3.00 SQ
2.90
0.50 BSC
10
6
PIN 1
INDICATOR
AREA
EXPOSED
PAD
1.74
1.64
1.49
0.50
0.40
0.30
0.20 MIN
PIN 1
INDICATOR AR EA OP T
(SEE DETAIL A)
1
5
BOTTOM VIEW
TOP VIEW
SIDE VIEW
IONS
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
0.30
0.25
0.20
SEATING
PLANE
0.20 REF
Figure 98. 10-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Buck Output
Voltage (V)
LDO Output
Voltage (V)
Temperature
Range
Package
Description
Package
Option
Marking
Code
Model1
LET
LEQ
LER
LES
LEX
LEU
LEY
LEZ
LH8
LGE
LF0
LF1
LF2
LF4
LF3
ADP2140ACPZ1218R7
ADP2140ACPZ1228R7
ADP2140ACPZ1233R7
ADP2140ACPZ1528R7
ADP2140ACPZ1533R7
ADP2140ACPZ1812R7
ADP2140ACPZ1815R7
ADP2140ACPZ1833R7
1.2
1.2
1.2
1.5
1.5
1.8
1.8
1.8
1.8
2.8
3.3
2.8
3.3
1.2
1.5
3.3
1.2
1.8
1.2
1.5
1.8
2.5
2.8
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
10-Lead LFCSP
10-Lead LFCSP
10-Lead LFCSP
10-Lead LFCSP
10-Lead LFCSP
10-Lead LFCSP
10-Lead LFCSP
10-Lead LFCSP
10-Lead LFCSP
10-Lead LFCSP
10-Lead LFCSP
10-Lead LFCSP
10-Lead LFCSP
10-Lead LFCSP
10-Lead LFCSP
Evaluation Board
CP-10-9
CP-10-9
CP-10-9
CP-10-9
CP-10-9
CP-10-9
CP-10-9
CP-10-9
CP-10-9
CP-10-9
CP-10-9
CP-10-9
CP-10-9
CP-10-9
CP-10-9
ADP2140ACPZ18812R7 1.875
ADP2140ACPZ2518R7
ADP2140ACPZ3312R7
ADP2140ACPZ3315R7
ADP2140ACPZ3318R7
ADP2140ACPZ3325R7
ADP2140ACPZ3328R7
ADP2140CPZ-REDYKIT
2.5
3.3
3.3
3.3
3.3
3.3
1 Z = RoHS Compliant Part.
Rev. B | Page 30 of 32
Data Sheet
NOTES
ADP2140
Rev. B | Page 31 of 32
ADP2140
NOTES
Data Sheet
©2010–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07932-0-10/19(B)
Rev. B | Page 32 of 32
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