ADP1972 [ADI]
Buck or Boost, PWM Controller for Battery Test Solutions;
| 型号： | ADP1972 |
| 厂家： | 
ADI |
| 描述： | Buck or Boost, PWM Controller for Battery Test Solutions 电池 |
| 文件： | 总18页 (文件大小：415K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Buck or Boost, PWM Controller
for Battery Test Solutions
Data Sheet
ADP1972
FEATURES
GENERAL DESCRIPTION
Input voltage range: 6 V to 60 V
On-board 5 V low dropout regulator
Selective buck or boost mode
Excellent PWM linearity with high amplitude PWM sawtooth
4.0 V p-p
FAULT input compatible with AD8450
COMP input compatible with AD8450
Adjustable frequency from 50 kHz to 300 kHz
Synchronization output or input with adjustable phase shift
Programmable maximum duty cycle
Maximum internal duty cycle: 98%
Programmable soft start
Peak hiccup current limit protection
Input voltage UVLO protection
TSD protection
The ADP1972 is a constant frequency, voltage mode, pulse-width
modulation (PWM) controller for buck or boost, dc-to-dc,
asynchronous applications. The ADP1972 is designed for use in
asynchronous battery testing applications with an external, high
voltage field effect transistor (FET), half bridge driver, and an
external control device, such as the AD8450. The asynchronous
device operates as a buck converter in battery charge mode and
operates as a boost converter in recycle mode to recycle energy
to the input bus.
The ADP1972 high voltage, VIN supply pin can withstand a
maximum operating voltage of 60 V and reduces the need for
additional system supply voltages. The ADP1972 has integrated
features such as precision enable, pin selective buck or boost
mode operation, internal and external synchronization control
with programmable phase shift, programmable maximum duty
cycle, and programmable peak hiccup current limit. Additional
protection features include soft start to limit input inrush current
during startup, input voltage undervoltage lockout (UVLO),
and thermal shutdown (TSD). The ADP1972 also has a COMP
pin to provide external control of the PWM operation and a
FAULT pin that can be signaled to disable the DH and DL
outputs if a fault condition occurs externally to the ADP1972.
16-lead TSSOP
APPLICATIONS
PWM battery test systems with recycle capability including
hybrid vehicles, PCs, and camera batteries
Compatible with AD8450 constant voltage (CV) and constant
current (CC) monitors
The ADP1972 is available in a 16-lead TSSOP package.
TYPICAL APPLICATION CIRCUIT
24V
VIN
SYNC
SCFG
24V RECYLCING
DC BUS
VREG
DH
MODE
EN
HV
MOSFET
DRIVER
FROM
CENTRAL PC
ADP1972
DL
CL
COMP
FAULT
FROM
ANALOG IC
FREQ
DMAX
GND
GND
SENSE
SS
Figure 1.
Rev. B
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ADP1972
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
PWM Drive Signals.................................................................... 12
External COMP Control ........................................................... 12
Current Limit.............................................................................. 12
PWM Frequency Control.......................................................... 12
Maximum Duty Cycle ............................................................... 13
External Fault Signaling ............................................................ 13
Thermal Shutdown (TSD) ........................................................ 13
Applications Information.............................................................. 14
Buck or Boost Selection............................................................. 14
Selecting RS to Set the Current Limit....................................... 14
Adjusting the Operating Frequency ........................................ 14
Programming the Maximum Duty Cycle ............................... 15
Adjusting the Soft Start Period................................................. 16
PCB Layout Guidelines.................................................................. 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 18
Applications....................................................................................... 1
General Description......................................................................... 1
Typical Application Circuit ............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Operating Ranges......................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 10
Supply Pins .................................................................................. 10
EN/Shutdown.............................................................................. 11
Undervoltage Lockout (UVLO) ............................................... 11
Soft Start ...................................................................................... 11
Operating Modes........................................................................ 11
REVISION HISTORY
11/14—Rev. A to Rev. B
Changes to EN Threshold Falling Parameter, Unit
Column, Table 1................................................................................ 4
Changes to the Programming Maximum Duty Cycle Section...... 15
6/14—Rev. 0 to Rev. A
Changes to Maximum Duty Cycle Range Parameter, Table 1.... 3
Changes to Equation 7 and Equation 9 ....................................... 15
Changes to Ordering Guide .......................................................... 18
1/14—Revision 0: Initial Version
Rev. B | Page 2 of 18
Data Sheet
ADP1972
SPECIFICATIONS
VIN = 24 V and the specifications are valid for TJ = −40°C to +125°C, unless otherwise specified. Typical values are at TA = 25°C.
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min Typ
Max Unit
INPUT VOLTAGE (VIN)
Voltage Range
VIN Supply Current
VIN Shutdown Current
UVLO Threshold Rising
UVLO Threshold Falling
SOFT START (SS)
SS Pin Current
SS Threshold Rising
SS Threshold Falling
VIN
IVIN
ISHDN
6
60
2.5
70
6
V
RFREQ = 100 kΩ, VSS = 0 V, SYNC floating
1.5
15
5.71
mA
μA
V
VEN = 0 V
VIN rising
VIN falling
5.1
4
5.34
V
ISS
VSS = 0 V
5
0.52
0.5
6
0.65
μA
V
V
0.4
PWM CONTROL
FREQ
Frequency Range
Oscillator Frequency
FREQ Pin Voltage
fSET
fOSC
VFREQ
50
90
1.2
300
110
1.252 1.3
kHz
kHz
V
RFREQ = 100 kΩ
RFREQ = 100 kΩ
100
SYNC
Maximum SYNC Pin Voltage
SYNC Pull-Down Resistor
SYNC Output (Internal Frequency Control)
Internal SYNC Range
SYNC Output Clock Duty Cycle
SYNC Sink Resistance
SYNC Input (External Frequency Control)
External SYNC Range
SYNC Threshold Rising
SYNC Threshold Falling
RFREQ Slave to Master Ratio for Synchronization
SCFG
5.5
1.5
V
MΩ
0.5
1
VSCFG ≥ 4.53 V or SCFG pin floating
For SYNC output
VSCFG = VVREG, RFREQ = 100 kΩ
VSCFG = 5 V, ISYNC = 10 mA
VSCFG < 4.25 V
fSET
50
40
300
60
20
kHz
%
Ω
50
10
RSYNC
fSYNC
For SYNC input clock
50
300
1.5
kHz
V
V
1.2
1.05
1.11
0.7
For example, RFREQ (SLAVE) = 1.11 × RFREQ (MASTER)
VSCFG
SCFG High Threshold Rising
SCFG High Threshold Falling
SCFG Low Threshold Rising
SCFG Low Threshold Falling
SCFG Current
4.53
4.25 4.51
0.52
4.7
V
V
V
V
0.65
0.4
9.5
0.5
11
IISCFG
RFREQ = 100 kΩ
12.5 μA
DMAX
Maximum Internal Duty Cycle
DMAX Setting Current
DMAX and SCFG Current Matching1
COMP
VCOMP, VDMAX, VSS, and VSCFG = 5 V
VDMAX = 0 V, RFREQ = 100 kΩ
97.37
11
%
IDMAX
9.5
12.5 μA
10
%
Maximum COMP Pin Voltage
Internal Peak-to-Peak Ramp Voltage
COMP Maximum Internal Ramp Voltage
COMP Minimum Internal Ramp Voltage
DH and DL Shutdown Range2
Maximum Duty Cycle Range2
VCOMP
V p-p
5
V
V
V
V
V
V
4
4.5
0.45 0.5
Internal oscillator is disabled
COMP not regulated
0.55
0.45
VCOMP
VCOMP
4.4
Rev. B | Page 3 of 18
ADP1972
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min Typ
Max Unit
PRECISION ENABLE LOGIC (EN)
Maximum EN Pin Voltage
EN Threshold Rising
EN Threshold Falling
EN Pin Current
60
1.4
V
V
V
μA
1.25
1.22
0.32
1.1
VEN = 5 V
2
MODE LOGIC
Maximum MODE Pin Voltage
MODE Threshold Rising
MODE Threshold Falling
CURRENT LIMIT (CL)
Set Current
Buck Internal Reference
Boost Internal Reference
Hiccup Detect Time
Hiccup Off-Time
5.5
1.5
V
V
V
1.20
1.05
0.7
18
ICL
VCL = 0 V
20
21
μA
mV
mV
ms
ms
VREF (BUCK)
VREF (BOOST)
250 300
450 500
350
550
6.1
6.1
RFREQ = 100 kΩ
RFREQ = 100 kΩ
4.4
4.4
5.2
5.2
VREG
LDO Regulator Output Voltage
Guaranteed Output Current
Line Regulation
VVREG
IOUT (MAX)
VIN = 6 V to 60 V
VIN = 6 V
VIN = 6 V to 60 V
VIN = 6 V, IOUT = 0 mA to 5 mA
4.9
0.7
0.5
5
5.1
5
5.1
5.1
V
mA
V
5
5
Load Regulation
V
FAULT
Maximum FAULT Pin Voltage
FAULT Threshold Rising
FAULT Threshold Falling
FAULT Pin Current
60
1.5
V
V
V
μA
1.2
1.05
0.49
VFAULT = 5 V
2
PWM DRIVE LOGIC SIGNALS (DH/DL)
DL Drive Voltage
DH Drive Voltage
DL and DH Sink Resistance
DL and DH Source Resistance
DL and DH Pull-Down Resistor
THERMAL SHUTDOWN (TSD)
TSD Threshold Rising
TSD Threshold Falling
VDL
VDH
No load
No load
IDL = 10 mA
IDL = 10 mA
VREG
VREG
1.2
1.4
1
V
V
Ω
Ω
2.4
2.6
1.5
MΩ
150
135
°C
°C
1 The DMAX and SCFG current matching specification is calculated by taking the absolute value of the difference between the measured ISCFG and IDMAX currents, dividing
them by the 11 μA typical value, and multiplying this answer by 100.
ISCFG IDMAX
DMAX and SCFG Current Matching(%)
100
11μA
2 See Figure 11 for a graph of the duty cycle vs. the applied COMP pin voltage.
Rev. B | Page 4 of 18
Data Sheet
ADP1972
ABSOLUTE MAXIMUM RATINGS
In applications with high power dissipation and poor printed
Table 2.
circuit board (PCB) thermal resistance, the maximum ambient
temperature may need to be derated. In applications with
moderate power dissipation and low PCB thermal resistance,
the maximum ambient temperature can exceed the maximum
limit when the junction temperature is within specification
limits.
Parameter
Rating
VIN, EN, FAULT to GND
SYNC, COMP, MODE to GND
DH, DL, SS, DMAX, SCFG, CL to GND
GNDSENSE to GND
−0.3 V to +61 V
−0.3 V to +5.5 V
−0.3 V to VREG + 0.3 V
−0.3 V to +0.3 V
Operating Ambient Temperature Range −40°C to +85°C
The junction temperature (TJ) of the device is dependent on the
ambient temperature (TA), the power dissipation of the device (PD),
and the junction to ambient thermal resistance of the package (θJA).
Use the following equation to calculate the maximum junction
temperature (TJ) from the ambient temperature (TA) and power
dissipation (PD):
Junction Temperature
Storage Temperature Range
125°C
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
TJ = TA + (PD × θJA)
(1)
For additional information on thermal resistance, refer to
Application Note AN-000, Thermal Characteristics of IC
Assembly.
Absolute maximum ratings apply individually only, not in
combination.
ESD CAUTION
THERMAL OPERATING RANGES
The ADP1972 can be damaged when the junction temperature
limits are exceeded. The maximum operating junction
temperature (TJ MAX) takes precedence over the maximum
operating ambient temperature (TA MAX). Monitoring ambient
temperature does not guarantee that the junction temperature
(TJ) is within the specified temperature limits.
Rev. B | Page 5 of 18
ADP1972
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DL
DH
CL
GND
GND
SENSE
VREG
VIN
ADP1972
SCFG
FREQ
DMAX
SS
TOP VIEW
EN
(Not to Scale)
MODE
SYNC
FAULT
COMP
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
DL
DH
VREG
Logic Drive Low Output for External Low-Side MOSFET Driver.
Logic Drive High Output for External High-Side MOSFET Driver.
Internal Low Dropout (LDO) Voltage Regulator Output and Internal Bias Supply. A bypass capacitance of 1 µF or
greater from this pin to ground is required.
4
5
6
VIN
EN
MODE
High Input Voltage Supply Pin. Bypass this pin with a 4.7 µF capacitor to ground.
Logic Enable Input. Drive EN logic low to shut down the device. Drive EN logic high to turn on the device.
Mode Select. Drive MODE logic low to place the device in boost/recycle mode. Drive MODE logic high to place
the device in buck/charge mode of operation.
7
SYNC
FAULT
COMP
SS
Synchronization Pin. This pin is used as an input and synchronized to an external clock or used as an output
clock to synchronize with other channels.
Fault Input Pin. Signaled by an overcurrent protection (OCP) or overvoltage protection (OVP) fault condition on
the companion ASIC, AD8450. The ADP1972 is disabled until this pin is logic high.
Output Error Amplifier Signal from the companion ASIC, AD8450. This pin is the error input to the ADP1972 and
is compared internally to the linear ramp to produce the PWM signal. Do not leave this pin floating.
Soft Start Control Pin. A capacitor connected from SS to ground brings the output up slowly during power-up
and reduces the inrush current.
8
9
10
11
DMAX
Maximum Duty Cycle Input. Connect an external resistor to ground to set the maximum duty cycle. If the 98%
internal maximum duty cycle is sufficient for the application, tie this pin to VREG. If DMAX is left floating, this
pin is internally tied to VREG.
12
13
FREQ
SCFG
Frequency Set Pin. Connect an external resistor between this pin and ground to set the frequency between
50 kHz and 300 kHz.
Synchronization Configuration Input. Drive VSCFG ≥ 4.53 V to configure SYNC as an output clock signal. Drive
VSCFG < 4.25 V to configure SYNC as an input. Connect a resistor to ground with 0.65 V < VSCFG < 4.25 V to
introduce a phase shift to the synchronized clock. Drive VSCFG ≤ 0.5 V to configure SYNC as an input with no
phase shift so that it synchronizes the device to an external clock source. If SCFG is left floating, the SYNC pin
is internally tied to VREG, and SYNC is configured as an output.
14
15
16
GND
GNDSENSE
CL
Power and Analog Ground Pin.
Ground Sense for the Current-Limit Setting Resistor.
Current-Limit Programming Pin. Connect a current-limit sense resistor in series with the FET source to set the
peak current limit.
Rev. B | Page 6 of 18
Data Sheet
ADP1972
TYPICAL PERFORMANCE CHARACTERISTICS
VVIN = VEN = VFAULT = 24 V, VMODE = VCL = VSS = VCOMP = 0 V, TA = 25°C, unless otherwise noted.
5.8
5.7
5.6
5.5
5.4
5.3
5.2
0.45
0.40
0.35
0.30
0.25
0.20
0.15
RISING
FALLING
T
T
T
= +125°C
= +25°C
= –40°C
A
A
A
–40
–5
30
65
100
6
15
24
33
42
51
60
TEMPERATURE (°C)
EN PIN VOLTAGE (V)
Figure 3. Input Voltage UVLO Threshold vs. Temperature,
VFAULT = 0 V
Figure 6. EN Pin Current vs. EN Pin Voltage, VEN = 5 V and VFAULT = 0 V
30
25
20
15
10
5
1.25
T
T
T
= +125°C
= +25°C
= –40°C
A
A
A
RISING
1.24
1.23
1.22
FALLING
1.21
1.20
0
6
15
24
33
42
51
60
–40
–5
30
65
100
INPUT VOLTAGE (V)
TEMPERATURE (°C)
Figure 4. Shutdown Current vs. Input Voltage, VEN = 0 V and VFAULT = 0 V
Figure 7. EN Pin Threshold vs. Temperature, VFAULT = 0 V
1.9
5.00
4.98
4.96
4.94
4.92
4.90
4.88
V
V
V
= 6V
T
T
T
T
= +125°C
= +85°C
= +25°C
= –40°C
IN
IN
IN
A
A
A
A
= 24V
= 60V
1.8
1.7
1.6
1.5
1.4
1.3
6
15
24
33
42
51
60
–40
0
40
80
120
INPUT VOLTAGE (V)
TEMPERATURE (°C)
Figure 5. Nonswitching Quiescent Current vs. Input Voltage (SYNC = Floating)
Figure 8. SS Pin Current vs. Temperature
Rev. B | Page 7 of 18
ADP1972
Data Sheet
97.8
97.7
97.6
97.5
97.4
97.3
210
190
170
150
130
110
90
70
T
T
T
= +125°C
= +25°C
= –40°C
A
A
A
50
97.2
6
30
50
15
24
33
42
51
60
100
150
200
(kHz)
250
300
INPUT VOLTAGE (V)
f
SET
Figure 9. Maximum Internal Duty Cycle vs. Input Voltage,
Figure 12. RFREQ (MASTER) vs. Switching Frequency (fSET)
RFREQ = 100 kΩ, VCOMP = 5 V, and No Load on DL, DH, or DMAX
450
5.020
5.015
5.010
5.005
5.000
4.995
4.990
T
T
T
= +125°C
= +25°C
= –40°C
T
T
T
T
= +125°C
= +85°C
= +25°C
= –40°C
A
A
A
A
A
A
A
400
350
300
250
200
150
100
50
0
0
20
40
60
80
100
6
15
24
33
42
51
60
DUTY CYCLE (%)
INPUT VOLTAGE (V)
Figure 10. RDMAX vs. Duty Cycle, RFREQ = 100 kΩ, VCOMP = 5 V, and
No Load on DL or DH
Figure 13. VREG vs. Input Voltage, No Load
100
5.020
5.015
5.010
5.005
5.000
4.995
4.990
4.985
4.980
T
T
T
= +125°C
= +25°C
= –40°C
A
A
A
80
60
40
20
0
T
T
T
T
= +125°C
= +85°C
= +25°C
= –40°C
A
A
A
A
0.5
1.0
1.5
2.0
2.5
3.0
(V)
3.5
4.0
4.5
5.0
0
1
2
3
4
5
V
LOAD CURRENT (mA)
COMP
Figure 11. Duty Cycle vs. VCOMP, RFREQ = 100 kΩ, and
No Load on DL, DH, or DMAX
Figure 14. VREG vs. Load Current
Rev. B | Page 8 of 18
Data Sheet
ADP1972
T
EN
1
VREG
2
V
V
= 24V
IN
COMP
= 2.5V
NO C
SS
SYNC
3
DL
4
CH1 10.0V CH2 5.0V 100µs
CH3 5.0V CH4 5.0V
5.0GS/s
10M POINTS
14.42%
CH1
7.00V
T
Figure 15. Startup
Rev. B | Page 9 of 18
ADP1972
Data Sheet
THEORY OF OPERATION
C
C
4.7µF
VREG
1µF
IN
VIN
VREG
MODE
24V
MODE
SELECT
15V
5V
EN
VREG
M1
M2
DH
DL
VREG = 5V
1MΩ
1MΩ
L
EXTERNAL
DRIVER
DRIVE
LOGIC
VOUT
C
OUT
TSD
BAND GAP
UVLO
V
= 1.252V
BG
FAULT
SYNC
MODE
SELECT
AD8450
VREG
8.5MΩ
I
500mV
CL
20µA
SYNC
DETECT
R
CL
20kΩ
CL
1MΩ
R
S
GND
SENSE
FREQ
300mV
OSCILLATOR
I
FREQ
VREG
RFREQ
VREG
I
I
FREQ
CONFIG
DETECT
FREQ
SCFG
DMAX
4V
GND
C
DMAX
R
DMAX
AGND PGND
COMP
AD8450
VREG
ADP1972
I
SS
5µA
SS
C
SS
Figure 16. Block Diagram
The ADP1972 is a constant frequency, voltage mode, PWM
controller for buck or boost, dc-to-dc, asynchronous
applications with an external, high voltage FET, half bridge
driver, and an external error signal generating device, such as
the AD8450. The ADP1972 has a high input voltage range,
multiple externally programmed control pins, and integrated
safety features.
The VREG pin is the output of the internal LDO regulator. The
internal LDO regulator generates the 5 V (typical) rail that is
used internally to bias the control circuitry and can be used
externally as a pull-up voltage for the MODE, SYNC, DMAX,
and FAULT pins. Bypass the VREG pin to ground with a 1 µF
ceramic capacitor.
When operating with an input voltage above 50 V, additional
input filtering is necessary. Figure 17 shows the recommended
filter configuration.
SUPPLY PINS
The ADP1972 has two voltage supply pins, VIN and VREG.
The VIN pin operates from an external supply that ranges from
6 V to 60 V and is the supply voltage for the internal LDO
regulator of the ADP1972. Bypass the VIN pin to ground with a
4.7 µF or greater ceramic capacitor.
ADP1972
R
VIN
SUPPLY > 50V
4.7µF
C
Figure 17. Recommended Filter Configuration for
Input Voltages Greater than 50 V
Rev. B | Page 10 of 18
Data Sheet
ADP1972
EN/SHUTDOWN
OPERATING MODES
The EN input turns the ADP1972 on or off. The EN pin of the
ADP1972 can operate from voltages up to 60 V and is designed
with stable 20ꢀ thresholds for precision enable control. When
the EN voltage is less than 1.22 V (typical), the ADP1972 shuts
down, driving both DL and DH low. When the ADP1972 is shut
down, the VIN supply current is 15 μA (typical). When the EN
voltage is greater than 1.25 V (typical), the ADP1972 is enabled.
The ADP1972 can be programmed to operate as an asynchronous
boost or as an asynchronous buck. If the MODE pin is driven
low by less than 1.05 V (typical), then the ADP1972 operates in
a boost configuration. A boost configuration is ideal for power
recycling and discharging in battery charging applications.
When the MODE pin is driven high by greater than 1.20 V
(typical), the ADP1972 operates in a buck configuration for
battery charging. See Figure 19 and Figure 20 for the ADP1972
behavior in each mode. When the ADP1972 is enabled, the
internal LDO regulator connected to the VREG pin also powers up.
On the rising edge of VREG, the state of the MODE pin is latched,
preventing the mode of operation from being changed while the
device is enabled. To change between boost and buck modes of
operation, shutdown or disable the ADP1972, adjust the MODE
pin to change the operating mode, and restart the system.
The device can be disabled via the EN pin, a fault condition
indicated by a TSD event, a UVLO condition, or an external
fault condition signaled via the FAULT pin.
UNDERVOLTAGE LOCKOUT (UVLO)
There is internal UVLO for the VIN pin. When VIN rises, the
UVLO does not allow the ADP1972 to turn on unless VIN is
greater than 5.71 V (typical). When VIN falls, the UVLO disables
the device when VIN drops below 5.34 V (typical). The UVLO
prevents potentially erratic operation of the application at low
input voltages that may damage the ADP1972 and the external
circuitry. The UVLO levels have ~370 mV of hysteresis to ensure
glitch free startup.
The operating mode can be changed when the EN pin is driven
low, the FAULT pin is driven low, or the ADP1972 is disabled
via a TSD event or UVLO condition. On the rising edge of the
FAULT control signal, the state of the MODE pin is latched,
preventing the mode of operation from being changed while the
device is enabled.
SOFT START
BOOST MODE CONFIGURATION
The ADP1972 is equipped with a programmable soft start that
prevents output voltage overshoot during startup. When the
ADP1972 is enabled with the EN pin, the VREG voltage begins
rising to 5 V. When VREG reaches 90ꢀ of its 5 V (typical) value,
the 5 μA (typical) internal soft start current (ISS) begins charging
the soft start capacitor (CSS), causing the voltage on the SS pin
(VSS) to rise. While VSS is less than 0.52 V (typical), the ADP1972
switching control remains disabled.
MODE ≤ 1.05V (TYPICAL)
V
≥ 4.53V (TYPICAL)
SCFG
4.5V
COMP
INTERNAL RAMP
(4V p-p)
0.5V
0V
VREG (5V TYPICAL)
DH
0V
When VSS reaches 0.52 V (typical), switching is enabled, and
regulation of the ADP1972 control loop begins. As CSS continues
to charge and VSS rises, the PWM duty cycle gradually increases,
allowing the output voltage to rise linearly with little to no over-
shoot during startup. CSS charges and VSS rises until VSS reaches
the internal VREG voltage (5 V typical). When the internal system
duty cycle is less than the soft start duty cycle, the internal control
loop takes control of the ADP1972. See Figure 18 for a soft start
diagram.
VREG (5V TYPICAL)
DL
0V
Figure 19. Signal Diagram for Boost Configuration
BUCK MODE CONFIGURATION
MODE ≥ 1.2V (TYPICAL)
V
≥ 4.53V (TYPICAL)
SCFG
4.5V
COMP
INTERNAL RAMP
(4V p-p)
There is an active, internal, pull-down resistor on the SS pin
that discharges CSS when the device shuts down to prevent a
fault from occurring.
0.5V
0V
VREG (5V TYPICAL)
tREG
DH
VOUT
0V
VREG
VREG (5V TYPICAL)
DL
V
SS
0V
Figure 20. Signal Diagram for Buck Configuration
0.52V
0V
ENABLE
ADP1972
BEGIN
REGULATION
Figure 18. Soft Start Diagram
Rev. B | Page 11 of 18
ADP1972
Data Sheet
When the SS pin exceeds 0.52 V (typical), the ADP1972 resumes
PWM regulation.
PWM DRIVE SIGNALS
The ADP1972 has two output drive signals, DH and DL, that
are compatible with drivers similar to the IR2110S.
Figure 21 shows the current limit block diagram for peak
current limit protection.
The drive signal DL is active when the MODE pin is logic low
and the ADP1972 is configured in the boost/recycle mode. The
DL drive signal turns on and off the low-side switch driven from
the external driver. While in the boost/recycle mode, the DH
signal is driven low to prevent the high-side switch from turning
on and only allows the body diode to conduct.
MODE
SELECT
M2
VREG
I
500mV
CL
20µA
R
CL
20kΩ
CL
R
The drive signal DH is active when the MODE pin is logic high
and the ADP1972 is configured in the buck/charge mode. The
DH drive signal turns on and off the high-side switch driven
from the external driver. While in the buck/charge mode, the
DL signal is driven low to prevent the low-side switch from
turning on, and it only allows the body diode to conduct.
S
300mV
Figure 21. Current Limit Block Diagram
PWM FREQUENCY CONTROL
The FREQ, SYNC, and SCFG pins are all used to determine the
source, frequency, and synchronization of the clock signal that
operates the PWM control of the ADP1972.
When driving capacitive loads with the DH and DL pins, a
20 Ω resistor must be placed in series with the capacitive load
to reduce ground noise and ensure signal integrity.
Internal Frequency Control
EXTERNAL COMP CONTROL
The ADP1972 frequency can be programmed with an external
resistor connected between FREQ and ground. The range of
frequency can be set from a minimum of 50 kHz to a maximum
of 300 kHz. If the SCFG pin is tied to VREG, forcing VSCFG ≥ 4.53 V,
or if the SCFG pin is left floating, the SYNC pin is configured as
an output, and the ADP1972 operates at the frequency set by
The ADP1972 COMP pin is the input to the error amplifier that
controls the PWM output on the DH pin or DL pin. The ADP1972
uses voltage mode control that compares an error signal, applied to
the COMP pin by an external device, such as the AD8450, to an
internal 4 V p-p triangle waveform. As the load changes, the error
signal increases or decreases. The internal PWM comparator
determines the appropriate duty cycle drive signal by monitoring
the error signal at the COMP pin and the internal 4 V p-p ramp
signal. The internal PWM comparator subsequently drives the
external gate driver at the determined duty cycle through the DH
and DL drive control pins.
RFREQ, which outputs from the SYNC pin through the open drain
device. The output clock of the SYNC pin operates with a 50%
(typical) duty cycle. In this configuration, the SYNC pin can be
used to synchronize other switching regulators in the system to
the ADP1972. When the SYNC pin is configured as an output,
an external pull-up resistor is needed from the SYNC pin to an
external supply. The VREG pin of the ADP1972 is used as the
external supply rail for the pull-up resistor.
The functional voltage range of the COMP pin is from 0 V to
5.0 V. If V COMP is less than 0.5 V (typical), the DH and DL
outputs are disabled. If VCOMP is between 0.5 V and 4.5 V, the
ADP1972 regulates the DH and DL outputs accordingly. If
External Frequency Control
When VSCFG ≤ 0.5 V, the SYNC pin is configured as an input,
and the ADP1972 synchronizes to the external clock applied to
the SYNC pin and operates as a slave device. This synchronization
allows the ADP1972 to operate at the same switching frequency
with the same phase as other switching regulators or devices in
the system. When operating the ADP1972 with an external
clock, select RFREQ to provide a frequency that approximates but
is not equal to the external clock frequency, which is further
explained in the Applications Information section.
VCOMP is greater than 4.5 V, the ADP1972 operates the DH and
DL outputs at the maximum programmed duty cycle (98%
default). The input to the COMP pin must never exceed the
5.5 V absolute maximum rating.
The DL and DH signals swing from VREG (5 V typical) to ground.
The external FET driver used must have input control pins
compatible with a 5 V logic signal.
CURRENT LIMIT
Operating Frequency Phase Shift
The ADP1972 features a peak hiccup current limit implementation.
When the peak inductor current exceeds the programmed current
limit for more than 500 consecutive clock cycles, 5.2 ms (typical)
for a 100 kHz programmed frequency, the peak hiccup current
limit condition occurs. PWM regulation of the output voltage
then disables for 500 clock cycles, which is enough time for the
output to discharge, and the average power dissipation to reduce.
When the 500 clock cycles have expired, the ADP1972 restarts.
When the voltage applied to the SCFG pin is 0.65 V < VSCFG
<
4.25 V, the SYNC pin is configured as an input, and the ADP1972
synchronizes to a phase shifted version of the external clock
applied to the SYNC pin. To adjust the phase shift, place a
resistor (RSCFG) from SCFG to ground. The phase shift reduces
the input supply ripple for systems containing multiple
switching power supplies.
Rev. B | Page 12 of 18
Data Sheet
ADP1972
low to prevent switching of the system dc-to-dc converter, and
the soft start is reset. When a voltage greater than 1.20 V
(typical) is applied to the FAULT pin, the ADP1972 begins
switching. A voltage ranging from 0 V to 60 V can be applied to
the FAULT pin of the ADP1972.
MAXIMUM DUTY CYCLE
The maximum duty cycle of the ADP1972 can be externally
programmed to any value between 0% and 98% via an external
resistor on the DMAX pin connected from DMAX to ground.
The maximum duty cycle defaults to 98% if DMAX is left
floating, is tied to VREG, or is programmed to a value greater
than 98%.
THERMAL SHUTDOWN (TSD)
The ADP1972 has a TSD protection circuit. The thermal
shutdown triggers and disables switching when the junction
temperature of the ADP1972 reaches 150°C (typical). While in
TSD, the DL and DH signals are driven low and the CSS capacitor
discharges to ground. VREG remains high. When the junction
temperature decreases to 135°C (typical), the ADP1972 restarts
the application control loop.
EXTERNAL FAULT SIGNALING
The ADP1972 is equipped with a FAULT pin that signals the
ADP1972 when an external fault condition occurs. The external
fault signal stops PWM operation of the system to avoid damage to
the application and components. When a voltage less than 1.05
V (typical) is applied to the FAULT pin, the ADP1972 disables.
In this state, the DL and DH PWM drive signals are both driven
Rev. B | Page 13 of 18
ADP1972
Data Sheet
APPLICATIONS INFORMATION
The ADP1972 has many programmable features that are
optimized and controlled for a given application. The ADP1972
provides pins for selecting the operating mode, controlling the
current limit, selecting an internal or external clock, setting the
operating frequency, phase shifting the operating frequency,
programming the maximum duty cycle, and adjusting the
soft start.
ADJUSTING THE OPERATING FREQUENCY
If the SCFG pin is tied to VREG, forcing VSCFG ≥ 4.53 V, or if
SCFG is left floating and internally tied to VREG, the ADP1972
operates at the frequency set by RFREQ, and the SYNC pin outputs
a clock at the programmed frequency. When VSCFG ≥ 4.53 V, the
output clock on the SYNC pin can be used as a master clock in
applications that require synchronization.
BUCK OR BOOST SELECTION
If VSCFG is ≤ 0.5 V, the SYNC pin is configured as an input,
and the ADP1972 operates as a slave device. As a slave device,
the ADP1972 synchronizes to the external clock applied to
the SYNC pin. If the voltage applied to the SCFG pin is
0.65 V < VSCFG < 4.25 V, and a resistor is connected between
SCFG and ground, the SYNC pin is configured as an input,
and the ADP1972 synchronizes to a phase shifted version of the
external clock applied to the SYNC pin.
To operate the ADP1972 in boost/recycle mode, apply a voltage
less than 1.05 V (typical) to the MODE pin. To operate the
ADP1972 in buck/discharge mode, drive the MODE pin high,
greater than 1.2 V (typical). The state of the MODE pin can
only be changed when the ADP1972 is shutdown via the EN
pin, or disabled via an external fault condition signaled on the
FAULT pin, a TSD event, or a UVLO condition.
Whether operating the ADP1972 as a master or as a slave
device, RFREQ must be carefully selected using the equations in
the following sections.
SELECTING RS TO SET THE CURRENT LIMIT
See Figure 21 for the current-limit block diagram for peak
current-limit control. Use using the following equation to set
the current limit:
Selecting RFREQ for a Master Device
When VSCFG is ≥ 4.53 V, t h e ADP1972 operates as a master device.
When functioning as a master device, the ADP1972 operates at
the frequency set by the external RFREQ resistor connected between
FREQ and ground, and the ADP1972 outputs a clock at the
programmed frequency on the SYNC pin.
100 mV
IPK
(
mA
)
=
(1)
RS
where:
PK is the desired peak current-limit in mA.
RS is the sense resistor used to set the peak current limit in Ω.
I
Figure 22 shows the relationship between the programmed
When the ADP1972 is configured to operate in buck/charge
mode, the internal current-limit reference is set to 300 mV
(typical). When the ADP1972 is configured to operate in
boost/recycle mode, the internal current-limit reference is set to
500 mV (typical). The external resistor, RCL, is needed to offset
the current properly to detect the peak in both buck and boost
operation. Set the value of RCL to 20 kΩ. In operation, the
equation for setting the peak current follows:
switching frequency (fSET) and the value of RFREQ
.
210
190
170
150
130
110
90
For buck/charge mode, it is
VREF (BUCK) = (ICL) × (RCL) − (IPK) × (RS)
For boost/recycle mode, it is
VREF (BOOST) = (ICL) × (RCL) + (IPK) × (RS)
where:
(2)
(3)
70
50
30
50
100
150
200
(kHz)
250
300
f
SET
VREF (BUCK) = 300 mV, typical.
REF (BOOST) = 500 mV, typical.
Figure 22. RFREQ vs. Switching Frequency (fSET
)
V
I
CL = 20 µA, typical.
Use the following equation to calculate the RFREQ value for a
desired master clock synchronization frequency:
RCL = 20 kΩ.
The ADP1972 is designed so that the peak current limit is
104
SET (kHz)
the same in both the buck mode and boost mode of operation.
A 1% or better tolerance for the RCL and RS resistors is
recommended.
RFREQ (MASTER)
(
kΩ
)
=
(4)
f
where:
SET is the switching frequency in kHz.
FREQ (MASTER) is the resistor in kΩ to set the frequency for master
devices.
f
R
Rev. B | Page 14 of 18
Data Sheet
ADP1972
Selecting RFREQ for a Slave Device
Lastly, to calculate the phase delay (TDELAY), use the following
equation:
To configure the ADP1972 as a slave device, drive VSCFG < 4.53 V.
When functioning as a slave device, the ADP1972 operates at
the frequency of the external clock applied to the SYNC pin. To
ensure proper synchronization, select RFREQ to set the frequency
to a value slightly slower than that of the master clock by using
the following equation:
RSCFG (kΩ) = 0.45 × RFREQ (SLAVE) (kΩ) + 50 × TDELAY (ꢀs)
(9)
where:
R
SCFG is the corresponding resistor for the desired phase shift
in kHz.
When using the phase shift feature, connect a capacitor of 47 pF
or greater in parallel with RSCFG
R
FREQ (SLAVE) = 1.11 × RFREQ (MASTER)
where:
FREQ (MASTER) is the resistor value that corresponds to the
frequency of the master clock applied to the SYNC pin.
FREQ (SLAVE) is the resistor value that appropriately scales the
(5)
.
Alternatively, the SCFG pin can be controlled with a voltage
source. When using an independent voltage source, ensure
R
VSCFG ≤ VREG under all conditions. When the ADP1972 is
R
disabled via the EN pin or UVLO, VREG = 0 V, and the voltage
source must adjust accordingly to ensure VSCFG ≤ VREG.
frequency for the slave device, and 1.11 is the RFREQ slave to
master ratio for synchronization.
Figure 23 shows the internal voltage ramp of the ADP1972. The
voltage ramp has a well controlled 4 V p-p.
The frequency of the slave device is set to a frequency slightly
lower than that of the master device to allow the digital
synchronization loop of the ADP1972 to synchronize to the
T
4.5V
master clock period. The slave device has approximately a 30%
range capability to adjust to match the master clock value.
Setting RFREQ (SLAVE) to 1.11× larger than RFREQ (MASTER) runs the
synchronization loop in approximately the center of the
adjustment range.
0.5V
0.01T
0.99T
Programming the External Clock Phase Shift
Figure 23. Internal Voltage Ramp
If a phase shift is not required for slave devices, connect SCFG
of each slave device to ground. For devices that require a phase
shifted version of the synchronization clock that is applied to
PROGRAMMING THE MAXIMUM DUTY CYCLE
The ADP1972 is designed with a 98% (typical) internal
maximum duty cycle. By connecting a resistor from DMAX to
ground, the maximum duty cycle can be programmed at any
value from 0% to 98%, using the following equation:
the SYNC pin of the slave devices, connect a resistor (RSCFG
)
from SCFG to ground to program the desired phase shift. To
determine the RSCFG for a desired phase shift (φSHIFT), start by
calculating the frequency of the slave clock (fSLAVE).
21.5VFREQ RDMAX
DMAX
%
10.5
(10)
104
RFREQ(SLAVE)
RFREQ
f
SLAVE (kHz)
(6)
(7)
where:
D
V
MAX is the programmed maximum duty cycle.
FREQ is 1.252 V (typical).
Next, calculate the period of the slave clock.
1
103
R
DMAX is the value of the resistance used to program the
maximum duty cycle.
FREQ is the frequency set resistor used in the application.
TSLAVE
μs
f
SLAVE (kHz)
R
where:
SLAVE is the period of the master clock in ꢀs.
SLAVE is the frequency of the master clock in kHz.
T
f
The current source of DMAX is equivalent to the programmed
current of the FREQ pin:
Next, determine the phase time delay (TDELAY) for the desired
phase shift (φSHIFT) using the following equation:
VFREQ
RFREQ
IDMAX IFREQ
(11)
φ
SHIFT TSLAVE
μs
where IDMAX = IFREQ = the current programmed on the
FREQ pin.
TDELAY
where:
T
φ
μs
(8)
360
The maximum allowable duty cycle of the ADP1972 is 98%
(typical). If the resistor on DMAX sets a maximum duty cycle
larger than 98%, the ADP1972 defaults to its internal
DELAY is the phase delay in ꢀs.
SHIFT is the desired phase shift.
maximum. If the 98% internal maximum duty cycle is sufficient
for the application, tie the DMAX pin to VREG or leave it floating.
The CDMAX capacitor connected from the DMAX pin to GND
must be 47 pF or greater.
Rev. B | Page 15 of 18
ADP1972
Data Sheet
A CSS capacitor is not required for the ADP1972. When the CSS
capacitor is not used, the internal 5 µA (typical) current source
immediately pulls the SS pin voltage to VREG. When a CSS
capacitor is not used, there is no soft start control internal to the
ADP1972, and the system could produce a large output overshoot
and a large peak inductor spike during startup. When a CSS is
not used, ensure that the output overshoot is not large enough
to trip the hiccup current limit during startup.
ADJUSTING THE SOFT START PERIOD
The ADP1972 has a programmable soft start feature that
prevents output voltage overshoot during startup. Refer to
Figure 18 for a soft start diagram. Use the following equation to
calculate the delay time before switching is enabled (tREG):
0.52
tREG
=
×CSS
(12)
ISS
where ISS = 5 µA, typical.
Rev. B | Page 16 of 18
Data Sheet
ADP1972
PCB LAYOUT GUIDELINES
•
When building a system with a master and multiple slave
devices, the capacitance of the trace attached to the SYNC
pin must be minimized.
For high efficiency, good regulation, and stability, a well
designed PCB layout is required.
Use the following guidelines when designing the PCB (see
Figure 16 for the block diagram and Figure 2 for the pin
configuration).
o For small systems with only a few slave devices, a
resistor connected in series between the master SYNC
signal and the slave SYNC input pins limits the
capacitance of the trace and reduces the fast ground
currents that can inject noise into the master device.
o For larger applications, the series resistance is not
enough to isolate the master SYNC clock. In larger
systems, use an external buffer to reduce the
capacitance of the trace. The external buffer has the
drive capability to support a large number of slave
devices.
•
•
•
•
•
•
Keep the low effective series resistance (ESR) input supply
capacitor for VIN (CIN) as close as possible to the VIN and
GND pins to minimize noise being injected into the device
from board parasitic inductance.
Keep the low ESR input supply capacitor for VREG (CVREG
as close as possible to the VREG and GND pins to
minimize noise being injected into the device from board
parasitic inductance.
Place the components for the SCFG, FREQ, DMAX, and SS
pins close to the corresponding pins. Tie these components
collectively to an AGND plane that makes a Kelvin connection
to the GND pin.
Keep the trace from the COMP pin to the accompanying
device (for example, AD8450) as short as possible. Avoid
routing this trace near switching signals and shield the
trace if possible.
)
NMOS
POWER
FET
SOURCE
R
CL
20kΩ
CL
GND
SENSE
R
S
GND
GROUND
BUS
Place any trace or components for the SYNC pin away from
sensitive analog nodes. When using an external pull-up, it is
best to use a local 0.1 µF bypass capacitor from the supply
of the pull-up resistor to GND.
Figure 24. Recommended RS Kelvin Ground Connection
Keep the traces from the DH and DL pins to the external
components as short as possible to minimize parasitic
inductance and capacitance, which affect the control
signal. The DH and DL pins are switching nodes; do not
route them near any sensitive analog circuitry.
Keep high current traces as short and as wide as possible.
Connect the ground connection of the ADP1972 directly
to the ground connection of the current sense, RS, resistor.
Connect CL through a 20 kΩ resistor directly to RS.
Use a Kelvin connection shown in Figure 24 and Figure 25
from the following:
•
•
•
•
o
o
o
The GND pin to the ground point for RS
The GNDSENSE pin to the ground point for RS
The system power ground to the ground point of RS
Extra resistance due to PCB routing introduces a voltage
difference between the GND pin and the GNDSENSE pin.
This voltage difference must not exceed 0.3 V.
CL
GNDSENSE
GND
Figure 25. Recommended RS Kelvin Ground Connection on PCB Layout
Rev. B | Page 17 of 18
ADP1972
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 26. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Package
Ordering
Quantity
Model1
Package Description
Option
RU-16
RU-16
ADP1972ARUZ-R7
ADP1972ARUZ-RL
ADP1972-EVALZ
−40°C to +125°C
−40°C to +125°C
16-Lead Thin Shrink Small Outline Package [TSSOP], 7”Tape and Reel
16-Lead Thin Shrink Small Outline Package [TSSOP], 13”Tape and Reel
Evaluation Board
1,000
2,500
1 Z = RoHS Compliant Part.
©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11884-0-11/14(B)
Rev. B | Page 18 of 18
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