ADP1851-EVALZ [ADI]
Wide Range Input, Synchronous, Step-Down DC-to-DC Controller;
| 型号： | ADP1851-EVALZ |
| 厂家： | 
ADI |
| 描述： | Wide Range Input, Synchronous, Step-Down DC-to-DC Controller |
| 文件： | 总24页 (文件大小：1117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Wide Range Input, Synchronous,
Step-Down DC-to-DC Controller
Data Sheet
ADP1851
FEATURES
TYPICAL OPERATION CIRCUIT
V
IN
Input voltage range: 2.75 V to 20 V
Output voltage range: 0.6 V to 90% VIN
Maximum output current of more than 25 A
Current mode architecture
R
RAMP
VIN
DH
RAMP
EN
M1
L
V
BST
OUT
Configurable to voltage mode
1% output voltage accuracy over temperature
Voltage tracking
Programmable frequency: 200 kHz to 1.5 MHz
Synchronization input
Power saving mode at light load
Precision enable input
Power good with internal pull-up resistor
Adjustable soft start
Programmable current sense gain
Integrated bootstrap diode
SW
ILIM
FB
VCCO
ADP1851
M2
DL
SYNC
R
HIGH
CSG
PGND
FREQ
LOW
SS/TRK
COMP
PGOOD
AGND (EP)
Figure 1.
Starts into a precharged load
Externally adjustable slope compensation
Suitable for any output capacitor
Overvoltage and overcurrent-limit protection
Thermal overload protection
Input undervoltage lockout (UVLO)
Available in 16-lead, 4 mm × 4 mm LFCSP
Supported by ADIsimPower design tool
The ADP1851 provides a high speed, high peak current gate
driving capability to enable energy efficient power conversion.
The device can be configured to operate in power saving mode
by skipping pulses, reducing switching losses, and improving
efficiency at light load and standby conditions.
The accurate current limit allows design within a narrower
range of tolerances and can reduce overall converter size and
cost. The ADP1851 can regulate down to 0.6 V output using a
high accuracy reference with 1% tolerance over the
temperature range of −40°C to +125°C.
APPLICATIONS
Intermediate bus and POL systems requiring sequencing and
tracking, including
Telecom base station and networking
Industrial and instrumentation
Medical and healthcare
With its wide range input voltage, the ADP1851 provides the
designer with maximum flexibility for use in a variety of system
configurations; loop compensation, soft start, frequency setting,
power saving mode, current limit, and current sense gain can
all be programmed using external components. In addition, the
external RAMP resistor allows the selection of optimal slope
and VIN feedforward in both current and voltage modes for
excellent line rejection. The linear regulator and the bootstrap
diode for the high-side driver are internal.
GENERAL DESCRIPTION
The ADP1851 is a wide range input, dc-to-dc, synchronous
buck controller capable of running from commonly used 3.3 V
to 12 V (up to 20 V) voltage inputs. The device nominally
operates in current mode with valley current sensing providing
the fastest step response for digital loads. It can also be config-
ured as a voltage mode controller with low noise and crosstalk
for sensitive loads.
Protection features include undervoltage lockout, overvoltage,
overcurrent/short circuit, and overtemperature.
The ADP1851 is ideal in system applications requiring multiple
output voltages. The ADP1851 includes a synchronization feature
to eliminate beat frequencies between switching devices. It also
provides accurate tracking capability between supplies and
includes precision enable and power-good functions for simple,
robust sequencing.
Rev. B
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ADP1851
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Enable/Disable Control ............................................................. 14
Thermal Overload Protection .................................................. 14
Applications Information.............................................................. 15
ADIsimPower Design Tool ....................................................... 15
Setting the Output Voltage........................................................ 15
Soft Start ...................................................................................... 15
Setting the Current Limit.......................................................... 15
Accurate Current-Limit Sensing.............................................. 15
Input Capacitor Selection.......................................................... 15
VIN Pin Filter ............................................................................. 16
Boost Capacitor Selection ......................................................... 16
Inductor Selection...................................................................... 16
Output Capacitor Selection....................................................... 16
MOSFET Selection..................................................................... 17
Loop Compensation—Voltage Mode...................................... 18
Loop Compensation—Current Mode ..................................... 19
Switching Noise and Overshoot Reduction............................ 20
Voltage Tracking......................................................................... 21
PCB Layout Guidelines.............................................................. 21
Typical Operating Circuits............................................................ 22
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 23
Applications....................................................................................... 1
General Description......................................................................... 1
Typical Operation Circuit................................................................ 1
Revision History ............................................................................... 2
Simplified Block Diagram ............................................................... 3
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 11
Control Architecture.................................................................. 11
Oscillator Frequency.................................................................. 11
Synchronization.......................................................................... 12
PWM and Pulse Skip Modes of Operation............................. 12
Synchronous Rectifier and Dead Time ................................... 13
Input Undervoltage Lockout..................................................... 13
Internal Linear Regulator .......................................................... 13
Overvoltage Protection.............................................................. 13
Power Good................................................................................. 13
Short-Circuit and Current-Limit Protection.......................... 14
REVISION HISTORY
4/2019—Rev. A to Rev. B
Changes to Figure 24...................................................................... 15
2/2017—Rev. 0 to Rev. A
Updated Outline Dimensions....................................................... 23
Change to Ordering Guide............................................................ 23
8/2012—Revision 0: Initial Version
Rev. B | Page 2 of 24
Data Sheet
ADP1851
SIMPLIFIED BLOCK DIAGRAM
VIN
VCCO
AGND
(EPAD)
OV
0.6V
UV
THERMAL
SHUTDOWN
LDO
REF
VCCO
UVLO
OV
UV
0.63V
LOGIC
LOGIC
EN_SW
12.5kΩ
EN
OV_TH
PGOOD
FB
SYNC
1MΩ
UV_TH
PH
OSCILLATOR
FREQ
COMP
FB
VCCO
ERROR
AMPLIFIER
–
+
+
SS/TRK
BST
DH
PH
EN_SW
OVER_LIM
OV
V
= 0.6V
REF
DRIVER LOGIC
–
+
CONTROL AND
STATE
VCCO
SW
DL
PULSE SKIP
6.5µA
0.9V
MACHINE
VCCO
OV
LOGIC
–
+
FAULT
3kΩ
EN OVER_LIM
PWM
CS GAIN
COMPARATOR
DCM
+
SLOPE COMPENSATION
AND RAMP GENERATOR
PGND
ZERO
CROSS
DETECT
–
RAMP
–
A
= 0*, 3, 6, 12
V
CURRENT SENSE
AMPLIFIER
VCCO
50µA
+
+
CURRENT-LIMIT
CONTROL
OVER_LIM
ILIM
–
*0 (ZERO) GAIN IS FOR VOLTAGE MODE WITH RAMP FROM 0.7V TO 2.2V.
Figure 2. Simplified Block Diagram
Rev. B | Page 3 of 24
ADP1851
Data Sheet
SPECIFICATIONS
All limits at temperature extremes, TJMIN and TJMAX, are guaranteed via correlation using standard statistical quality control (SQC). VIN =
12 V. The specifications are valid for TJ = −40°C to +125°C, unless otherwise specified. Typical values are at TA = 25°C.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
POWER SUPPLY
Input Voltage
Undervoltage Lockout Threshold UVLOTRSH
VIN
2.75
2.55
2.35
20
2.75
2.50
V
V
V
V
VIN rising
VIN falling
2.65
2.45
0.2
Undervoltage Lockout Hysteresis UVLOHYST
Quiescent Current
IIN
EN = VIN = 12 V, VCOMP = 0.6 V in forced pulse-
width modulation (PWM) mode (not
switching), SYNC = VCCO
4.2
5.7
mA
EN = VIN = 12 V, VCOMP = 0.6 V in PSM mode,
SYNC = AGND
EN = AGND, VIN = 5.5 V or 20 V
2.5
mA
µA
Shutdown Current
ERROR AMPLIFIER
FB Input Bias Current
Open-Loop Gain1
Gain Bandwidth Product1
IIN_SD
IFB
100
200
−100
+1
80
20
3
+100
nA
dB
MHz
V/V
CURRENT SENSE AMPLIFIER GAIN
ACS
Current sense gain resistor connected
2.6
3.4
between DL and PGND, RCSG = 47 kΩ 5%
Current sense gain resistor connected
between DL and PGND, RCSG = 22 kΩ 5%
5.2
6
6.8
V/V
Default setting, RCSG = open
Voltage mode operation, resistor connected
between DL and PGND, RCSG = 100 kΩ 5%
10.5
12
0
13.5
V/V
V/V
OUTPUT CHARACTERISTICS
Feedback Accuracy Voltage
VFB
597
594
600
600
603
606
mV
mV
%/V
%
TJ = −40°C to +85°C
TJ = −40°C to +125°C
Line Regulation of PWM
Load Regulation of PWM1
OSCILLATOR
VFB/VIN
0.015
0.3
VFB/VCOMP VCOMP range = 0.9 V to 2.2 V
Frequency
fOSC
RFREQ = 332 kΩ to AGND
170
720
1275
240
480
170
100
200
800
1500
300
600
230
880
1725
360
720
kHz
kHz
kHz
kHz
kHz
kHz
ns
RFREQ = 78.7 kΩ to AGND
RFREQ = 40.2 kΩ to AGND
FREQ connected to AGND
FREQ connected to VCCO
RFREQ range from 332 kΩ to 40.2 kΩ
SYNC Input Frequency Range1
SYNC Input Pulse Width1
SYNC Pin Capacitance to AGND
LINEAR REGULATOR
fSYNC
tSYNCMIN
CSYNC
1725
5
pF
VCCO Output Voltage
VCCO Load Regulation
VCCO Line Regulation
VCCO Current Limit1
VCCO Short-Circuit Current1
VIN to VCCO Dropout Voltage2
LOGIC INPUTS
IVCCO = 100 mA
4.7
5.0
35
10
350
370
0.33
5.3
V
IVCCO = 0 mA to 100 mA
VIN = 5.5 V to 20 V, IVCCO = 20 mA
VCCO drops to 4 V from 5 V
VCCO < 0.5 V
mV
mV
mA
mA
V
400
VDROPOUT
IVCCO = 100 mA, VIN ≤ 5 V
EN Threshold Voltage
EN Hysteresis
EN Input Leakage Current
EN rising
0.57
0.63
0.03
1
0.68
200
V
V
nA
IEN
VIN = 2.75 V to 20 V
Rev. B | Page 4 of 24
Data Sheet
ADP1851
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
V
V
SYNC Logic Input Low
SYNC Logic Input High
1.3
1.9
SYNC Input Pull-Down Resistance RSYNC
GATE DRIVERS
1
MΩ
DH Rise Time
DH Fall Time
DL Rise Time
DL Fall Time
DH to DL Dead Time
DH or DL Driver RON, Sourcing
Current1
CDH = 3 nF, VBST − VSW = 5 V
CDH = 3 nF, VBST − VSW = 5 V
CDL = 3 nF
CDL = 3 nF
External 3 nF connected to DH and DL
Sourcing 2 A with a 100 ns pulse
16
14
16
14
25
2
ns
ns
ns
ns
ns
Ω
RON_SOURCE
Sourcing 1 A with a 100 ns pulse, VIN = 3 V
VIN = 3 V or 12 V
Sinking 2 A with a 100 ns pulse
2.3
0.3
1.5
Ω
%/°C
Ω
DH or DL Driver RON, Tempco
DH or DL Driver RON, Sinking
Current1
TCRON
RON_SINK
Sinking 1 A with a 100 ns pulse, VIN = 3 V
fOSC = 300 kHz
fOSC = 1500 kHz
fOSC = 200 kHz to 1500 kHz
fOSC = 200 kHz to 1500 kHz
fOSC = 200 kHz to 1500 kHz
2
Ω
DH Maximum Duty Cycle1
90
50
%
%
ns
ns
ns
Minimum DH On Time
Minimum DH Off Time
Minimum DL On Time
85
345
295
COMP VOLTAGE RANGE
COMP Pulse Skip Threshold
COMP Clamp High Voltage
THERMAL SHUTDOWN
VCOMP,THRES
VCOMP,HIGH
In pulse skip mode (PSM)
0.9
V
V
2.2
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
TTMSD
155
20
°C
°C
OVERVOLTAGE AND POWER-GOOD
THRESHOLDS
FB Overvoltage Threshold
FB Overvoltage Hysteresis
FB Undervoltage Threshold
FB Undervoltage Hysteresis
SOFT START/TRACK
VOV
VUV
VFB rising
VFB falling
0.630
0.525
0.65
18
0.55
15
0.670
0.575
V
mV
V
mV
SS/TRK Output Current
SS/TRK Pull-Down Resistor
SS/TRK Input Voltage Range1
FB to SS/TRK Offset
ISS
During startup
During a fault condition
4.6
6.5
3
8.4
µA
kΩ
V
0
−10
5
+10
VSS/TRK = 0.1 V to 0.6 V; offset = VFB − VSS/TRK
Internal pull-up resistor to VCCO
mV
PGOOD
PGOOD Pull-Up Resistor
PGOOD Delay
Overvoltage or Undervoltage
Minimum Duration
ILIM Threshold Voltage1
RPGOOD
12.5
12
10
kΩ
µs
µs
Minimum duration required to trigger the
PGOOD signal
Relative to PGND
ILIM = PGND
After DL goes high; current limit is not sensed
during this period
−5
45
0
50
100
+5
55
mV
µA
ns
ILIM Output Current
Current Sense Blanking Period
INTEGRATED RECTIFIER
(BOOST DIODE) RESISTANCE
At 20 mA forward current
16
2
Ω
ZERO CURRENT CROSS OFFSET
(SW TO PGND)1
In pulse skip mode only; fOSC = 300 kHz
0
4
mV
1 Guaranteed by design.
2 Connect VIN to VCCO when VIN < 5.5 V.
Rev. B | Page 5 of 24
ADP1851
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Parameter
Rating
VIN, EN, RAMP
FB, COMP, SS/TRK, FREQ, SYNC, VCCO,
PGOOD
ILIM, SW to PGND
BST, DH to PGND
DL to PGND
BST to SW
BST to PGND, 20 ns Transients
SW to PGND, 20 ns Transients
DL, SW, ILIM to PGND, 20 ns
Negative Transients
21 V
−0.3 V to +6 V
−0.3 V to +21 V
−0.3 V to +28 V
−0.3 V to VCCO + 0.3 V
−0.3 V to +6 V
32 V
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages are
referenced to AGND.
25 V
−8 V
ESD CAUTION
PGND to AGND
PGND to AGND, 20 ns Transients
θJA (Natural Convection)1, 2
−0.3 V to +0.3 V
−8 V to +4 V
40°C/W
Operating Junction Temperature Range3 −40°C to +125°C
Storage Temperature Range
Maximum Soldering Lead Temperature
−65°C to +150°C
260°C
1 Measured with exposed pad attached to PCB.
2 Junction-to-ambient thermal resistance (θJA) of the package was calculated
or simulated on a multilayer PCB.
3 The junction temperature (TJ) of the device is dependent on the ambient
temperature (TA), the power dissipation of the device (PD), and the junction-
to-ambient thermal resistance of the package (θJA). Maximum junction
temperature is calculated from the ambient temperature and power
dissipation using the formula TJ = TA + PD × θJA.
Rev. B | Page 6 of 24
Data Sheet
ADP1851
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
EN 1
12 BST
SS/TRK
2
3
4
ADP1851
TOP
VIEW
11 DH
10 SW
FB
9
DL
COMP
NOTES
1. THE EXPOSED PAD IS THE AGND
POWER INPUT OF THE IC; CONNECT
IT TO THE SYSTEM AGND PLANE.
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1
EN
Enable Input. Drive EN high to turn the controller on, and drive EN low to turn the controller off. Tie EN to VIN for
automatic startup. For a precision UVLO, connect an appropriately sized resistor divider from VIN to AGND, and
tie the midpoint to this pin.
2
SS/TRK
Soft Start/Tracking Input. Connect a capacitor from SS/TRK to AGND to set the soft start time. This node is
internally pulled up to VCCO through a 6.5 µA current source. Use this pin as the TRK input for tracking an
external voltage during startup.
3
4
FB
COMP
Output Voltage Feedback Input. Connect this pin to an output via a resistor divider.
Compensation Node. Output of the error amplifier. Connect a resistor/capacitor (RC) network from COMP to FB
to compensate the regulation control loop.
5
SYNC
Frequency Synchronization Input. This pin accepts an external clock signal with a frequency close to 1× the
internal oscillator frequency, fOSC, set by the FREQ pin. The controller operates in forced PWM mode when a
periodic clock signal is detected at SYNC or when SYNC is high (connected to VCCO). The resulting switching
frequency is 1× the SYNC frequency. When SYNC is low or left floating, the controller operates in pulse skip
mode.
6
7
VIN
Input Voltage. Connect to main power supply. Bypass with a 1 µF or larger ceramic capacitor connected as close
as possible to this pin and AGND.
Output of the Internal Low Dropout (LDO) Regulator. The internal circuitry and gate drivers are powered from
VCCO. Bypass VCCO to AGND with a 1 μF or larger ceramic capacitor. The VCCO output remains active even
when EN is low. For operations at VIN below 5.5 V, VIN can be connected to VCCO. Do not use the LDO to power
other auxiliary system loads.
VCCO
8
9
PGND
DL
Power Ground. Ground for internal driver. Differential current is sensed between SW and PGND.
Low-Side Synchronous Rectifier Gate Driver Output. To program the gain of the current sense amplifier in a
current mode or to set voltage mode control, connect a resistor between DL and PGND. This pin is capable of
driving MOSFETs with a total input capacitance up to 20 nF.
10
11
12
SW
DH
BST
Power Switch Node/Current Sense Amplifier Input. Connect this pin to the source of the high-side N-channel
MOSFET and the drain of the low-side N-channel MOSFET. Differential current is sensed between SW and PGND.
High-Side Switch Gate Driver Output. This pin is capable of driving MOSFETs with a total input capacitance up
to 20 nF.
Bootstrapped Upper Rail of High-Side Internal Driver. Connect a multilayer ceramic capacitor (MLCC) with a
value from 0.1 µF to 0.22 µF between BST and SW. An internal boost diode rectifier is connected between VCCO
and BST.
13
ILIM
Current-Limit Sense Comparator Inverting Input. Connect a resistor between ILIM and SW to set the current-
limit offset. For accurate current-limit sensing, connect ILIM to a current sense resistor at the source of the
low-side MOSFET.
14
15
PGOOD
RAMP
Power Good. PGOOD is the open-drain power-good indicator logic output with an internal 12.5 kΩ resistor
connected between PGOOD and VCCO.
Programmable Current Setting for Slope Compensation. Connect a resistor from RAMP to VIN. The voltage at
RAMP is 0.2 V during operation. This pin is high impedance when the controller is disabled.
Rev. B | Page 7 of 24
ADP1851
Data Sheet
Pin No. Mnemonic
Description
16
FREQ
Internal Oscillator Frequency, fOSC. Sets the desired operating frequency between 200 kHz and 1.5 MHz with one
resistor between FREQ and AGND. Connect FREQ to AGND for a preprogrammed 300 kHz, or tie FREQ to VCCO
for 600 kHz operating frequency.
EPAD (AGND)
Exposed Pad, Analog Ground. The exposed pad is the AGND power input of the IC. Connect the exposed pad to
the system AGND plane.
Rev. B | Page 8 of 24
Data Sheet
ADP1851
TYPICAL PERFORMANCE CHARACTERISTICS
100
100
90
80
70
60
50
40
30
20
10
0
PULSE SKIP
PULSE SKIP
FORCED PWM
FORCED PWM
90
80
70
60
50
40
30
20
10
0
0.1
1
10
100
0.1
1
10
100
LOAD (A)
LOAD (A)
Figure 4. Efficiency Plot
Figure 7. Efficiency Plot
12 VIN to 1.8 VOUT, 600 kHz (see Figure 34 for Circuit)
12 VIN to 3.3 VOUT, 300 kHz (see Figure 35 for Circuit)
LOAD
CURRENT
LOAD CURRENT
4
4
VOUT_AC
VOUT_AC
2
2
B
B
B
M 100µs 50MS/s A CH4
20ns/pt
13.4A
CH2 200mV
CH4 10A
M 100µs 5.0MS/s
200ns/pt
A CH4
14.2A
CH2 100mV
CH4 10A
W
W
W
W
Ω B
Ω
Figure 8. 10 A to 20 A Load Step,
Figure 5. 10 A to 20 A Load Step,
12 VIN to 3.3 VOUT, 300 kHz, Voltage Mode
12 VIN to 1.8 VOUT, 600 kHz, Current Mode
VIN
VIN
1
2
1
VOUT_AC
VOUT_AC
2
B
B
W
B
B
M 100µs 250MS/s A CH1
4ns/pt
11.3V
CH1 5V
CH2 200mV
CH1 5V
CH2 100mV
M 100µs 125MS/s A CH1
8.0ns/pt
11.3V
W
W
W
Figure 6. 9 V to 15 V Line Step,
1.8 VOUT, 20 A Load, Current Mode
Figure 9. 9 V to 15 V Line Step,
3.3 VOUT, 15 A Load, Voltage Mode
Rev. B | Page 9 of 24
ADP1851
Data Sheet
EN
SYNC
1
3
1
SW
DH
3
4
VOUT
DL
2
B
B
B
B
B
CH2 500mV
W
M 1.0µs 250MS/s A CH1
4ns/pt
3.1V
M 2ms 250kS/s A CH1
4µs/pt
580mV
CH1 5V
CH1 1V
W
W
W
W
B
CH3 10V
CH4 5V
CH3 10V
W
Figure 10. Synchronization, fSYNC = 600 kHz
Figure 13. Soft Start with Precharged Output, 1.8 VOUT Forced PWM Mode
35
45
V
= 12V
T
= 25°C
IN
A
OUTPUT IS LOADED
OUTPUT IS LOADED
34
33
32
31
30
29
28
27
26
25
43
41
39
37
35
33
31
29
27
25
HS FET = BSC080N03LS
LS FET = BSC030N03LS
HS FET = BSC080N03LS
LS FET = BSC030N03LS
DEAD TIME BETWEEN SW FALLING EDGE
AND DL RISING EDGE, INCLUDING DIODE RECOVERY TIME
DEAD TIME BETWEEN SW FALLING EDGE
AND DL RISING EDGE, INCLUDING DIODE RECOVERY TIME
–40
–20
0
20
40
60
80
100
120
140
0
5
10
(V)
15
20
TEMPERATURE (°C)
V
IN
Figure 14. Dead Time vs. VIN
Figure 11. Dead Time vs. Temperature
4.5
350
300
250
200
150
100
50
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 2.75V, SOURCING
IN
DH MINIMUM OFF TIME
V
= 12V, SOURCING
IN
V
= 2.75V, SINKING
IN
V
= 12V, SINKING
IN
DH MINIMUM ON TIME
2.5
5.0
7.5
10.0
12.5
(V)
15.0
17.5
20.0
–40
–15
10
35
60
85
110
135
V
TEMPERATURE (°C)
IN
Figure 12. Typical DH Minimum On Time and Off Time
Figure 15. Driver Resistance vs. Temperature
Rev. B | Page 10 of 24
Data Sheet
ADP1851
THEORY OF OPERATION
The ADP1851 is a fixed frequency, step-down, synchronous
switching controller with integrated drivers and bootstrapping
for external N-channel power MOSFETs. The current mode
control loop can also be configured to voltage mode. The
controller can be set to operate in pulse skip mode for power
saving at light loads or in forced PWM mode. The ADP1851
includes programmable soft start, output overvoltage
protection, programmable current limit, power good, and
tracking functions. The controller can operate at a switching
frequency between 200 kHz and 1.5 MHz that is programmed
with a resistor or synchronized to an external clock.
As shown in Figure 16, the emulated current ramp is generated
inside the IC, but offers programmability through the RAMP
pin. Selecting an appropriate value resistor to connect between
VIN and the RAMP pin programs a desired slope compensation
value and, at the same time, provides a VIN feedforward feature.
Control logic enforces antishoot-through operation to limit
cross-conduction of the internal drivers and external MOSFETs.
OSCILLATOR FREQUENCY
The internal oscillator frequency, which ranges from 200 kHz
to 1.5 MHz, is set by an external resistor, RFREQ, at the FREQ
pin. Some common fOSC values are shown in Table 4, and a
graphical relationship is shown in Figure 17. For example,
a 78.7 kΩ resistor sets the oscillator frequency to 800 kHz.
Connecting FREQ to AGND or FREQ to VCCO sets the oscil-
lator frequency to 300 kHz or 600 kHz, respectively. For other
frequencies that are not listed in Table 4, the values of RFREQ and
CONTROL ARCHITECTURE
The ADP1851 is based on a fixed frequency, emulated peak
current mode, PWM control architecture. The inductor current
is sensed by the voltage drop measured across the external low-
side MOSFET, RDSON, or across the sense resistor placed in series
between the low-side MOSFET source and the power ground.
The current is sensed during the off period of the switching
cycle and is conditioned with the internal current sense
amplifier.
f
OSC can be obtained from Figure 17, or use the following
empirical formula to calculate these values:
R
FREQ(kΩ) = 96,568 × fOSC (kHz)−1.065
The gain of the current sense amplifier is programmable to
3 V/V, 6 V/V, or 12 V/V during the controller power-up
initialization before the device starts switching. A 47 kΩ resistor
between DL and PGND programs a gain of 3 V/V; a 22 kΩ
resistor sets a gain of 6 V/V. Without a resistor, the gain is
programmed to 12 V/V.
Table 4. Setting the Oscillator Frequency
RFREQ
fOSC (Typical)
332 kΩ
78.7 kΩ
60.4 kΩ
51 kΩ
40.2 kΩ
FREQ to AGND
FREQ to VCCO
200 kHz
800 kHz
1000 kHz
1200 kHz
1500 kHz
300 kHz
600 kHz
The output signal of the current sense amplifier is held, added
to the emulated current ramp in the next switching cycle during
the DH on time, and fed into the PWM comparator, as shown
in Figure 16. This signal is compared with the COMP signal
from the error amplifier and resets the flip-flop, which
generates the PWM pulse. If voltage mode control is selected by
placing a 100 kΩ resistor between DL and PGND, the emulated
current ramp is fed to the PWM comparator without adding the
current sense signal.
410
360
310
260
210
160
110
60
–1.065
R
(kΩ) = 96,568 fOSC (kHz)
FREQ
TO
DRIVERS
OSC
Q
S
V
V
IN
IN
FF
R
RAMP
I
RAMP
R
Q
A
R
10
100
C
R
400
700
1000
fOSC (kHz)
1300
1600
1900
SW
PGND
V
CS
Figure 17. RFREQ vs. fOSC
A
CS
FROM
ERROR AMP
Figure 16. Simplified Control Architecture
Rev. B | Page 11 of 24
ADP1851
Data Sheet
SYNCHRONIZATION
SW
The switching frequency of the ADP1851 can be synchronized
to an external clock signal by connecting it to the SYNC pin.
The internal oscillator frequency, programmed by the resistor at
the FREQ pin, must be set close to the external clock frequency;
therefore, the external clock frequency can vary between 0.85×
and 1.3× the internal clock set. The resulting switching frequency
is 1× the external SYNC frequency. When synchronized, the
ADP1851 operates in PWM mode.
3
COMP
1
2
VOUT_AC
INDUCTOR
CURRENT
When an external clock is detected at the first SYNC edge, the
internal oscillator is reset, and the clock control shifts to SYNC.
The SYNC edges then trigger subsequent clocking of the PWM
outputs. The DH rising edge appears approximately 100 ns after
the corresponding SYNC edge, and the frequency is locked to
the external signal. If the external SYNC signal disappears during
operation, the ADP1851 reverts to its internal oscillator. When
the SYNC function is used, it is recommended that a pull-up
resistor be connected from SYNC to VCCO so that when the
SYNC signal is lost, the ADP1851 continues to operate in
PWM mode.
4
B
B
B
W
M 100µs 250MS/s A CH3
4ns/pt
8.2V
CH1 500mV
CH3 10V
CH2 100mV
CH4 10A
W
W
Ω
Figure 18. Example of Pulse Skip Mode Under a Light Load
When the output load is greater than the pulse skip threshold
current, that is, when VCOMP reaches the threshold of 0.9 V, the
ADP1851 exits the pulse skip mode of operation and enters
the fixed frequency discontinuous conduction mode (DCM),
as shown in Figure 19. When the load increases further, the
ADP1851 enters continuous conduction mode (CCM).
PWM AND PULSE SKIP MODES OF OPERATION
The SYNC pin is a multifunctional pin. PWM mode is enabled
when SYNC is connected to VCCO or a high logic. When SYNC is
connected to ground or left floating, pulse skip mode is enabled.
Switching SYNC from low to high or high to low on the fly causes
the controller to transition from forced PWM mode to pulse
skip mode or from pulse skip mode to forced PWM mode,
respectively, in two clock cycles.
DH
3
DL
1
VOUT_AC
2
Table 5. Mode of Operation
INDUCTOR
CURRENT
4
SYNC Pin
Mode of Operation
Low
Pulse skip mode
High
No Connect
Clock Signal
Forced PWM mode
Pulse skip mode
Forced PWM mode
B
B
B
B
M 2µs 1.25GS/s A CH3
IT 40ps/pt
8.2V
CH1 5V
CH2 100mV
CH4 10A
W
W
W
W
CH3 10V
Ω
Figure 19. Example of Discontinuous Conduction Mode (DCM) Waveform
In forced PWM mode, the ADP1851 always operates in CCM at
any load; therefore, the inductor current is always continuous.
The ADP1851 has pulse skip sensing circuitry that allows the
controller to skip PWM pulses, reducing the switching
frequency at light loads and, therefore, maintaining better
efficiency during light load operation. The resulting output
ripple is larger than that of the fixed frequency forced PWM
mode. Figure 18 shows the ADP1851 operating in pulse skip
mode under a light load. Pulse skip frequency under a light load
is dependent on the inductor, output capacitance, output load,
and input and output voltages.
Rev. B | Page 12 of 24
Data Sheet
ADP1851
SYNCHRONOUS RECTIFIER AND DEAD TIME
VIN = 2.75V TO 5.5V
In the ADP1851, the antishoot-through circuit monitors the
DH to SW and DL to PGND voltages and adjusts the low-side
and high-side drivers to ensure break-before-make switching
that prevents cross-conduction or shoot-through between the
high-side and low-side MOSFETs. This break-before-make
switching is known as dead time, which is not fixed and depends
on how fast the MOSFETs are turned on and off. In a typical
application circuit that uses medium sized MOSFETs with an
input capacitance of approximately 3 nF, the typical dead time
is approximately 25 ns. When small and fast MOSFETs with fast
diode recovery times are used, the dead time can be as low as 13 ns.
VIN VCCO
ADP1851
Figure 20. Configuration for VIN < 5.5 V
OVERVOLTAGE PROTECTION
The ADP1851 has a built-in circuit for detecting output over-
voltage at the FB node. When the FB voltage, VFB, rises above
the overvoltage threshold, the high-side N-channel MOSFET
(NMOSFET) is turned off, and the low-side NMOSFET is turned
on until VFB drops below the undervoltage threshold. This action is
known as the crowbar overvoltage protection. If the overvoltage
condition is not removed, the controller maintains the feedback
voltage between the overvoltage and undervoltage thresholds,
and the output is regulated to within typically +8% and −8% of
the regulation voltage. During an overvoltage event, the SS/TRK
node discharges through an internal 3 kΩ pull-down resistor.
When the voltage at FB drops below the undervoltage threshold,
the soft start sequence restarts. Figure 21 shows the overvoltage
protection in PSM.
INPUT UNDERVOLTAGE LOCKOUT
When the bias input voltage at the VIN pin is less than the
undervoltage lockout (UVLO) threshold of 2.65 V typical, the
switch drivers stay inactive. If EN is high, the controller starts
switching and the VIN pin voltage exceeds the UVLO threshold.
INTERNAL LINEAR REGULATOR
The internal linear regulator is a low dropout (LDO) VCCO.
VCCO powers up the internal control circuitry and provides
power for the gate drivers. It is guaranteed to have more than
200 mA of output current capability, which is sufficient to handle
the gate driver requirements of typical logic threshold MOSFETs
driven at up to 1.5 MHz. VCCO is always active and cannot be
shut down by the EN signal; however, the over-temperature
protection event disables the LDO together with the controller.
Bypass VCCO to AGND with a 1 µF or greater capacitor.
DH
3
DL
1
VOUT
Because the LDO supplies the gate driver current, the output of
VCCO is subject to sharp transient currents as the drivers switch
and the boost capacitors recharge during each switching cycle.
The LDO has been optimized to handle these transients without
overload faults. Due to the gate drive loading, using the VCCO
output for other external auxiliary system loads is not
recommended.
2
PGOOD
4
B
B
B
B
M 200µs 250MS/s A CH4
40ns/pt
1.0V
CH1 5V
CH3 10V
CH2 1V
CH4 5V
W
W
W
W
The LDO includes a current limit that is well above the
expected maximum gate driver load. This current limit also
includes a short-circuit foldback to further limit the VCCO
current in the event of a short-circuit fault.
Figure 21. Overvoltage Protection in PSM Mode, VOUT Shorted to 2.0 V
POWER GOOD
The PGOOD pin is an open-drain NMOSFET. An internal
12.5 kΩ pull-up resistor is connected between PGOOD and
VCCO. PGOOD is internally pulled up to VCCO during normal
operation and is active low when triggered. When the feedback
voltage, VFB, rises above the overvoltage threshold or falls below
the undervoltage threshold, the PGOOD output is pulled to
ground after a delay of 12 µs. The overvoltage or undervoltage
condition must exist for at least 10 µs for PGOOD to become
active. The PGOOD output also becomes active if a thermal
overload condition is detected.
For an input voltage of less than 5.5 V, it is recommended to
bypass the LDO by connecting VIN to VCCO, as shown in
Figure 20, thus eliminating the dropout voltage. However, if
the input range is 4 V to 7 V, the LDO cannot be bypassed by
shorting VIN to VCCO because the 7 V input has exceeded the
maximum voltage rating of the VCCO pin. In this case, use the
LDO to drive the internal drivers, but keep in mind that there is
a dropout when VIN is less than 5 V.
Rev. B | Page 13 of 24
ADP1851
Data Sheet
SHORT-CIRCUIT AND CURRENT-LIMIT
PROTECTION
ENABLE/DISABLE CONTROL
The EN pin is used to enable or disable the ADP1851 controller;
the typical precision enable threshold is 0.63 V. When the voltage at
EN rises above the threshold voltage, the controller is enabled and
starts normal operation after initialization of the internal oscillator,
references, settings, and the soft start period. When the voltage
at EN falls to typically 30 mV (hysteresis) below the threshold
voltage, the driver and the internal controller circuits in the
ADP1851 are turned off. The initial settings are still valid;
therefore, reenabling the controller does not change the settings
until the power at the VIN pin is cycled. In addition, the EN
signal does not shut down the LDO regulator at VCCO, which
is always active when VIN is above the UVLO threshold.
When the output is shorted or the output current exceeds the
current limit set by the current-limit setting resistor (between
ILIM and SW) for eight consecutive cycles, the ADP1851 shuts
off both the high-side and low-side drivers and restarts the soft
start sequence every 10 ms, which is known as hiccup mode.
The SS node discharges to zero through an internal 3 kΩ resistor
during an overcurrent or short-circuit event. Figure 22 shows
that the ADP1851 on a high current application circuit maintains
current-limit hiccup mode when the output is shorted.
SW
For the purpose of start-up power sequencing, the startup of the
ADP1851 can be programmed by connecting an appropriate
resistor divider from the master power supply to the EN pin, as
shown in Figure 23. For example, if the desired start-up voltage
from the master power supply is 10 V, R1 and R2 can be set to
156 kΩ and 10 kΩ, respectively.
3
VOUT
2
INDUCTOR
CURRENT
MASTER
SUPPLY
VOLTAGE
V
OUT
ADP1851
4
R1
R2
R
TOP
B
M 4ms 2.5MS/s
400ns/pt
A CH4
18.2V
CH2 1V
CH4 10A
W
W
FB
EN
B
B
CH3 10V
Ω
W
R
BOT
Figure 22. Current-Limit Hiccup Mode, 30 A Current Limit
Figure 23. Optional Power-Up Sequencing Circuit
THERMAL OVERLOAD PROTECTION
The ADP1851 has an internal temperature sensor that senses the
junction temperature of the chip. When the junction tempera-
ture of the ADP1851 reaches approximately 155°C, the ADP1851
goes into thermal shutdown, the converter is turned off, and the
SS/TRK pin discharges toward zero through an internal 3 kΩ
resistor. At the same time, VCCO discharges to zero. When the
junction temperature falls below 135°C, the ADP1851 resumes
normal operation after the soft start sequence.
Rev. B | Page 14 of 24
Data Sheet
ADP1851
APPLICATIONS INFORMATION
ADIsimPower DESIGN TOOL
SETTING THE CURRENT LIMIT
The ADP1851 is supported by the ADIsimPower™ design tool
set. ADIsimPower is a collection of tools that produce complete
power designs optimized for a specific design goal. The tools
allow the user to generate a full schematic and bill of materials
and to calculate performance in minutes. ADIsimPower can
optimize designs for cost, area, efficiency, and parts count while
taking into consideration the operating conditions and limitations
of the IC and all real external components. The ADIsimPower
tool can be found at www.analog.com/ADIsimPower, and the
user can request an unpopulated board through the tool.
The current-limit comparator measures the voltage across the
low-side MOSFET to determine the load current.
The current limit is set by an external current-limit resistor, RILIM
,
between ILIM and SW. The current sense pin, ILIM, sources
nominally 50 ꢀA to this external resistor. This creates an offset
voltage of RILIM multiplied by 50 ꢀA. When the drop across the
current sense element RCS (low-side MOSFET, RDSON) is equal to
or greater than this offset voltage, the ADP1851 flags a current-
limit event.
1.06ILPK RCS
RILIM
SETTING THE OUTPUT VOLTAGE
50 ꢀA
The output voltage is set using a resistive voltage divider from
the output to FB. For RBOT, use a 1 kΩ to 20 kΩ resistor. Choose
RTOP to set the output voltage by using the following equation:
where:
LPK is the peak inductor current.
I
ACCURATE CURRENT-LIMIT SENSING
VOUT VFB
RTOP RBOT
The RDSON of the MOSFET can vary by more than 50% over the
temperature range. Accurate current-limit sensing is achieved
by adding a current sense resistor from the source of the low-
side MOSFET to PGND. Make sure that the power rating of the
current sense resistor is adequate for the application. Figure 24
illustrates the implementation of accurate current-limit sensing.
VFB
where:
R
R
V
TOP is the high-side voltage divider resistance.
BOT is the low-side voltage divider resistance.
OUT is the regulated output voltage.
VFB is the feedback regulation threshold, 0.6 V.
V
IN
SOFT START
ADP1851
The soft start period is set by an external capacitor between SS
and AGND. The soft start function limits the input inrush current
and prevents output overshoot. When EN is enabled, a current
source of 6.5 μA starts charging the capacitor, and the regulation
voltage is reached when the voltage at SS reaches 0.6 V. The soft
start time is approximated by
DH
SW
R
ILIM
ILIM
DL
R
SENSE
Figure 24. Accurate Current-Limit Sensing
0.6 V
t
SS
CSS
INPUT CAPACITOR SELECTION
6.5 ꢀA
Use two parallel capacitors placed close to the drain of the high-
side switch MOSFET (one bulk capacitor of sufficiently high
current rating and a 10 ꢀF ceramic decoupling capacitor).
The SS pin reaches a final voltage equal to VCCO.
When a controller is disabled, for example, if EN is pulled low or
experiences an overcurrent limit condition, the soft start capacitor
is discharged through an internal 3 kꢁ pull-down resistor.
Select the input bulk capacitor based on its ripple current
rating. The minimum input capacitance required for a
particular load is
IO D(1 D)
CIN,MIN
(VPP IO DRESR ) fSW
where:
IO is the output current.
D is the duty cycle.
VPP is the desired input ripple voltage.
R
ESR is the equivalent series resistance of the capacitors.
Rev. B | Page 15 of 24
ADP1851
Data Sheet
VIN PIN FILTER
OUTPUT CAPACITOR SELECTION
It is recommended that a low-pass filter be connected to the
VIN pin. Connecting a resistor, between 2 Ω and 10 Ω, in series
with VIN and a 1 µF ceramic capacitor between VIN and AGND
creates a low-pass filter that effectively filters out any unwanted
glitches caused by the switching regulator. Keep in mind that the
input current may be larger than 100 mA when driving large
MOSFETs. A 100 mA current across a 10 Ω resistor creates a
1 V drop, which is the same voltage drop in VCCO. In this
case, a lower resistor value is desirable.
For maximum allowed switching ripple at the output, choose an
output capacitor that is larger than
∆IL
1
COUT
≅
×
∆VOUT 2 − ∆IL
×
(
RESR
−
(4 fSW × LESL )2 )
2
2
8
fSW
where:
∆IL is the inductor ripple current.
∆VOUT is the target maximum output ripple voltage.
ESR is the equivalent series resistance of the output capacitor
(or the parallel combined ESR of all output capacitors).
LESL is the equivalent series inductance of the output capacitor
R
ADP1851
2Ω TO 10Ω
V
VIN
IN
1µF
(or the parallel combined ESL of all capacitors).
AGND
The impedance of the output capacitor at the switching
frequency multiplied by the ripple current gives the output
voltage ripple. The impedance is made up of the capacitive
impedance plus the nonideal parasitic characteristics, the
equivalent series resistance (ESR), and the equivalent series
inductance (ESL).
Figure 25. Input Filter Configuration
BOOST CAPACITOR SELECTION
Connect a boost capacitor between the SW and BST pins to
provide the current for the high-side driver during switching.
Choose a ceramic capacitor with a value between 0.1 µF and
0.22 µF.
Usually the capacitor impedance is dominated by ESR. The
maximum ESR rating of the capacitor, such as in electrolytic
or polymer capacitors, is provided in the manufacturer’s data
sheet; therefore, the output ripple reduces to
INDUCTOR SELECTION
For most applications, choose an inductor value such that
the inductor ripple current is between 20% and 40% of the
maximum dc output load current.
∆VOUT ≅ ∆IL × RESR
Electrolytic capacitors also have significant ESL, on the order
of 5 nH to 20 nH, depending on type, size, and geometry. PCB
traces contribute some ESR and ESL as well. However, using the
maximum ESR rating from the capacitor data sheet usually
provides some margin such that measuring the ESL may not be
required.
Choose the inductor value using the following equation:
VIN −VOUT VOUT
L =
×
fSW × ∆IL
VIN
where:
L is the inductor value.
In the case of output capacitors where the impedances of the
ESR and ESL are small at the switching frequency, for example,
where the output capacitor is a bank of parallel MLCC capaci-
tors, the capacitive impedance dominates; therefore, the output
capacitance must be larger than
VIN is the input voltage.
V
OUT is the output voltage.
f
SW is the switching frequency.
∆IL is the peak-to-peak inductor ripple current.
Check the inductor data sheet to make sure that the saturation
current of the inductor is well above the peak inductor current
of a particular design.
∆IL
COUT
≅
(1)
8 ∆VOUT × fSW
Make sure that the ripple current rating of the output capacitors
is greater than the maximum inductor ripple current.
To meet the requirement of the output voltage overshoot during
load release, the output capacitance should be larger than
∆ISTEP2L
(VOUT + ∆VOVERSHOOT ) −VOUT
COUT
≅
2
2
(2)
where:
∆VOVERSHOOT is the maximum allowed overshoot.
Select the largest output capacitance given by either Equation 1
or Equation 2.
Rev. B | Page 16 of 24
Data Sheet
ADP1851
If QGSW is not given in the data sheet, it can be approximated by
MOSFET SELECTION
QGS
2
The choice of MOSFET directly affects the dc-to-dc converter
performance. A MOSFET with low on resistance reduces I2R losses,
and low gate charge reduces transition losses. The MOSFET should
have low thermal resistance to ensure that the power dissipated
in the MOSFET does not result in excessive MOSFET die
temperature.
QGSW QGD
where:
GD and QGS are the gate-to-drain and gate-to-source charges
given in the MOSFET data sheet.
Q
I
DRIVER_RISE and IDRIVER_FALL can be estimated by
The high-side MOSFET carries the load current during on time
and usually carries most of the transition losses of the converter.
Typically, the lower the on resistance of the MOSFET, the higher
the gate charge, and vice versa. Therefore, it is important to choose
a high-side MOSFET that balances the two losses. The conduction
loss of the high-side MOSFET is determined by the equation
VDD VSP
RON _ SOURCE RGATE
IDRIVER _ RISE
VSP
IDRIVER _ FALL
RON _ SINK RGATE
where:
DD is the input supply voltage to the driver and is between
)2 RDSON
V
P (I
C
LOAD(RMS)
2.75 V and 5 V, depending on the input voltage.
VSP is the switching point where the MOSFET fully conducts;
this voltage can be estimated by inspecting the gate charge
graph given in the MOSFET data sheet.
where:
DSON is the MOSFET on resistance.
R
The gate charging loss is approximated by the equation
R
ON_SOURCE is the on resistance of the ADP1851 internal driver,
given in Table 1, when charging the MOSFET.
ON_SINK is the on resistance of the ADP1851 internal driver,
given in Table 1, when discharging the MOSFET.
GATE is the on gate resistance of the MOSFET, given in the
MOSFET data sheet. If an external gate resistor is added, add
this external resistance to RGATE
PG VPV QG fSW
where:
R
V
PV is the gate driver supply voltage.
QG is the MOSFET total gate charge.
R
Note that the gate charging power loss is not dissipated in the
MOSFET but rather in the ADP1851 internal drivers. This power
loss should be taken into consideration when calculating the
overall power efficiency.
.
The total power dissipation of the high-side MOSFET is the
sum of the conduction and transition losses:
The high-side MOSFET transition loss is approximated by the
equation
PHS P P
C
T
The synchronous rectifier, or low-side MOSFET, carries the
inductor current when the high-side MOSFET is off. The low-
side MOSFET transition loss is small and can be ignored in the
calculation. For high input voltage and low output voltage, the
low-side MOSFET carries the current most of the time. Therefore,
to achieve high efficiency, it is critical to optimize the low-side
MOSFET for low on resistance. In cases where the power loss
exceeds the MOSFET rating or lower resistance is required than
is available in a single MOSFET, connect multiple low-side
MOSFETs in parallel. The equation for low-side MOSFET
conduction power loss is
VIN ILOAD (tR tF ) fSW
P
T
2
where:
PT is the high-side MOSFET transition loss power.
tR is the rise time in charging the high-side MOSFET.
tF is the fall time in discharging the high-side MOSFET.
tR and tF can be estimated by
QGSW
IDRIVER _ RISE
tR
CLS (ILOAD(RMS))2 RDSON
QGSW
IDRIVER _ FALL
P
tF
where:
Q
GSW is the gate charge of the MOSFET during switching and is
given in the MOSFET data sheet.
DRIVER_RISE and IDRIVER_FALL are the driver current outputs from the
ADP1851 internal gate drivers.
I
Rev. B | Page 17 of 24
ADP1851
Data Sheet
There is also additional power loss during the time, known as
dead time, between the turn-off of the high-side switch and the
turn-on of the low-side switch, when the body diode of the low-
side MOSFET conducts the output current. The power loss in
the body diode is given by
Type III Compensation
G
(dB)
–90°
PHASE
–270°
fZ
fP
PBODYDIODE = VF × tD × fSW × IO
where:
C
HF
VF is the forward voltage drop of the body diode, typically 0.7 V.
tD is the dead time in the ADP1851, typically 25 ns when
driving a medium size MOSFET with input capacitance, CISS,
of approximately 3 nF. The dead time is not fixed. Its effective
value varies with gate drive resistance and CISS; therefore,
R
C
FF FF
R
C
I
Z
R
TOP
V
OUT
FB
COMP
EA
R
BOT
P
BODYDIODE increases in high load current designs and low voltage
INTERNAL
designs.
V
REF
Therefore, the power loss in the low-side MOSFET is
Figure 26. Type III Compensation
PLS = PCLS + PBODYDIODE
If the output capacitor ESR zero frequency is greater than one-
half of the crossover frequency, use the Type III compensator as
shown in Figure 26.
Note that the MOSFET on resistance, RDSON, increases with
increasing temperature, with a typical temperature coefficient of
0.4%/°C. The MOSFET junction temperature (TJ) rise over the
ambient temperature is
Calculate the output LC filter resonant frequency as follows:
1
fLC
=
TJ = TA + θJA × PD
2π LC
(4)
(5)
where:
Choose a crossover frequency that is 1/10 of the switching
frequency:
TA is the ambient temperature.
θJA is the thermal resistance of the MOSFET package.
PD is the total power dissipated in the MOSFET.
fSW
fCO
=
10
LOOP COMPENSATION—VOLTAGE MODE
Set the controller to voltage mode operation by placing a
100 kΩ resistor between DL and PGND. Choose the largest
possible ramp amplitude for the voltage mode below 1.5 V.
The ramp voltage is programmed by a resistor placed between
VIN and the RAMP pin as follows:
Set the poles and zeros as follows:
1
(6)
(7)
f
P1 = fP2
=
fSW
2
fCO fSW
1
f
Z1 = fZ2
=
=
=
4
40 2πRZCI
VIN − 0.2 V
RRAMP
=
or
100 pF × fSW ×VRAMP
fLC
2
1
The voltage at the RAMP pin is fixed at 0.2 V, and the current
going into RAMP should be between 10 µA and 160 µA. Make
sure that the following condition is satisfied:
(8)
f
Z1 = fZ2
=
=
2πRZCI
Use the lower zero frequency from Equation 7 or Equation 8.
Calculate the compensation resistor, RZ, as follows:
VIN −0.2 V
10μA ≤
≤160μA
(3)
RRAMP
RTOPVRAMP fZ1 fCO
(9)
RZ
=
2
VIN fLC
For example, with an input voltage of 12 V, RRAMP should not be
less than 73.8 kΩ.
Next, calculate CI.
Assuming that the LC filter design is complete, the feedback control
system can be compensated. In general, aluminum electrolytic
capacitors have high ESR; however, if several aluminum electrolytic
capacitors are connected in parallel and produce a low effective
ESR, then Type III compensation is needed. In addition, ceramic
capacitors have very low ESR (only a few milliohms), making
Type III compensation a better choice.
1
CI =
(10)
2πRZ fZ1
Because of the finite output current drive of the error amplifier,
CI must be less than 10 nF. If it is larger than 10 nF, choose a
larger RTOP and recalculate RZ and CI until CI is less than 10 nF.
Rev. B | Page 18 of 24
Data Sheet
ADP1851
Because CHF << CI, calculate CHF as follows:
1
For example, with an input voltage of 12 V, RRAMP should not
exceed 1.1 MΩ. If the calculated RRAMP value produces less than
10 µA, then select an RRAMP value that produces between 10 µA
and 15 µA.
CHF
=
(11)
(12)
πfSW RZ
Next, calculate the feedforward capacitor, CFF, assuming
Figure 27 illustrates the connection of the slope compensation
RFF << RTOP
RFF
.
resistor, RRAMP, and the current sense gain resistor, RCSG
.
V
IN
1
R
RAMP
=
πCFF fSW
RAMP
Check that the calculated component values are reasonable.
For example, capacitors smaller than about 10 pF should be
avoided. In addition, RZ values less than 3 kΩ and CI values
greater than 10 nF should be avoided. If necessary, recalculate
the compensation network with a different starting value for
ADP1851
DH
SW
R
ILIM
ILIM
DL
RTOP. If RZ is too small or CI is too big, start with a larger value
R
CSG
for RTOP. This compensation technique should yield a good
working solution.
Figure 27. Slope Compensation and CS Gain Connection
When precise compensation is needed, use the ADIsimPower
design tool.
Setting the Current Sense Gain
The voltage drop across the external low-side MOSFET is sensed
by a current sense amplifier by multiplying the peak inductor
current and the RDSON of the MOSFET. The result is then amplified
by a gain factor of 3 V/V, 6 V/V, or 12 V/V, which is programmable
by an external resistor, RCSG, connected to the DL pin. This gain
is sensed only during power-up and not during normal operation.
The amplified voltage is summed with the slope compensation
ramp voltage and fed into the PWM controller for a stable
regulation voltage.
LOOP COMPENSATION—CURRENT MODE
Compensate the ADP1851 error voltage loop in current mode
using Type II compensation.
Setting the Slope Compensation
In a current mode control topology, slope compensation is needed
to prevent subharmonic oscillations in the inductor current and
to maintain a stable output. The external slope compensation is
implemented by summing the amplified sense signal and a scaled
voltage at the RAMP pin. To set the effective slope compensation,
connect a resistor (RRAMP) between the RAMP pin and the input
voltage (VIN). RRAMP is calculated by
The voltage range of the internal node, VCS, is between 0.4 V and
2.2 V. Select the current sense gain such that the internal minimum
amplified voltage (VCSMIN) is above 0.4 V and the maximum
amplified voltage (VCSMAX) is 2.1 V. Note that VCSMIN or VCSMAX is
not the same as VCOMP, which has a range of 0.9 V to 2.2 V. Make
sure that the maximum VCOMP (VCOMPMAX) does not exceed 2.2 V
to account for temperature and part-to-part variations. See the
7×106 ×L
RRAMP
=
ACS ×RCS
where:
following equations for VCSMIN, VCSMAX, and VCOMPMAX
.
L is the inductor value measured in µH.
1
2
RCS (mΩ) is the resistance of the current sense element between
SW and PGND (RDSON_MAX is the low-side MOSFET maximum
on resistance).
VCSMIN = 0.75 V − IL ×RDSON _ MIN ×ACS
1
2
VCSMAX = 0.75 V+(ILOADMAX
−
IL )×RDSON _ MAX × ACS
A
CS is the current sense amplifier gain and is 3 V/V, 6 V/V,
(VIN − 0.2 V)×tON
or 12 V / V.
VCOMPMAX
=
+VCSMAX
100 pF × RRAMP
Thus, the voltage ramp amplitude, VRAMP, is:
where:
CSMIN is the minimum amplified voltage of the internal current
VIN − 0.2 V
VRAMP
=
V
100 pF × fSW ×RRAMP
sense amplifier at zero output current.
IL is the peak-to-peak ripple current in the inductor.
where 100 pF is the effective capacitance of the internal ramp
capacitor, CRAMP, with 4% tolerance over the temperature and
VIN range.
R
DSON_MIN is the low-side MOSFET minimum on resistance. The
zero current level voltage of the current sense amplifier is 0.75 V.
CSMAX is the maximum amplified voltage of the internal current
sense amplifier at the maximum output current.
LOADMAX is the maximum output dc load current.
DSON_MAX is the low-side MOSFET maximum on resistance.
ACS is the current sense amplifier gain.
The voltage at the RAMP pin is fixed at 0.2 V, and the current
going into RAMP should be between 10 µA and 160 µA. Make
sure that the following condition is satisfied:
V
I
R
VIN −0.2 V
10μA ≤
≤160μA
RRAMP
Rev. B | Page 19 of 24
ADP1851
Data Sheet
V
COMPMAX is the maximum voltage at the COMP pin.
Use the larger value of CI from Equation 16 or Equation 17.
t
ON is the high-side driver (DH) on time.
Because of the finite output current drive of the error amplifier,
CI must be less than 10 nF. If it is larger than 10 nF, choose a
larger RTOP and recalculate RZ and CI until CI is less than 10 nF.
Replace RDSON with the resistance value of the current sense
element, RCS, if it is used.
Next, choose the high frequency pole, fP1, to be 1/2 of fSW.
Type II Compensation
1
2
fP1
fSW
(18)
(19)
G
(dB)
Because CHF << CI,
PHASE
fZ
fP
1
f
P1
–180°
–270°
2RZCHF
C
HF
Combine Equation 18 and Equation 19, and solve for CHF.
1
R
C
I
Z
CHF
fSW RZ
R
TOP
(20)
V
OUT
FB
EA
COMP
R
BOT
For maximally precise compensation solutions, use the
ADIsimPower design tool.
INTERNAL
SWITCHING NOISE AND OVERSHOOT REDUCTION
V
REF
To reduce voltage ringing and noise, it is recommended that an
RC snubber be added between SW and PGND for high current
applications, as illustrated in Figure 29.
Figure 28. Type II Compensation
For Type II compensation, use the circuit shown in Figure 28.
Calculate the compensation resistor, RZ, with the following
equation:
In most applications, RSNUB is typically 2 Ω to 4 Ω, and CSNUB is
typically 1.2 nF to 3 nF.
RZ RTOP RS 2 COUT fCO
where:
(13)
The size of the RC snubber components must be chosen
correctly to handle the power dissipation. The power dissipated
in RSNUB is
f
CO is 1/10 of fSW.
RS = ACS × RDSON_MIN
.
2
PSNUB VIN CSNUB fSW
ACS is the current sense amplifier gain of 3 V/V, 6 V/V, or
12 V/V, set by the gain resistor between DL and PGND.
In most applications, a component size of 0805 for RSNUB is
sufficient. The RC snubber does not reduce the voltage over-
shoot. A resistor, RRISE in Figure 29, at the BST pin helps to reduce
overshoot and is generally between 2 Ω and 4 Ω. Adding a resistor
in series, typically between 2 Ω and 4 Ω, with the gate driver also
helps to reduce overshoot. If a gate resistor is added, RRISE is
not needed.
If the current is sensed on a current sense resistor, RCS, then RS
becomes
RS ACS RCS
Next, choose the compensation capacitor to set the compensa-
tion zero, fZ1, to the lesser of 1/5 of the crossover frequency or
1/2 of the LC resonant frequency.
ADP1851
V
fCO
5
fSW
50
1
IN
R
RISE
(14)
f
Z1
BST
2RZCI
M1
M2
DH
L
V
SW
OUT
or
R
SNUB
C
OUT
fLC
2
1
DL
C
SNUB
(15)
f
Z1
PGND
2RZCI
Figure 29. Application Circuit with a Snubber
Solving for CI in Equation 14 yields
25
RZ fSW
CI
(16)
Solving for CI in Equation 15 yields
1
CI
(17)
RZ fLC
Rev. B | Page 20 of 24
Data Sheet
ADP1851
As the master voltage rises, the slave voltage rises identically.
VOLTAGE TRACKING
Eventually, the slave voltage reaches its regulation voltage, at
which point the internal reference takes over the regulation
while the SS/TRK input continues to increase, thus removing
itself from influencing the output voltage.
The ADP1851 includes a tracking feature that tracks a master
voltage. In all tracking configurations, the output can be set as
low as 0.6 V for a given operating condition.
Two tracking configurations are possible with the ADP1851:
coincident and ratiometric tracking.
To ensure that the output voltage accuracy is not compromised
by the SS/TRK pin being too close in voltage to the reference
voltage (VFB, typically 0.6 V), make sure that the final value of
the SS/TRK voltage of the slave channel is at least 30 mV above VFB.
Coincident Tracking
The most common application is coincident tracking, used
in core vs. I/O voltage sequencing and similar applications. As
shown in Figure 30, coincident tracking forces the ramp rate of
the output voltage to be the same for the master and slave until
the slave output reaches its regulation voltage. Connect the slave
SS/TRK input to a resistor divider from the master voltage that
is the same as the divider used on the slave FB pin. This forces the
slave voltage to be the same as the master voltage. For coincident
tracking, use RTRKT = RTOP and RTRKB = RBOT, as shown in Figure 31.
Ratiometric Tracking
Ratiometric tracking limits the output voltage to a fraction of
the master voltage, as illustrated in Figure 32 and Figure 33. The
final SS/TRK voltage of the slave channel should be set to at
least 30 mV above VFB.
MASTER VOLTAGE
MASTER VOLTAGE
SLAVE VOLTAGE
SLAVE VOLTAGE
TIME
Figure 32. Ratiometric Tracking
3.3V
OUT_MASTER
1.8V
OUT_SLAVE
TIME
V
V
Figure 30. Coincident Tracking
ADP1851
R
R
20kΩ
3.3V
OUT_MASTER
1.8V
OUT_SLAVE
TRKT
TOP
V
V
41.2kΩ
SS/
FB
ADP1851
0.65V
0.6V
TRK
R
20kΩ
R
20kΩ
TRKT
TOP
R
10kΩ
R
10kΩ
TRKB
BOT
SS/
FB
1.1V
0.6V
TRK
R
10kΩ
R
10kΩ
TRKB
BOT
Figure 33. Example of a Ratiometric Tracking Circuit
PCB LAYOUT GUIDELINES
Figure 31. Example of a Coincident Tracking Circuit
The recommended board layout practices for the synchronous
buck controller are described in the AN-1119 Application Note.
The ratio of the slave output voltage to the master voltage is a
function of the two dividers.
RTOP
RBOT
1+
1+
VOUT _SLAVE
VOUT _MASTER
=
RTRKT
RTRKB
Rev. B | Page 21 of 24
ADP1851
Data Sheet
TYPICAL OPERATING CIRCUITS
V
= 9V TO 15V
IN
TO
VCCO
140kΩ
4.99kΩ
1.15kΩ
BST
C
IN
16 15 14 13
EN
SS/TRK
FB
1
2
3
4
12
11
10
9
0.1µF
0.1µF
2Ω
M1
DH
SW
DL
ADP1851
L
V
OUT
1.8V
620pF
25A
21kΩ
EP
C
OUT
COMP
M2
75pF
5
6
7
8
2.49kΩ
1µF
2Ω
TO V
IN
1µF
fSW = 600kHz
: OS-CON 150µF/20V, 20SEP150M, SANYO + 2× CAP CER 10µF 25V X7R 1210, MURATA GRM32DR71E106KA12
C
IN
L: 0.3µH COILCRAFT SER1408-301ME
M1: 2× INFINEON BSC052N03LS
M2: 2× INFINEON BSC0902NS
C
: 2× POSCAP 330µF/2.5V SANYO 2R5TPE330M7 + 2× CAP CER 47µF 10V X5R 1210 MURATA GRM32ER61A476KE20 L
OUT
Figure 34. 25 A Circuit Operating in Current Mode
V
= 9V TO 15V
IN
510pF
196kΩ
32.4kΩ
2.74kΩ
BST
2kΩ
C
IN
16 15 14 13
EN
SS/TRK
1
2
3
4
12
11
10
9
0.1µF
0.1µF
M1
DH
SW
DL
ADP1851
L
V
OUT
FB
3.3V
1600pF
25A
21.5kΩ
75pF
EP
COMP
C
OUT
M2
5
6
7
8
100kΩ
7.15kΩ
1µF
2Ω
TO V
IN
1µF
fSW = 300kHz
: OS-CON 150µF/20V, 20SEP150M, SANYO + CAP CER 10µF 25V X7R 1210, MURATA GRM32DR71E106KA12
C
IN
L: 1µH COILCRAFT SER1412-102ME
M1: INFINEON BSC052N03LS
M2: INFINEON BSC0902NS
C
: POSCAP 330µF/6.3V SANYO 6TPE330MFL + CAP CER 22µF 10V X5R 1210 MURATA GRM32ER61A226KE20L
OUT
Figure 35. 25 A Circuit Operating in Voltage Mode
Rev. B | Page 22 of 24
Data Sheet
ADP1851
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
4.10
4.00 SQ
3.90
0.35
0.30
0.25
PIN 1
INDICATOR
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
13
16
0.65
BSC
12
1
2.70
2.60 SQ
2.50
EXPOSED
PAD
4
9
8
5
0.45
0.40
0.35
0.20 MIN
BOTTOM VIEW
TOP VIEW
SIDE VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
Figure 36. 16-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-16-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
CP-16-17
ADP1851ACPZ-R7
ADP1851-EVALZ
−40°C to +125°C
16-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board: 1.8 V, 25 A Output
1 Z = RoHS Compliant Part.
Rev. B | Page 23 of 24
ADP1851
NOTES
Data Sheet
©2012–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10595-0-4/19(B)
Rev. B | Page 24 of 24
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