ADP151AUJZ-1.8-R7_技术文档

Ultralow Noise,200 mA,

CMOS Linear Regulator

ADP151

TYPICAL APPLICATION CIRCUIT

FEATURES

Ultralow noise: 9 μV rms

V

= 2.3V

V

= 1.8V

IN

OUT

5

1

2

3

VIN

GND

EN

VOUT

NC

No noise bypass capacitor required

Stable with 1 μF ceramic input and output capacitors

Maximum output current: 200 mA

Input voltage range: 2.2 V to 5.5 V

Low quiescent current

1µF

ON

4

OFF

NC = NO CONNECT

Figure 1. TSOT ADP151 with Fixed Output Voltage, 1.8 V

IGND = 10 μA with 0 load

1

2

IGND = 265 ꢀA with 200 mA load

Low shutdown current: <1 μA

Low dropout voltage: 140 mV at 200 mA load

Initial accuracy: 1ꢁ

V

= 1.8V

OUT

V

= 2.3V

OUT

IN

VIN

VOUT

A

C

IN

1µF

TOP VIEW

(Not to Scale)

ON

Accuracy over line, load, and temperature: 2.5ꢁ

16 fixed output voltage options: 1.1 V to 3.3 V

PSRR performance of 70 dB at 10 kHz

Current limit and thermal overload protection

Logic controlled enable

EN

GND

OFF

B

Figure 2. WLCSP ADP151 with Fixed Output Voltage, 1.8 V

Internal pull-down resistor on EN input

5-lead TSOT package

4-ball, 0.4mm pitch WLCSP

APPLICATIONS

RF, VCO, and PLL power supplies

Mobile phones

Digital camera and audio devices

Portable and battery-powered equipment

Post dc-to-dc regulation

Portable medical devices

GENERAL DESCRIPTION

The ADP151 is an ultralow noise, low dropout, linear regulator

that operates from 2.2 V to 5.5 V and provides up to 200 mA of

output current. The low 140 mV dropout voltage at 200 mA

load improves efficiency and allows operation over a wide input

voltage range.

The ADP151 is specifically designed for stable operation with

tiny 1 ꢀF, 30% ceramic input and output capacitors to meet

the requirements of high performance, space constrained

applications.

The ADP151 is capable of 16 fixed output voltage options,

ranging from 1.1 V to 3.3 V.

Using an innovative circuit topology, the ADP151 achieves

ultralow noise performance without the necessity of a bypass

capacitor, making it ideal for noise-sensitive analog and RF

applications. The ADP151 also achieves ultralow noise per-

formance without compromising PSRR or transient line and

load performance. The low 265 μA of quiescent current at

200 mA load makes the ADP151 suitable for battery-operated

portable equipment.

Short-circuit and thermal overload protection circuits prevent

damage in adverse conditions. The ADP151 is available in tiny

5-lead TSOT and 4-ball, 0.4 mm pitch, halide-free WLCSP

packages for the smallest footprint solution to meet a variety of

portable power application requirements.

The ADP151 also includes an internal pull-down resistor on the

EN input.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADP151

TABLE OF CONTENTS

Features .............................................................................................. 1

Typical Performance Characteristics ..............................................7

Theory of Operation ...................................................................... 11

Applications Information .............................................................. 12

Capacitor Selection .................................................................... 12

Enable Feature ............................................................................ 13

Adjustable Output Voltage Operation..................................... 13

Current Limit and Thermal Overload Protection ................. 15

Thermal Considerations............................................................ 15

Printed Circuit Board Layout Considerations............................ 19

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 21

Applications....................................................................................... 1

Typical Application Circuit ............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Input and Output Capacitor, Recommended Specifications.. 4

Absolute Maximum Ratings............................................................ 5

Thermal Data ................................................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

REVISION HISTORY

3/10—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

ADP151

SPECIFICATIONS

V_IN= (V_OUT+ 0.4 V) or 2.2 V, whichever is greater; EN= V_IN, I_OUT= 10 mA, C_IN= C_OUT= 1 μF, T_A= 25°C, unless otherwise noted.

Table 1.

Parameter

Symbol

V_IN

Conditions

Min

Typ

10

Max

Unit

V

INPUT VOLTAGE RANGE

OPERATING SUPPLY CURRENT

T_J= −40°C to +125°C

I_OUT= 0 μA

I_OUT= 0 μA, T_J= −40°C to +125°C

I_OUT= 100 μA

I_OUT= 100 μA, T_J= −40°C to +125°C

I_OUT= 10 mA

I_OUT= 10 mA, T_J= −40°C to +125°C

I_OUT= 200 mA

2.2

5.5

I_GND

μA

ꢀA

μA

20

40

60

90

265

0.2

I_OUT= 200 mA, T_J= −40°C to +125°C

EN = GND

EN = GND, T_J= −40°C to +125°C

350

1.0

+1

SHUTDOWN CURRENT

OUTPUT VOLTAGE ACCURACY

TSOT

I_GND-SD

V_OUT

I_OUT= 10 mA

T_J= −40°C to +125°C

−1

%

V_OUT< 1.8 V

100 μA < I_OUT< 200 mA, V_IN= (V_OUT+ 0.4 V) to 5.5 V

V_OUT≥1.8 V

100 μA < I_OUT< 200 mA, V_IN= (V_OUT+ 0.4 V) to 5.5 V

T_J= −40°C to +125°C

−3

+2

%

−2.5

+1.5

WLCSP

V_OUT

V_OUT< 1.8 V

100 μA < I_OUT< 200 mA, V_IN= (V_OUT+ 0.4 V) to 5.5 V

V_OUT≥1.8 V

100 μA < I_OUT< 200 mA, V_IN= (V_OUT+ 0.4 V) to 5.5 V

−2.5

−2

+2

%

+1.5

REGULATION

Line Regulation

Load Regulation (TSOT)¹

∆V_OUT/∆V_INV_IN= (V_OUT+ 0.4 V) to 5.5 V, T_J= −40°C to +125°C

−0.05

+0.05 %/V

%/mA

∆V_OUT/∆I_OUTV_OUT< 1.8 V

I_OUT= 100 μA to 200 mA

I_OUT= 100 μA to 200 mA, T_J= −40°C to +125°C

V_OUT≥ 1.8 V

0.006

0.003

0.004

%/mA

0.012 %/mA

I_OUT= 100 μA to 200 mA

%/mA

0.008 %/mA

%/mA

I_OUT= 100 μA to 200 mA, T_J= −40°C to +125°C

∆V_OUT/∆I_OUTV_OUT< 1.8 V

Load Regulation (WLCSP)¹

I_OUT= 100 μA to 200 mA

%/mA

I_OUT= 100 μA to 200 mA, T_J= −40°C to +125°C

V_OUT≥1.8 V

0.009 %/mA

I_OUT= 100 μA to 200 mA

I_OUT= 100 μA to 200 mA, T_J= −40°C to +125°C

0.002

10

%/mA

0.006 %/mA

mV

DROPOUT VOLTAGE²

TSOT

V_DROPOUT

I_OUT= 10 mA

I_OUT= 10 mA, T_J= −40°C to +125°C

I_OUT= 200 mA

I_OUT= 200 mA, T_J= −40°C to +125°C

I_OUT= 200 mA

30

mV

150

135

230

200

WLCSP

I_OUT= 200 mA, T_J= −40°C to +125°C

Rev. 0 | Page 3 of 24

ADP151

Parameter

START-UP TIME³

Symbol

T_START-UP

I_LIMIT

Conditions

Min

Typ

180

300

Max

400

Unit

µs

V_OUT= 3.3 V

CURRENT LIMIT THRESHOLD⁴

UNDERVOLTAGE LOCKOUT

Input Voltage Rising

Input Voltage Falling

Hysteresis

T_J= −40°C to +125°C

220

mA

UVLO_RISE

UVLO_FALL

UVLO_HYS

1.96

V

mV

1.28

1.2

120

THERMAL SHUTDOWN

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

TS_SD

T_Jrising

150

15

°C

TS_SD-HYS

EN INPUT

EN Input Logic High

EN Input Logic Low

EN Input Pull-Down Resistance

OUTPUT NOISE

V_IH

V_IL

R_EN

2.2 V ≤ V_IN≤ 5.5 V

V_IN= V_EN= 5.5 V

V

MΩ

0.4

2.6

9

OUT_NOISE

10 Hz to 100 kHz, V_IN= 5 V, V_OUT= 3.3 V

10 Hz to 100 kHz, V_IN= 5 V, V_OUT= 2.5 V

10 Hz to 100 kHz, V_IN= 5 V, V_OUT= 1.1 V

µV rms

9

POWER SUPPLY REJECTION RATIO

V_IN= V_OUT+ 0.5 V

PSRR

10 kHz, V_IN= 3.8 V, V_OUT= 3.3 V, I_OUT= 10 mA

100 kHz, V_IN= 3.8 V, V_OUT= 3.3 V, I_OUT= 10 mA

10 kHz, V_IN= 4.3 V, V_OUT= 3.3 V, I_OUT= 10 mA

100 kHz, V_IN= 4.3 V, V_OUT= 3.3 V, I_OUT= 10 mA

10 kHz, V_IN= 2.2 V, V_OUT= 1.1 V, I_OUT= 10 mA

100 kHz, V_IN= 2.2 V, V_OUT= 1.1 V, I_OUT= 10 mA

70

55

70

55

70

55

dB

V_IN= V_OUT+ 1V

¹Based on an end-point calculation using 0.1 mA and 200 mA loads. See Figure 6 for typical load regulation performance for loads less than 1 mA.

²Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output

voltages above 2.2 V.

³Start-up time is defined as the time between the rising edge of EN and V_OUTbeing at 90% of its nominal value.

⁴Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V (that is, 2.7 V).

INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Minimum Input and Output

Capacitance¹

C_MIN

T_A= −40°C to +125°C

0.7

µF

Capacitor ESR

R_ESR

T_A= −40°C to +125°C

0.001

0.2

Ω

¹The minimum input and output capacitance should be greater than 0.7 μF over the full range of operating conditions. The full range of operating conditions in the

application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;

Y5V and Z5U capacitors are not recommended for use with any LDO.

Rev. 0 | Page 4 of 24

ADP151

ABSOLUTE MAXIMUM RATINGS

Table 2.

specified values of θ_JAare based on a 4-layer, 4 in. × 3 in. circuit

board. See JESD51-7 and JESD51-9 for detailed information

on the board construction. For additional information, see the

AN-617 Application Note, MicroCSP™ Wafer Level Chip Scale

Package, available at www.analog.com.

Parameter

Rating

VIN to GND

VOUT to GND

−0.3 V to +6.5 V

−0.3 V to VIN

EN to GND

−0.3 V to +6.5V

−65°C to +150°C

−40°C to +125°C

JEDEC J-STD-020

Ψ_JBis the junction-to-board thermal characterization parameter

with units of °C/W. Ψ_JBof the package is based on modeling and

calculation using a 4-layer board. The JESD51-12, Guidelines for

Reporting and Using Electronic Package Thermal Information,

states that thermal characterization parameters are not the same

as thermal resistances. Ψ_JBmeasures the component power

flowing through multiple thermal paths rather than a single

path as in thermal resistance, θ_JB. Therefore, Ψ_JBthermal paths

include convection from the top of the package as well as

radiation from the package, factors that make Ψ_JBmore useful

in real-world applications. Maximum junction temperature (T_J)

is calculated from the board temperature (T_B) and power

dissipation (P_D) using the formula

Storage Temperature Range

Operating Junction Temperature Range

Operating Ambient Temperature Range

Soldering Conditions

Stresses above those listed under absolute maximum ratings

may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or

any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

THERMAL DATA

T_J= T_B+ (P_D× Ψ_JB)

Absolute maximum ratings apply individually only, not in

combination. The ADP151 can be damaged when the junction

temperature limits are exceeded. Monitoring ambient temperature

does not guarantee that T_Jis within the specified temperature

limits. In applications with high power dissipation and poor

thermal resistance, the maximum ambient temperature may

have to be derated.

See JESD51-8 and JESD51-12 for more detailed information

about Ψ_JB.

THERMAL RESISTANCE

θ_JAand Ψ_JBare specified for the worst-case conditions, that is, a

device soldered in a circuit board for surface-mount packages.

In applications with moderate power dissipation and low PCB

thermal resistance, the maximum ambient temperature can

exceed the maximum limit as long as the junction temperature

is within specification limits. The junction temperature (T_J) of

the device is dependent on the ambient temperature (T_A), the

power dissipation of the device (P_D), and the junction-to-ambient

thermal resistance of the package (θ_JA).

Table 3. Thermal Resistance

Package Type

θ_JA

Ψ_JB

43

Unit

°C/W

5-Lead TSOT

170

260

4-Ball, 0.4 mm Pitch WLCSP

58

ESD CAUTION

Maximum junction temperature (T_J) is calculated from the

ambient temperature (T_A) and power dissipation (P_D) using the

formula

T_J= T_A+ (P_D× θ_JA)

Junction-to-ambient thermal resistance (θ_JA) of the package is

based on modeling and calculation using a 4-layer board. The

junction-to-ambient thermal resistance is highly dependent on

the application and board layout. In applications where high

maximum power dissipation exists, close attention to thermal

board design is required. The value of θ may vary, depending on

JA

PCB material, layout, and environmental conditions. The

Rev. 0 | Page 5 of 24

ADP151

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

2

1

2

3

5

VIN

GND

EN

VOUT

A

B

VIN

VOUT

ADP151

TOP VIEW

(Not to Scale)

TOP VIEW

(Not to Scale)

4

NC

EN

GND

NC = NO CONNECT

Figure 3. 5-Lead TSOT Pin Configuration

Figure 4. 4-Ball WLCSP Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

TSOT WLCSP Mnemonic Description

1

2

3

A1

B2

B1

VIN

GND

EN

Regulator Input Supply. Bypass VIN to GND with a 1 µF or greater capacitor.

Ground.

Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic

startup, connect EN to VIN.

4

5

N/A

A2

NC

VOUT

No Connect. Not connected internally.

Regulated Output Voltage. Bypass VOUT to GND with a 1 µF or greater capacitor.

Rev. 0 | Page 6 of 24

ADP151

TYPICAL PERFORMANCE CHARACTERISTICS

V_IN= 5 V, V_OUT= 3.3 V, I_OUT= 1 mA, C_IN= C_OUT= 1 µF, T_A= 25°C, unless otherwise noted.

3.35

3.33

3.31

3.29

3.27

3.25

300

200

100

LOAD = 10µA

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 10µA

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

0

–40

–5

25

85

125

–40

–5

25

85

125

JUNCTION TEMPERATURE (°C)

Figure 5. Output Voltage vs. Junction Temperature

Figure 8. Ground Current vs. Junction Temperature

3.35

3.33

3.31

3.29

3.27

3.25

1k

100

10

0.01

0.1

1

10

(mA)

100

1000

0.1

1

10

(mA)

100

1000

I

LOAD

Figure 6. Output Voltage vs. Load Current

Figure 9. Ground Current vs. Load Current

3.35

3.33

3.31

3.29

3.27

3.25

1k

100

10

LOAD = 10µA

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 10µA

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

3.6

3.8

4.0

4.2

4.4

4.6

(V)

4.8

5.0

5.2

5.4

3.6

3.8

4.0

4.2

4.4

4.6

(V)

4.8

5.0

5.2

5.4

V

IN

Figure 7. Output Voltage vs. Input Voltage

Figure 10. Ground Current vs. Input Voltage

Rev. 0 | Page 7 of 24

ADP151

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

800

700

600

500

400

300

200

100

0

I

= 1mA

= 5mA

= 10mA

= 50mA

= 100mA

= 200mA

V

= 3.6V

= 3.8V

= 4.2V

= 4.4V

= 4.8V

= 5.5V

OUT

IN

0

–50

–25

0

25

50

75

100

125

3.10 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 3.55

TEMPERATURE (°C)

V

(V)

IN

Figure 11. Shutdown Current vs. Temperature at Various Input Voltages

Figure 14. Ground Current vs. Input Voltage (in Dropout)

120

0

200mA

100mA

10mA

1mA

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

100

80

60

40

20

0

100µA

1

10

100

1000

10

100

1k

10k

100k

1M

10M

I

(mA)

LOAD

FREQUENCY (Hz)

Figure 12. Dropout Voltage vs. Load Current

Figure 15. Power Supply Rejection Ratio vs. Frequency, V_OUT= 1.2 V

3.40

3.35

3.30

3.25

3.20

3.15

3.10

3.05

3.00

0

200mA

100mA

10mA

1mA

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

100µA

I

= 1mA

= 5mA

= 10mA

= 50mA

= 100mA

= 200mA

OUT

3.10 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 3.55

10

100

1k

10k

100k

1M

10M

V

(V)

FREQUENCY (Hz)

IN

Figure 16. Power Supply Rejection Ratio vs. Frequency, V_OUT= 2.8 V

Figure 13. Output Voltage vs. Input Voltage (in Dropout)

Rev. 0 | Page 8 of 24

ADP151

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

14

13

12

11

10

9

200mA

100mA

10mA

1mA

3.3V

2.8V

1.2V

1.1V

100µA

8

7

6

5

4

3

2

1

0

10

100

1k

10k

100k

1M

10M

0.001

0.01

0.1

1

10

100

1k

FREQUENCY (Hz)

LOAD CURRENT (mA)

Figure 17. Power Supply Rejection Ratio vs. Frequency, V_OUT= 3.3 V

Figure 20. Output Noise vs. Load Current and Output Voltage,

V_IN= 5 V, C_OUT= 1 μF

0

1

V

= 3.3V, I

= 2.8V, I

= 1.1V, I

= 200mA

= 10mA

= 200mA

= 10mA

= 200mA

= 10mA

3.3V

OUT

2.8V

1.2V

1.1V

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0.1

0.01

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

FREQUENCY (Hz)

Figure 21. Output Noise Spectrum, V_IN= 5 V, I_LOAD= 10 mA, C_OUT= 1 μF

Figure 18. Power Supply Rejection Ratio vs. Frequency at

Various Output Voltages and Load Currents

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

T

I

= 200mA, V = 3.3V

IN

= 10mA, V =3.3V

IN

= 200mA, V = 3.8V

IN

= 10mA, V = 3.8V

IN

OUT

LOAD CURRENT

1

2

V

OUT

CH1 200mA CH2 50mV

M20µs

A

CH1

64.0mA

10

100

1k

10k

100k

1M

10M

T

10.00%

FREQUENCY (Hz)

Figure 19. Power Supply Rejection Ratio vs. Frequency at Various Voltages

and Load Currents, V_OUT= 2.8 V

Figure 22. Load Transient Response, C_IN, C_OUT= 1 μF, I_LOAD= 1 mA to 200 mA

Rev. 0 | Page 9 of 24

ADP151

T

INPUT VOLTAGE

2

1

2

1

V

OUT

CH1 1V

CH2 2mV

M10µs

A

CH1

4.56V

CH1 1V

CH2 2mV

M10µs

A

CH1

4.56V

T

10.80%

T 10.80%

Figure 23. Line Transient Response, C_IN, C_OUT= 1 μF, I_LOAD= 200 mA

Figure 24. Line Transient Response, C_IN, C_OUT=1 μF, I_LOAD= 1 mA

Rev. 0 | Page 10 of 24

ADP151

THEORY OF OPERATION

The ADP151 is an ultralow noise, low quiescent current, low

dropout linear regulator that operates from 2.2 V to 5.5 V and

can provide up to 200 mA of output current. Drawing a low

265 μA of quiescent current (typical) at full load makes the

ADP151 ideal for battery-operated portable equipment. Shut-

down current consumption is typically 200 nA.

Internally, the ADP151 consists of a reference, an error

amplifier, a feedback voltage divider, and a PMOS pass

transistor. Output current is delivered via the PMOS pass

device, which is controlled by the error amplifier. The error

amplifier compares the reference voltage with the feedback

voltage from the output and amplifies the difference. If the

feedback voltage is lower than the reference voltage, the gate of

the PMOS device is pulled lower, allowing more current to pass

and increasing the output voltage. If the feedback voltage is

higher than the reference voltage, the gate of the PMOS device

is pulled higher, allowing less current to pass and decreasing the

output voltage.

Using new innovative design techniques, the ADP151 provides

superior noise performance for noise-sensitive analog and RF

applications without the need for a noise bypass capacitor. The

ADP151 is also optimized for use with small 1 µF ceramic

capacitors.

VIN

GND

EN

VOUT

An internal pull-down resistor on the EN input holds the input

low when the pin is left open.

R1

The ADP151 is available in 16 output voltage options, ranging

from 1.1 V to 3.3 V. The ADP151 uses the EN pin to enable and

disable the VOUT pin under normal operating conditions.

When EN is high, VOUT turns on; when EN is low, VOUT

turns off. For automatic startup, EN can be tied to VIN.

SHORT CIRCUIT,

UVLO, AND

THERMAL

PROTECT

SHUTDOWN

R2

REFERENCE

R

EN

Figure 25. Internal Block Diagram

Rev. 0 | Page 11 of 24

ADP151

APPLICATIONS INFORMATION

Figure 27 depicts the capacitance vs. voltage bias characteristic

of an 0402, 1 µF, 10 V, X5R capacitor. The voltage stability of a

capacitor is strongly influenced by the capacitor size and voltage

rating. In general, a capacitor in a larger package or higher voltage

rating exhibits better stability. The temperature variation of the

X5R dielectric is ~ 15% over the −40°C to +85°C temperature

range and is not a function of package or voltage rating.

1.2

CAPACITOR SELECTION

Output Capacitor

The ADP151 is designed for operation with small, space-saving

ceramic capacitors but functions with most commonly used

capacitors as long as care is taken with regard to the effective series

resistance (ESR) value. The ESR of the output capacitor affects the

stability of the LDO control loop. A minimum of 1 µF capacitance

with an ESR of 1 Ω or less is recommended to ensure the stability

of the ADP151. Transient response to changes in load current is

also affected by output capacitance. Using a larger value of output

capacitance improves the transient response of the ADP151 to

large changes in load current. Figure 26 shows the transient

responses for an output capacitance value of 1 µF.

1.0

0.8

0.6

0.4

0.2

0

T

LOAD CURRENT

1

0

2

4

6

8

10

VOLTAGE

2

Figure 27. Capacitance vs. Voltage Characteristic

V

OUT

Use Equation 1 to determine the worst-case capacitance accounting

for capacitor variation over temperature, component tolerance,

and voltage.

CH1 200mA CH2 50mV

M20µs

A

CH1

64mA

C_EFF= C_BIAS× (1 − TEMPCO) × (1 − TOL)

(1)

T

10.00%

where:

Figure 26. Output Transient Response, C_OUT= 1 µF

C

_BIASis the effective capacitance at the operating voltage.

Input Bypass Capacitor

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

Connecting a 1 µF capacitor from VIN to GND reduces the

circuit sensitivity to printed circuit board (PCB) layout,

especially when long input traces or high source impedance

are encountered. If greater than 1 µF of output capacitance is

required, the input capacitor should be increased to match it.

In this example, the worst-case temperature coefficient (TEMPCO)

over −40°C to +85°C is assumed to be 15% for an X5R dielectric.

The tolerance of the capacitor (TOL) is assumed to be 10%, and

C

_BIASis 0.94 μF at 1.8 V, as shown in Figure 27.

Substituting these values in Equation 1 yields

_EFF= 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF

Input and Output Capacitor Properties

C

Any good quality ceramic capacitors can be used with the

ADP151, as long as they meet the minimum capacitance and

maximum ESR requirements. Ceramic capacitors are manufac-

tured with a variety of dielectrics, each with different behavior

over temperature and applied voltage. Capacitors must have a

dielectric adequate to ensure the minimum capacitance over the

necessary temperature range and dc bias conditions. X5R or

X7R dielectrics with a voltage rating of 6.3 V or 10 V are

recommended. Y5V and Z5U dielectrics are not recommended,

due to their poor temperature and dc bias characteristics.

Therefore, the capacitor chosen in this example meets the

minimum capacitance requirement of the LDO over temper-

ature and tolerance at the chosen output voltage.

To guarantee the performance of the ADP151, it is imperative

that the effects of dc bias, temperature, and tolerances on the

behavior of the capacitors be evaluated for each application.

Rev. 0 | Page 12 of 24

ADP151

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

ENABLE FEATURE

The ADP151 uses the EN pin to enable and disable the VOUT

pin under normal operating conditions. As shown in Figure 28,

when a rising voltage on EN crosses the active threshold, VOUT

turns on. When a falling voltage on EN crosses the inactive

threshold, VOUT turns off.

3.0

2.5

2.0

1.5

1.0

0.5

0

ENABLE

3.3V

2.8V

1.1V

0

50

100

150

200

250

300

350

400

450

TIME (µs)

Figure 30. Typical Start-Up Behavior

ADJUSTABLE OUTPUT VOLTAGE OPERATION

The unique architecture of the ADP151 makes an adjustable

version difficult to implement in silicon. However, it is possible

to create an adjustable regulator at the expense of increasing the

quiescent current of the regulator circuit.

0

0.5

1.0

1.5

2.0

2.5

ENABLE VOLTAGE

Figure 28. ADP151 Typical EN Pin Operation

The ADP151, and similar LDOs, are designed to regulate the

output voltage, V_OUT, appearing at the VOUT pin with respect

to the GND pin. If the GND pin is at a potential other than 0 V

(for example, at V_OFFSET), the ADP151 output voltage is V_OUT

_OFFSET. By taking advantage of this behavior, it is possible to

As shown in Figure 28, the EN pin has hysteresis built in. This

prevents on/off oscillations that can occur due to noise on the

EN pin as it passes through the threshold points.

+

V

The EN pin active/inactive thresholds are derived from the VIN

voltage. Therefore, these thresholds vary with changing input

voltage. Figure 29 shows typical EN active/inactive thresholds

when the input voltage varies from 2.2 V to 5.5 V.

1200

create an adjustable ADP151 circuit that retains most of the

desirable characteristics of the ADP151.

V

IN

OUT

1

2

3

VIN

GND

EN

VOUT

U1

5

C1

C2

4

1000

NC

V

OFFSET

R2

V

RISE

EN

R1

800

600

400

200

0

C3

FALL

V

= V × (1 + R1/R2)

LDO

EN

OUT

Figure 31. Adjustable LDO Using the ADP151

The circuit shown in Figure 31 is an example of an adjustable

LDO using the ADP151. A stable V_OFFSETvoltage is created by

passing a known current through R2. The current through R2 is

determined by the voltage across R1. Because the voltage across

R1 is set by the voltage between VOUT and GND, the current

passing through R2 is fixed, and V_OFFSETis stable.

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

INPUT VOLTAGE

To minimize the effect variation of the ADP151 ground current,

Figure 29. Typical EN Pin Thresholds vs. Input Voltage

I

_GND, with load, it is best to keep R1 as small as possible. It is also

The ADP151 uses an internal soft start to limit the inrush current

when the output is enabled. The start-up time for the 3.3 V

option is approximately 160 μs from the time the EN active

threshold is crossed to when the output reaches 90% of its final

value. As shown in Figure 30, the start-up time is dependent on

the output voltage setting.

best to size the current passing through R2 to at least 20×

greater than the maximum expected ground current.

To create a 4 V LDO circuit, start with the 3.3 V version of the

ADP151 to minimize the value of R2. Because V_OUTis 4 V,

V

R1 is, therefore, 3.3 V/7 mA or 471 Ω. A 470 Ω standard value

introduces less than 1% error. Capacitor C3 is necessary to stabilize

the LDO; a value of 1 μF is adequate.

_OFFSETmust be 0.7 V, and the current through R2 must be 7 mA.

Rev. 0 | Page 13 of 24

ADP151

11

10

9

Figure 32 through Figure 36 show the typical performance of the

4 V LDO circuit.

The noise performance of the 4 V LDO circuit is only about 1 μV

worse than the same LDO used at 3.3 V because the output noise of

the circuit is almost solely determined by the LDO and not the

external components. The small difference may be attributed to the

internally generated noise in the LDO ground current working

with R2. By keeping R2 small, this noise contribution can be

minimized.

The PSRR of the 4 V circuit is as much as 10 dB poorer than the

3.3. V LDO with 500 mV of headroom because the ground current

of the LDO varies somewhat with input voltage. This, in turn,

modulates V_OFFSETand reduces the PSRR of the regulator. By

increasing the headroom to 1 V, the PSRR performance is nearly

restored to the performance of the fixed output LDO.

4.04

8

1

10

100

1k

LOAD CURRENT (mA)

Figure 34. 4 V Load Circuit, Typical RMS Output Noise, 10 Hz to 100 kHz

T

4.03

4.02

4.01

4.00

1

2

3.99

LOAD = 10mA

LOAD = 20mA

LOAD = 50mA

LOAD = 100mA

LOAD = 150mA

LOAD = 200mA

3.98

3.97

3.96

CH1 100mA CH2 50mV

M40µs

10.20%

A

CH1

52.0mA

T

–40

–5

25

85

125

Figure 35. 4 V Load Circuit, Typical PSRR vs. Load Current, 1 V Headroom

JUNCTION TEMPERATURE (°C)

Figure 32. 4 V LDO Circuit, Typical Load Regulation over Temperature

T

4.040

LOAD = 10mA

LOAD = 20mA

4.035

1

LOAD = 50mA

LOAD = 100mA

4.030

LOAD = 150mA

LOAD = 200mA

4.025

4.020

4.015

4.010

4.005

4.000

2

CH1 100mA CH2 50mV

M40µs

10.20%

A

CH1

52.0mA

T

4.4

4.6

4.8

5.0

(V)

5.2

5.4

Figure 36. 4 V Load Circuit, Typical PSRR vs. Load Current, 500 mV Headroom

V

IN

Figure 33. 4 V LDO Circuit, Typical Line Regulation over Load Current

Rev. 0 | Page 14 of 24

ADP151

changes. These parameters include ambient temperature, power

dissipation in the power device, and thermal resistances

CURRENT LIMIT AND THERMAL OVERLOAD

PROTECTION

between the junction and ambient air (θ ). The θ_JAnumber is

JA

The ADP151 is protected against damage due to excessive

power dissipation by current and thermal overload protection

circuits. The ADP151 is designed to current limit when the

output load reaches 300 mA (typical). When the output load

exceeds 300 mA, the output voltage is reduced to maintain a

constant current limit.

dependent on the package assembly compounds that are used

and the amount of copper used to solder the package GND pins

to the PCB.

Table 5 shows typical θ values of the 5-lead TSOT package for

JA

various PCB copper sizes. Table 6 shows the typical Ψ_JBvalues of

the 5-lead TSOT and 4-b a l l W L C S P.

Thermal overload protection is included, which limits the

junction temperature to a maximum of 150°C (typical). Under

extreme conditions (that is, high ambient temperature and

power dissipation) when the junction temperature starts to rise

above 150°C, the output is turned off, reducing the output

current to 0. When the junction temperature drops below

135°C, the output is turned on again, and output current is

restored to its nominal value.

Table 5. Typical θ_JAValues

θ

_JA(°C/W)

WLCSP

Copper Size (mm²)

TSOT

170

152

146

134

131

0¹

260

159

157

153

151

50

100

300

500

Consider the case where a hard short from VOUT to ground

occurs. At first, the ADP151 current limits, so that only 300 mA

is conducted into the short. If self-heating of the junction is

great enough to cause its temperature to rise above 150°C,

thermal shutdown activates, turning off the output and

reducing the output current to 0. As the junction temperature

cools and drops below 135°C, the output turns on and

conducts 300 mA into the short, again causing the junction

temperature to rise above 150°C. This thermal oscillation

between 135°C and 150°C causes a current oscillation between

300 mA and 0 mA that continues as long as the short remains

at the output.

¹Device soldered to minimum size pin traces.

Table 6. Typical Ψ_JBValues

Model

Ψ_JB(°C/W)

TSOT

WLCSP

43

58

The junction temperature of the ADP151 can be calculated

from the following equation:

T_J= T_A+ (P_D× θ_JA)

(2)

(3)

where:

T_Ais the ambient temperature.

P_Dis the power dissipation in the die, given by

Current and thermal limit protections are intended to protect

the device against accidental overload conditions. For reliable

operation, device power dissipation must be externally limited

so that junction temperatures do not exceed 125°C.

P_D= [(V_IN− V_OUT) × I_LOAD] + (V_IN× I_GND

)

where:

I

_LOADis the load current.

THERMAL CONSIDERATIONS

I_GNDis the ground current.

In most applications, the ADP151 does not dissipate much heat

due to its high efficiency. However, in applications with high

ambient temperature, high supply voltage to output voltage

differential, the heat dissipated in the package is large enough

that it can cause the junction temperature of the die to exceed

the maximum junction temperature of 125°C.

V_INand V_OUTare input and output voltages, respectively.

Power dissipation due to ground current is quite small and can

be ignored. Therefore, the junction temperature equation

simplifies to the following:

T_J= T_A+ {[(V_IN− V_OUT) × I_LOAD] × θ_JA}

(4)

As shown in Equation 4, for a given ambient temperature, input-

to-output voltage differential, and continuous load current,

there exists a minimum copper size requirement for the PCB

to ensure that the junction temperature does not rise above 125°C.

Figure 37 to Figure 50 show junction temperature calculations

for different ambient temperatures, load currents, V_IN-to-V_OUT

differentials, and areas of PCB copper.

When the junction temperature exceeds 150°C, the converter

enters thermal shutdown. It recovers only after the junction

temperature has decreased below 135°C to prevent any permanent

damage. Therefore, thermal analysis for the chosen application

is very important to guarantee reliable performance over all

conditions. The junction temperature of the die is the sum of

the ambient temperature of the environment and the tempera-

ture rise of the package due to the power dissipation, as shown

in Equation 2.

To guarantee reliable operation, the junction temperature of

the ADP151 must not exceed 125°C. To ensure that the junction

temperature stays below this maximum value, the user must be

aware of the parameters that contribute to junction temperature

Rev. 0 | Page 15 of 24

ADP151

140

120

100

80

140

120

100

80

MAXIMUM JUNCTION TEMPERATURE

60

40

20

I

= 1mA

= 10mA

= 50mA

I

= 100mA

= 150mA

= 200mA

I

= 1mA

= 10mA

= 50mA

I

= 100mA

= 150mA

= 200mA

LOAD

0

0.3

0

0.3

0.8

1.3

1.8

2.3

– V

2.8

(V)

3.3

3.8

4.3

4.8

0.8

1.3

1.8

2.3

– V

2.8

(V)

3.3

3.8

4.3

4.8

V

IN

OUT

IN

OUT

Figure 37. WLCSP 500 mm²of PCB Copper, T_A= 25°C

Figure 40. WLCSP 500 mm²of PCB Copper, T_A= 50°C

140

120

100

80

140

120

100

80

MAXIMUM JUNCTION TEMPERATURE

60

40

20

I

= 1mA

= 10mA

= 50mA

I

= 100mA

= 150mA

= 200mA

I

= 1mA

= 10mA

= 50mA

I

= 100mA

= 150mA

= 200mA

LOAD

0

0.3

0.8

1.3

1.8

2.3

– V

2.8

(V)

3.3

3.8

4.3

0.8

1.3

1.8

2.3

– V

2.8

(V)

3.3

3.8

4.3

V

IN

OUT

IN

OUT

Figure 38. WLCSP 100 mm²of PCB Copper, T_A= 25°C

Figure 41. WLCSP 100 mm²of PCB Copper, T_A= 50°C

140

120

100

80

140

120

100

80

MAXIMUM JUNCTION TEMPERATURE

60

40

20

I

= 1mA

= 10mA

= 50mA

I

= 100mA

= 150mA

= 200mA

I

= 1mA

= 10mA

= 50mA

I

= 100mA

= 150mA

= 200mA

LOAD

0

0.3

0.8

1.3

1.8

2.3

– V

2.8

(V)

3.3

3.8

4.3

0.8

1.3

1.8

2.3

– V

2.8

(V)

3.3

3.8

4.3

V

IN

OUT

IN

OUT

Figure 39. WLCSP 50 mm²of PCB Copper, T_A= 25°C

Figure 42. WLCSP 50 mm²of PCB Copper, T_A= 50°C

Rev. 0 | Page 16 of 24

ADP151

140

120

100

80

140

120

100

80

MAXIMUM JUNCTION TEMPERATURE

60

40

20

I

= 1mA

= 10mA

= 50mA

I

= 100mA

= 150mA

= 200mA

I

= 1mA

= 10mA

= 50mA

I

= 100mA

= 150mA

= 200mA

LOAD

0

0.3

0

0.3

0.8

1.3

1.8

2.3

– V

2.8

(V)

3.3

3.8

4.3

4.8

0.8

1.3

1.8

2.3

– V

2.8

(V)

3.3

3.8

4.3

4.8

V

IN

OUT

IN

OUT

Figure 43. TSOT 500 mm²of PCB Copper, T_A= 25°C

Figure 46. TSOT 500 mm²of PCB Copper, T_A= 50°C

140

120

100

80

140

120

100

80

MAXIMUM JUNCTION TEMPERATURE

60

40

20

I

= 1mA

= 10mA

= 50mA

I

= 100mA

= 150mA

= 200mA

I

= 1mA

= 10mA

= 50mA

I

= 100mA

= 150mA

= 200mA

LOAD

0

0.3

0

0.3

0.8

1.3

1.8

2.3

– V

2.8

(V)

3.3

3.8

4.3

0.8

1.3

1.8

2.3

– V

2.8

(V)

3.3

3.8

4.3

V

IN

OUT

IN

OUT

Figure 44. TSOT 100 mm²of PCB Copper, T_A= 25°C

Figure 47. TSOT 100 mm²of PCB Copper, T_A= 50°C

140

120

100

80

140

120

100

80

MAXIMUM JUNCTION TEMPERATURE

60

40

20

I

= 1mA

= 10mA

= 50mA

I

= 100mA

= 150mA

= 200mA

I

= 1mA

= 10mA

= 50mA

I

= 100mA

= 150mA

= 200mA

LOAD

0

0.3

0

0.3

0.8

1.3

1.8

2.3

– V

2.8

(V)

3.3

3.8

4.3

0.8

1.3

1.8

2.3

– V

2.8

(V)

3.3

3.8

4.3

V

IN

OUT

IN

OUT

Figure 45. TSOT 50 mm²of PCB Copper, T_A= 25°C

Figure 48. TSOT 50 mm²of PCB Copper, T_A= 50°C

Rev. 0 | Page 17 of 24

ADP151

140

120

100

80

In the case where the board temperature is known, use the

thermal characterization parameter, Ψ_JB, to estimate the

junction temperature rise (see Figure 49 and Figure 50).

Maximum junction temperature (T_J) is calculated from the

board temperature (T_B) and power dissipation (P_D) using the

following formula:

MAXIMUM JUNCTION TEMPERATURE

T_J= T_B+ (P_D× Ψ_JB)

(5)

60

The typical value of Ψ is 58°C/W for the 4-ball WLCSP package

JB

40

and 43°C/W for the 5-lead TSOT package.

140

20

I

= 1mA

= 10mA

= 50mA

I

= 100mA

= 150mA

= 200mA

LOAD

MAXIMUM JUNCTION TEMPERATURE

120

100

80

0

0.3

0.8

1.3

1.8

2.3

– V

2.8

(V)

3.3

3.8

4.3

4.8

V

IN

OUT

Figure 50. TSOT, T_A= 85°C

60

40

20

I

= 1mA

= 10mA

= 50mA

I

= 100mA

= 150mA

= 200mA

LOAD

0

0.3

0.8

1.3

1.8

2.3

– V

2.8

(V)

3.3

3.8

4.3

4.8

V

IN

OUT

Figure 49. WLCSP, T_A= 85°C

Rev. 0 | Page 18 of 24

ADP151

PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS

Heat dissipation from the package can be improved by increasing

the amount of copper attached to the pins of the ADP151.

However, as listed in Table 5, a point of diminishing returns is

eventually reached, beyond which an increase in the copper size

does not yield significant heat dissipation benefits.

Place the input capacitor as close as possible to the VIN and

GND pins. Place the output capacitor as close as possible to the

VOUT and GND pins. Use of 0402 or 0603 size capacitors and

resistors achieves the smallest possible footprint solution on

boards where area is limited.

Figure 52. Example WLCSP PCB Layout

Figure 51. Example TSOT PCB Layout

Rev. 0 | Page 19 of 24

ADP151

OUTLINE DIMENSIONS

2.90 BSC

5

1

4

3

2.80 BSC

1.60 BSC

2

0.95 BSC

1.90

BSC

*

0.90 MAX

0.70 MIN

*

1.00 MAX

0.20

0.08

8°

4°

0°

0.10 MAX

0.50

0.30

0.60

0.45

0.30

SEATING

PLANE

*

COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH

THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.

Figure 53. 5-Lead Thin Small Outline Transistor Package [TSOT]

(UJ-5)

Dimensions show in millimeters

0.660

0.600

0.540

0.800

0.760 SQ

0.720

0.430

0.400

0.370

SEATING

PLANE

2

1

A

B

0.280

0.260

0.240

BALL A1

IDENTIFIER

0.40

BALL PITCH

TOP VIEW

(BALL SIDE DOWN)

BOTTOM VIEW

(BALL SIDE UP)

0.230

0.200

0.170

0.050 NOM

COPLANARITY

Figure 54. 4-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-4-3)

Dimensions show in millimeters

Rev. 0 | Page 20 of 24

ADP151

ORDERING GUIDE

Temperature

Range

Output

Package

Description

Package

Option

Model¹

Voltage (V)²

Branding

ADP151ACBZ-1.2-R7

ADP151ACBZ-1.5-R7

ADP151ACBZ-1.8-R7

ADP151ACBZ-2.5-R7

ADP151ACBZ-2.75-R7

ADP151ACBZ-2.8-R7

ADP151ACBZ-2.85-R7

ADP151ACBZ-3.0-R7

ADP151ACBZ-3.3-R7

ADP151ACBZ-2.1-R7

ADP151AUJZ-1.2-R7

ADP151AUJZ-1.5-R7

ADP151AUJZ-1.8-R7

ADP151AUJZ-2.5-R7

ADP151AUJZ-2.8-R7

ADP151AUJZ-3.0-R7

ADP151AUJZ-3.3-R7

–40°C to +125°C

1.2

1.5

1.8

2.5

2.75

2.8

2.85

3.0

3.3

2.1

1.2

1.5

1.8

2.5

2.8

3.0

3.3

4-Ball WLCSP

5-Lead TSOT

CB-4-3³

UJ-5

4R

4S

4T

4U

4V

4X

4Y

4Z

50

5E

LF6

LF7

LF8

LF9

LFG

LFH

LFJ

¹Z = RoHS Compliant Part.

²For additional voltage options, contact a local Analog Devices, Inc., sales or distribution representative.

³This package option is halide free.

Rev. 0 | Page 21 of 24

ADP151

NOTES

Rev. 0 | Page 22 of 24

ADP151

NOTES

Rev. 0 | Page 23 of 24

ADP151

NOTES

registered trademarks are the property of their respective owners.

D08627-0-3/10

Rev. 0 | Page 24 of 24


型号：	ADP151AUJZ-1.8-R7
厂家：	ADI
描述：	Ultralow Noise,200 mA, CMOS Linear Regulator 超低噪声200 mA时， CMOS线性稳压器线性稳压器IC 调节器电源电路光电二极管输出元件
文件：	总24页 (文件大小：526K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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