ADN8820-REEL7 [ADI]
EDFA and CW Laser Controller; 掺铒光纤放大器和CW激光控制器
| 型号： | ADN8820-REEL7 |
| 厂家： | 
ADI |
| 描述： | EDFA and CW Laser Controller |
| 文件： | 总9页 (文件大小：289K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EDFA and CW Laser Controller
ADN8820*
Preliminary Technical Data
Output Power (COP), or Constant EDFA Gain (CG). Multiple
pump laser applications are easily supported by the ADN8820.
Common-cathode-to-ground and common-anode-to-VDD
configurations are also supported.
FEATURES
Four Operational Modes Including:
Constant Laser Current
Constant Optical Output Power
Constant EDFA Gain
Constant Laser Power
High Power Efficiency: >90%
The ADN8820 has a high speed closed-loop control, making it
suitable for add/drop applications in telecommunication
systems. It has a low-current shutdown mode and a soft-start
feature to minimize power supply bounce on start-up.
Three Built-In Photodiode TIAs
Adjustable Laser Diode and EDFA Protection Limits
Free-run or Synchronous Switching Frequency Modes
Adjustable Phase Delay for Synchornous Clock Mode
Optional Dithering Built-In
Protection circuitry is built into the device. The protection
limits are easily adjustable and are used to set maximum output
current and voltage, optical output power, EDFA gain, and
pump or CW laser power.
Programmable Dither Frequency and Amplitude
The output stage consists of a high-efficiency PWM amplifier in
parallel with a high-speed linear amplifier. This provides the
fastest settling time response along with the lowest power and
heat dissipation. A pair of external MOSFETs on the PWM
amplifier provide output currents of up to 5A.
APPLICATIONS
EDFA Pump Laser Diode Control
CW Laser Bias Control
Raman Amplifiers
Three low-bias current TIAs are built-in. These allow
amplification for the laser back-facet photodiode and EDFA
input and output photodiodes. For CW laser applications, the
two unused TIAs can be used for etalon photodiode
GENERAL DESCRIPTION
The ADN8820 is a versatile Continuous Wave (CW) and EDFA
laser diode driver and controller. It provides a low noise and
precise current control for driving a source or pump laser diode.
amplification, allowing continuous wavelength monitoring.
The ADN8820 is available in a 7 x 7 mm lead-frame chip scale
package (LFCSP) with a package height of less than 1 mm.
It can be set to operate in one of four controller modes:
Constant Current (CC), Constant Laser Power (CLP), Constant
FUNCTIONAL BLOCK DIAGRAM
* U.S. Patent Pending
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
ADN8820 - SPECIFICATIONS1
Preliminary Technical Data
Table 1. ADN8820—Electrical Characteristics (AVDD = PVDD = 5V, AGND = PGND = 0V, TA = 25°C, using typical
circuit in Figure 1, unless otherwise noted.)2
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
TRANSIMPEDANCE AMPLIFIERS
Detection Range
0.005
0.005
5
5,000
5,000
5,000
IIP
From IPDIN Photodiode
From OPDIN Photodiode
From LPDIN Photodiode
IPDIN, OPDIN, LPDIN Amplifier
Inputs
µA
µA
µA
pA
pA
pA
V
V
V
V
IOP
ILP
Input Bias Current
IBIPDIN
IBOPDIN
IBLPDIN
VBLP, VB
VIPO
100
100
100
Input Voltage Range
Monitor Output Range
0
0
0
0
VDD
VDD
VDD
VDD
IPO, LPO, OPO Outputs
VLPO
VOPO
Input Offset Voltage
VOSIP
IPDIN, OPDIN, LPDIN Amplifiers
10
10
2
10
10
10
10
10
1
µV
µV
mV
mA
mA
mA
MHz
MHz
MHz
VOSOP
VOSLP
IOUTIPO
IOUTLPO
IOUTOPO
GBWIP
GBWOP
GBWLP
Maximum Output Current
Gain-Bandwidth Product
IPO, LPO, OPO Outputs
IPDIN, OPDIN, LPDIN Amplifiers
LIMIT CONTROLS
Input Voltage Range
VINLIM
IPMIN, OPLIM, LPLIM, ILIM, and
VLIM
0
2.6
V
Limiter Accuracy
Open Circuit Voltage
VOSLIM
VLIMNC
OPLIM, LPLIM, ILIM, IPMIN
Voltage for OPLIM, LPLIM, and ILIM 2.5
with no connection
10
2.7
mV
V
2.6
Pull-up Current
IBLIM
Flowing out of OPLIM, LPLIM, and
ILIM with LIM Voltage <2.0V
VIPO = 0V
Flowing into VLIM pin
|VLINOUT – VLIM|
500
200
nA
IPMIN Disable Threshold
VLIM Input Bias Current
VLIM Voltage Control Accuracy
ERROR AMPLIFIER
VIPMINLO
IVLIM
mV
µA
mV
1
50
Input Offset Voltage
VOSEA
10
25
µV
V
V
mA
MHz
Input Common-Mode Voltage Range VCMEA
0
0
VDD
VDD
Output Voltage Swing
Maximum Output Current
Gain-Bandwidth
VOUTEA
IMAXEA
GBWEA
10
10
SET INPUT
Input Voltage Range
Input Bias Current
VSET
IBSET
0
0
VDD
VDD
V
1
µA
MULTIPLEXERS
Ouput Impedance
Output Voltage Range
100
Ω
V
1 Specifications subject to change without notice
2 Capital letters denote pin names.
Rev. PrB | Page 2 of 9
ADN8820 - SPECIFICATIONS1
Preliminary Technical Data
Table 1. ADN8820—Electrical Characteristics (AVDD = PVDD = 5V, AGND = PGND = 0V, TA = 25°C, using typical
circuit in Figure 1, unless otherwise noted.)2
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
LINEAR OUTPUT
Short-Circuit Output Current
Output Voltage Compliance
IOUTLIN
300
4.5
mA
V
V
dB
MHz
VLINMAX
VLINMIN
PSRRLIN
GBWLIN
IOUTLIN = 300mA (sourcing)
IOUTLIN = -160mA (sinking)
0.5
Power Supply Rejection Ratio
Gain-Bandwidth Product
PWM OUTPUT
68
10
Offset Voltage
Non-Overlap Delay
Output Transistion Time
Output Driver Resistance
VOSPWM
VOSPWM = LINOUT - FB
10
mV
ns
tR, tF
40
6
FET CISS ≤ 3nF
RNGATE
RPGATE
Ω
6
Ω
Output Current Ripple
Soft-Start Time
IOUT = 300mA, VOUT = 2V
CSS = 0.1 µF
1
15
%
ms
Standby Mode Threshold
OSCILLATOR
Free-Run Oscillation Frequency
Synchornization Capture Range
Phase Adjustment
VSSSB
fCLK
PWM and LINOUT disabled
0.4
V
CMPOSC = VDD; SYNCIN = 0V
SYNCIN driven with external clock
100
100
45
1,000
1,000
315
kHz
kHz
degrees
φCLK
CURRENT SENSE AMPLIFIER
Input Common-Mode Voltage Range VCMCS
0
VDD
V
Input Resistance
Output Offset Voltage
Gain
Output Voltage Range
DITHER GENERATOR
Frequency Range
RINCS
VOSLIO
AVCS
VLIO
10.5
1
20
kΩ
mV
V/V
V
VCSP = VCSN = 2.5V
VLIO / (VCSP – VCSN
)
0
VDD
2
fDITHER
0.2
MHz
xx kΩ ≤ RT ≤ xx kΩ
Frequency Multiplier Programming
Voltage
See Table II
Dither Current Control Votlage
Programming Current Range
Maximum DO Output Current
DO Output Voltage
VDCTL
IDCTL
IMAXDO
VDO
VLIO = 2.5 V
VLIO = 2.5 V
1.2
0
1.25
1.3
100
21
V
µA
mA
V
19
20
1.5
POWER SUPPLY
Power Supply Range
Supply Current
VDD
ISY
3.0
5.5
30
V
mA
25
SD
DSEL/
≥ 0.8V; IOUT = 0A
-40°C ≤ TA ≤ +85°C
SD
Shutdown Current
ISD
10
DSEL/
≤ 0.2V
SS/ ≤ 0.2V
µA
mA
V
Standby Current
ISB
2.5
2.4
SB
Undervoltage Lockout
REFERNCE OUTPUT
Reference Voltage
VUVLO
2.5
2.6
VREF
2.4
2.5
68
V
V
I
REF ≤ 2 mA
Power Supply Rejection Ratio
PSRRREF
With respct to AVDD
1 Specifications subject to change without notice
2 Capital letters denote pin names.
Rev. PrB | Page 3 of 9
ADN8820 - SPECIFICATIONS1
Preliminary Technical Data
Table 1. ADN8820—Electrical Characteristics (AVDD = PVDD = 5V, AGND = PGND = 0V, TA = 25°C, using typical
circuit in Figure 1, unless otherwise noted.)2
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
DUAL OUTPUT
Output Voltage Range
Voltage Gain
VDUAL
0.4
VDD-0.4
V
I
DUAL ≤ 500 µA
AVDUAL
AVDUAL = DUAL / LIO; VILIM = 2.25V
20
V/V
with 1.9 V ≤ VLIO ≤ 2.1V
CONTROL LOOP STATUS OUTPUT
CLGD High
VCLGDHI
VCLGDLO
4.8
V
V
0.05 x VDD ≤ VEAOUT ≤ 0.95 x VDD
Otherwise
CLGD Low
0.2
0.2
0.2
1
LOGIC CONTROL
Logic Low Input Threshold
Logic High Input Threshold
Logic Low Output Level
Logic High Output Level
Input Current
VIL
MODE0, MODE1, SYNCIN
MODE0, MODE1, SYNCIN
V
V
V
V
VIH
VOL
VOH
VDD-0.2
VDD-0.2
µA
1 Specifications subject to change without notice
2 Capital letters denote pin names.
Figure 1. Typical Application Circuit
Rev. PrB | Page 4 of 9
ADN8820
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 3. Thermal Resistance
Table 2. Absolute Maximum Ratings (at 25°C, unless
otherwise noted)
1
Package Type
Unit
θJA
θJC
LFSCP-48 (CP-48)
32
12
°C/W
Parameter
Rating
Supply Voltage
6 V
Output Short-Circuit Duration to GND
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range: CP Packages
Indefinite
1 θJA is specified for the worst-case conditions, i.e., θJA is specified for device
soldered in circuit board for surface mount packages.
–65°C to +150°C
–40°C to +85°C
–65°C to +150°C
Lead Temperature Range (Soldering, 60 Sec) 300°C
Figure 2. System Block Diagram
PIN CONFIGURATION
Rev. PrB | Page 5 of 9
ADN8820
Preliminary Technical Data
PIN FUNCTIONS
Name
Pin
Function
Connections
AMPLIFIER INPUTS
IPDIN
LPDIN
OPDIN
VB
3
6
9
2
Input to TIA for EDFA input photodiode
Input to TIA for laser photodiode
Input to TIA for EDFA output photodiode
EDFA input photodiode and feedback resistor
Laser photodiode and feedback resistor
EDFA output photodiode and feedback resistor
Bias voltage for EDFA input and output photodiodes External bias voltage required
VBLP
CSP
5
37
38
Bias voltage for laser photodiode
Non-inverting input of current sense amplifier
Inverting input of current sense amplifier
External bias voltage required
High-side of laser current sense resistor (50 mΩ typ.)
Low-side of laser current sense resistor (50 mΩ typ.)
CSN
LIMIT INPUTS
VLIM
ILIM
OPLIM
LPLIM
IPMIN
1
Laser diode voltage will not exceed VLIM
Limits output voltage if LIO > ILIM
Limits output voltage if OPO > OPLIM
Limits output voltage if LPO > LPLIM
Limits output voltage if IPO is lower than IPMIN
External voltage required
45
47
46
48
External voltage or no connection (defaults to 2.5 V)
External voltage or no connection (defaults to 2.5 V)
External voltage or no connection (defaults to 2.5 V)
External voltage required
ERROR (COMPENSATION) AMPLIFIER (EA)
EANLP
41
Compensation network for laser diode loop
Compensation network for EDFA loop
Output of compensation amplifier
Internally connects inverting input of EA to laser diode
compensation network
Internally connects inverting input of EA to EDFA
compensation network
Internal connection to linear output amplifier
Connects to two external compensation networks: one
for EDFA loop, one for laser diode loop
EANOP
40
EAOUT
MUX
39
42
Allows separate compensation for EDFA and laser
diode
OPCMP
SET
44
8
Compensation for limiter section
Sets output power or current based on MODE
settings
R-C network to ground
External voltage or DAC
POWER OUTPUT AMPLIFIERS
LINOUT
PGATE
NGATE
SWITCH
FB
PWMCMP1
PWMCMP2
33
30
31
28
24
23
22
25
Linear amplifier output
Laser diode through 1 Ω series resistor
Gate of external PMOS for PWM output
Gate of external NMOS for PWM output
Drains of external NMOS, PMOS, and input of L-C filter
Output of L-C filter and laser diode
Series R-C networks to FB and PWMCMP2
Series R-C to PWMCMP1
Optional external FET can pull down and to engage
standby mode
PWM switching for PMOS
PWM switching for NMOS
PWM amplifier output
Feedback input for PWM amplifier
Compensation for PWM amplifier
Compensation for PWM amplifier
Constant current charges external capacitor to soft-
start PWM output from 0% duty cycle
SB
SS/
OUTPUT MONITOR VOLTAGES
IPO
4
10
7
11
12
Output of EDFA input photodiode TIA
Output of EDFA output photodiode TIA
Output of laser diode photodiode TIA
Output of current sense amplifier
Compares LIO to 90% of ILIM
Feedback resistor to IPDIN
Feedback resistor to OPDIN
Feedback resistor to LPDIN
OPO
LPO
LIO
DUAL
To SET pin of additional ADN8820 device in multi-
pump optical amplifier applications
EAOUT
39
Output of compesnation amplifier
Internal connection to linear output amplifier
OSCILLATOR SECTION
SYNCIN
SYNCOUT
27
26
Optional clock input signal for PLL
Follows rising edge of SYNCIN plus phase shift
Ground or external clock
Optional connection to SYNCIN of additional ADN8820
device
CMPOSC
PHASE
RT
16
17
15
Compensation for synchronizing PLL
Sets rising edge phase shift of SYNCOUT
Sets PWM clock frequency
R-C network to ground
External voltage or no connection (default is 0.7V)
Resistor (RT) to ground
Rev. PrB | Page 6 of 9
ADN8820
Preliminary Technical Data
Name
Pin
Function
Connections
DITHER GENERATOR
SD
21
36
35
4-level logic input to set dither frequency or engage External voltage
shutdown
DSEL/
DCTL
DO
Sets dither current as a percentage of the laser
diode current
Resistor (RDCTL) to ground
Optional dither AC current to laser diode
To laser diode through 1 nF series capacitor
LOGIC INPUTS
MODE1
MODE0
SD
DSEL/
SB
SS/
18
19
21
25
Sets control loop mode (see Table I)
Sets control loop mode (see Table I)
Pulling voltage low engages shutdown
Pulling voltage low engages standby
External logic voltage
External logic voltage
External voltage
470 pF soft-start capacitor to ground; optional external
FET can pull down to engage standby
LOGIC OUTPUTS
CLGD
20
Logic high if EAOUT is within 5% to 95% of AVDD;
Logic low otherwise
POWER
PVDD
AVDD
PGND
AGND
VREF
29, 34
43
32
14
13
Power for output amplifiers and digital sections
Low noise power for TIAs, limiter section, and EA
Current return for output amplifiers
Low noise ground
3.0 V to 5.5 V
3.0 V to 5.5 V
0 V
0 V
2.5 V reference voltage
Can be used as refernce for VB, VBLP, SET, and limiter
inputs
TABLE 4. MODE CONTROL LOGIC
MODE Inputs
MODE1 MODE0
Error Amplifier
MUX
Output Description
Mode Setting
-Input
+Input
0
0
1
1
0
1
0
1
Constant Current
EANLP
EANLP
EANOP
EANOP
SET
LIO
Maintains a fixed current through laser diode;
generally used for calibration.
Maintains a constant optical output power from
laser diode.
Maintains a constant optical power at output of
EDFA.
Constant Laser Power
Constant Ouptut Power
Constant Gain
SET
SET
IPO
LPO
OPO
OPO
Monitors both input and output optical power
to maintain constant gain from optical amplifier.
TABLE 5. PWM CLOCK FREQUENCY SELECTION LEVELS
SD
PWM Clock Frequency
DSEL/
Min
0
(V)
Max
Mode
Division
0.5
1.2
Shutdown
Active
N/A
0.7
f
f
f
DITHER ÷2
DITHER ÷4
DITHER ÷8
1.3
1.8
Active
2.0
VDD
Active
Note: fDITHER is the ADN8820 dither frequency and is set by a resistor connected from RT to ground.
Rev. PrB | Page 7 of 9
ADN8820
Preliminary Technical Data
OUTLINE DIMENSIONS
Figure 3. 48-Lead Frame (LFCSP-48) Chip Scale Package
7 x 7 mm Body
(CP-48)
Dimensions Shown in Millimeters
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although these products feature
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrB | Page 8 of 9
ADN8820
Preliminary Technical Data
ORDERING GUIDE
Table 6. ADN8820 Ordering Guide
Package
Product
Package
Option
Top
Mark
No. of Parts
per Reel
Temperature
Range (°C)
Description
ADN8820
48-Lead LFCSP CP-48
48-Lead LFCSP CP-48
Eval board N/A
TBD
TBD
N/A
N/A
TBD
N/A
–40 to +125
–40 to +125
–40 to +125
ADN8820-REEL7
ADN8820-EVAL
©
2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
C02747-0-4/03(C)
Rev. PrB | Page 9 of 9
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