ADN4666ARUZ-REEL7 [ADI]
3 V, LVDS, Quad CMOS Differential Line Receiver; 3 V ， LVDS ， CMOS四路差动线路接收器
| 型号： | ADN4666ARUZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | 3 V, LVDS, Quad CMOS Differential Line Receiver |
| 文件： | 总12页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3 V, LVDS, Quad CMOS
Differential Line Receiver
ADN4666
FEATURES
FUNꢁTIONAL BLOꢁK DIAGRAM
8 kꢀ ESD IEꢁ 61000-4-2 contact discharge on receiver input pins
400 Mbps (200 MHz) switching rates
100 ps channel-to-channel skew (typical)
100 ps differential skew (typical)
V
ADN4666
CC
R
R
R
IN1–
IN4–
R
IN1+
IN4+
R4
R1
3.3 ns propagation delay (maximum)
3.3 ꢀ power supply
R
R
OUT1
EN
OUT4
High impedance outputs on power-down
Low power design (10 mW quiescent typical)
Interoperable with existing 5 ꢀ LꢀDS drivers
Accepts small swing (350 mꢀ typical) differential
input signal levels
EN
R
R
OUT2
OUT3
R3
R2
Supports open, short, and terminated input fail-safe
ꢁonforms to TIA/EIA-644 LꢀDS standard
Industrial operating temperature range of −40°ꢁ to +85°ꢁ
Available in surface-mount SOIꢁ package and low profile
TSSOP package
R
R
R
IN2+
IN3+
R
IN2–
IN3–
GND
Figure 1.
APPLIꢁATIONS
Point-to-point data transmission
Multidrop buses
ꢁlock distribution networks
Backplane receivers
GENERAL DESꢁRIPTION
The ADN4666 is a quad-channel, CMOS low voltage differential
signaling (LVDS) line receiver offering data rates of over 400 Mbps
(200 MHz) and ultralow power consumption.
disable the receivers and switch the outputs to a high impedance
state. Consequently, the outputs of one or more ADN4666
devices can be multiplexed together to reduce the quiescent
power consumption to 10 mW typical.
The device accepts low voltage (350 mV typical) differential
input signals and converts them to a single-ended, 3 V TTL/CMOS
logic level.
The ADN4666 and its companion driver, the ADN4665, offer
a new solution to high speed, point-to-point data transmission
and offer a low power alternative to emitter-coupled logic (ECL)
or positive emitter-coupled logic (PECL).
The ADN4666 also offers active high and active low enable/disable
EN
inputs (EN and
) that control all four receivers. These inputs
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2009 Analog Devices, Inc. All rights reserved.
ADN4666
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................6
Pin Configuration and Function Descriptions..............................7
Typical Performance Characteristics ..............................................8
Theory of Operation .........................................................................9
Enable Inputs .................................................................................9
Applications Information.............................................................9
Outline Dimensions....................................................................... 10
Ordering Guide .......................................................................... 10
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings............................................................ 6
REꢀISION HISTORY
6/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
ADN4666
SPECIFICATIONS
VCC = 3.0 V to 3.6 V, CL = 15 pF to GND, all specifications TMIN to TMAX, unless otherwise noted.1, 2
Table 1.
Parameter
Symbol Min
Typ
Max
Unit
Test ꢁonditions/ꢁomments
LVDS INPUTS (RINx+, RINx−
Differential Input High Threshold at RINx+, RINx−
)
3
VTH
20
100
mV
VCM = 1.2 V, 0.05 V, 2.95 V
3
Differential Input Low Threshold at RINx+, RINx−
Common-Mode Voltage Range at RINx+, RINx−
Input Current at RINx+, RINx−
VTL
VCMR
IIN
−100
0.1
−10
−10
−20
2.0
GND
−10
−1.5
−20
mV
V
μA
μA
μA
V
V
μA
V
VCM = 1.2 V, 0.05 V, 2.95 V
VID = 200 mV p-p
VIN = 2.8 V, VCC = 3.6 V or 0 V
VIN = 0 V, VCC = 3.6 V or 0 V
VIN = 3.6 V, VCC = 0 V
4
2.3
5
1
1
+10
+10
+20
VCC
0.8
+10
Input High Voltage
Input Low Voltage
Input Current
VIH
VIL
IIN
1
−0.8
VIN = 0 V or VCC, other input = VCC or GND
ICL = −18 mA
Input Clamp Voltage
VCL
OUTPUTS (ROUTx
)
Output High Voltage
VOH
2.7
2.7
2.7
3.0
3.0
3.0
0.1
−48
1
V
V
V
V
mA
μA
IOH = −0.4 mA, VID = 200 mV
IOH = −0.4 mA, input terminated
IOH = −0.4 mA, input shorted
IOL = 2 mA, VID = −200 mV
Outputs enabled, VOUT = 0 V
Outputs disabled, VOUT = 0 V or VCC
Output Low Voltage
Output Short-Circuit Current5
Output Off State Current
VOL
IOS
IOZ
0.25
−120
+10
−15
−10
POWER SUPPLY
No Load Supply, Current Receivers Enabled
No Load Supply, Current Receivers Disabled
ICC
10
3
15
5
mA
mA
EN and EN = VCC or GND, inputs open
EN = GND and EN = VCC, inputs open
ICCZ
ESD PROTECTION
RINx+, RINx− Pins
8
15
4
kV
kV
kV
IEC 61000-4-2 contact discharge
Human body model
Human body model
All Pins Except RINx+, RINx−
1 Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground, unless otherwise specified.
2 All typical values are given for VCC = 3.3 V and TA = 25°C.
3 VCC is always higher than the RINx+ and RINx− voltage. RINx− and RINx+ have a voltage range of −0.2 V to VCC − VID/2. However, to be compliant with ac specifications, the
common-mode voltage range is 0.1 V to 2.3 V.
4 VCMR is reduced for larger input differential voltage (VID). For example, if VID is 400 mV, VCMR is 0.2 V to 2.2 V. The fail-safe condition with inputs shorted is not supported
over the common-mode range of 0 V to 2.4 V, but is supported only with inputs shorted and no external common-mode voltage applied. VID up to VCC − 0 V can be
applied to the RINx+/RINx− inputs with the common-mode voltage set to VCC/2. Propagation delay and differential pulse skew decrease when VID is increased from 200 mV to
400 mV. Skew specifications apply for 200 mV ≤ VID ≤ 800 mV over the common-mode range.
5 Output short-circuit current (IOS) is specified as magnitude only; a minus sign indicates direction only. Note that only one output should be shorted at a time; do not
exceed the maximum junction temperature specification (150°C).
Rev. 0 | Page 3 of 12
ADN4666
TIMING SPEꢁIFIꢁATIONS
VCC = 3.0 V to 3.6 V, CL = 15 pF to GND, all specifications TMIN to TMAX, unless otherwise noted.1
Table 2.
Parameter2
Symbol Min Typ3 Max Unit Test ꢁonditions/ꢁomments4, 5
AC CHARACTERISTICS
Differential Propagation Delay, High to Low tPHLD
Differential Propagation Delay, Low to High tPLHD
1.8
1.8
0
3.3
3.3
0.35 ns
ns
ns
CL = 15 pF, VID = 300 mV (see Figure 2 and Figure 3)
CL = 15 pF, VID = 300 mV (see Figure 2 and Figure 3)
CL = 15 pF, VID = 300 mV (see Figure 2 and Figure 3)
CL = 15 pF, VID = 300 mV (see Figure 2 and Figure 3)
Differential Pulse Skew6 |tPHLD − tPLHD
|
tSKD1
tSKD2
0.1
0.1
Differential Channel-to-Channel Skew
0
0.5
ns
(Same Device)7
Differential Part-to-Part Skew8
Differential Part-to-Part Skew9
Rise Time
tSKD3
tSKD4
tTLH
tTHL
tPHZ
tPLZ
tPZH
tPZL
fMAX
1.0
1.5
1.2
1.2
12
12
17
17
ns
ns
ns
ns
ns
ns
ns
ns
CL = 15 pF, VID = 300 mV (see Figure 2 and Figure 3)
CL = 15 pF, VID = 300 mV (see Figure 2 and Figure 3)
CL = 15 pF, VID = 300 mV (see Figure 2 and Figure 3)
CL = 15 pF, VID = 300 mV (see Figure 2 and Figure 3)
RL = 2 kΩ, CL = 15 pF (see Figure 4 and Figure 5)
RL = 2 kΩ, CL = 15 pF (see Figure 4 and Figure 5)
RL = 2 kΩ, CL = 15 pF (see Figure 4 and Figure 5)
RL = 2 kΩ, CL = 15 pF (see Figure 4 and Figure 5)
0.35
0.35
8
8
11
11
Fall Time
Disable Time, High to Z
Disable Time, Low to Z
Enable Time, Z to High
Enable Time, Z to Low
Maximum Operating Frequency10
200 250
MHz All channels switching
1 Generator waveform for all tests, unless otherwise specified: f = 1 MHz, ZO = 50 Ω, tTLH and tTHL (0% to 100%) ≤ 3 ns for RINx+/RINx−
2 AC parameters are guaranteed by design and characterization.
.
3 All typical values are given for VCC = 3.3 V and TA = 25°C.
4 Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground, unless otherwise specified.
5 CL includes load and jig capacitance.
6 tSKD1 is the magnitude difference in the differential propagation delay time between the positive-going edge and the negative-going edge of the same channel.
7 Channel-to-channel skew, tSKD2, is defined as the difference between the propagation delay of one channel and that of the others on the same chip with any event on
the inputs.
8 tSKD3 part-to-part skew is the differential channel-to-channel skew of any event between devices. The tSKD3 specification applies to devices at the same VCC and within
5°C of each other within the operating temperature range.
9 tSKD4 part-to-part skew is the differential channel-to-channel skew of any event between devices. The tSKD4 specification applies to devices over the recommended
operating temperature and voltage ranges and across process distribution. tSKD4 is defined as |maximum − minimum| differential propagation delay.
10
f
generator input conditions: f = 200 MHz, tTLH = tTHL < 1 ns (0% to 100%), 50% duty cycle, differential (1.05 V to 1.35 V p-p). fMAX generator output criteria: 60%/40%
MAX
duty cycle, VOL (maximum = 0.4 V), VOH (minimum = 2.7 V), and load = 15 pF (stray plus probes).
Test Circuits and Timing Diagrams
V
CC
R
R
INx+
SIGNAL
GENERATOR
R
OUTx
INx–
C
50Ω
50Ω
L
RECEIVER
IS ENABLED
NOTES
1. C = LOAD AND TEST JIG CAPACITANCE.
L
Figure 2. Test Circuit for Receiver Propagation Delay and Transition Time
Rev. 0 | Page 4 of 12
ADN4666
R
R
1.3V
1.1V
INx–
0V (DIFFERENTIAL)
1.2V
V
= 300mV p-p
ID
INx+
tPLHD
tPHLD
V
OH
80%
80%
R
1.5V
20%
1.5V
20%
OUTx
V
OL
tTLH
tTHL
Figure 3. Receiver Propagation Delay and Transition Time Waveforms
V
CC
S1
R
L
R
R
INx+
R
OUTx
INx–
EN
C
L
SIGNAL
GENERATOR
50Ω
EN
GND
NOTES
1. C INCLUDES LOAD AND TEST JIG CAPACITANCE.
L
2. S1 CONNECTED TO V FOR tPZL AND tPLZ MEASUREMENTS.
CC
3. S1 CONNECTED TO GND FOR tPZH AND tPHZ MEASUREMENTS.
Figure 4. Test Circuit for Receiver Enable/Disable Delay
3V
0V
EN WITH EN = GND
OR OPEN CIRCUIT
1.5V
1.5V
1.5V
3V
0V
EN WITH EN = V
1.5V
CC
tPHZ
tPZH
V
0.5V
OH
50%
50%
R
R
WITH V = +100mV
ID
OUTx
GND
V
CC
WITH V = –100mV
ID
OUTx
0.5V
V
OL
tPLZ
tPZL
Figure 5. Receiver Enable/Disable Delay Waveforms
Rev. 0 | Page 5 of 12
ADN4666
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
VCC to GND
−0.3 V to +4 V
−0.3 V to VCC + 0.3 V
−0.3 V to VCC + 0.3 V
−0.3 V to VCC + 0.3 V
−40°C to +85°C
−65°C to +150°C
150°C
Input Voltage (RINx+, RINx−) to GND
Enable Input Voltage (EN, EN) to GND
Output Voltage (ROUTx) to GND
Industrial Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature (TJ MAX
)
θJA Thermal Impedance
Power Dissipation
Reflow Soldering Peak Temperature,
Pb-Free
150.4°C/W
(TJ MAX − TA)/θJA
260°C 5°C
ESD ꢁAUTION
Rev. 0 | Page 6 of 12
ADN4666
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R
R
V
CC
IN1–
R
R
R
IN1+
IN4–
IN4+
OUT4
R
OUT1
EN
ADN4666
TOP VIEW
(Not to Scale)
R
OUT2
EN
R
IN2+
IN2–
R
OUT3
R
R
R
IN3+
GND
IN3–
Figure 6. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Description
1
RIN1−
RIN1+
ROUT1
EN
Receiver Channel 1 Inverting Input. When this input is more negative than RIN1+, ROUT1 is high. When this input is
more positive than RIN1+, ROUT1 is low.
Receiver Channel 1 Noninverting Input. When this input is more positive than RIN1−, ROUT1 is high. When this input
is more negative than RIN1−, ROUT1 is low.
Receiver Channel 1 Output (3 V TTL/CMOS). If the differential input voltage between RIN1+ and RIN1− is positive, this
output is high. If the differential input voltage is negative, this output is low.
2
3
4
EN
Active High Enable and Power-Down Input (3 V TTL/CMOS). When EN is low and
is high, the receiver outputs
EN
EN
are disabled and are in a high impedance state. When EN is high and
EN
is low or when EN is low and
is low,
the receiver outputs are enabled. When EN is high and
is high, the receiver outputs are enabled.
5
6
7
ROUT2
RIN2+
RIN2−
Receiver Channel 2 Output (3 V TTL/CMOS). If the differential input voltage between RIN2+ and RIN2− is positive, this
output is high. If the differential input voltage is negative, this output is low.
Receiver Channel 2 Noninverting Input. When this input is more positive than RIN2−, ROUT2 is high. When this input
is more negative than RIN2−, ROUT2 is low.
Receiver Channel 2 Inverting Input. When this input is more negative than RIN2+, ROUT2 is high. When this input is
more positive than RIN2+, ROUT2 is low.
8
9
GND
RIN3−
Ground Reference Point for All Circuitry on the Part.
Receiver Channel 3 Inverting Input. When this input is more negative than RIN3+, ROUT3 is high. When this input is
more positive than RIN3+, ROUT3 is low.
10
11
12
RIN3+
ROUT3
EN
Receiver Channel 3 Noninverting Input. When this input is more positive than RIN3−, ROUT3 is high. When this input
is more negative than RIN3−, ROUT3 is low.
Receiver Channel 3 Output (3 V TTL/CMOS). If the differential input voltage between RIN3+ and RIN3− is positive, this
output is high. If the differential input voltage is negative, this output is low.
EN
Active Low Enable and Power-Down Input with Pull-Down (3 V TTL/CMOS). ). When EN is low and
is high, the
is low or when EN is low
is high, the receiver outputs are enabled.
EN
receiver outputs are disabled and are in a high impedance state. When EN is high and
EN EN
and
is low, the receiver outputs are enabled. When EN is high and
13
14
15
16
ROUT4
RIN4+
RIN4−
VCC
Receiver Channel 4 Output (3 V TTL/CMOS). If the differential input voltage between RIN4+ and RIN4− is positive, this
output is high. If the differential input voltage is negative, this output is low.
Receiver Channel 4 Noninverting Input. When this input is more positive than RIN4−, ROUT4 is high. When this input
is more negative than RIN4−, ROUT4 is low.
Receiver Channel 4 Inverting Input. When this input is more negative than RIN4+, ROUT4 is high. When this input is
more positive than RIN4+, ROUT4 is low.
Power Supply Input. The ADN4666 can be operated from 3.0 V to 3.6 V.
Rev. 0 | Page 7 of 12
ADN4666
TYPICAL PERFORMANCE CHARACTERISTICS
80
200
150
100
70
3.6V SUPPLY
60
3.3V SUPPLY
3.6V SUPPLY
50
40
30
20
10
0
3.3V SUPPLY
50
0
3V SUPPLY
–50
3V SUPPLY
–100
–150
–200
0.01
0.1
1
10
100
1k
–0.1
0.4
0.9
1.4
1.9
2.4
2.9
3.4
3.9
FREQUENCY (MHz)
COMMON-MODE VOLTAGE (V)
Figure 7. Power Supply Current vs. Frequency
Figure 10. Skew vs. Common-Mode Voltage, 25°C
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
3
2
1
0
3V SUPPLY
V
T
= 3.3V
= 25°C
fIAN = 100MHz
CC
2 CHANNELS SWITCHING
MAX PROP DELAY MEASURED,
tPHLD, tPLHD = 2.54ns
MAX SKEW MEASURED
3.3V SUPPLY
|
tPLHD – tPHLD | = 280ps
3.6V SUPPLY
–0.1
0
0.1
0.2
0.3
0.4
(V)
0.5
0.6
0.7
0.8
–0.1
0.4
0.9
1.4
1.9
2.4
2.9
3.4
3.9
V
ID
COMMON-MODE VOLTAGE (V)
Figure 11. Typical Common-Mode Range Variation
with Respect to the Amplitude of the Differential Input
Figure 8. Differential Propagation Delay (tPLHD) vs. Common-Mode Voltage, 25°C
2.9
2.7
3V SUPPLY
2.5
3.3V SUPPLY
2.3
3.6V SUPPLY
2.1
1.9
–0.1
0.4
0.9
1.4
1.9
2.4
2.9
3.4
3.9
COMMON-MODE VOLTAGE (V)
Figure 9. Differential Propagation Delay (tPHLD) vs. Common-Mode Voltage, 25°C
Rev. 0 | Page 8 of 12
ADN4666
THEORY OF OPERATION
The ADN4666 is a quad-channel line receiver for low voltage
differential signaling (LVDS). It takes a differential input signal
of 350 mV typical and converts it into a single-ended, 3 V TTL/
CMOS logic signal.
This is similar to emitter-coupled logic (ECL) and positive emitter-
coupled logic (PECL), but without the high quiescent current of
ECL and PECL.
ENABLE INPUTS
A differential current input signal, received via a transmission
medium such as a twisted pair cable, develops a voltage across
a termination resistor, RT. This resistor is chosen to match the
characteristic impedance of the medium, typically around 100 Ω.
The differential voltage is detected by the receiver and converted
back into a single-ended logic signal.
The ADN4666 has active high and active low enable inputs that
put all the logic outputs into a high impedance state when disabled,
reducing device current consumption from 10 mA typical to 3 mA
typical. See Table 5 for a truth table of the enable inputs.
Table 5. Enable Inputs Truth Table
Pin Logic Level
When the noninverting receiver input, RINx+, is positive with respect
to the inverting input, RINx− (that is, when current flows through
RT from RINx+ to RINx−), ROUTx is high. When the noninverting
receiver input, RINx+, is negative with respect to the inverting
input, RINx− (that is, when current flows through RT from RINx−
to RINx+), ROUTx is low.
EN
EN
RINx+
RINx−
ROUTx
Low
Low
Low
High
High
High
Low
Low
Low
Low
X1
X1
High-Z
1.025 V
1.375 V
1.025 V
1.375 V
1.375 V
1.025 V
1.375 V
1.025 V
0
1
0
1
Using the ADN4665 as a driver, the received differential current
is between 2.5 mA and 4.5 mA ( 3.5 mA typical), developing
between 250 mV and 450 mV across a 100 Ω termination
resistor. The received voltage is centered around the receiver
offset of 1.2 V. Therefore, the noninverting receiver input is
typically 1.375 V (that is, 1.2 V + [350 mV/2]) and the inverting
receiver input is 1.025 V (that is, 1.2 V − [350 mV/2]) for a
Logic 1. For a Logic 0, the inverting and noninverting input
voltages are reversed. Note that because the differential voltage
reverses polarity, the peak-to-peak voltage swing across RT is
twice the differential voltage.
1 X = don’t care.
APPLIꢁATIONS INFORMATION
Figure 12 shows a typical application for point-to-point data
transmission using the ADN4665 as the driver and the
ADN4666 as the receiver.
1/4 ADN4665
1/4 ADN4666
EN
EN
EN
EN
D
D
R
INx+
OUTx+
Current-mode drivers offer considerable advantages over voltage-
mode drivers, such as the RS-422 drivers. The operating current
remains fairly constant with increased switching frequency,
whereas the operating current of voltage-mode drivers increases
exponentially in most cases. This increase is caused by the overlap
as internal gates switch between high and low, causing currents
to flow from VCC to ground. A current-mode device reverses a
constant current between its two outputs, with no significant
overlap currents.
R
T
100Ω
D
R
OUTx
INx
R
OUTx–
INx–
GND
GND
Figure 12. Typical Application Circuit
Rev. 0 | Page 9 of 12
ADN4666
OUTLINE DIMENSIONS
10.00 (0.3937)
9.80 (0.3858)
9
8
16
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
BSC
0.50 (0.0197)
0.25 (0.0098)
45°
1.75 (0.0689)
1.35 (0.0531)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 13. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 14. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range Package Description
Package Option
R-16
R-16
RU-16
RU-16
ADN4666ARZ1
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
16-Lead Thin Standard Small Outline Package [SOIC_N]
16-Lead Thin Standard Small Outline Package [SOIC_N]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
ADN4666ARZ-REEL71
ADN4666ARUZ1
ADN4666ARUZ-REEL71
1 Z = RoHS Compliant Part.
Rev. 0 | Page 10 of 12
ADN4666
NOTES
Rev. 0 | Page 11 of 12
ADN4666
NOTES
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08097-0-6/09(0)
Rev. 0 | Page 12 of 12
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