ADM691AARU-REEL [ADI]
1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO16, TSS0P-16;
| 型号： | ADM691AARU-REEL |
| 厂家： | 
ADI |
| 描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO16, TSS0P-16 光电二极管 |
| 文件： | 总12页 (文件大小：335K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Microprocessor
a
Supervisory Circuits
ADM691A/ADM693A/ADM800L/M
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Low Power Consumption:
Precision Voltage Monitor
BATT ON
؎2% Tolerance on ADM800L/M
Reset Time Delay—200 ms, or Adjustable
1 A Standby Current
1
4.65V
LOW LINE
V
CC
Automatic Battery Backup Power Switching
Fast Onboard Gating of Chip Enable Signals
Also Available in TSSOP Package (ADM691A)
V
OUT
V
BATT
CHIP ENABLE
OUTPUT
CONTROL
APPLICATIONS
Microprocessor Systems
Computers
CE
OUT
CE
IN
Controllers
Intelligent Instruments
Automotive Systems
Critical P Power Monitoring
RESET &
WATCHDOG
TIMEBASE
OSC IN
RESET &
GENERATOR
RESET
OSC SEL
RESET
WATCHDOG
WATCHDOG
TRANSITION DETECTOR
WATCHDOG
TIMER
WATCHDOG
INPUT (WDI)
OUTPUT (WDO)
POWER FAIL
INPUT (PFI)
GENERAL DESCRIPTION
POWER FAIL
1.25V
OUTPUT (PFO)
The ADM691A/ADM693A/ADM800L/ADM800M family of
supervisory circuits offers complete single chip solutions for
power supply monitoring and battery control functions in
microprocessor systems. These functions include µP reset,
backup-battery switchover, watchdog timer, CMOS RAM write
protection, and power-failure warning. The family of products
provides an upgrade for the MAX691A/93A/800M family of
products.
ADM691A/ADM693A
ADM800L/ADM800M
1
VOLTAGE DETECTOR = 4.4V (ADM693A/ADM800M)
INPUT
POWER
+5V
All parts are available in 16-pin DIP and SO packages. The
ADM691A is also available in a space-saving TSSOP package.
The following functionality is provided:
7805
0.1µF
V
CC
CMOS
RAM
V
V
BAT
ON
OUT
1. Power-on reset output during power-up, power-down and
brownout conditions. The circuitry remains operational with
CC
V
BATT
ADDRESS
DECODE
CE
BATTERY
OUT
R1
R2
CE
ADM691A
ADM693A
ADM800L
ADM800M
IN
V
CC as low as 1 V.
A0–A15
µP
POWER
PFI
GND
2. Battery backup switching for CMOS RAM, CMOS micro-
processor or other low power logic.
WDI
PFO
I/O LINE
NMI
OSC IN
µP
NC
RESET
RESET
OSC SEL
3. A reset pulse if the optional watchdog timer has not been
toggled within a specified time.
WDO
LOW LINE
4. A 1.25 V threshold detector for power fail warning, low bat-
tery detection, or to monitor a power supply other than +5 V.
SYSTEM
STATUS
INDICATORS
Figure 1. Typical Application
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1996
ADM691A/ADM693A/ADM800L/M–SPECIFICATIONS
(VCC = 4.75 V to 5.5 V (ADM691A, ADM800L) 4.5 V to 5.5 V (ADM693A, ADM800M) VBATT = +2.8 V, TA = TMIN to TMAX unless otherwise noted)
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
BATTERY BACKUP SWITCHING
VCC, VBATT Operating Voltage Range
VOUT Output Voltage
0
5.5
V
V
V
Ω
V
VCC – 0.05
VCC – 0.3
VCC – 0.02
VCC – 0.2
0.8
IOUT = 25 mA
IOUT = 250 mA
VCC = 4.5 V
VBATT = 4.5 V, IOUT = 20 mA
VBATT = 2.8 V, IOUT = 10 mA
VBATT = 2.0 V, IOUT = 5 mA
VBATT = 4.5 V
VBATT = 2.8 V
VBATT = 2.0 V
VCC > (VBATT – 1 V)
VCC < (VBATT – 1.2 V), VBATT = 2.8 V
5.5 V > VCC > VBATT + 0.2 V
(VBATT +0.2 V) < VCC , TA = +25°C
(VBATT +0.2 V) < VCC
Power Up
VCC to VOUT Output Resistance
VOUT in Battery Backup Mode
1.2
VBATT – 0.3
VBATT – 0.25
VBATT – 0.15
V
V
VBATT to VOUT Output Resistance
12
20
25
100
1
Ω
Ω
Ω
µA
µA
Supply Current (Excludes IOUT
)
70
0.04
Supply Current in B. Backup (Excludes IOUT
Battery Standby Current
(+ = Discharge, – = Charge)
)
–0.1
–1.0
+0.02
+0.02
µA
µA
V
Battery Switchover Threshold
VCC–VBATT
VBATT + 0.03
VBATT – 0.03
V
Power Down
Battery Switchover Hysteresis
BATT ON Output Voltage Low
60
mV
V
V
mA
µA
0.1
0.7
60
0.4
1.5
ISINK = 3.2 mA
ISINK = 25 mA
Sink Current
BATT ON Output Short Circuit Current
1
15
100
Source Current
RESET AND WATCHDOG TIMER
Reset Voltage Threshold
ADM691A, ADM800L
ADM693A, ADM800M
ADM800L, VCC Falling
ADM800M, VCC Falling
4.5
4.65
4.40
4.75
4.50
4.70
4.45
V
V
V
V
4.25
4.55
4.3
TA = +25°C
TA = +25°C
Reset Threshold Hysteresis
VCC to RESET Delay
LOW LINE to RESET Delay
Reset Timeout Period Internal Oscillator
Reset Timeout Period External Clock
15
80
mV
µs
ns
ms
Power Down
800
200
2048
1.6
100
4096
1024
140
280
Power Up
Cycles Power Up
s
ms
Cycles Long Period
Cycles Short Period
Watchdog Timeout Period, Internal Oscillator
1.0
70
2.25
140
Long Period
Short Period
Watchdog Timeout Period, External Clock
Minimum WDI Input Pulse Width
RESET Output Voltage
100
ns
V
V
V
mA
V
V
V
µA
V
V
VIL = 0.4, VIH = 0.75 × VCC
0.004
0.1
0.3
0.4
ISINK = 50 µA, VCC = 1 V, VBATT = 0 V
ISINK = 3.2 mA, VCC = 4.25 V
ISOURCE = 1.6 mA, VCC = 5 V
3.5
0.1
RESET Output Short Circuit Current
RESET Output Voltage Low
LOW LINE Output Voltage
7
0.4
20
ISINK = 3.2 mA
ISINK = 3.2 mA, VCC = 4.25 V
ISOURCE = 1 µA, VCC = 5 V
0.4
3.5
1
LOW LINE Short Circuit Source Current
WDO Output Voltage
15
3
100
0.4
ISINK = 3.2 mA, VCC = 4.25 V
ISOURCE = 500 µA, VCC = 5 V
3.5
WDO Short Circuit Source Current
WDI Input Threshold
Logic Low
10
mA
0.8
V
Logic High
0.75 × VCC
V
WDI Input Current
–50
–10
20
µA
µA
WDI = 0 V
WDI = VOUT
50
POWER FAIL DETECTOR
PFI Input Threshold ADM69xA
PFI Input Threshold ADM800L/M
PFI Input Current
1.2
1.225
1.25
1.25
±0.01
1.3
V
V
nA
V
VCC = 5 V
VCC = 5 V
1.275
±25
0.4
PFO Output Voltage
ISINK = 3.2 mA
3.5
1
ISOURCE = 1 µA
PFO Short Circuit Source Current
PFI to PFO Delay
15
25
60
100
µA
µs
µs
VIN = –20 mV
VIN = 20 mV
REV. 0
–2–
ADM691A/ADM693A/ADM800L/M
Parameter
Min
Typ
Max
Units
Test Conditions/Comments
CHIP ENABLE GATING
CEIN Leakage Current
CEIN to CEOUT Resistance
CEIN to CEOUT Propagation Delay
CEOUT Short-Circuit Current
CEOUT Output Voltage
±0.005
40
6
±1
150
10
µA
Ω
ns
mA
V
Disable Mode
Enable Mode
RIN = 50 Ω, CLOAD = 50 pF
Disable Mode, CEOUT = 0 V
VCC = 5 V, IOUT = –100 µA
VCC = 0 V, VBATT = 2.8 V, IOUT = 1 µA
Power Down
0.1
3.5
2.7
0.75
2.0
V
µs
RESET to CEOUT Propagation Delay
12
OSCILLATOR
OSC IN Input Current
0.1
10
10
500
VOUT – 0.6
3.65
100
±5
100
100
µA
µA
µA
kHz
V
OSC SEL = 0 V
OSC SEL = VOUT or Floating
OSC SEL = 0 V
OSC SEL = 0 V
VIH
OSC In Input Pullup Current
OSC SEL Input Pullup Current
OSC IN Frequency Range
OSC IN Threshold Voltage
VOUT – 0.4
2.00
V
kHz
VIL
OSC IN Frequency with Ext Capacitor
OSC SEL = 0 V, COSC = 47 pF
NOTES
1Either VCC or VBATT can be 0 V if the other > +2.0 V.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C unless otherwise noted)
ORDERING GUIDE
Temperature
Range
Package
Option
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
All Other Inputs . . . . . . . . . . . . . . . . . –0.3 V to VOUT + 0.5 V
Input Current
Model
ADM691AAN
ADM691AARN
ADM691AARW
ADM691AARU
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
N-16
R-16N
R-16W
RU-16
V
V
V
V
CC (Peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mA
CC (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA
BATT (Peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA
BATT (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
ADM693AAN
ADM693AARN
ADM693AARW
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
N-16
R-16N
R-16W
GND, BATT ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Power Dissipation, N-16 DIP . . . . . . . . . . . . . . . . . . 842 mW
ADM800LAN
ADM800LARN
ADM800LARW
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
N-16
R-16N
R-16W
θ
ϑA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W
Power Dissipation, R-16 Narrow SOIC . . . . . . . . . . . 700 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . .110°W
Power Dissipation, R-16 Wide SOIC . . . . . . . . . . . . . 762 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W
Power Dissipation, RU-16 TSSOP . . . . . . . . . . . . . . 500 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 158°C/W
Operating Temperature Range
ADM800MAN
ADM800MARN
ADM800MARW
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
N-16
R-16N
R-16W
Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods of time may affect device reliability.
Table I. Product Selection Table
Watchdog
Power On
Reset Time
Low VCC
Threshold
Battery Backup
Base Drive
Ext PNP
Chip Enable
Signals
Part No.
Timeout
Switching
ADM691A
ADM693A
ADM800M
ADM800L
200 ms or Adj.
200 ms or Adj.
200 ms or Adj.
200 ms or Adj.
4.65 V ± 3%
4.4 V ± 3%
4.4 V ± 2%
4.65 V ± 2%
100 ms, 1.6 s, Adj.
100 ms, 1.6 s, Adj.
100 ms, 1.6 s, Adj.
100 ms, 1.6 s, Adj.
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
REV. 0
–3–
ADM691A/ADM693A/ADM800L/M
PIN DESCRIPTIONS
Pin
Mnemonic
Function
1
VBATT
Backup Battery Input. Connect to external battery or capacitor. Connect to ground if a backup battery is
not used.
2
VOUT
Output Voltage, VCC or VBATT is internally switched to VOUT depending on which is at the highest poten-
tial. When VCC is higher than VBATT and is also higher than the reset threshold, VCC is switched to VOUT
When VCC is lower than VBATT and below the reset threshold, VBATT is switched to VOUT. Connect VOUT to
CC if a backup battery is not being used.
.
V
3
4
5
VCC
Power Supply Input; +5 V.
GND
0 V. Ground reference for all signals.
BATT ON
Logic Output. BATT ON goes high when VOUT is internally switched to the VBATT input. It goes low when
V
OUT is internally switched to VCC. The output may also be used to drive the base (via a resistor) of an ex-
ternal PNP transistor to increase the output current above the 250 mA rating of VOUT
Logic Output. LOW LINE goes low when VCC falls below the reset threshold. It returns high as soon as
CC rises above the reset threshold.
.
6
7
LOW LINE
V
OSC IN
Oscillator Logic Input. With OSC SEL high or floating, the internal oscillator is enabled and sets the reset
delay and the watchdog timeout period. Connecting OSCIN low selects 100 ms while leaving it floating
selects 1.6 sec. With OSC SEL low, OSC IN can be driven by an external clock signal or an external ca-
pacitor can be connected between OSC IN and GND. This sets both the reset active pulse timing and the
watchdog timeout period. (See Table II and Figure 4.)
8
OSC SEL
Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal oscil-
lator sets the reset active time and watchdog timeout period. When OSC SEL is low, the external oscillator
input, OSC IN, is enabled. OSC SEL has a 10 µA internal pullup.
9
PFI
Power Fail Input. PFI is the noninverting input to the Power Fail Comparator. When PFI is less than
1.25 V, PFO goes low. Connect PFI to GND or VOUT when not used.
10
11
PFO
WDI
Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI is less than
1.25 V.
Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than the watch-
dog timeout period, RESET pulses low and WDO goes low. The timer resets with each transition on the
WDI line. The Watchdog Timer may be disabled if WDI is left floating or is driven to midsupply.
12
CEOUT
Output. CEOUT goes low only when CEIN is low and VCC is above the reset threshold. If CEIN is low when
reset is asserted, CEOUT will remain low for 15 µs or until CEIN goes high, whichever occurs first.
13
14
CEIN
Chip Enable Input. The input to the CE gating circuit. Connect to GND or VOUT if not used.
WDO
Logic Output. The Watchdog Output, WDO, goes low if WDI remains either high or low for longer than
the Watchdog timeout period. WDO is set high by the next transition at WDI. WDO remains high if WDI
is unconnected.
15
16
RESET
Logic Output. RESET goes low if VCC falls below the Reset Threshold. It remains low for 200 ms typ after
V
CC goes above the reset threshold.
RESET
Logic Output. RESET is an open-drain output. It is the inverse of RESET.
PIN CONFIGURATIONS
V
1
2
3
4
5
6
7
8
16 RESET
15
BATT
V
RESET
14 WDO
OUT
V
CC
ADM691A
ADM693A
ADM800L
ADM800M
CE
CE
GND
13
12
IN
BATT ON
LOW LINE
OSC IN
OUT
11 WDI
TOP VIEW
(Not to Scale)
PFO
10
9
PFI
OSC SEL
REV. 0
–4–
Typical Performance Curves–ADM691A/ADM693A/ADM800L/M
1.2
100
90
1.1
80
1.0
0.9
0.8
70
60
50
40
30
20
0.7
0.6
–50
–30
–10
10
30
50
70
90
–50
–25
0
25
50
75
100
125
TEMPERATURE – °C
TEMPERATURE – °C
Figure 5. VCC to VOUT ON-Resistance vs. Temperature
Figure 2. ICC vs. Temperature: Normal Operation
80
70
60
60
55
R
= 0.67Ω
OUT
50
45
40
35
30
50
40
30
20
10
0
–50
–30
–10
10
30
50
70
90
40
60
80
100
120
I
– mA
TEMPERATURE – °C
OUT
Figure 6. VCC to VOUT Voltage Drop vs. Current
Figure 3. IBATT vs. Temperature: Battery Backup Mode
70
60
80
70
R
= 7Ω
OUT
50
40
30
20
10
0
60
50
40
30
20
4
6
8
10
–50
–25
0
25
50
75
100
125
I
– mA
TEMPERATURE – °C
OUT
Figure 7. VBATT to VOUT Voltage Drop vs. Current
Figure 4. Chip Enable ON-Resistance vs. Temperature
REV. 0
–5–
ADM691A/ADM693A/ADM800L/M
16
14
12
10
V
BATT
= 2.8V
9
8
7
6
5
4
3
2
1
0
10
8
6
4
2
0
0
50
100
150
200
250
300
0
0.5
1.0
1.5
2.0
2.5
– V
3.0
3.5
4.0
4.5
5.0
V
LOAD CAPACITANCE – pF
CC
Figure 11. Chip Enable Propagation Delay vs.
Load Capacitance
Figure 8. Battery Current vs. Input Supply Voltage
100
230
220
210
200
190
180
170
LONG WATCHDOG TIMEOUT PERIOD
10
RESET ACTIVE
TIMEOUT PERIOD = >
1
SHORT WATCHDOG
TIMEOUT PERIOD
0.1
10
–50
–30
–10
10
30
50
70
90
100
– pF
1k
C
TEMPERATURE – °C
OSC
Figure 12. Reset Timeout Relay vs. Temperature
Figure 9. Watchdog and Reset Timeout Period vs.
OSC IN Capacitor
1200
1000
7.0
6.5
V
= 5V, V
= 2.8V
CC
BATT
800
600
400
200
0
6.0
5.5
5.0
SOURCING CURRENT
V
CC
= 0V, V
= 2.8V
SINKING CURRENT
BATT
4.5
4.0
–50
–20
40
70
100
130
10
–50
–25
0
25
50
75
100
125
TEMPERATURE – °C
TEMPERATURE – °C
Figure 10. Chip Enable Propagation Delay vs.
Temperature
Figure 13. RESET Output Resistance vs. Temperature
REV. 0
–6–
ADM691A/ADM693A/ADM800L/M
100
90
100
90
10
10
0%
0%
1V
400ms
1V
10µs
Figure 14. RESET Output Voltage vs. Supply
Figure 15. RESET Response Time
POWER FAIL RESET OUTPUT
The normal (short) timeout period becomes effective following
the first transition of WDI after reset has gone inactive. The
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to high transition on the WDI pin
must occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be is-
sued after each timeout period (1.6 seconds). The watchdog
monitor can be deactivated by floating the Watchdog Input
(WDI). If floating, an internal resistor network biases WDI to
around 1.6 V.
RESET is an active low output that provides a reset signal to the
Microprocessor whenever VCC is at an invalid level. When VCC
falls below the reset threshold, the RESET output is forced
low. The reset voltage threshold is 4.65 V (ADM691A/
ADM800L) or 4.4 V (ADM693A/ADM800M).
On power-up RESET will remain low for 200 milliseconds after
V
CC rises above the appropriate reset threshold. This allows time
for the power supply and microprocessor to stabilize. On power-
down, the RESET output remains low with VCC as low as 1 V.
This ensures that the microprocessor is held in a stable shut-
down condition. If RESET is required to be low for voltages be-
low 1 V, this may be achieved by connecting a pull-down resistor
on the RESET line. The resistor will help maintain RESET low
down to VCC = 0 V. Note that this is only necessary if VBATT is
below 2 V. With battery voltages ≥2 V RESET will function cor-
rectly with VCC from 0 V to +5.5 V.
BATT ON
1
4.65V
LOW LINE
V
CC
V
OUT
This reset active time is adjustable by using an external oscillator
or by connecting an external capacitor to the OSC IN pin. Refer
to Table II.
V
BATT
CHIP ENABLE
OUTPUT
CONTROL
The guaranteed minimum and maximum thresholds of the
ADM691A/ADM800L are 4.5 V and 4.75 V, while the guaran-
teed thresholds of the ADM693A/ADM800M are 4.25 V and
4.5 V. The ADM691A/ADM800L is therefore compatible with
5 V supplies with a +10%, –5% tolerance while the ADM693A/
ADM800M is compatible with 5 V ± 10% supplies.
CE
OUT
CE
IN
RESET &
WATCHDOG
TIMEBASE
OSC IN
RESET &
RESET
GENERATOR
OSC SEL
RESET
WATCHDOG
WATCHDOG
TRANSITION DETECTOR
WATCHDOG
TIMER
WATCHDOG
INPUT (WDI)
OUTPUT (WDO)
In addition to RESET an active high RESET output is provided.
This is the complement of RESET and is useful for processors
requiring an active high RESET signal.
POWER FAIL
INPUT (PFI)
POWER FAIL
1.25V
OUTPUT (PFO)
ADM691A/ADM693A
ADM800L/ADM800M
Watchdog Timer Reset
The watchdog timer circuit monitors the activity of the micro-
processor in order to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within the
selected timeout period, a reset pulse is generated. The watch-
dog timeout period may be configured for either a fixed “short”
100 ms or a “long” 1.6 second timeout period or for an adjust-
able timeout period. Note that even if the short timeout period
is selected, the first time out immediately following a reset is
1.6 sec. This is to allow additional time for the microprocessor
to regain control following a reset.
1
VOLTAGE DETECTOR = 4.4V (ADM693A/ADM800M)
Figure 16. Functional Block Diagram
Watchdog Output (WDO)
The Watchdog Output WDO provides a status output that goes
low if the watchdog timer “times out” and remains low until set
high by the next transition on the watchdog input. WDO is also
set high when VCC goes below the reset threshold. If WDI re-
mains high or low indefinitely, RESET and RESET will gener-
ate 200 ms pulses every 1.6 sec.
The watchdog timer is restarted at the end of reset, whether the
reset was caused by lack of activity on WDI or by VCC falling be-
low the reset threshold.
REV. 0
–7–
ADM691A/ADM693A/ADM800L/M
Changing the Watchdog and Reset Timeout
When VCC is below the reset threshold, the watchdog function is
disabled and WDI goes high impedance as it is disconnected
from its internal resistor network.
The watchdog and reset timeout periods may be controlled us-
ing OSC SEL and OSC IN. Please refer to Table II. With both
these inputs floating (or connected to VOUT) as in Figure 16, the
reset timeout is fixed at 200 ms and the watchdog timeout is
fixed at 1.6 sec.. If OSC IN is connected to GND as in Figure
16, the reset timeout period remains at 200 ms but a short
(100 ms) watchdog timeout period is selected (except immedi-
ately following a reset where it reverts to 1.6 sec). By connecting
OSC SEL to GND it is possible to select alternative timeout pe-
riods by either connecting a capacitor from OSC IN to GND or
by overdriving OSC IN with an external clock. With an external
capacitor, the watchdog timeout period is
The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods.
OSC SEL
tRS
V
CC
tRS
RESET
THRESHOLD
80µs
80µs
RESET
Twd (ms) = 600 (C/47 pF)
and the reset active period is
RESET
Treset (ms) = 1200 (C/47 pF)
CE
IN
With an external clock connected to OSC IN, the timeout
periods become
12µs
CE
OUT
Twd = 1024 (1/fCLK
Treset = 2048 (1/fCLK
Battery-Switchover Section
)
)
Figure 17. RESET and Chip Enable Timing
During normal operation with VCC higher than the reset thresh-
old and higher than VBATT, VCC is internally switched to VOUT
via an internal PMOS transistor switch. This switch has a typi-
cal on-resistance of 0.75 Ω and can supply up to 250 mA at the
8
OSC SEL
ADM69_A
ADM800_
7
CLOCK
0 TO 250kHz
V
OUT terminal. VOUT is normally used to drive a RAM memory
OSC IN
bank which may require instantaneous currents of greater than
250 mA. If this is the case then a bypass capacitor should be
connected to VOUT. The capacitor will provide the peak current
transients to the RAM. A capacitance value of 0.1 µF or greater
may be used.
Figure 18a. External Clock Source
8
If the continuous output current requirement at VOUT exceeds
250 mA or if a lower VCC–VOUT voltage differential is desired,
an external PNP pass transistor may be connected in parallel
with the internal transistor. The BATT ON output can drive
the base of the external transistor.
NC
OSC SEL
ADM69_A
ADM800_
7
OSC IN
NC
If VCC drops below VBATT and below the reset threshold, battery
backup is selected. A 7 Ω MOSFET switch connects the VBATT
input to VOUT. This MOSFET has very low input-to-output
differential (dropout voltage) at the low current levels required for
battery backup of CMOS RAM or other low power CMOS cir-
cuitry. The supply current in battery backup is typically 0.04 µA.
Figure 18b. Internal Oscillator (1.6 s Watchdog)
8
OSC SEL
ADM69_A
ADM800_
7
High value capacitors, either standard electrolytic or the farad-
size double layer capacitors, can also be used for short-term
memory backup.
OSC IN
C
OSC
If the battery-switchover section is not used, VBATT should be
Figure 18c. External Capacitor
connected to GND and VOUT should be connected to VCC
.
Table II. Reset Pulse Width and Watchdog Timeout Selections
Watchdog Timeout Period
OSC SEL
OSC IN
Normal
Immediately After Reset
Reset Active Period
Low
Low
Floating
Floating
External Clock Input
External Capacitor
Low
1024 clks
600 ms × C/47 pF
100 ms
4096 clks
2.4 s × C/47 pF
1.6 s
2048 clks
1200 ms × C/47 pF
200 ms
Floating or VOUT
1.6 s
1.6 s
200 ms
REV. 0
–8–
ADM691A/ADM693A/ADM800L/M
INPUT
8
7
OSC SEL
OSC IN
POWER
POWER
R1
POWER
FAIL
OUTPUT
PFO
1.25V
FAIL
ADM69_A
ADM800_
INPUT
R2
C
OSC
Figure 20. Power Fail Comparator
Figure 18d. Internal Oscillator (100 ms Watchdog)
Table III. Input and Output Status in Battery Backup Mode
WDI
Signal
Status
VBATT
VOUT
Supply Current is <1 µA.
VOUT is connected to VBATT via an internal
PMOS switch.
WDO
VCC
Switchover comparator monitors VCC for
active switchover.
t2
t3
GND
0 V.
BATT ON
Logic High. The open circuit voltage is equal
RESET
to VOUT
.
LOW LINE
OSC IN
OSC SEL
PFI
Logic Low.
t1
t1
t1
OSC IN is ignored.
OSC SEL is ignored.
t1 = RESET TIME.
t2 = NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD.
The Power Fail Comparator remains active in
the battery-backup mode for VCC ≥ VBATT
–1.2 V. With VCC lower than this, PFO is
forced low.
t3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET.
Figure 19. Watchdog Timing
CE Gating and RAM Write Protection
PFO
The Power Fail Comparator remains active in
the battery-backup mode for VCC ≥ VBATT
–1.2 V. With VCC lower than this, PFO is
forced low.
All products include memory protection circuitry which ensures
the integrity of data in memory by preventing write operations
when VCC is at an invalid level. There are two additional pins,
CEIN and CEOUT, that control the Chip Enable or Write inputs
of CMOS RAM. When VCC is present, CEOUT is a buffered rep-
lica of CEIN, with a 5 ns propagation delay. When VCC falls be-
low the reset voltage threshold, an internal gate forces CEOUT
high, independent of CEIN.
WDI
WDI is ignored.
CEOUT
Logic High. The open circuit voltage is equal
to VOUT
.
CEIN
High Impedance.
WDO
Logic High. The open circuit voltage is equal
CEOUT typically drives the CE, CS, or Write input of battery
backed up CMOS RAM. This ensures the integrity of the data
in memory by preventing write operations when VCC is at an in-
valid level. Similar protection of EEPROMs can be achieved by
using the CEOUT to drive the Store or Write inputs of an
EEPROM, EAROM, or NOVRAM.
to VOUT
.
RESET
Logic Low.
RESET
High Impedance.
Power Fail Warning Comparator
An additional comparator is provided for early warning of fail-
ure in the microprocessor’s power supply. The Power Fail Input
(PFI) is compared to an internal +1.25 V reference. The Power
Fail Output (PFO) goes low when the voltage at PFI is less than
1.3 V. Typically PFI is driven by an external voltage divider that
senses either the unregulated dc input to the system’s 5 V regu-
lator or the regulated 5 V output. The voltage divider ratio can
be chosen such that the voltage at PFI falls below 1.25 V several
milliseconds before the +5 V power supply falls below the reset
threshold. PFO is normally used to interrupt the microprocessor
so that data can be stored in RAM and the shut- down proce-
dure executed before power is lost.
REV. 0
–9–
ADM691A/ADM693A/ADM800L/M
APPLICATIONS INFORMATION
INPUT
POWER
INCREASING THE DRIVE CURRENT
TO
µP NMI
R1
R2
(PFO)
1.25V
If the continuous output current requirements at VOUT exceeds
250 mA or if a lower VCC–VOUT voltage differential is desired, an
external PNP pass transistor may be connected in parallel with
the internal transistor. The BATT ON output can drive the
base of the external transistor via a current limiting transistor.
PFI
R3
R2+R3
V
H
= 1.25 1+
R1
PNP
TRANSISTOR
R2 × R3
+5V
INPUT
POWER
1.25
V
–1.25
CC
5V
V
= 1.25+R1
0.1µF
0.1µF
L
R2
R3
R1+R2
R2
V
= 1.25
PFO
0V
MID
V
V
OUT
BATT
ON
CC
V
BATT
BATTERY
0V
V
V
M
L
V
IN
Figure23. AddingHysteresistothePowerFailComparator
Figure 21. Increasing the Drive Current
Typical Operating Circuit
Using a Rechargeable Battery for Backup
A typical operating circuit is shown in Figure 24. The circuit
features power supply monitoring, battery backup switching
and watchdog timing.
If a capacitor or a rechargeable battery is used for backup, then
the charging resistor should be connected to VOUT since this
eliminates the discharge path that would exist during power
down if the resistor were connected to VCC.
CMOS RAM is powered from VOUT . When 5 V power is
present, this is routed to VOUT. If VCC fails, then VBATT is
routed to VOUT. VOUT can supply up to 250 mA from VCC, but
if more current is required, an external PNP transistor can be
added. When VCC is higher than VBATT and the reset threshold,
BATT ON goes low, providing base drive for the external tran-
sistor. When VCC is lower than VBATT and the reset threshold,
an internal 7 Ω. MOSFET connects the backup battery to
+5V
INPUT
POWER
V
– V
R
OUT
BATT
I =
0.1µF
R
0.1µF
V
V
OUT
CC
V
BATT
ADM69_A
ADM800_
RECHARGEABLE
BATTERY
VOUT
.
Reset Output
The internal voltage detector monitors VCC and generates a
RESET output to hold the microprocessor’s RESET line low
when VCC is below the reset threshold. An internal timer holds
RESET low for 200 ms after VCC rises above the threshold.
This prevents repeated toggling of RESET even if the 5 V
power drops out and recovers with each power line cycle.
Figure 22. Rechargeable Battery
Adding Hysteresis to the Power Fail Comparator
For increased noise immunity, hysteresis may be added to the
power fail comparator. Since the comparator circuit is noninverting,
hysteresis can be added simply by connecting a resistor between
the PFO output and the PFI input as shown in Figure 23. When
PFO is low, resistor R3 sinks current from the summing junction
at the PFI pin. When PFO is high, R3 sources current into the
PFI summing junction. This results in differing trip levels for the
comparator. Resistors R1 and R2 therefore set the trip point
while R3 adds hysteresis. R3 should be larger than 10 kΩ so that
it does not cause excessive loading on the PFO output. Addi-
tional noise rejection and filtering may be achieved by adding a
capacitor from PFI to GND.
Early Power Fail Detector
The input power line is monitored via a resistive potential di-
vider connected to the Power Fail Input (PFI). When the volt-
age at PFI falls below 1.25 V, the Power Fail Output (PFO)
drives the processor’s NMI input low. If a Power Fail threshold
of 7 V is set with resistors R1 and R2, the microprocessor will
have the time when VCC drops below 7 V to save data into
RAM. Power supply capacitance will extend the time available.
This will allow more time for microprocessor housekeeping
tasks to be completed before power is lost.
REV. 0
–10–
ADM691A/ADM693A/ADM800L/M
RESET also goes low if the Watchdog Timer is enabled and
WDI remains either high or low for longer than the watchdog
timeout period.
RAM Write Protection
The CEOUT line drives the Chip Select inputs of the CMOS
RAM. CEOUT follows CEIN as long as VCC is above the reset
threshold. If VCC falls below the reset threshold, CEOUT goes
high, independent of the logic level at CEIN. This prevents the
microprocessor from writing erroneous data into RAM during
power-up, power-down, brownouts and momentary power in-
terruptions. The LOW LINE output goes low when VCC falls
below the reset threshold.
The RESET output has an internal 1.6 mA pullup, and can ei-
ther connect to an open collector RESET bus or directly drive a
CMOS gate without an external pullup resistor.
INPUT POWER
+5V
0.1µF
0.1µF
Watchdog Timer
The microprocessor drives the WATCHDOG INPUT (WDI)
with an I/O line. When OSC IN and OSC SEL are uncon-
nected, the microprocessor must toggle the WDI pin once every
1.6 seconds to verify proper software execution. If a hardware or
software failure occurs such that WDI not toggled a 200 ms
RESET pulse will be generated after 1.6 seconds. This typi-
cally restarts the microprocessor’s power-up routine. A new
RESET pulse is issued every 1.6 seconds until WDI is again
strobed.
V
V
BATT
ON
OUT
CC
CMOS
RAM
3V
CE
V
OUT
BATT
BATTERY
ADM691A
ADM693A
ADM800L
ADM800M
ADDRESS
DECODE
R1
R2
CE
IN
PFI
GND
A0–A15
I/O LINE
WDI
PFO
NC
OSC IN
µP
NMI
OSC SEL
LOW LINE
RESET
RESET
WDO
0.1µF
RESET
The WATCHDOG OUTPUT (WDO) goes low if the watch-
dog timer is not serviced within its timeout period. Once WDO
goes low it remains low until a transition occurs at WDI. The
watchdog timer feature can be disabled by leaving WDI uncon-
nected. OSC IN and OSC SEL also allow other watchdog tim-
ing options.
SYSTEM STATUS
INDICATORS
Figure 24. Typical Application Circuit
REV. 0
–11–
ADM691A/ADM693A/ADM800L/M
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead TSSOP
(RU-16)
16-Lead Plastic DIP
(N-16)
0.201 (5.10)
0.193 (4.90)
0.840 (21.33)
0.745 (18.93)
16
9
16
1
9
8
0.280 (7.11)
0.240 (6.10)
0.325 (8.25)
0.195 (4.95)
0.115 (2.93)
0.300 (7.62)
PIN 1
0.060 (1.52)
0.015 (0.38)
1
8
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
PIN 1
0.015 (0.381)
0.008 (0.204)
0.006 (0.15)
0.002 (0.05)
0.070 (1.77) SEATING
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.0433
(1.10)
MAX
PLANE
0.045 (1.15)
0.028 (0.70)
0.020 (0.50)
8°
0°
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
16-Lead Wide SOIC
(R-16W)
16-Lead Narrow SOIC
(R-16N)
0.4133 (10.50)
0.3977 (10.00)
0.3937 (10.00)
0.3859 (9.80)
16
9
16
1
9
0.1574 (4.00)
0.1497 (5.80)
0.2550 (6.20)
8
0.2284 (5.80)
1
8
0.0688 (1.75)
0.0532 (1.35)
PIN 1
0.0196 (0.50)
x 45°
0.0098 (0.25)
0.0040 (0.10)
0.0099 (0.25)
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
PIN 1
x 45°
0.0118 (0.30)
0.0040 (0.10)
0.0098 (0.25)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
0.0138 (0.35)
–12–
REV. 0
相关型号：
ADM691AARWZ
Microprocessor Supervisor with Backup Battery Switchover, Adjustable Reset and Watchdog Periods, Chip Enable Signals, 4.65V Threshold Voltage, Watchdog, Battery Backup and Low VCC Status O/Ps and 250mA Output Current
ADI
ADM691AARWZ-REEL
Microprocessor Supervisor with Backup Battery Switchover, Adjustable Reset and Watchdog Periods, Chip Enable Signals, 4.65V Threshold Voltage, Watchdog, Battery Backup and Low VCC Status O/Ps and 250mA Output Current
ADI
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