ADM6711SAKS [ADI]
Microprocessor Supervisory Circuit in 4-Lead SC70; 微处理器监控电路采用4引脚SC70型号: | ADM6711SAKS |
厂家: | ADI |
描述: | Microprocessor Supervisory Circuit in 4-Lead SC70 |
文件: | 总8页 (文件大小:150K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Microprocessor Supervisory
Circuit in 4-Lead SC70
ADM6711/ADM6713
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Specified Over Temperature
Low Power Consumption (12 A)
Precision Monitoring of 2.5 V, 3 V, 3.3 V, and 5 V Power
Supply Voltages
Reset Timeout Period of 140 ms (Min)
Manual Reset Input
ADM6711
V
CC
RESET
GENERATOR
240 ms
RESET
V
REF
Output Stages
Push-Pull RESET Output (ADM6711)
Open-Drain RESET Output (ADM6713)
Reset Assertion Down to 1 V VCC
Power Supply Glitch Immunity
4-Lead SC70 Package
DEBOUNCE
MR
GND
ADM6713
APPLICATIONS
Microprocessor Systems
Computers
V
CC
RESET
GENERATOR
240 ms
RESET
V
REF
Controllers
Intelligent Instruments
Automotive Systems
Portable Instruments
DEBOUNCE
MR
GND
GENERAL DESCRIPTION
The parts are highly reliable with accurate voltage references
and immunity to fast, negative-going transients on VCC. Low
current consumption and space-efficient 4-lead SC70 packaging
make the ADM6711/ADM6713 ideal for use in low power
portable applications.
The ADM6711/ADM6713 are reset generator circuits suitable
for use in microprocessor based systems. They provide a reset
signal on power-up, power-down, and whenever the supply volt-
age falls below a preset threshold. In addition, both parts have a
debounced manual reset input so that a reset signal can also be
initiated with an external switch or logic signal.
V
CC
With six different reset threshold options available ranging from
2.32 V to 4.63 V, the ADM6711/ADM6713 are suitable for
monitoring 2.5 V, 3 V, 3.3 V, and 5 V supplies. A reset timeout
of at least 140 ms occurs when VCC rises above the threshold.
This gives the supply voltage time to stabilize before the micro-
processor starts up.
V
V
CC
CC
*R
PULL-UP
ADM6711/
ADM6713
P
SYSTEM
RESET
RESET
MR
GND
GND
The ADM6711 has a push-pull output, so no additional external
components are needed. The ADM6713’s open-drain output
requires an external pull-up resistor, which can be connected to a
voltage higher than VCC, if desired.
*ADM6713 ONLY
Figure 1. Typical Operating Circuit
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
(V = Full Operating Range; T = TMIN to TMAX; VCC Typ = 5 V
ADM6711/ADM6713–SPECIFICATIONS
CC
A
for L/M, 3.3 V for T/S, 3 V for R, and 2.5 V for Z models; unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SUPPLY
V
CC Operating Voltage Range
1.0
1.2
5.5
5.5
35
V
V
µA
TA = 0°C to 70°C
TA = –40°C to +125°C
VCC < 5.5 V, ADM671_L/M,
TA = –40°C to +85°C
Supply Current
16
12
30
60
60
µA
µA
µA
VCC < 3.6 V, ADM671_R/S/T/Z,
TA = –40°C to +85°C
VCC < 5.5 V, ADM671_L/M,
TA = 85°C to 125°C
VCC < 3.6 V, ADM671_R/S/T/Z,
TA = 85°C to 125°C
RESET VOLTAGE THRESHOLD
ADM671_L
4.56
4.50
4.44
4.31
4.25
4.20
3.04
3.00
2.95
2.89
2.85
2.81
2.59
2.55
2.52
2.28
2.25
2.22
4.63
4.38
3.08
2.93
2.63
2.32
4.70
4.75
4.82
4.45
4.50
4.56
3.11
3.15
3.21
2.96
3.00
3.05
2.66
2.70
2.74
2.35
2.38
2.42
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
TA = 25°C
TA = –40°C to +85°C
TA = 85°C to 125°C
TA = 25°C
ADM671_M
ADM671_T
ADM671_S
ADM671_R
ADM671_Z
TA = –40°C to +85°C
TA = 85°C to 125°C
TA = 25°C
TA = –40°C to +85°C
TA = 85°C to 125°C
TA = 25°C
TA = –40°C to +85°C
TA = 85°C to 125°C
TA = 25°C
TA = –40°C to +85°C
TA = 85°C to 125°C
TA = 25°C
TA = –40°C to +85°C
TA = 85°C to 125°C
RESET THRESHOLD TEMPERATURE
COEFFICIENT
30
ppm/°C
µs
VCC to RESET DELAY
20
VCC = VTH to (VTH – 100 mV)
RESET ACTIVE TIMEOUT PERIOD
140
100
240
460
640
ms
ms
TA = –40°C to +85°C
TA = 85°C to 125°C
RESET OUTPUT VOLTAGE
Low (ADM6711/ADM6713)
0.3
0.4
0.3
V
V
VCC = VTH min, ISINK = 1.2 mA,
ADM671_R/S/T/Z
VCC = VTH min, ISINK = 3.2 mA,
ADM671_L/M
VCC >1.0 V, ISINK = 50 µA
VCC > VTH max, ISOURCE = 500 µA,
ADM6711R/S/T/Z
V
V
High (ADM6711)
0.8 VCC
0.8 VCC
V
VCC > VTH max, ISOURCE = 800 µA,
ADM6711L/M
RESET OPEN-DRAIN OUTPUT
LEAKAGE CURRENT
1
µA
VCC > VTH, RESET deasserted
MANUAL RESET (MR)
Input Threshold
0.3 VCC
V
V
VIL
VIH
0.7 VCC
Pull-Up Resistance
Minimum Pulsewidth
Glitch Immunity
Reset Delay
10
1
20
kΩ
µs
ns
ns
100
200
Specifications subject to change without notice.
–2–
REV. 0
ADM6711/ADM6713
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C, unless otherwise noted.)
Table I. RESET Threshold Options
Model
RESET Threshold (V)
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
RESET (Push-Pull) . . . . . . . . . . . . . . –0.3 V to (VCC + 0.3 V)
RESET (Open-Drain) . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
MR . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (VCC + 0.3 V)
Input Current
ADM671_L
ADM671_M
ADM671_T
ADM671_S
ADM671_R
ADM671_Z
4.63
4.38
3.08
2.93
2.63
2.32
VCC, MR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Output Current
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Rate of Rise, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V/µs
JA Thermal Impedance, SC70 . . . . . . . . . . . . . . . . . 146°C/W
Operating Temperature Range . . . . . . . . . . –40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods of time may affect device reliability.
ORDERING GUIDE
RESET Threshold (V) Temperature Range
Model
Branding
Quantity (k)
ADM6711LAKS-REEL
ADM6711LAKS-REEL-7
ADM6711MAKS-REEL
ADM6711MAKS-REEL-7
ADM6711TAKS-REEL
ADM6711TAKS-REEL-7
ADM6711SAKS-REEL
ADM6711SAKS-REEL-7
ADM6711RAKS-REEL
ADM6711RAKS-REEL-7
ADM6711ZAKS-REEL
ADM6711ZAKS-REEL-7
ADM6713LAKS-REEL
ADM6713LAKS-REEL-7
ADM6713MAKS-REEL
ADM6713MAKS-REEL-7
ADM6713TAKS-REEL
ADM6713TAKS-REEL-7
ADM6713SAKS-REEL
ADM6713SAKS-REEL-7
ADM6713RAKS-REEL
ADM6713RAKS-REEL-7
ADM6713ZAKS-REEL
ADM6713ZAKS-REEL-7
4.63
4.63
4.38
4.38
3.08
3.08
2.93
2.93
2.63
2.63
2.32
2.32
4.63
4.63
4.38
4.38
3.08
3.08
2.93
2.93
2.63
2.63
2.32
2.32
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
M0B
M0B
M0C
M0C
M0D
M0D
M0E
M0E
M0F
M0F
M0G
M0G
M0H
M0H
M0J
10
3
10
3
10
3
10
3
10
3
10
3
10
3
10
3
10
3
10
3
10
3
10
3
M0J
M0K
M0K
M0L
M0L
M0M
M0M
M0N
M0N
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADM6711/ADM6713 feature proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. 0
–3–
ADM6711/ADM6713
PIN CONFIGURATION
4
1
V
CC
GND
ADM6711
ADM6713
TOP VIEW
(Not to Scale)
3
2
MR
RESET
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic
Function
Ground Reference for All Signals. 0 V.
1
2
GND
RESET
Active Low Logic Output.
RESET remains low while VCC is below the reset threshold and remains low for 240 ms (typ) after VCC rises
above the reset threshold.
3
4
MR
Manual Reset.
This active low debounced input will ignore input pulses of 100 ns (typ) and is guaranteed to accept input
pulses of greater than 1 µs. Leave floating when not used.
VCC
Supply Voltage Being Monitored.
–4–
REV. 0
Typical Performance Characteristics–ADM6711/ADM6713
12
289
284
I
@ V = 5.5V
CC
DD
ADM671_L/M
10
8
279
274
269
264
259
254
I
@ V = 3V
CC
DD
6
4
ADM671_R/S/T/Z
2
0
I
@ V = 1V
DD CC
249
244
–40 –20
0
20
30
50
70
85
100 120
–40 –20
0
20
30
50
70
85
100 120
TEMPERATURE (؇C)
TEMPERATURE (؇C)
TPC 1. Supply Current vs. Temperature
TPC 4. Power-Up Reset Timeout vs. Temperature
1000
1.007
1.006
1.005
1.004
1.003
1.002
1.001
1.000
0.999
0.998
0.997
0.996
0.995
900
800
700
600
500
400
300
200
V
= 20mV
OD
V
= 125mV
20
OD
100
0
V
= 200mV
OD
–40 –20
0
30
50
70
85
100 120
–40 –20
0
20
30
50
70
85
100 120
TEMPERATURE (؇C)
TEMPERATURE (؇C)
TPC 2. Power-Down RESET Delay vs. Temperature
TPC 5. RESET Threshold Deviation vs. Temperature
ADM671_R/S/T/Z
400
350
300
250
900
800
700
600
500
200
ADM671_L/M
V
= 20mV
400
300
200
100
0
OD
150
100
ADM671_R/S/T/Z
50
V
= 125mV
OD
V
= 200mV
OD
0
1
10
100
1000
–40 –20
0
20
30
50
70
85
100 120
RESET COMPARATOR OVERDRIVE,V –V (mV)
TH CC
TEMPERATURE (؇C)
TPC 6. Maximum Transient Duration without Causing a
RESET Pulse vs. RESET Comparator Overdrive
TPC 3. Power-Down RESET Delay vs. Temperature
ADM671_L/M
REV. 0
–5–
ADM6711/ADM6713
DETAILED DESCRIPTION
ADM6713 RESET OUTPUT LOGIC LEVELS
The ADM6711/ADM6713 are designed to protect the integrity
of a system’s operation by ensuring the proper operation of the
system during power-up, power-down, and brownout conditions.
The ADM6713’s open-drain RESET output is designed for use
with an external pull-up resistor. This resistor can be tied to VCC
or any other reasonable voltage level, offering the flexibility to use
the ADM6713 to drive a variety of different logic level circuitry.
When the ADM6711/ADM6713 are powered up, the RESET
output will remain low for a period equal to the typical reset
active timeout period. This is designed to give the system time
to power up correctly and for the power supply to stabilize
before any devices are brought out of reset and allowed to begin
executing instructions. Initializing a system in this way provides
a more reliable startup for microprocessor systems.
ENSURING A VALID RESET OUTPUT DOWN
TO VCC = 0 V
When VCC falls below 0.8 V, the ADM6711’s RESET output no
longer sinks current. Therefore, a high impedance CMOS logic
input connected to RESET may drift to undetermined logic
levels. To eliminate this problem, a pull-down resistor should be
connected from RESET to ground. A 100 kΩ resistor is large
enough not to load RESET and small enough to pull RESET
to ground.
MANUAL RESET INPUT
The ADM6711/ADM6713’s manual reset (MR) input allows
the system operator to reset a system by means of an external
manual switch. Alternatively, a logic signal from another digital
circuit can be used to trigger a reset via the MR input.
V
CC
The MR input will ignore negative-going pulses faster than
100 ns (typically) and is guaranteed to accept any negative-
going input pulse of a duration greater than or equal to 1 µs.
The RESET output will remain low while MR is held low and
for 240 ms (typically) after MR returns high.
V
CC
ADM6711
RESET
If MR is connected to long cables or is used in a noisy environ-
ment, then placing a 0.1 µF capacitor between the MR input
and ground will help to remove any fast, negative-going transients.
100k⍀
GND
POWER SUPPLY GLITCH IMMUNITY
The ADM6711/ADM6713 contain internal filtering circuitry
that provides immunity to fast transient glitches on the power
supply line. TPC 6 illustrates glitch immunity performance by
showing the maximum transient duration without causing a
reset pulse for glitches with amplitudes in the range of 1 mV to
1000 mV.
Figure 2. Ensuring a Valid RESET Output Down
to VCC = 0 V
Glitch immunity makes the ADM6711/ADM6713 suitable for
use in noisy environments. Mounting a 0.1 µF decoupling
capacitor as close as possible to the VCC pin improves glitch
immunity further.
–6–
REV. 0
ADM6711/ADM6713
OUTLINE DIMENSIONS
4-Lead Thin Shrink Small Outline Transistor Package [SC70]
(EIAJ SC82 body)
(KS-4)
Dimensions shown in millimeters
2.20
1.80
1.35
1.15
3
4
1
2.40
1.80
2
PIN 1
0.50 BSC
0.65 BSC
1.00
0.80
1.10
0.80
0.18
0.10
0.30
0.10
SEATING
PLANE
0.10 MAX
0.70
0.50
0.30
0.15
0.10 COPLANARITY
PACKAGE OUTLINE CORRESPONDS IN FULL TO EIAJ SC82
EXCEPT FOR WIDTH OF PIN-2 AS SHOWN
REV. 0
–7–
–8–
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