ADM1166ACPZ_技术文档

Super Sequencer with Margining Control

and Nonvolatile Fault Recording

ADM1166

FUNCTIONAL BLOCK DIAGRAM

FEATURES

AUX1 AUX2

REFIN

REFOUT REFGND SDA SCL A1

A0

Complete supervisory and sequencing solution for up to

10 supplies

16 event deep black box nonvolatile fault recording

10 supply fault detectors enable supervision of supplies to

<0.5% accuracy at all voltages at 25°C

ADM1166

SMBus

INTERFACE

VREF

12-BIT

SAR ADC

EEPROM

<1.0% accuracy across all voltages and temperatures

5 selectable input attenuators allow supervision of supplies to

14.4 V on VH

CLOSED-LOOP

FAULT RECORDING

MARGINING SYSTEM

VX1

VX2

VX3

VX4

VX5

PDO1

PDO2

PDO3

PDO4

PDO5

PDO6

CONFIGURABLE

OUTPUT

DRIVERS

DUAL-

FUNCTION

INPUTS

6 V on VP1 to VP4 (VPx)

(LOGIC INPUTS

OR

(HV CAPABLE OF

DRIVING GATES

OF N-FET)

5 dual-function inputs, VX1 to VX5 (VXx)

High impedance input to supply fault detector with

thresholds between 0.573 V and 1.375 V

General-purpose logic input

10 programmable driver outputs, PDO1 to PDO10 (PDOx)

Open-collector with external pull-up

SFDs)

SEQUENCING

ENGINE

VP1

VP2

VP3

VP4

VH

PDO7

PDO8

PDO9

CONFIGURABLE

OUTPUT

DRIVERS

PROGRAMMABLE

RESET

GENERATORS

(LV CAPABLE

OF DRIVING

LOGIC SIGNALS)

(SFDs)

PDO10

Push/pull output, driven to VDDCAP or VPx

Open collector with weak pull-up to VDDCAP or VPx

Internally charge-pumped high drive for use with external

N-FET (PDO1 to PDO6 only)

AGND

PDOGND

VDDCAP

VDD

ARBITRATOR

V_OUTV_OUTV_OUTV_OUTV_OUTV_OUT

DAC DAC DAC DAC DAC DAC

DAC1 DAC2 DAC3 DAC4 DAC5 DAC6

VCCP GND

Sequencing engine (SE) implements state machine control of

PDO outputs

Figure 1.

State changes conditional on input events

Enables complex control of boards

Power-up and power-down sequence control

Fault event handling

APPLICATIONS

Central office systems

Servers/routers

Multivoltage system line cards

DSP/FPGA supply sequencing

In-circuit testing of margined supplies

Interrupt generation on warnings

Watchdog function can be integrated in SE

Program software control of sequencing through SMBus

Complete voltage-margining solution for 6 voltage rails

6 voltage output 8-bit DACs (0.300 V to 1.551 V) allow voltage

adjustment via dc-to-dc converter trim/feedback node

12-bit ADC for readback of all supervised voltages

2 auxiliary (single-ended) ADC inputs

Reference input (REFIN) has 2 input options

Driven directly from 2.048 V ( 0.25%) REFOUT pin

More accurate external reference for improved ADC

performance

Device powered by the highest of VPx, VH for improved

redundancy

User EEPROM: 256 bytes

Industry-standard 2-wire bus interface (SMBus)

Guaranteed PDO low with VH, VPx = 1.2 V

Available in 40-lead, 6 mm × 6 mm LFCSP and

48-lead, 7 mm × 7 mm TQFP packages

GENERAL DESCRIPTION

The ADM1166 Super Sequencer® is a configurable supervisory/

sequencing device that offers a single-chip solution for supply

monitoring and sequencing in multiple-supply systems. In addition

to these functions, the ADM1166 integrates a 12-bit ADC and

six 8-bit voltage output DACs. These circuits can be used to

implement a closed-loop margining system that enables supply

adjustment by altering either the feedback node or reference of

a dc-to-dc converter using the DAC outputs.

Supply margining can be performed with a minimum of external

components. The margining loop can be used for in-circuit testing

of a board during production (for example, to verify board func-

tionality at −5% of nominal supplies), or it can be used dynamically

to accurately control the output voltage of a dc-to-dc converter.

For more information about the ADM1166 register map,

refer to the AN-698 Application Note

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADM1166

TABLE OF CONTENTS

Features .............................................................................................. 1

Sequencing Engine Application Example............................... 18

Fault and Status Reporting........................................................ 19

Nonvolatile Black Box Fault Recording................................... 20

Black Box Writes with No External Supply ............................ 20

Voltage Readback............................................................................ 21

Supply Supervision with the ADC........................................... 21

Supply Margining ........................................................................... 22

Overview ..................................................................................... 22

Open-Loop Supply Margining ................................................. 22

Closed-Loop Supply Margining............................................... 22

Writing to the DACs .................................................................. 23

Choosing the Size of the Attenuation Resistor....................... 23

DAC Limiting and Other Safety Features ............................... 23

Applications Diagram.................................................................... 24

Communicating with the ADM1166........................................... 25

Configuration Download at Power-Up................................... 25

Updating the Configuration ..................................................... 25

Updating the Sequencing Engine............................................. 26

Internal Registers........................................................................ 26

EEPROM ..................................................................................... 26

Serial Bus Interface..................................................................... 26

SMBus Protocols for RAM and EEPROM.............................. 28

Write Operations........................................................................ 29

Read Operations......................................................................... 30

Outline Dimensions....................................................................... 32

Ordering Guide .......................................................................... 32

Functional Block Diagram .............................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Detailed Block Diagram .................................................................. 3

Specifications..................................................................................... 4

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Pin Configurations and Function Descriptions ........................... 8

Typical Performance Characteristics ........................................... 10

Powering the ADM1166................................................................ 13

Inputs................................................................................................ 14

Supply Supervision..................................................................... 14

Programming the Supply Fault Detectors............................... 14

Input Comparator Hysteresis.................................................... 14

Input Glitch Filtering ................................................................. 15

Supply Supervision with VXx Inputs....................................... 15

VXx Pins as Digital Inputs ........................................................ 15

Outputs ............................................................................................ 16

Supply Sequencing Through Configurable Output Drivers. 16

Default Output Configuration.................................................. 16

Sequencing Engine ......................................................................... 17

Overview...................................................................................... 17

Warnings...................................................................................... 17

SMBus Jump (Unconditional Jump)........................................ 17

REVISION HISTORY

12/10—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

ADM1166

The device also provides up to 10 programmable inputs for

monitoring undervoltage faults, overvoltage faults, or out-of-

window faults on up to 10 supplies. In addition, 10 programmable

outputs can be used as logic enables. Six of these programmable

outputs can also provide up to a 12 V output for driving the gate

of an N-FET that can be placed in the path of a supply.

A block of nonvolatile EEPROM is available that can be used to

store user-defined information and may also be used to hold a

number of fault records that are written by the sequencing engine

defined by the user when a particular fault or sequence occurs.

The device is controlled via configuration data that can be

programmed into an EEPROM. The entire configuration can

be programmed using an intuitive GUI-based software package

provided by Analog Devices, Inc.

The logical core of the device is a sequencing engine. This state-

machine-based construction provides up to 63 different states.

This design enables very flexible sequencing of the outputs, based

on the condition of the inputs.

DETAILED BLOCK DIAGRAM

REFIN REFOUT

AUX2 AUX1

REFGND SDA SCL A1

SMBus

VREF

A0

ADM1166

INTERFACE

OSC

DEVICE

12-BIT

SAR ADC

CONTROLLER

EEPROM

FAULT RECORDING

GPI SIGNAL

CONDITIONING

CONFIGURABLE

OUTPUT DRIVER

(HV)

PDO1

VX1

SFD

PDO2

PDO3

PDO4

PDO5

VX2

VX3

VX4

GPI SIGNAL

CONDITIONING

CONFIGURABLE

OUTPUT DRIVER

(HV)

PDO6

SEQUENCING

ENGINE

VX5

VP1

SFD

CONFIGURABLE

OUTPUT DRIVER

(LV)

SELECTABLE

ATTENUATOR

PDO7

VP2

VP3

VP4

PDO8

PDO9

CONFIGURABLE

OUTPUT DRIVER

(LV)

SELECTABLE

ATTENUATOR

VH

SFD

PDO10

AGND

PDOGND

REG 5.25V

CHARGE PUMP

V

OUT

DAC

OUT

DAC

VDDCAP

VDD

ARBITRATOR

GND

VCCP

DAC1 DAC2 DAC3 DAC4 DAC5 DAC6

Figure 2. Detailed Block Diagram

Rev. 0 | Page 3 of 32

ADM1166

SPECIFICATIONS

VH = 3.0 V to 14.4 V¹, VPx = 3.0 V to 6.0 V¹, T_A= −40°C to +85°C, unless otherwise noted.

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

POWER SUPPLY ARBITRATION

VH, VPx

VPx

VH

VDDCAP

3.0

V

Minimum supply required on one of VPx, VH

Maximum VDDCAP = 5.1 V, typical

VDDCAP = 4.75 V

Regulated LDO output

Minimum recommended decoupling capacitance

6.0

14.4

5.4

2.7

10

4.75

C_VDDCAP

μF

POWER SUPPLY

Supply Current, I_VH, I_VPx

Additional Currents

All PDOx FET Drivers On

4.2

1

6

2

mA

VDDCAP = 4.75 V, PDO1 to PDO10 off, DACs off, ADC off

mA

VDDCAP = 4.75 V, PDO1 to PDO6 loaded with 1 μA each,

PDO7 to PDO10 off

Maximum additional load that can be drawn from all PDO

pull-ups to VDDCAP

Current Available from

VDDCAP

DAC Supply Currents

ADC Supply Current

EEPROM Erase Current

SUPPLY FAULT DETECTORS

VH Pin

2.2

1

10

mA

Six DACs on with 100 μA maximum load on each

Running round-robin loop

1 ms duration only, VDDCAP = 3 V

Input Impedance

Input Attenuator Error

Detection Ranges

High Range

52

0.05

kΩ

%

Midrange and high range

6

2.5

14.4

6

V

Midrange

VPx Pins

Input Impedance

Input Attenuator Error

Detection Ranges

Midrange

Low Range

Ultralow Range

VXx Pins

Input Impedance

Detection Range

Ultralow Range

Absolute Accuracy

52

0.05

kΩ

%

Low range and midrange

No input attenuation error

2.5

1.25

0.573

6

3

V

1.375

1

MΩ

0.573

1.375

1

V

%

VREF error + DAC nonlinearity + comparator offset error +

input attenuation error

Threshold Resolution

Digital Glitch Filter

8

0

100

Bits

μs

Minimum programmable filter length

Maximum programmable filter length

Rev. 0 | Page 4 of 32

ADM1166

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

ANALOG-TO-DIGITAL CONVERTER

Signal Range

0

V_REFIN

V

The ADC can convert signals presented to the VH, VPx,

and VXx pins; VPx and VH input signals are attenuated

depending on the selected range; a signal at the pin

corresponding to the selected range is from 0.573 V to

1.375 V at the ADC input

Input Reference Voltage on

REFIN Pin, V_REFIN

Resolution

INL

Gain Error

Conversion Time

2.048

12

V

Bits

LSB

%

ms

LSB

2.5

0.05

Endpoint corrected, V_REFIN= 2.048 V

V_REFIN= 2.048 V

One conversion on one channel

All 12 channels selected, 16× averaging enabled

V_REFIN= 2.048 V

0.44

84

Offset Error

2

Input Noise

0.25

8

LSB rms Direct input (no attenuator)

MΩ

AUX1, AUX2 Input Impedance

BUFFERED VOLTAGE OUTPUT DACs

Resolution

1

Bits

Code 0x7F Output Voltage

Six DACs are individually selectable for centering on

one of four output voltage ranges

Range 1

Range 2

Range 3

Range 4

Output Voltage Range

LSB Step Size

0.592

0.796

0.996

1.246

0.6

0.8

1

1.25

601.25

2.36

0.603

0.803

1.003

1.253

V

mV

Same range, independent of center point

Endpoint corrected

INL

0.75 LSB

DNL

Gain Error

0.4

LSB

%

1

Maximum Load Current (Source)

Maximum Load Current (Sink)

Maximum Load Capacitance

Settling Time to 50 pF Load

Load Regulation

PSRR

100

μA

pF

μs

mV

dB

50

2

2.5

60

40

Per mA

DC

100 mV step in 20 ns with 50 pF load

REFERENCE OUTPUT

Reference Output Voltage

Load Regulation

2.043

1

2.048

−0.25

0.25

2.053

V

No load

mV

μF

dB

Sourcing current, I_DACxMAX= −100 μA

Sinking current, I_DACxMAX= 100 μA

Capacitor required for decoupling, stability

DC

Minimum Load Capacitance

PSRR

60

PROGRAMMABLE DRIVER OUTPUTS

High Voltage (Charge-Pump) Mode

(PDO1 to PDO6)

Output Impedance

500

12.5

12

kΩ

V

V_OH

11

10.5

8

14

13.5

I_OH= 0 μA

I_OH= 1 μA

I_OH= 7 μA

2

V_OH

10

V

I_OUTAVG

20

μA

2 V < V_OH< 7 V

Rev. 0 | Page 5 of 32

ADM1166

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Standard (Digital Output) Mode

(PDO1 to PDO10)

V_OH

2.4

V

mA

kΩ

mA

V_PU(pull-up to VDDCAP or VPx) = 2.7 V, I_OH= 0.5 mA

V_PUto VPx = 6.0 V, I_OH= 0 mA

V_PU≤ 2.7 V, I_OH= 0.5 mA

4.5

V_PU− 0.3

0

V_OL

0.50

20

60

29

2

I_OL= 20 mA

2

I_OL

Maximum sink current per PDOx pin

Maximum total sink for all PDOx pins

Internal pull-up

Current load on any VPx pull-ups, that is, total source

current available through any number of PDO pull-up

switches configured onto any one VPx pin

2

I_SINK

R_PULL-UP

I_SOURCE(VPx)²

16

20

Three-State Output Leakage

Current

10

μA

V_PDO= 14.4 V

Oscillator Frequency

DIGITAL INPUTS (VXx, A0, A1)

Input High Voltage, V_IH

Input Low Voltage, V_IL

Input High Current, I_IH

Input Low Current, I_IL

Input Capacitance

90

2.0

−1

100

110

kHz

All on-chip time delays derived from this clock

V

μA

pF

μA

Maximum V_IN= 5.5 V

V_IN= 5.5 V

0.8

1

V_IN= 0 V

5

20

Programmable Pull-Down Current,

I_PULL-DOWN

VDDCAP = 4.75V, T_A= 25°C, if known logic state is required

SERIAL BUS DIGITAL INPUTS (SDA, SCL)

Input High Voltage, V_IH

2.0

V

Input Low Voltage, V_IL

0.8

0.4

2

Output Low Voltage, V_OL

I_OUT= −3.0 mA

SERIAL BUS TIMING³

Clock Frequency, f_SCLK

Bus Free Time, t_BUF

Start Setup Time, t_SU;STA

Stop Setup Time, t_SU;STO

Start Hold Time, t_HD;STA

SCL Low Time, t_LOW

SCL High Time, t_HIGH

SCL, SDA Rise Time, t_R

SCL, SDA Fall Time, t_F

Data Setup Time, t_SU;DAT

Data Hold Time, t_HD;DAT

Input Low Current, I_IL

SEQUENCING ENGINE TIMING

State Change Time

400

kHz

μs

ns

μA

1.3

0.6

1.3

0.6

300

100

250

1

V_IN= 0 V

10

μs

¹At least one of the VH and VPx pins must be ≥ 3.0 V to maintain the device supply on VDDCAP.

²Specification is not production tested but is supported by characterization data at initial product release.

³Guaranteed by design.

Rev. 0 | Page 6 of 32

ADM1166

ABSOLUTE MAXIMUM RATINGS

Table 2.

THERMAL RESISTANCE

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Parameter

Rating

Voltage on VH Pin

16 V

Voltage on VPx Pins

Voltage on VXx Pins

Voltage on AUX1, AUX2 Pins

Voltage on A0, A1 Pins

Voltage on REFIN, REFOUT Pins

Voltage on VDDCAP, VCCP Pins

Voltage on DACx Pins

Voltage on PDOx Pins

Voltage on SDA, SCL Pins

7 V

Table 3. Thermal Resistance

−0.3 V to +6.5 V

−0.3 V to +5 V

−0.3 V to +7 V

5 V

6.5 V

Package Type

40-Lead LFCSP

48-Lead TQFP

θ_JA

26.5

50

Unit

°C/W

ESD CAUTION

16 V

7 V

Voltage on GND, AGND, PDOGND, REFGND Pins −0.3 V to +0.3 V

Input Current at Any Pin

Package Input Current

5 mA

20 mA

Maximum Junction Temperature (T_Jmax)

Storage Temperature Range

Lead Temperature

150°C

−65°C to +150°C

Soldering Vapor Phase, 60 sec

ESD Rating, All Pins

215°C

2000 V

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. 0 | Page 7 of 32

ADM1166

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

48 47 46 45 44 43 42 41 40 39 38 37

NC

VX1

VX2

VX3

VX4

VX5

VP1

VP2

VP3

1

2

3

4

5

6

7

8

9

36 NC

PIN 1

INDICATOR

VX1

VX2

VX3

VX4

VX5

VP1

VP2

VP3

VP4

1

2

3

4

5

6

7

8

9

30 PDO1

29 PDO2

28 PDO3

27 PDO4

35 PDO1

34 PDO2

33 PDO3

32 PDO4

31 PDO5

30 PDO6

29 PDO7

28 PDO8

27 PDO9

26 PDO10

25 NC

ADM1166

26

25

24

PDO5

PDO6

PDO7

TOP VIEW

(Not to Scale)

ADM1166

23 PDO8

22 PDO9

21 PDO10

TOP VIEW

VH 10

(Not to Scale)

VP4 10

VH 11

NC 12

NOTE

13 14 15 16 17 18 19 20 21 22 23 24

1. EXPOSED PAD SHOULD BE SOLDERED

TO THE BOARD FOR IMPROVED

MECHANICAL STABILITY.

NC = NO CONNECT

Figure 4. 48-Lead TQFP Pin Configuration

Figure 3. 40-Lead LFCSP Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

40-Lead 48-Lead

LFCSP

TQFP

Mnemonic

Description

1, 12, 13, 24,

25, 36, 37, 48

NC

No Connect.

1 to 5

6 to 9

2 to 6

VX1 to VX5 (VXx) High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to

1.375 V. Alternatively, these pins can be used as general-purpose digital inputs.

VP1 to VP4 (VPx) Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the

input attenuation on a potential divider connected to these pins, the output of which

connects to a supply fault detector. These pins allow thresholds from 2.5 V to 6.0 V, from

1.25 V to 3.00 V, and from 0.573 V to 1.375 V.

7 to 10

10

11

VH

High Voltage Input to Supply Fault Detectors. Two input ranges can be set by altering the

input attenuation on a potential divider connected to this pin, the output of which connects

to a supply fault detector. This pin allows thresholds from 6.0 V to 14.4 V and from 2.5 V to 6.0 V.

11

12

13

14

15

16

AGND¹

REFGND¹

REFIN

Ground Return for Input Attenuators.

Ground Return for On-Chip Reference Circuits.

Reference Input for ADC. Nominally, 2.048 V. This pin must be driven by a reference voltage.

The on-board reference can be used by connecting the REFOUT pin to the REFIN pin.

14

17

REFOUT

Reference Output, 2.048 V. Typically connected to REFIN. Note that the capacitor must be

connected between this pin and REFGND. A 10 μF capacitor is recommended for this purpose.

15 to 20 18 to 23

21 to 30 26 to 35

DAC1 to DAC6

PDO10 to PDO1 Programmable Driver Outputs.

PDOGND¹

Voltage Output DACs. These pins default to high impedance at power-up.

31

32

38

39

Ground Return for Driver Outputs.

Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between

this pin and GND. A 10 μF capacitor is recommended for this purpose.

VCCP

33

34

35

36

40

41

42

43

A0

A1

SCL

SDA

Logic Input. This pin sets the seventh bit of the SMBus interface address.

Logic Input. This pin sets the sixth bit of the SMBus interface address.

SMBus Clock Pin. Bidirectional, open-drain pin that requires external resistive pull-up.

SMBus Data Pin. Bidirectional, open-drain pin that requires external resistive pull-up.

Auxiliary, Single-Ended ADC Inputs.

37, 38

44, 45

AUX2, AUX1

Rev. 0 | Page 8 of 32

ADM1166

Pin No.

40-Lead 48-Lead

LFCSP

TQFP

Mnemonic

Description

39

46

VDDCAP

Device Supply Voltage. Linearly regulated from the highest of the VPx and VH pins to a

typical of 4.75 V. Note that the capacitor must be connected between this pin and GND.

A 10 μF capacitor is recommended for this purpose.

40

47

GND¹

Supply Ground.

Not applicable EPAD

Exposed Pad. This pad is a no connect (NC). If possible, this pad should be soldered to the

board for improved mechanical stability.

¹In a typical application, all ground pins are connected together.

Rev. 0 | Page 9 of 32

ADM1166

TYPICAL PERFORMANCE CHARACTERISTICS

6

180

160

140

120

100

80

5

4

3

2

1

0

60

40

20

0

1

2

3

4

5

6

0

1

2

3

4

5

6

V

(V)

V

(V)

VP1

Figure 8. I_VP1vs. V_VP1(VP1 Not as Supply)

Figure 5. V_VDDCAPvs. V_VP1

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

6

5

4

3

2

1

0

2

4

6

8

10

12

14

16

0

2

4

6

8

10

12

14

16

V

(V)

V

(V)

VH

Figure 9. I_VHvs. V_VH(VH as Supply)

Figure 6. V_VDDCAPvs. V_VH

350

300

250

200

150

100

50

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

1

2

3

4

5

6

0

1

2

3

4

5

6

V

(V)

V

(V)

VH

VP1

Figure 10. I_VHvs. V_VH(VH Not as Supply)

Figure 7. I_VP1vs. V_VP1(VP1 as Supply)

Rev. 0 | Page 10 of 32

ADM1166

14

12

10

8

1.0

0.8

0.6

0.4

0.2

0

6

–0.2

–0.4

–0.6

–0.8

–1.0

4

2

0

2.5

5.0

7.5

(µA)

10.0

12.5

15.0

0

1000

2000

3000

4000

I

CODE

LOAD

Figure 11. Charge-Pumped V_PDO1(FET Drive Mode) vs. I_LOAD

Figure 14. DNL for ADC

5.0

1.0

0.8

0.6

0.4

0.2

0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

VP1 = 5V

VP1 = 3V

–0.2

–0.4

–0.6

–0.8

–1.0

0

1

2

3

4

5

6

0

1000

2000

3000

4000

I

(mA)

CODE

LOAD

Figure 15. INL for ADC

Figure 12. V_PDO1(Strong Pull-Up to VPx) vs. I_LOAD

12000

10000

8000

6000

4000

2000

0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

9894

VP1 = 5V

VP1 = 3V

25

81

2047

2048

2049

0

10

20

30

(µA)

40

50

60

CODE

I

LOAD

Figure 16. ADC Noise, Midcode Input, 10,000 Reads

Figure 13. V_PDO1(Weak Pull-Up to VPx) vs. I_LOAD

Rev. 0 | Page 11 of 32

ADM1166

1.005

1.004

1.003

1.002

1.001

1.000

0.999

0.998

0.997

0.996

0.995

VP1 = 3.0V

DAC

BUFFER

OUTPUT

20kΩ

47pF

PROBE

POINT

VP1 = 4.75V

1

CH1 200mV

M1.00µs

CH1

756mV

–40

–20

0

20

40

60

80

100

TEMPERATURE (°C)

Figure 17. Transient Response of DAC Code Change into Typical Load

Figure 19. DAC Output vs. Temperature

2.058

2.053

2.048

2.043

2.038

VP1 = 3.0V

DAC

BUFFER

OUTPUT

100kΩ

1V

VP1 = 4.75V

PROBE

POINT

1

CH1 200mV

M1.00µs

CH1

944mV

–40

–20

0

20

40

60

80

100

TEMPERATURE (°C)

Figure 18. Transient Response of DAC to Turn-On from High-Z State

Figure 20. REFOUT vs. Temperature

Rev. 0 | Page 12 of 32

ADM1166

POWERING THE ADM1166

The ADM1166 is powered from the highest voltage input on

either the positive-only supply inputs (VPx) or the high voltage

supply input (VH). This technique offers improved redundancy

because the device is not dependent on any particular voltage rail

to keep it operational. The same pins are used for supply fault

detection (see the Supply Supervision section). A V_DDarbitrator

on the device chooses which supply to use. The arbitrator can

be considered an OR’ing of five low dropout regulators (LDOs)

together. A supply comparator chooses the highest input to provide

the on-chip supply. There is minimal switching loss with this

architecture (~0.2 V), resulting in the ability to power the ADM1166

from a supply as low as 3.0 V. Note that the supply on the VXx

pins cannot be used to power the device.

In cases where this 12 V supply is hot swapped, it is recommended

that the ADM1166 not be connected directly to the supply. Suitable

precautions, such as the use of a hot swap controller or RC filter

network, should be taken to protect the device from transients

that could cause damage during hot swap events.

When two or more supplies are within 100 mV of each other,

the supply that first takes control of V_DDkeeps control. For

example, if VP1 is connected to a 3.3 V supply, V_DDpowers up

to approximately 3.1 V through VP1. If VP2 is then connected to

another 3.3 V supply, VP1 still powers the device, unless VP2

goes 100 mV higher than VP1.

VDDCAP

VP1

VP2

VP3

VP4

VH

IN

OUT

4.75V

LDO

An external capacitor to GND is required to decouple the on-chip

supply from noise. This capacitor should be connected to the

VDDCAP pin, as shown in Figure 21. The capacitor has another

use during brownouts (momentary loss of power). Under these

conditions, when the input supply (VPx or VH) dips transiently

below V_DD, the synchronous rectifier switch immediately turns

off so that it does not pull V_DDdown. The V_DDcapacitor can

then act as a reservoir to keep the device active until the next

highest supply takes over the powering of the device. A 10 μF

capacitor is recommended for this reservoir/decoupling function.

EN

IN

4.75V

LDO

EN

IN

4.75V

LDO

EN

IN

4.75V

LDO

EN

IN

INTERNAL

DEVICE

SUPPLY

4.75V

LDO

The value of the VDDCAP capacitor may be increased if it is

necessary to guarantee a complete fault record is written into

EEPROM should all supplies fail. The value of capacitor to use

is discussed in the Black Box Writes with No External Supply

section.

EN

SUPPLY

COMPARATOR

The VH input pin can accommodate supplies up to 14.4 V, which

allows the ADM1166 to be powered using a 12 V backplane supply.

Figure 21. V_DDArbitrator Operation

Rev. 0 | Page 13 of 32

ADM1166

INPUTS

SUPPLY SUPERVISION

The threshold value required is given by

The ADM1166 has 10 programmable inputs. Five of these are

dedicated supply fault detectors (SFDs). These dedicated inputs

are called VH and VPx (VP1 to VP4) by default. The other five

inputs are labeled VXx (VX1 to VX5) and have dual functionality.

They can be used either as SFDs, with functionality similar to that

of VH and VPx, or as CMOS-/TTL-compatible logic inputs to

the device. Therefore, the ADM1166 can have up to 10 analog

inputs, a minimum of five analog inputs and five digital inputs,

or a combination thereof. If an input is used as an analog input,

it cannot be used as a digital input. Therefore, a configuration

requiring 10 analog inputs has no available digital inputs. Table 6

shows the details of each input.

V_T= (V_R× N)/255 + V_B

where:

V_Tis the desired threshold voltage (undervoltage or overvoltage).

V_Ris the voltage range.

N is the decimal value of the 8-bit code.

V_Bis the bottom of the range.

Reversing the equation, the code for a desired threshold is given by

N = 255 × (V_T− V_B)/V_R

For example, if the user wants to set a 5 V overvoltage threshold

on VP1, the code to be programmed in the PS1OVTH register

(as discussed in the AN-698 Application Note) is given by

PROGRAMMING THE SUPPLY FAULT DETECTORS

N = 255 × (5 − 2.5)/3.5

The ADM1166 can have up to 10 SFDs on its 10 input channels.

These highly programmable reset generators enable the supervision

of up to 10 supply voltages. The supplies can be as low as 0.573 V

and as high as 14.4 V. The inputs can be configured to detect an

undervoltage fault (the input voltage drops below a prepro-

grammed value), an overvoltage fault (the input voltage rises

above a preprogrammed value), or an out-of-window fault (the

input voltage is outside a preprogrammed range). The thresholds

can be programmed to an 8-bit resolution in registers provided in

the ADM1166. This translates to a voltage resolution that is

dependent on the range selected.

Therefore, N = 182 (1011 0110 or 0xB6).

INPUT COMPARATOR HYSTERESIS

The UV and OV comparators shown in Figure 22 are always

looking at VPx. To avoid chatter (multiple transitions when the

input is very close to the set threshold level), these comparators

have digitally programmable hysteresis. The hysteresis can be

programmed up to the values shown in Table 6.

RANGE

SELECT

ULTRA

LOW

OV

COMPARATOR

+

–

VPx

GLITCH

FILTER

FAULT

OUTPUT

The resolution is given by

VREF

Step Size = Threshold Range/255

+

–

LOW

MID

Therefore, if the high range is selected on VH, the step size can

be calculated as

UV

FAULT TYPE

SELECT

COMPARATOR

(14.4 V − 6.0 V)/255 = 32.9 mV

Figure 22. Supply Fault Detector Block

Table 5 lists the upper and lower limits of each available range,

the bottom of each range (V_B), and the range itself (V_R).

The hysteresis is added after a supply voltage goes out of

tolerance. Therefore, the user can program the amount above

the undervoltage threshold to which the input must rise before

an undervoltage fault is deasserted. Similarly, the user can program

the amount below the overvoltage threshold to which an input

must fall before an overvoltage fault is deasserted.

Table 5. Voltage Range Limits

Voltage Range (V)

0.573 to 1.375

1.25 to 3.00

V_B(V)

0.573

1.25

2.5

V_R(V)

0.802

1.75

3.5

2.5 to 6.0

6.0 to 14.4

6.0

8.4

Table 6. Input Functions, Thresholds, and Ranges

Input Function Voltage Range (V)

Maximum Hysteresis

425 mV

Voltage Resolution (mV)

Glitch Filter (μs)

0 to 100

VH

High voltage analog input

2.5 to 6.0

13.7

6.0 to 14.4

0.573 to 1.375

1.25 to 3.00

2.5 to 6.0

1.02 V

32.9

0 to 100

VPx

Positive analog input

97.5 mV

212 mV

425 mV

3.14

6.8

13.7

0 to 100

VXx

High-Z analog input

Digital input

0.573 to 1.375

0 to 5.0

97.5 mV

Not applicable

3.14

Not applicable

0 to 100

Rev. 0 | Page 14 of 32

ADM1166

An additional supply supervision function is available when the

VXx pins are selected as digital inputs. In this case, the analog

function is available as a second detector on each of the dedicated

analog inputs, VPx and VH. The analog function of VX1 is

mapped to VP1, VX2 is mapped to VP2, and so on. VX5 is

mapped to VH. In this case, these SFDs can be viewed as

secondary or warning SFDs.

The hysteresis value is given by

V

_HYST= V_R× N_THRESH/255

where:

V

N

_HYSTis the desired hysteresis voltage.

_THRESHis the decimal value of the 5-bit hysteresis code.

Note that N_THRESHhas a maximum value of 31. The maximum

hysteresis for the ranges is listed in Table 6.

The secondary SFDs are fixed to the same input range as the

primary SFDs. They are used to indicate warning levels rather

than failure levels. This allows faults and warnings to be generated

on a single supply using only one pin. For example, if VP1 is set

to output a fault when a 3.3 V supply drops to 3.0 V, VX1 can be

set to output a warning at 3.1 V. Warning outputs are available for

readback from the status registers. They are also OR’ed together

and fed into the SE, allowing warnings to generate interrupts on

the PDOs. Therefore, in this example, if the supply drops to 3.1 V,

a warning is generated, and remedial action can be taken before

the supply drops out of tolerance.

INPUT GLITCH FILTERING

The final stage of the SFDs is a glitch filter. This block provides

time-domain filtering on the output of the SFD comparators,

which allows the user to remove any spurious transitions such

as supply bounce at turn-on. The glitch filter function is in addition

to the digitally programmable hysteresis of the SFD comparators.

The glitch filter timeout is programmable up to 100 μs.

For example, when the glitch filter timeout is 100 μs, any pulse

appearing on the input of the glitch filter block that is less than

100 μs in duration is prevented from appearing on the output of

the glitch filter block. Any input pulse that is longer than 100 μs

appears on the output of the glitch filter block. The output is

delayed with respect to the input by 100 μs. The filtering process is

shown in Figure 23.

VXx PINS AS DIGITAL INPUTS

As discussed in the Supply Supervision with VXX Inputs section,

the VXx input pins on the ADM1166 have dual functionality.

The second function is as a digital logic input to the device.

Therefore, the ADM1166 can be configured for up to five digital

inputs. These inputs are TTL-/CMOS-compatible inputs. Standard

logic signals can be applied to the pins: RESET from reset generators,

PWRGD signals, fault flags, and manual resets. These signals are

available as inputs to the SE and, therefore, can be used to control

the status of the PDOs. The inputs can be configured to detect

either a change in level or an edge.

INPUT PULSE SHORTER

THAN GLITCH FILTER TIMEOUT

INPUT PULSE LONGER

THAN GLITCH FILTER TIMEOUT

PROGRAMMED

TIMEOUT

PROGRAMMED

TIMEOUT

INPUT

When configured for level detection, the output of the digital

block is a buffered version of the input. When configured for edge

detection, a pulse of programmable width is output from the

digital block once the logic transition is detected. The width is

programmable from 0 μs to 100 μs. The digital blocks feature the

same glitch filter function that is available on the SFDs. This

enables the user to ignore spurious transitions on the inputs. For

example, the filter can be used to debounce a manual reset switch.

t₀

t_GF

t₀

t_GF

OUTPUT

t₀

t_GF

t₀

t_GF

When configured as digital inputs, each VXx pin has a weak

(10 μA) pull-down current source available for placing the input

into a known condition, even if left floating. The current source,

if selected, weakly pulls the input to GND.

Figure 23. Input Glitch Filter Function

SUPPLY SUPERVISION WITH VXx INPUTS

The VXx inputs have two functions. They can be used as either

supply fault detectors or digital logic inputs. When selected as

analog (SFD) inputs, the VXx pins have functionality that is very

similar to the VH and VPx pins. The primary difference is that the

VXx pins have only one input range: 0.573 V to 1.375 V. Therefore,

these inputs can directly supervise only the very low supplies.

However, the input impedance of the VXx pins is high, allowing

an external resistor divide network to be connected to the pin.

Thus, potentially any supply can be divided down into the input

range of the VXx pin and supervised. This enables the ADM1166

to monitor other supplies, such as +24 V, +48 V, and −5 V.

VXx

+

(DIGITAL INPUT)

TO

GLITCH

FILTER

SEQUENCING

ENGINE

DETECTOR

–

VREF = 1.4V

Figure 24. VXx Digital Input Function

Rev. 0 | Page 15 of 32

ADM1166

OUTPUTS

The data driving each of the PDOs can come from one of three

sources. The source can be enabled in the PDOxCFG configu-

ration register (see the AN-698 Application Note for details).

SUPPLY SEQUENCING THROUGH CONFIGURABLE

OUTPUT DRIVERS

Supply sequencing is achieved with the ADM1166 using the

programmable driver outputs (PDOs) on the device as control

signals for supplies. The output drivers can be used as logic

enables or as FET drivers.

The data sources are as follows:

•

Output from the SE.

Directly from the SMBus. A PDO can be configured so that

the SMBus has direct control over it. This enables software

control of the PDOs. Therefore, a microcontroller can be

used to initiate a software power-up/power-down sequence.

The sequence in which the PDOs are asserted (and, therefore,

the supplies are turned on) is controlled by the sequencing engine

(SE). The SE determines what action is taken with the PDOs,

based on the condition of the ADM1166 inputs. Therefore, the

PDOs can be set up to assert when the SFDs are in tolerance, the

correct input signals are received on the VXx digital pins, and

no warnings are received from any of the inputs of the device.

The PDOs can be used for a variety of functions. The primary

function is to provide enable signals for LDOs or dc-to-dc

converters that generate supplies locally on a board. The PDOs

can also be used to provide a PWRGD signal, when all the SFDs

are in tolerance, or a RESET output if one of the SFDs goes out

of specification (this can be used as a status signal for a DSP,

FPGA, or other microcontroller).

•

On-chip clock. A 100 kHz clock is generated on the device.

This clock can be made available on any of the PDOs. It

can be used, for example, to clock an external device such

as an LED.

DEFAULT OUTPUT CONFIGURATION

All of the internal registers in an unprogrammed ADM1166

device from the factory are set to 0. Because of this, the PDOx pins

are pulled to GND by a weak (20 kΩ), on-chip pull-down resistor.

As the input supply to the ADM1166 ramps up on VPx or VH,

all PDOx pins behave as follows:

The PDOs can be programmed to pull up to a number of different

options. The outputs can be programmed as follows:

•

Input supply = 0 V to 1.2 V. The PDOs are high impedance.

Input supply = 1.2 V to 2.7 V. The PDOs are pulled to GND

by a weak (20 kΩ), on-chip pull-down resistor.

Supply > 2.7 V. Factory-programmed devices continue to

pull all PDOs to GND by a weak (20 kΩ), on-chip pull-down

resistor. Programmed devices download current EEPROM

configuration data, and the programmed setup is latched. The

PDO then goes to the state demanded by the configuration.

This provides a known condition for the PDOs during

power-up.

•

Open drain (allowing the user to connect an external

pull-up resistor).

•

Open drain with weak pull-up to V_DD

.

Open drain with strong pull-up to V_DD

Open drain with weak pull-up to VPx.

Open drain with strong pull-up to VPx.

Strong pull-down to GND.

Internally charge pumped high drive (12 V, PDO1 to

PDO6 only).

.

The internal pull-down can be overdriven with an external pull-up

of suitable value tied from the PDOx pin to the required pull-up

voltage. The 20 kΩ resistor must be accounted for in calculating

a suitable value. For example, if PDOx must be pulled up to 3.3 V,

and 5 V is available as an external supply, the pull-up resistor

value is given by

The last option (available only on PDO1 to PDO6) allows the

user to directly drive a voltage high enough to fully enhance an

external N-FET, which is used to isolate, for example, a card-

side voltage from a backplane supply (a PDO can sustain greater

than 10.5 V into a 1 μA load). The pull-down switches can also

be used to drive status LEDs directly.

3.3 V = 5 V × 20 kΩ/(R_UP+ 20 kΩ)

Therefore,

R

_UP= (100 kΩ − 66 kΩ)/3.3 V = 10 kΩ

VFET (PDO1 TO PDO6 ONLY)

V

DD

VP4

VP1

SEL

CFG4 CFG5 CFG6

SE DATA

SMBus DATA

CLK DATA

PDO

Figure 25. Programmable Driver Output

Rev. 0 | Page 16 of 32

ADM1166

SEQUENCING ENGINE

OVERVIEW

MONITOR

FAULT

The ADM1166 sequencing engine (SE) provides the user with

powerful and flexible control of sequencing. The SE implements

state machine control of the PDO outputs, with state changes

conditional on input events. SE programs can enable complex

control of boards such as power-up and power-down sequence

control, fault event handling, and interrupt generation on warnings.

A watchdog function that verifies the continued operation of a

processor clock can be integrated into the SE program. The SE

can also be controlled via the SMBus, giving software or firmware

control of the board sequencing.

STATE

TIMEOUT

SEQUENCE

Figure 26. State Cell

The ADM1166 offers up to 63 state definitions. The signals

monitored to indicate the status of the input pins are the outputs

of the SFDs.

The SE state machine comprises 63 state cells. Each state has the

following attributes:

WARNINGS

The SE also monitors warnings. These warnings can be generated

when the ADC readings violate their limit register value or

when the secondary voltage monitors on VPx or VH are triggered.

The warnings are OR’ed together and are available as a single

warning input to each of the three blocks that enable exiting a state.

•

Monitors signals indicating the status of the 10 input pins,

VP1 to VP4, VH, and VX1 to VX5.

•

Can be entered from any other state.

Three exit routes move the state machine onto a next state:

sequence detection, fault monitoring, and timeout.

Delay timers for the sequence and timeout blocks can be

programmed independently and changed with each state

change. The range of timeouts is from 0 ms to 400 ms.

Output condition of the 10 PDO pins is defined and fixed

within a state.

Transition from one state to the next is made in less than

20 μs, which is the time needed to download a state definition

from EEPROM to the SE.

SMBus JUMP (UNCONDITIONAL JUMP)

•

The SE can be forced to advance to the next state unconditionally.

This enables the user to force the SE to advance. Examples of

the use of this feature include moving to a margining state or

debugging a sequence. The SMBus jump or go-to command

can be seen as another input to sequence and timeout blocks to

provide an exit from each state.

•

Can trigger a write of the black box fault and status

registers into the black box section of EEPROM.

Table 7. Sample Sequence State Entries

State

IDLE1

IDLE2

EN3V3

Sequence

Timeout

Monitor

If VX1 is low, go to State IDLE2.

If VP1 is okay, go to State EN3V3.

If VP2 is okay, go to State EN2V5.

If VP2 is not okay after 10 ms,

go to State DIS3V3.

If VP1 is not okay, go to State IDLE1.

DIS3V3

EN2V5

If VX1 is high, go to State IDLE1.

If VP3 is okay, go to State PWRGD.

If VP3 is not okay after 20 ms,

go to State DIS2V5.

If VP1 or VP2 is not okay, go to State FSEL2.

DIS2V5

FSEL1

FSEL2

If VX1 is high, go to State IDLE1.

If VP3 is not okay, go to State DIS2V5.

If VP2 is not okay, go to State DIS3V3.

If VX1 is high, go to State DIS2V5.

If VP1 or VP2 is not okay, go to State FSEL2.

If VP1 is not okay, go to State IDLE1.

If VP1, VP2, or VP3 is not okay, go to State FSEL1.

PWRGD

Rev. 0 | Page 17 of 32

ADM1166

If a timer delay is specified, the input to the sequence detector

must remain in the defined state for the duration of the timer

delay. If the input changes state during the delay, the timer is reset.

SEQUENCING ENGINE APPLICATION EXAMPLE

The application in this section demonstrates the operation of

the SE. Figure 28 shows how the simple building block of a

single SE state can be used to build a power-up sequence for a

three-supply system.

The sequence detector can also help to identify monitoring faults.

In the sample application shown in Figure 28, the FSEL1 and

FSEL2 states first identify which of the VP1, VP2, or VP3 pins

has faulted, and then they take appropriate action.

Table 8 lists the PDO outputs for each state in the same SE

implementation. In this system, a good 5 V supply on the VP1 pin

and the VX1 pin held low are the triggers required to start a

power-up sequence. Next, the sequence turns on the 3.3 V supply,

then the 2.5 V supply (assuming successful turn-on of the 3.3 V

supply). When all three supplies have turned on correctly, the

PWRGD state is entered, where the SE remains until a fault occurs

on one of the three supplies or until it is instructed to go through a

power-down sequence by VX1 going high.

SEQUENCE

STATES

IDLE1

VX1 = 0

IDLE2

VP1 = 1

Faults are dealt with throughout the power-up sequence on a

case-by-case basis. The following three sections (the Sequence

Detector section, the Monitoring Fault Detector section, and

the Timeout Detector section) describe the individual blocks

and use the sample application shown in Figure 28 to demonstrate

the actions of the state machine.

MONITOR FAULT

STATES

TIMEOUT

STATES

EN3V3

10ms

VP1 = 0

VP2 = 1

Sequence Detector

The sequence detector block is used to detect when a step in a

sequence has been completed. It looks for one of the SE inputs

to change state, and is most often used as the gate for successful

progress through a power-up or power-down sequence. A timer

block that is included in this detector can insert delays into a

power-up or power-down sequence, if required. Timer delays

can be set from 10 μs to 400 ms. Figure 27 is a block diagram of

the sequence detector.

EN2V5

DIS3V3

20ms

(VP1 + VP2) = 0

VX1 = 1

VP3 = 1

PWRGD

DIS2V5

VP2 = 0

(VP1 + VP2 + VP3) = 0

VX1 = 1

FSEL1

(VP1 +

VP2) = 0

SUPPLY FAULT

DETECTION

VP3 = 0

VP1

SEQUENCE

DETECTOR

FSEL2

VP1 = 0

LOGIC INPUT CHANGE

VX5

VP2 = 0

OR FAULT DETECTION

TIMER

WARNINGS

Figure 28. Sample Application Flow Diagram

INVERT

FORCE FLOW

(UNCONDITIONAL JUMP)

SELECT

Figure 27. Sequence Detector Block Diagram

Table 8. PDO Outputs for Each State

PDO Outputs

PDO1 = 3V3ON

PDO2 = 2V5ON

PDO3 = FAULT

IDLE1

IDLE2

EN3V3

EN2V5

DIS3V3

DIS2V5

PWRGD

FSEL1

FSEL2

0

1

0

1

0

1

0

1

0

1

Rev. 0 | Page 18 of 32

ADM1166

Monitoring Fault Detector

Timeout Detector

The monitoring fault detector block is used to detect a failure

on an input. The logical function implementing this is a wide

OR gate that can detect when an input deviates from its expected

condition. The clearest demonstration of the use of this block is

in the PWRGD state, where the monitor block indicates that a

failure on one or more of the VPx, VXx, or VH inputs has

occurred.

The timeout detector allows the user to trap a failure to ensure

proper progress through a power-up or power-down sequence.

In the sample application shown in Figure 28, the timeout next-

state transition is from the EN3V3 and EN2V5 states. For the

EN3V3 state, the signal 3V3ON is asserted on the PDO1 output

pin upon entry to this state to turn on a 3.3 V supply.

This supply rail is connected to the VP2 pin, and the sequence

detector looks for the VP2 pin to go above its undervoltage

threshold, which is set in the supply fault detector (SFD)

attached to that pin.

No programmable delay is available in this block because the

triggering of a fault condition is likely to be caused by a supply

falling out of tolerance. In this situation, the device must react

as quickly as possible. Some latency occurs when moving out of

this state because it takes a finite amount of time (~20 μs) for the

state configuration to download from the EEPROM into the SE.

Figure 29 is a block diagram of the monitoring fault detector.

The power-up sequence progresses when this change is detected. If,

however, the supply fails (perhaps due to a short circuit overloading

this supply), the timeout block traps the problem. In this example,

if the 3.3 V supply fails within 10 ms, the SE moves to the DIS3V3

state and turns off this supply by bringing PDO1 low. It also

indicates that a fault has occurred by taking PDO3 high. Timeout

delays of 100 μs to 400 ms can be programmed.

MONITORING FAULT

DETECTOR

1-BIT FAULT

DETECTOR

FAULT

SUPPLY FAULT

DETECTION

VP1

FAULT AND STATUS REPORTING

MASK

The ADM1166 has a fault latch for recording faults. Two registers,

FSTAT1 and FSTAT2, are set aside for this purpose. A single bit

is assigned to each input of the device, and a fault on that input

sets the relevant bit. The contents of the fault register can be

read out over the SMBus to determine which input(s) faulted.

The fault register can be enabled or disabled in each state. To

latch data from one state, ensure that the fault latch is disabled

in the following state. This ensures that only real faults are

captured and not, for example, undervoltage conditions that

may be present during a power-up or power-down sequence.

SENSE

1-BIT FAULT

DETECTOR

FAULT

LOGIC INPUT CHANGE

OR FAULT DETECTION

VX5

MASK

SENSE

1-BIT FAULT

DETECTOR

FAULT

WARNINGS

The ADM1166 also has a number of input status registers. These

include more detailed information, such as whether an under-

voltage or overvoltage fault is present on a particular input. The

status registers also include information on ADC limit faults.

MASK

Figure 29. Monitoring Fault Detector Block Diagram

There are two sets of these registers with different behaviors.

The first set of status registers is not latched in any way and,

therefore, can change at any time in response to changes on the

inputs. These registers provide information as the UV and OV

state of the inputs, the digital state of the GPI VXx inputs, and

also the ADC warning limit status.

The second set of registers update each time the sequence engine

changes state and are latched until the next state change. The

second set of registers provides the same information as the first

set, but in a more compact form. The reason for this is that

these registers are used by the black box feature when writing

status information for the previous state into EEPROM.

See the AN-698 Application Note for full details about the

ADM1166 registers.

Rev. 0 | Page 19 of 32

ADM1166

are fault records to be read. Alternatively, one of the PDOx outputs

can be used to generate an interrupt for a processor in the fault

record write state to signal the need to come and read one or more

fault records.

NONVOLATILE BLACK BOX FAULT RECORDING

A section of EEPROM, from Address 0xF900 to Address 0xF9FF, is

provided which, by default, can be used to store user-defined settings

and information. Part of this section of EEPROM, Address 0xF980 to

Address 0xF9FF, can, instead, be used to store up to 16 fault records.

After reading fault records during normal operation, the following

two things must be done before the fault recorder will be able to

reuse the EEPROM locations:

Any sequencing engine state can be designated as a black box write

state. Each time the sequence engine enters that state a fault record

is written into EEPROM. The fault record provides a snapshot of the

entire ADM1166 state at the point in time when the last state was

exited, just prior to entering the designated black box write state. A

fault record contains the following information:

•

The EEPROM section must be erased.

The fault recorder must be reset so that it performs its search

again for the first unused location of EEPROM that is

available to store a fault record.

•

A flag bit set to 0 after the fault record has been written

The state number of the previous state prior to the fault

record write state

Did a sequence/timeout/monitor condition cause the

previous state to exit?

UVSTATx and OVSTATx input comparator status

VXx GPISTAT status

LIMSTATx status

BLACK BOX WRITES WITH NO EXTERNAL SUPPLY

In cases where all the input supplies fail, for example, if the card

has been removed from a powered backplane, the state machine

can be programmed to trigger a write into the black box EEPROM.

The decoupling capacitors on the rail that power the ADM1166

and other loads on the board form an energy reservoir. Depending

on the other loads on the board and their behavior as the supply

rails drop, there may be sufficient energy in the decoupling

capacitors to allow the ADM1166 to write a complete fault record

(8 bytes of data).

•

A checksum byte

Each fault record contains eight bytes, with each byte taking

typically about 250 μs to write to EEPROM, for a total write

time of about 2 ms. Once the black box begins to write a fault

record into EEPROM, the ADM1166 ensures the write is complete

before attempting to write any additional fault records. This

means that if consecutive sequencing engine states are designated

as black box write states, then a time delay must be used in the

first state to ensure that the fault record is written before moving to

the next state.

Typically, it takes 2 ms to write to the eight bytes of a fault record. If

the ADM1166 is powered using a 12 V supply on the VH pin, then

a UV threshold at 6 V could be set and used as the state machine

trigger to start writing a fault record to EEPROM. The higher the

threshold, the earlier the black box write will begin, and the more

energy available in the decoupling capacitors to ensure it completes

successfully.

Provided the VH supply, or another supply connected to a VPx pin,

remains above 3.0 V during the time to write, the entire fault record

would always be written to EEPROM. In many cases, there will be

sufficient decoupling capacitors on a board to power the ADM1166

as it writes into EEPROM.

When the ADM1166 powers on initially, it performs a search

to find the first fault record that has not been written to. It does

this by checking the flag bit in each fault record until it finds

one where the flag bit is 1. The first fault record is stored at

Address 0xF980 and at multiples of eight bytes after that,

with the last record stored at Address 0xF9F8.

In cases where the decoupling capacitors are not able to supply

sufficient energy for a complete fault record to be written after the

board is removed, the value of the capacitor on VDDCAP may

be increased. In the worst case, assuming that no energy is

supplied to the ADM1166 by external decoupling capacitors,

but that the VDDCAP capacitor has 4.75 V across it at the start

of the black box write to EEPROM, then a VDDCAP of 68 μF is

sufficient to guarantee a single complete black box record can

be written to EEPROM.

The fault recorder is only able to write in the EEPROM. It is

not able to erase the EEPROM prior to writing the fault record.

Therefore, to ensure correct operation, it is important that the fault

record EEPROM be erased prior to use. Once all the EEPROM

locations for the fault records are used, no more fault records can

be written. This ensures that the first fault in any cascading fault is

stored and not overwritten and lost.

To avoid the fault recorder filling up and fault records being lost, an

application can periodically poll the ADM1166 to determine if there

Rev. 0 | Page 20 of 32

ADM1166

VOLTAGE READBACK

The ADM1166 has an on-board, 12-bit accurate ADC for

voltage readback over the SMBus. The ADC has a 12-channel

analog mux on the front end. The 12 channels consist of the

10 SFD inputs (VH, VPx, and VXx) and two auxiliary (single-

ended) ADC inputs (AUX1 and AUX2). Any or all of these inputs

can be selected to be read, in turn, by the ADC. The circuit

controlling this operation is called the round-robin circuit.

This circuit can be selected to run through its loop of conversions

once or continuously. Averaging is also provided for each channel.

In this case, the round-robin circuit runs through its loop of

conversions 16 times before returning a result for each channel. At

the end of this cycle, the results are written to the output registers.

Table 9. ADC Input Voltage Ranges

Attenuation

Factor

ADC Input Voltage

Range (V)

SFD Input Range (V)

0.573 to 1.375

1.25 to 3.00

2.5 to 6.0

6.0 to 14.4

1

0 to 2.048

0 to 4.46

0 to 6.0¹

2.181

4.363

10.472

0 to 14.4¹

¹The upper limit is the absolute maximum allowed voltage on the VPx and

VH pins.

The typical way to supply the reference to the ADC on the REFIN

pin is to connect the REFOUT pin to the REFIN pin. REFOUT

provides a 2.048 V reference. As such, the supervising range covers

less than half the normal ADC range. It is possible, however, to

provide the ADC with a more accurate external reference for

improved readback accuracy.

The ADC samples single-sided inputs with respect to the AGND

pin. A 0 V input gives out Code 0, and an input equal to the

voltage on REFIN gives out full code (4095 decimal).

The inputs to the ADC come directly from the VXx pins and

from the back of the input attenuators on the VPx and VH pins,

as shown in Figure 30 and Figure 31.

Supplies can also be connected to the input pins purely for ADC

readback, even though these pins may go above the expected

supervisory range limits (but not above the absolute maximum

ratings on these pins). For example, a 1.5 V supply connected to

the VX1 pin can be correctly read out as an ADC code of approxi-

mately 3/4 full scale, but it always sits above any supervisory limits

that can be set on that pin. The maximum setting for the REFIN

pin is 2.048 V.

DIGITIZED

VOLTAGE

READING

NO ATTENUATION

12-BIT

ADC

VXx

2.048V VREF

SUPPLY SUPERVISION WITH THE ADC

Figure 30. ADC Reading on VXx Pins

In addition to the readback capability, another level of supervision

is provided by the on-chip 12-bit ADC. The ADM1166 has limit

registers with which the user can program a maximum or minimum

allowable threshold. Exceeding the threshold generates a warning

that can either be read back from the status registers or input

into the SE to determine what sequencing action the ADM1166

should take. Only one register is provided for each input channel.

Therefore, either an undervoltage threshold or overvoltage

threshold (but not both) can be set for a given channel. The

round-robin circuit can be enabled via a SMBus write, or it

can be programmed to turn on in any state in the SE program.

For example, it can be set to start after a power-up sequence is

complete and all supplies are known to be within expected

tolerance limits.

ATTENUATION NETWORK

VPx/VH

(DEPENDS ON RANGE SELECTED)

DIGITIZED

VOLTAGE

READING

12-BIT

ADC

2.048V VREF

Figure 31. ADC Reading on VPx/VH Pins

The voltage at the input pin can be derived from the following

equation:

ADC Code

V =

× Attenuation Factor × V_REFIN

4095

where V_REFIN= 2.048 V when the internal reference is used (that

is, the REFIN pin is connected to the REFOUT pin).

Note that latency is built into this supervision, dictated by the

conversion time of the ADC. With all 12 channels selected, the

total time for the round-robin operation (averaging off) is

approximately 6 ms (500 μs per channel selected). Supervision

using the ADC, therefore, does not provide the same real-time

response as the SFDs.

The ADC input voltage ranges for the SFD input ranges are listed

in Table 9.

Rev. 0 | Page 21 of 32

ADM1166

SUPPLY MARGINING

fall to compensate for this. The dc-to-dc converter output can

be forced high by setting the DACx output voltage lower than

the feedback node voltage. The series resistor can be split in two,

and the node between them can be decoupled with a capacitor

to ground. This can help to decouple any noise picked up from

the board. Decoupling to a ground local to the dc-to-dc converter

is recommended.

OVERVIEW

It is often necessary for the system designer to adjust supplies, either

to optimize their level or force them away from nominal values

to characterize the system performance under these conditions.

This is a function typically performed during an in-circuit test (ICT),

such as when a manufacturer wants to guarantee that a product

under test functions correctly at nominal supplies minus 10%.

The ADM1166 can be commanded to margin a supply up or down

over the SMBus by updating the values on the relevant DAC output.

OPEN-LOOP SUPPLY MARGINING

The simplest method of margining a supply is to implement an

open-loop technique (see Figure 32). A popular way to do this

is to switch extra resistors into the feedback node of a power

module, such as a dc-to-dc converter or LDO. The extra resistor

alters the voltage at the feedback or trim node and forces the

output voltage to margin up or down by a certain amount.

CLOSED-LOOP SUPPLY MARGINING

A more accurate and comprehensive method of margining is to

implement a closed-loop system (see Figure 33). The voltage on

the rail to be margined can be read back to accurately margin the

rail to the target voltage. The ADM1166 incorporates all the circuits

required to do this, with the 12-bit successive approximation ADC

used to read back the level of the supervised voltages, and the six

voltage output DACs, implemented as described in the Open-

Loop Supply Margining section, used to adjust supply levels. These

circuits can be used along with other intelligence, such as a

microcontroller, to implement a closed-loop margining system that

allows any dc-to-dc converter or LDO supply to be set to any voltage,

accurate to within 0.5% of the target.

The ADM1166 can perform open-loop margining for up to six

supplies. The six on-board voltage DACs (DAC1 to DAC6) can

drive into the feedback pins of the power modules to be margined.

The simplest circuit to implement this function is an attenuation

resistor that connects the DACx pin to the feedback node of a

dc-to-dc converter. When the DACx output voltage is set equal

to the feedback voltage, no current flows into the attenuation

resistor, and the dc-to-dc converter output voltage does not change.

Taking DACx above the feedback voltage forces current into the

feedback node, and the output of the dc-to-dc converter is forced to

VIN

MICROCONTROLLER

ADM1166

V

OUT

DEVICE

CONTROLLER

(SMBus)

OUTPUT

DC-TO-DC

ATTENUATION

RESISTOR, R3

CONVERTER

R1

R2

DACx

FEEDBACK

DAC

PCB

GND

TRACE NOISE

DECOUPLING

CAPACITOR

Figure 32. Open-Loop Margining System Using the ADM1166

MICROCONTROLLER

VIN

ADM1166

MUX

VH/VPx/VXx

DACx

DC-TO-DC

CONVERTER

ADC

DAC

ATTENUATION

RESISTOR, R3

OUTPUT

DEVICE

CONTROLLER

(SMBus)

R1

R2

FEEDBACK

GND

PCB

TRACE NOISE

DECOUPLING

CAPACITOR

Figure 33. Closed-Loop Margining System Using the ADM1166

Rev. 0 | Page 22 of 32

ADM1166

CHOOSING THE SIZE OF THE ATTENUATION

To implement closed-loop margining,

RESISTOR

1. Disable the six DACx outputs.

2. Set the DAC output voltage equal to the voltage on the

feedback node.

3. Enable the DAC.

The size of the attenuation resistor, R3, determines how much

the DAC voltage swing affects the output voltage of the dc-to-dc

converter that is being margined (see Figure 33).

4. Read the voltage at the dc-to-dc converter output that is

connected to one of the VPx, VH, or VXx pins.

5. If necessary, modify the DACx output code up or down to

adjust the dc-to-dc converter output voltage. Otherwise,

stop because the target voltage has been reached.

6. Set the DAC output voltage to a value that alters the supply

output by the required amount (for example, 5%).

7. Repeat Step 4 through Step 6 until the measured supply

reaches the target voltage.

Because the voltage at the feedback pin remains constant, the

current flowing from the feedback node to GND through R2 is

a constant. In addition, the feedback node itself is high impedance.

This means that the current flowing through R1 is the same as

the current flowing through R3.

Therefore, a direct relationship exists between the extra voltage

drop across R1 during margining and the voltage drop across R3.

This relationship is given by the following equation:

Step 1 to Step 3 ensures that when the DACx output buffer is

turned on, it has little effect on the dc-to-dc converter output.

The DAC output buffer is designed to power up without glitching

by first powering up the buffer to follow the pin voltage. It does not

drive out onto the pin at this time. Once the output buffer is

properly enabled, the buffer input is switched over to the DAC,

and the output stage of the buffer is turned on. Output glitching

is negligible.

R1

R3

ΔV_OUT

=

(V_FB− V_DACOUT)

where:

ΔV_OUTis the change in V_OUT

V_FBis the voltage at the feedback node of the dc-to-dc converter.

V_DACOUTis the voltage output of the margining DAC.

.

This equation demonstrates that if the user wants the output

voltage to change by 300 mV, then R1 = R3. If the user wants the

output voltage to change by 600 mV, R1 = 2 × R3, and so on.

WRITING TO THE DACS

Four DAC ranges are offered. They can be placed with midcode

(Code 0x7F) at 0.6 V, 0.8 V, 1.0 V, and 1.25 V. These voltages are

placed to correspond to the most common feedback voltages.

Centering the DAC outputs in this way provides the best use of

the DAC resolution. For most supplies, it is possible to place the

DAC midcode at the point where the dc-to-dc converter output

is not modified, thereby giving half of the DAC range to margin

up and the other half to margin down.

It is best to use the full DAC output range to margin a supply.

Choosing the attenuation resistor in this way provides the most

resolution from the DAC, meaning that with one DAC code

change, the smallest effect on the dc-to-dc converter output

voltage is induced. If the resistor is sized up to use a code such

as 27 decimal to 227 decimal to move the dc-to-dc converter output

by 5%, it takes 100 codes to move 5% (each code moves the

output by 0.05%). This is beyond the readback accuracy of the

ADC, but it should not prevent the user from building a circuit

to use the most resolution.

The DAC output voltage is set by the code written to the DACx

register. The voltage is linear with the unsigned binary number

in this register. Code 0x7F is placed at the midcode voltage, as

described previously. The output voltage is given by

DAC LIMITING AND OTHER SAFETY FEATURES

Limit registers (called DPLIMx and DNLIMx) on the device

offer the user some protection from firmware bugs that can

cause catastrophic board problems by forcing supplies beyond

their allowable output ranges. Essentially, the DAC code written

into the DACx register is clipped such that the code used to set

the DAC voltage is given by

DAC Output = (DACx − 0x7F)/255 × 0.6015 + V_OFF

where V_OFFis one of the four offset voltages.

There are 256 DAC settings available. The midcode value is

located at DAC Code 0x7F as close as possible to the middle

of the 256 code range. The full output swing of the DACs is

+302 mV (+128 codes) and −300 mV (−127 codes) around

the selected midcode voltage. The voltage range for each midcode

voltage is shown in Table 10.

DAC Code

= DACx,

= DNLIMx,

= DPLIMx,

DACx ≥ DNLIMx and DACx ≤ DPLIMx

DACx < DNLIMx

DACx > DPLIMx

Table 10. Ranges for Midcode Voltages

In addition, the DAC output buffer is three-stated if DNLIMx >

DPLIMx. By programming the limit registers this way, the user

can make it very difficult for the DAC output buffers to be

turned on during normal system operation. The limit registers

are among the registers downloaded from EEPROM at startup.

Midcode

Voltage (V)

Minimum Voltage

Output (V)

Maximum Voltage

Output (V)

0.6

0.8

1.0

1.25

0.300

0.500

0.700

0.950

0.902

1.102

1.302

1.552

Rev. 0 | Page 23 of 32

ADM1166

APPLICATIONS DIAGRAM

12V IN

5V IN

3V IN

12V OUT

5V OUT

3V OUT

IN

DC-TO-DC1

EN

OUT

3.3V OUT

2.5V OUT

1.8V OUT

VH

ADM1166

5V OUT

3V OUT

VP1

VP2

VP3

VP4

VX1

VX2

VX3

PDO1

PDO2

3.3V OUT

2.5V OUT

1.8V OUT

1.2V OUT

0.9V OUT

IN

DC-TO-DC2

EN OUT

PDO3

PDO4

PDO5

PWRGD

POWRON

RESET

PDO6

PDO7

VX4

VX5

SIGNAL VALID

SYSTEM RESET

IN

DC-TO-DC3

PDO8

PDO9

EN

OUT

PDO10

DAC1*

3.3V OUT

REFOUT

IN

REFIN VCCP VDDCAP GND

LDO

EN

OUT

0.9V OUT

1.2V OUT

10µF

3.3V OUT

IN

*ONLY ONE MARGINING CIRCUIT

SHOWN FOR CLARITY. DAC1 TO DAC6

ALLOW MARGINING FOR UP TO SIX

VOLTAGE RAILS.

OUT

EN

TRIM

DC-TO-DC4

Figure 34. Applications Diagram

Rev. 0 | Page 24 of 32

ADM1166

COMMUNICATING WITH THE ADM1166

Option 1

CONFIGURATION DOWNLOAD AT POWER-UP

The configuration of the ADM1166 (undervoltage/overvoltage

thresholds, glitch filter timeouts, and PDO configurations) is

dictated by the contents of the RAM. The RAM comprises digital

latches that are local to each function on the device. The latches are

double buffered and have two identical latches, Latch A and Latch B.

Therefore, when an update to a function occurs, the contents of

Latch A are updated first, and then the contents of Latch B are

updated with identical data. The advantages of this architecture are

explained in detail in the Updating the Configuration section.

Update the configuration in real time. The user writes to the RAM

across the SMBus, and the configuration is updated immediately.

Option 2

Update the Latch As without updating the Latch Bs. With this

method, the configuration of the ADM1166 remains unchanged

and continues to operate in the original setup until the instruction

is given to update the Latch Bs.

Option 3

Change the EEPROM register contents without changing the RAM

contents, and then download the revised EEPROM contents to

the RAM registers. With this method, the configuration of the

ADM1166 remains unchanged and continues to operate in the

original setup until the instruction is given to update the RAM.

The instruction to download from the EEPROM in Option 3 is

also a useful way to restore the original EEPROM contents if

revisions to the configuration are unsatisfactory. For example, if

the user needs to alter an overvoltage threshold, the RAM register

can be updated as described in the Option 1 section. However,

if the user is not satisfied with the change and wants to revert to

the original programmed value, the device controller can issue a

command to download the EEPROM contents to the RAM again,

as described in the Option 3 section, restoring the ADM1166 to

its original configuration.

The topology of the ADM1166 makes this type of operation

possible. The local, volatile registers (RAM) are all double-

buffered latches. Setting Bit 0 of the UPDCFG register to 1 leaves

the double-buffered latches open at all times. If Bit 0 is set to 0

when a RAM write occurs across the SMBus, only the first side

of the double-buffered latch is written to. The user must then

write a 1 to Bit 1 of the UPDCFG register. This generates a pulse

to update all the second latches at once. EEPROM writes occur

in a similar way.

The two latches are volatile memory and lose their contents at

power-down. Therefore, the configuration in the RAM must be

restored at power-up by downloading the contents of the EEPROM

(nonvolatile memory) to the local latches. This download occurs in

steps, as follows:

1. With no power applied to the device, the PDOs are all high

impedance.

2. When 1.2 V appears on any of the inputs connected to the

VDD arbitrator (VH or VPx), the PDOs are all weakly

pulled to GND with a 20 kΩ resistor.

3. When the supply rises above the undervoltage lockout of

the device (UVLO is 2.5 V), the EEPROM starts to

download to the RAM.

4. The EEPROM downloads its contents to all Latch As.

5. When the contents of the EEPROM are completely

downloaded to the Latch As, the device controller signals

all Latch As to download to all Latch Bs simultaneously,

completing the configuration download.

6. At 0.5 ms after the configuration download completes, the first

state definition is downloaded from the EEPROM into the SE.

Note that any attempt to communicate with the device prior to

the completion of the download causes the ADM1166 to issue

a no acknowledge (NACK).

UPDATING THE CONFIGURATION

The final bit in this register can enable or disable EEPROM page

erasure. If this bit is set high, the contents of an EEPROM page can

all be set to 1. If this bit is set low, the contents of a page cannot be

erased, even if the command code for page erasure is programmed

across the SMBus. The bit map for the UPDCFG register is shown

in the AN-698 Application Note. A flow diagram for download at

power-up and subsequent configuration updates is shown in

Figure 35.

After power-up, with all the configuration settings loaded from

the EEPROM into the RAM registers, the user may need to alter

the configuration of functions on the ADM1166, such as changing

the undervoltage or overvoltage limit of an SFD, changing the fault

output of an SFD, or adjusting the rise time delay of one of the PDOs.

The ADM1166 provides several options that allow the user to

update the configuration over the SMBus interface. The following

three options are controlled in the UPDCFG register.

SMBus

POWER-UP

CC

DEVICE

(V > 2.5V)

CONTROLLER

E

P

R

O

M

L

R

A

M

L

U

P

D

A

T

D

A

LATCH A

LATCH B

FUNCTION

D

(OV THRESHOLD

ON VP1)

EEPROM

Figure 35. Configuration Update Flow Diagram

Rev. 0 | Page 25 of 32

ADM1166

Page 8 to Page 11 are available for customer use to store any

UPDATING THE SEQUENCING ENGINE

information that may be required by the customer in their

application. Customers can store information on Page 12 to

Page 15, or these pages can store the fault records written by the

sequencing engine if users have decided to enable writing of the

fault records for different states.

Sequencing engine (SE) functions are not updated in the same

way as regular configuration latches. The SE has its own dedicated

512-byte nonvolatile, electrically erasable, programmable, read-

only memory (EEPROM) for storing state definitions, providing

63 individual states each with a 64-bit word (one state is reserved).

At power-up, the first state is loaded from the SE EEPROM into

the engine itself. When the conditions of this state are met, the

next state is loaded from the EEPROM into the engine, and so

on. The loading of each new state takes approximately 10 μs.

Data can be downloaded from the EEPROM to the RAM in one

of the following ways:

•

At power-up, when Page 0 to Page 4 are downloaded.

By setting Bit 0 of the UDOWNLD register (0xD8), which

performs a user download of Page 0 to Page 4.

To alter a state, the required changes must be made directly to

the EEPROM. RAM for each state does not exist. The relevant

alterations must be made to the 64-bit word, which is then

uploaded directly to the EEPROM.

When the sequence engine is enabled, it is not possible to access

the section of EEPROM from Address 0xFA00 to Address 0xFBFF.

The sequence engine must be halted before it is possible to read

or write to this range. Attempting to read or write to this range if

the sequence engine is not halted will generate a no acknowledge,

or NACK.

INTERNAL REGISTERS

The ADM1166 contains a large number of data registers. The

principal registers are the address pointer register and the

configuration registers.

Read/write access to the configuration and user EEPROM ranges

from Address 0xF800 to Address 0xF89F and Address 0xF900

to Address 0xF9FF depends on whether the black box fault

recorder is enabled. If the fault recorder is enabled and one or

more states have been set as fault record trigger states, then it is

not possible to access any EEPROM location in this range

without first halting the black box. Attempts to read or write

this EEPROM range while the fault recorder is operating are

acknowledged by the device but do not return any useful data

or modify the EEPROM in any way.

Address Pointer Register

The address pointer register contains the address that selects

one of the other internal registers. When writing to the ADM1166,

the first byte of data is always a register address that is written to

the address pointer register.

Configuration Registers

The configuration registers provide control and configuration

for various operating parameters of the ADM1166.

If none of the states are set as fault record trigger states, then the

black box is considered disabled, and read/write access is allowed

without having to halt the black box fault recorder.

EEPROM

The ADM1166 has two 512-byte cells of nonvolatile EEPROM

from Address 0xF800 to Address 0xFBFF. The EEPROM is used

for permanent storage of data that is not lost when the ADM1166 is

powered down. One EEPROM cell, 0xF800 to 0xF9FF, contains the

configuration data, user information and, if enabled, any fault

records of the device; the other section, 0xFA00 to 0xFBFF, contains

the state definitions for the SE. Although referred to as read-only

memory, the EEPROM can be written to, as well as read from,

using the serial bus in exactly the same way as the other registers.

SERIAL BUS INTERFACE

The ADM1166 is controlled via the serial system management

bus (SMBus) and is connected to this bus as a slave device under

the control of a master device. It takes approximately 1 ms after

power-up for the ADM1166 to download from its EEPROM.

Therefore, access to the ADM1166 is restricted until the

download is complete.

The major differences between the EEPROM and other

registers are as follows:

Identifying the ADM1166 on the SMBus

The ADM1166 has a 7-bit serial bus slave address (see Table 11).

The device is powered up with a default serial bus address. The

five MSBs of the address are set to 01101; the two LSBs are

determined by the logical states of Pin A1 and Pin A0. This

allows the connection of four ADM1166s to one SMBus.

•

An EEPROM location must be blank before it can be

written to. If it contains data, the data must first be erased.

Writing to the EEPROM is slower than writing to the RAM.

Writing to the EEPROM should be restricted because it has

a limited write/cycle life of typically 10,000 write operations

due to the usual EEPROM wear-out mechanisms.

•

Table 11. Serial Bus Slave Address

A1 Pin

A0 Pin

Hex Address

7-Bit Address¹

0110100x

0110101x

0110110x

The first EEPROM is split into 16 (0 to 15) pages of 32 bytes each.

Page 0 to Page 3, from Address 0xF800 to Address 0xF89F, hold

the configuration data for the applications on the ADM1166

(such as the SFDs and PDOs). These EEPROM addresses are

the same as the RAM register addresses, prefixed by F8. Page 5

to Page 7, from Address 0xF8A0 to Address 0xF8FF, are reserved.

Low

0x68

Low

High

Low

High

0x6A

0x6C

0x6E

0110111x

¹x = Read/write bit. The address is shown only as the first 7 MSBs.

Rev. 0 | Page 26 of 32

ADM1166

The device also has several identification registers (read-only)

that can be read across the SMBus. Table 12 lists these registers

with their values and functions.

All other devices on the bus remain idle while the selected

device waits for data to be read from or written to it. If the

W

R/ bit is a 0, the master writes to the slave device. If the

W

R/ bit is a 1, the master reads from the slave device.

Table 12. Identification Register Values and Functions

2. Data is sent over the serial bus in sequences of nine clock

pulses: eight bits of data followed by an acknowledge bit

from the slave device. Data transitions on the data line

must occur during the low period of the clock signal and

remain stable during the high period because a low-to-high

transition when the clock is high could be interpreted as a

stop signal. If the operation is a write operation, the first

data byte after the slave address is a command byte. This

command byte tells the slave device what to expect next. It

may be an instruction telling the slave device to expect a

block write, or it may be a register address that tells the

slave where subsequent data is to be written. Because data

Name

Address Value Function

MANID 0xF4

0x41

Manufacturer ID for Analog

Devices

REVID

MARK1 0xF6

MARK2 0xF7

0xF5

0x02

0x00

Silicon revision

Software brand

General SMBus Timing

Figure 36, Figure 37, and Figure 38 are timing diagrams for general

read and write operations using the SMBus. The SMBus specification

defines specific conditions for different types of read and write

operations, which are discussed in the Write Operations and the

Read Operations sections.

W

can flow in only one direction, as defined by the R/ bit,

sending a command to a slave device during a read operation

is not possible. Before a read operation, it may be necessary

to perform a write operation to tell the slave what sort of

read operation to expect and/or the address from which

data is to be read.

The general SMBus protocol operates in the following three steps.

1. The master initiates data transfer by establishing a start

condition, defined as a high-to-low transition on the serial

data line SDA, while the serial clock line SCL remains high.

This indicates that a data stream follows. All slave peripherals

connected to the serial bus respond to the start condition

and shift in the next eight bits, consisting of a 7-bit slave

3. When all data bytes have been read or written, stop conditions

are established. In write mode, the master pulls the data line

high during the 10^thclock pulse to assert a stop condition.

In read mode, the master device releases the SDA line during

the low period before the ninth clock pulse, but the slave device

does not pull it low. This is known as a no acknowledge.

The master then takes the data line low during the low

period before the 10^thclock pulse and then high during the

10^thclock pulse to assert a stop condition.

W

address (MSB first) plus an R/ bit. This bit determines

the direction of the data transfer, that is, whether data is

written to or read from the slave device (0 = write, 1 = read).

The peripheral whose address corresponds to the transmitted

address responds by pulling the data line low during the

low period before the ninth clock pulse, known as the

acknowledge bit, and by holding it low during the high period

of this clock pulse.

1

9

1

9

SCL

SDA

0

1

0

1

A1

A0 R/W

D7

D6 D5 D4

D3 D2

D1

D0

ACK. BY

SLAVE

ACK. BY

SLAVE

START BY

MASTER

FRAME 1

SLAVE ADDRESS

FRAME 2

COMMAND CODE

1

9

1

9

SCL

(CONTINUED)

SDA

(CONTINUED)

D7 D6

D5 D4

D3 D2

D1

D7

D6 D5 D4

D3 D2

D1

D0

STOP

BY

MASTER

ACK. BY

SLAVE

ACK. BY

SLAVE

FRAME 3

FRAME N

DATA BYTE

Figure 36. General SMBus Write Timing Diagram

Rev. 0 | Page 27 of 32

ADM1166

1

9

1

9

SCL

SDA

0

1

0

1

A1

A0 R/W

D7

D6 D5 D4

D3 D2

D1

D0

ACK. BY

SLAVE

ACK. BY

MASTER

START BY

MASTER

FRAME 1

SLAVE ADDRESS

FRAME 2

DATA BYTE

1

9

1

9

SCL

(CONTINUED)

SDA

(CONTINUED)

D7 D6

D5 D4

D3 D2

D1

D7

D6 D5 D4

D3 D2

D1

D0

NO ACK.

D0

STOP

BY

MASTER

ACK. BY

MASTER

FRAME 3

FRAME N

DATA BYTE

Figure 37. General SMBus Read Timing Diagram

t_R

t_F

t_HD;STA

t_LOW

t_HD;STA

t_HD;DAT

SCL

SDA

t_HIGH

t_SU;STA

t_SU;STO

t_SU;DAT

t_BUF

P

S

P

Figure 38. Serial Bus Timing Diagram

EEPROM erasure cannot be done at the byte level. The EEPROM

is arranged as 32 pages of 32 bytes each, and an entire page

must be erased.

SMBus PROTOCOLS FOR RAM AND EEPROM

The ADM1166 contains volatile registers (RAM) and nonvolatile

registers (EEPROM). User RAM occupies Address 0x00 to

Address 0xDF, and the EEPROM occupies Address 0xF800 to

Address 0xFBFF.

Page erasure is enabled by setting Bit 2 in the UPDCFG register

(Address 0x90) to 1. If this bit is not set, page erasure cannot

occur, even if the command byte (0xFE) is programmed across

the SMBus.

Data can be written to and read from both the RAM and the

EEPROM as single data bytes. Data can be written only to

unprogrammed EEPROM locations. To write new data to a

programmed location, the location contents must first be erased.

Rev. 0 | Page 28 of 32

ADM1166

The master sends a command code telling the slave device

to erase the page. The ADM1166 command code for a page

erasure is 0xFE (1111 1110). Note that for a page erasure to

take place, the page address must be given in the previous

write word transaction (see the Write Byte/Word section). In

addition, Bit 2 in the UPDCFG register (Address 0x90)

must be set to 1.

WRITE OPERATIONS

The SMBus specification defines several protocols for different

types of read and write operations. The following abbreviations

are used in Figure 39 to Figure 47:

•

S = Start

P = Stop

R = Read

W = Write

A = Acknowledge

1

2

3

4

5

6

COMMAND

BYTE

(0xFE)

SLAVE

ADDRESS

S

W

A

P

= No acknowledge

A

Figure 40. EEPROM Page Erasure

As soon as the ADM1166 receives the command byte,

page erasure begins. The master device can send a stop

command as soon as it sends the command byte. Page

erasure takes approximately 20 ms. If the ADM1166 is

accessed before erasure is complete, it responds with a

no acknowledge (NACK).

The ADM1166 uses the following SMBus write protocols.

Send Byte

In a send byte operation, the master device sends a single

command byte to a slave device, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device asserts an acknowledge (ACK)

on SDA.

Write Byte/Word

In a write byte/word operation, the master device sends a command

byte and one or two data bytes to the slave device, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device asserts an ACK on SDA.

4. The master sends a command code.

5. The slave asserts an ACK on SDA.

6. The master sends a data byte.

4. The master sends a command code.

5. The slave asserts an ACK on SDA.

6. The master asserts a stop condition on SDA, and the

transaction ends.

In the ADM1166, the send byte protocol is used for two

purposes:

•

To write a register address to the RAM for a subsequent

single byte read from the same address, or for a block read

or block write starting at that address, as shown in Figure 39.

7. The slave asserts an ACK on SDA.

8. The master sends a data byte or asserts a stop condition.

9. The slave asserts an ACK on SDA.

10. The master asserts a stop condition on SDA to end the

transaction.

1

2

3

4

5

6

RAM

SLAVE

ADDRESS

S

W

A

ADDRESS

A

P

(0x00 TO 0xDF)

In the ADM1166, the write byte/word protocol is used for three

purposes:

Figure 39. Setting a RAM Address for Subsequent Read

•

To erase a page of EEPROM memory. EEPROM memory

can be written to only if it is unprogrammed. Before writing

to one or more EEPROM memory locations that are already

programmed, the page(s) containing those locations must

first be erased. EEPROM memory is erased by writing a

command byte.

•

To write a single byte of data to the RAM. In this case, the

command byte is RAM Address 0x00 to RAM Address 0xDF,

and the only data byte is the actual data, as shown in Figure 41.

1

2

3

4

5

6

7

8

RAM

SLAVE

ADDRESS

S

W

A

ADDRESS

A

DATA

A

P

(0x00 TO 0xDF)

Figure 41. Single Byte Write to the RAM

•

To set up a 2-byte EEPROM address for a subsequent read,

write, block read, block write, or page erase. In this case, the

command byte is the high byte of EEPROM Address 0xF8

to EEPROM Address 0xFB. The only data byte is the low

byte of the EEPROM address, as shown in Figure 42.

1

2

3

4

5

6

7

8

EEPROM

ADDRESS

HIGH BYTE

(0xF8 TO 0xFB)

EEPROM

ADDRESS

LOW BYTE

(0x00 TO 0xFF)

SLAVE

ADDRESS

S

W

A

P

Figure 42. Setting an EEPROM Address

Rev. 0 | Page 29 of 32

ADM1166

Because a page consists of 32 bytes, only the three MSBs of

Unlike some EEPROM devices that limit block writes to within

a page boundary, there is no limitation on the start address

when performing a block write to EEPROM, except when

the address low byte are important for page erasure. The

lower five bits of the EEPROM address low byte specify the

addresses within a page and are ignored during an erase

operation.

•

There must be at least N locations from the start address to

the highest EEPROM address (0xFBFF) to avoid writing to

invalid addresses.

•

To write a single byte of data to the EEPROM. In this case,

the command byte is the high byte of EEPROM Address 0xF8

to EEPROM Address 0xFB. The first data byte is the low

byte of the EEPROM address, and the second data byte is

the actual data, as shown in Figure 43.

•

An address crosses a page boundary. In this case, both

pages must be erased before programming.

Note that the ADM1166 features a clock extend function for writes

to the EEPROM. Programming an EEPROM byte takes approxi-

mately 250 μs, which limits the SMBus clock for repeated or block

write operations. The ADM1166 pulls SCL low and extends the

clock pulse when it cannot accept any more data.

1

2

3

4

5

6

7

8

9

10

EEPROM

ADDRESS

HIGH BYTE

(0xF8 TO 0xFB)

EEPROM

ADDRESS

LOW BYTE

(0x00 TO 0xFF)

SLAVE

ADDRESS

S

W

A

DATA

A

P

Figure 43. Single Byte Write to the EEPROM

READ OPERATIONS

Block Write

The ADM1166 uses the following SMBus read protocols.

Receive Byte

In a block write operation, the master device writes a block of

data to a slave device. The start address for a block write must

have been set previously. In the ADM1166, a send byte opera-

tion sets a RAM address, and a write byte/word operation sets

an EEPROM address, as follows:

In a receive byte operation, the master device receives a single

byte from a slave device, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

read bit (high).

3. The addressed slave device asserts an ACK on SDA.

4. The master receives a data byte.

5. The master asserts a NACK on SDA.

6. The master asserts a stop condition on SDA, and the

transaction ends.

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by

the write bit (low).

3. The addressed slave device asserts an ACK on SDA.

4. The master sends a command code that tells the slave

device to expect a block write. The ADM1166 command

code for a block write is 0xFC (1111 1100).

5. The slave asserts an ACK on SDA.

In the ADM1166, the receive byte protocol is used to read a

single byte of data from a RAM or EEPROM location whose

address has previously been set by a send byte or write

byte/word operation, as shown in Figure 44.

6. The master sends a data byte that tells the slave device how

many data bytes are being sent. The SMBus specification

allows a maximum of 32 data bytes in a block write.

7. The slave asserts an ACK on SDA.

1

2

3

4

5

6

8. The master sends N data bytes.

SLAVE

S

R

A

DATA

A

P

ADDRESS

9. The slave asserts an ACK on SDA after each data byte.

10. The master asserts a stop condition on SDA to end the

transaction.

Figure 44. Single Byte Read from the EEPROM or RAM

1

2

3

4

5

6

7

8

9

10

SLAVE

ADDRESS

COMMAND 0xFC

(BLOCK WRITE)

BYTE

COUNT

DATA

1

DATA

2

DATA

N

S

W

A

A P

Figure 45. Block Write to the EEPROM or RAM

Rev. 0 | Page 30 of 32

ADM1166

Block Read

Error Correction

In a block read operation, the master device reads a block of

data from a slave device. The start address for a block read must

have been set previously. In the ADM1166, this is done by a

send byte operation to set a RAM address, or a write byte/word

operation to set an EEPROM address. The block read operation

itself consists of a send byte operation that sends a block read

command to the slave, immediately followed by a repeated start

and a read operation that reads out multiple data bytes, as follows:

The ADM1166 provides the option of issuing a packet error correc-

tion (PEC) byte after a write to the RAM, a write to the EEPROM,

a block write to the RAM/EEPROM, or a block read from the

RAM/EEPROM. This option enables the user to verify that the data

received by or sent from the ADM1166 is correct. The PEC byte

is an optional byte sent after the last data byte has been written

to or read from the ADM1166. The protocol is the same as a

block read for Step 1 to Step 12 and then proceeds as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device asserts an ACK on SDA.

4. The master sends a command code that tells the slave

device to expect a block read. The ADM1166 command

code for a block read is 0xFD (1111 1101).

13. The ADM1166 issues a PEC byte to the master. The master

checks the PEC byte and issues another block read, if the

PEC byte is incorrect.

14. A NACK is generated after the PEC byte to signal the end

of the read.

15. The master asserts a stop condition on SDA to end the

transaction.

5. The slave asserts an ACK on SDA.

Note that the PEC byte is calculated using CRC-8. The frame

check sequence (FCS) conforms to CRC-8 by the polynomial

6. The master asserts a repeat start condition on SDA.

7. The master sends the 7-bit slave address followed by the

read bit (high).

C(x) = x⁸+ x²+ x¹+ 1

8. The slave asserts an ACK on SDA.

See the SMBus Version 1.1 specification for details. An example

of a block read with the optional PEC byte is shown in Figure 47.

9. The ADM1166 sends a byte-count data byte that tells the

master how many data bytes to expect. The ADM1166

always returns 32 data bytes (0x20), which is the maximum

allowed by the SMBus Version 1.1 specification.

10. The master asserts an ACK on SDA.

11. The master receives 32 data bytes.

12. The master asserts an ACK on SDA after each data byte.

13. The master asserts a stop condition on SDA to end the

transaction.

1

2

3

4

5

6

7

8

9

10 11 12

DATA

SLAVE

ADDRESS

COMMAND 0xFD

(BLOCK READ)

SLAVE

ADDRESS

BYTE

COUNT

S

W

A

S

R A

A

1

13

P

DATA

32

A

Figure 46. Block Read from the EEPROM or RAM

1

2

3

4

5

6

7

8

9

10 11 12

DATA

SLAVE

ADDRESS

COMMAND 0xFD

(BLOCK READ)

SLAVE

ADDRESS

BYTE

COUNT

S

W

A

S

R A

A

1

13 14 15

PEC A

DATA

32

A

P

Figure 47. Block Read from the EEPROM or RAM with PEC

Rev. 0 | Page 31 of 32

ADM1166

OUTLINE DIMENSIONS

6.10

6.00 SQ

5.90

0.30

0.25

0.18

PIN 1

INDICATOR

PIN 1

INDICATOR

31

30

40

1

0.50

BSC

*

4.70

EXPOSED

PAD

4.60 SQ

4.50

21

20

10

11

0.45

0.40

0.35

0.20 MIN

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-5

WITH EXCEPTION TO EXPOSED PAD DIMENSION.

Figure 48. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

6 mm × 6 mm Body, Very Thin Quad

(CP-40-7)

Dimensions shown in millimeters

1.20

9.00

0.75

0.60

0.45

MAX

BSC SQ

37

36

48

1

PIN 1

7.00

BSC SQ

TOP VIEW

(PINS DOWN)

0° MIN

1.05

1.00

0.95

0.20

0.09

7°

3.5°

0°

0.08 MAX

COPLANARITY

12

25

24

0.15

0.05

13

SEATING

PLANE

VIEW A

0.50

BSC

0.27

0.22

0.17

LEAD PITCH

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026ABC

Figure 49. 48-Lead Thin Plastic Quad Flat Package [TQFP]

(SU-48)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

CP-40-7

SU-48

ADM1166ACPZ

ADM1166ACPZ-REEL

ADM1166ASUZ

ADM1166ASUZ-REEL

EVAL-ADM1166TQEBZ

−40°C to +85°C

40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

48-Lead Thin Plastic Quad Flat Package [TQFP]

Evaluation Kit [TQFP]

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D09332-0-12/10(0)

Rev. 0 | Page 32 of 32


型号：	ADM1166ACPZ
厂家：	ADI
描述：	Super Sequencer with Margining Control and Nonvolatile Fault Recording 超序与余量控制和非易失故障记录
文件：	总32页 (文件大小：498K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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