ADM1028ARQ-REEL7_技术文档

LowCostPCTemperature

a

Preliminary Technical Data

MonitorandFanControlASIC

ADM1028

FEATURES

G E NE R AL D E S C R IP T IO N

T he ADM1028 is a low-cost temperature monitor and fan

controller for microprocessor-based systems. T he tem-

perature of a remote sensor diode may be measured, al-

lowing monitoring of processor temperature in single

processor systems. An on-chip temp sensor monitors

ambient system temperature.

On-Chip Tem perature Sensor

External Tem perature Measurem ent w ith Rem ote Diode

Interrupt and Overtem perature Outputs

Fault Tolerant Fan Control With Auto Hardw are Trip Point

Rem ote Reset and Pow er Dow n Functions

LDCM Support

Measured values can be read out via the System Manage-

ment Bus, and values for limit comparisons can be pro-

grammed in over the same serial bus.

System Managem ent Bus (SMBus) Com m unications

Standby Mode to Minim ize Pow er Consum ption

Lim it Com parison of all Monitored Values

T he ADM1028 also contains a DAC for fan speed con-

trol. An automatic hardware temperature trip point is pro-

vided and the fan will be driven to full speed if it is

exceeded.

APPLICATIONS

Netw ork Servers and Personal Com puters

Microprocessor-Based Office Equipm ent

Test Equipm ent and Measuring Instrum ents

Finally, the chip has remote reset and power down

functionality, allowing it to be remotely shutdown via the

SM Bu s.

T he ADM1028’s 3.0V to 5.5V supply voltage range, low

supply current, and SMBus make it ideal for a wide range

of applications. T hese include hardware monitoring

applications in PCs, electronic test equipment, and office

electronics.

FUNCTIO NAL BLO CK D IAGRAM

V_CC3AUX

5

V_CC3AUX

POWER ON

RESET

SDA

SCL

16

15

SERIAL BUS

INTERFACE

10k⍀

13

7

R_OFF

R_RST

REMOTE

FUNCTION

REGISTER

ANALOG

8

FAN_SPD/TEST_IN

OUTPUT REGISTER

AND 8-BIT DAC

ADDRESS

POINTER

REGISTER

RESET

AUXRST

3

6

VALUE AND

LIMIT

ADM1028

ALERT

STATUS

REGISTERS

FAN_SPD SHUTOFF &

R_OFF RESET

REGISTER

RST

D+

LIMIT

COMPARATORS

10

9

ADC

INTERRUPT

STATUS

ANALOG

SIGNAL

REGISTERS

CONDITIONING

D-

2.5V

V_CC3AUX

INT MASK

REGISTER

BANDGAP

REFERENCE

14

INT

10k⍀

THERMA/TEST_OUT

11

12

MASK

GATING

THERMB

CONFIGURATION

REGISTER

1

FAN_OFF

2

4

GPI

GND

REV. PrD 05/2000

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 781/ 329-4700

Fax: 781/ 326-8703

World Wide Web Site: http:/ / w w w.analog.com

Analog Devices, Inc., 1998

(T = T_MINto T , V = V to V , unless otherwise noted)

ADM1028–SPECIFICATIONS

A

MAX CC

MIN

MAX

P ARAMETER

Min

Typ

M a x

Units

Test Conditions

P O WER SUP P LY

Supply Voltage, V_CC

Supply Current, I_CC

3.0

3.30

1.4

32

5.5

2.0

< 100

V

m A

µA

Interface Inactive, ADC Active

Standby Mode

TEMP .-TO -D IGITAL CO NVERTER

Internal Sensor Accuracy

± 3

± 2

^oC

°C

^oC

+60^OCՅ T _AՅ +100^oC

Resolution

1

External Diode Sensor Accuracy

± 5

± 3

^oC

Resolution

1

^oC

Remote Sensor Source Current

60

3.5

90

5.5

130

7.5

µA

H igh Level (D+ = D- +0.65V)

Low Level (D+ = D- +0.65V)

T otal Monitoring Cycle T ime, t_c

1.0

1.4

s

ANALO G O UTP UT

Output Voltage Range

T otal Unadjusted Error, T UE

Full-Scale Error

0

2.5

± 3

V

%

L S B

m A

I_L= 2mA

± 1

± 2

Zero Error

N o Load

Monotonic by Design

Differential Non-Linearity, DNL

Integral Non-Linearity

Output Source Current

Output Sink Current

± 1

2

1

VO LTAGE MO NITO R TH RESH O LD S

Reset T hreshold, V_CC3AUX

Hysteresis

2.85

2.925

50

3.00

V

m V

Measured with Vcc falling.

R_RST O U T P U T

Reset Output Voltage, V_OL

0.3

V

I_SINK= 1.2mA;

V_CC= V_{T H}(MAX)

Reset Output Pulse Width, t_{R_RST #}

V_CCto Reset Delay, t_D

125

7

4000

µs

20

10

THERMA O U T P U T

THERMA pull-up resistance

13

k Ω

–2–

REV. PrD

Preliminary Technical Data

ADM1028

Specifications(Continued)

P ARAMETER

Min

Typ

M a x

Units

Test Conditions/Com m ents

D IG IT AL O UT P UT THERMA/T E ST _O UT ,

R_OFF

Output High Voltage, V_OH

Output Low Voltage, V_OL

2.4

V

I_OUT= 3.0mA

0.4

O P EN-D RAIN D IGITAL O UTP UTS

(INT, THERMB, FAN_OFF, R_RST)

Output Low Voltage, V_OL

0.4

1

V

µA

I_OUT= -3.0mA

V_OUT= V_CC

High Level Output Leakage Current, I_OH

0.1

O P EN-D RAIN SERIAL D ATA

BUS O UTP UT (SD A)

Output Low Voltage, V_OL

0.4

1

V

µA

I_OUT= -3.0mA

V_OUT= V_CC

High Level Output Leakage Current, I_OH

SERIAL BUS D IGITAL INP UTS

(SCL, SD A)

Input High Voltage, V_IH

Input Low Voltage, V_IL

Input Leakage Current

Hysteresis

2.1

V (min)

V (max)

µA

0.8

± 5

500

m V

D IGITAL INP UT LO GIC LEVELS

(FAN_SP D /TEST_IN, GP I)

Input High Voltage, V_IH

2.2

-1

V

Input Low Voltage, V_IL

0.8

D IGITAL INP UT LEAKAGE CURRENT

(ALL D IGITAL INP UTS)

Input High Current, I_IH

Input Low Current, I_IL

Input Capacitance, C_IN

-0.005

0.005

5

µA

p F

V_IN= V_CC

V_IN= 0

1

SERIAL BUS TIMING

Clock Frequency, f_SCLK

Bus Free T ime, t_BUF

Start Setup T ime, t_{SU;ST A}

Start Hold T ime, t_{HD;ST A}

Stop Condition Setup T ime, t_{SU;ST O}

SCL Low T ime, t_LOW

SCL High T ime, t_HIGH

SCL, SDA Rise T ime, t_r

SCL, SDA Fall T ime, t_f

Data Setup T ime, t_SU;DAT

Data Hold T ime, t_HD;DAT

100

kH z

µs

ns

See Figure 1

4.7

4.0

4.7

4.0

1000

300

250

300

NOTES

¹T ypicals are at T _A=25°C and represent most likely parametric norm. Standby current typ is measured with V_CC= 3.3V.

³T iming specifications are tested at logic levels of V_IL= 0.8 V for a falling edge and V_IH= 2.2 V for a rising edge.

REV. PrD

–3–

Preliminary Technical Data

T H E R M AL C H AR AC T E R IS T IC S

16-Pin QSOP Package:

θ_JA105°C/Watt, θ_JC= 39°C/Watt

ADM1028

AB SO LUT E M AXIM UM RAT ING S*

Positive Supply Voltage (V_{C C}

Voltage on Digital Inputs except T herm

)

6.5 V

-0.3V to 6.5V

=

Voltage on T herm pin

Voltage on Any other Input

or Output Pin

Input Current at any pin

Package Input Current

M aximum Junction T emperature (T _Jmax)

Storage T emperature Range

Lead T emperature

-0.3V to Vcc +0.3V

-0.3V to V_CC+0.3V

O RD ERING GUID E

T em per atu r e

Ran ge

AD M 1028ARQ 0°C to +100°C

P ackage

D escr ip tion

P ackage

O p tion

± 5m A

± 20m A

150 °C

–65°C to +150°C

Model

16-Pin QSOP

Package

RQ-16

Soldering 10 sec

IR Reflow Peak temperature

ESD Rating (H uman Body Model)

+ 300°C

+ 220°C

4000 V

*Stressesabove those listed under “Absolute Maximum Ratings” maycause permanent

damage to the device. T his is a stress rating only; functional. Operation ofthe device

at these or anyother conditionsabove those indicated in the operationalsection ofthis

specification is not implied. Exposure to absolute maximum rating conditions for

extended periods mayaffect device reliability.

AD M 1028 P INO U T

SDA

SCL

FAN_OFF

GPI

1

2

16

15

14

13

12

11

3

4

5

6

7

AUXRST

GND

INT

R_OFF

ADM1028

TOP VIEW

V

THERMB

CC3AUX

(Not to Scale)

RST

R_RST

THERMA/NTEST_OUT

10 D+

D-

FAN_SPD/NTEST_IN

9

8

t

LOW

F

HD;STA

R

SCL

t

HD;STA

t

SU;STO

HD;DAT

t

SU;STA

t

HIGH

SU;DAT

SDA

t

BUF

S

P

S

Figure 1. Diagram for Serial Bus Tim ing

–4–

REV. PrD

Preliminary Technical Data

ADM1028

P IN FUNCTIO N D ESCRIP TIO N

P IN NO . MNEMO NIC

D E SC RIP TIO N

1

FAN_OFF

Digital Output (Open Drain) Fan Off Request. When asserted low this indicates a

request to shut the fan off independent of the FAN_SPD output. When negated

(output FET off) it indicates that the fan may be turned on.

2

GPI

Digital Input (12V tolerant). This pin is a general purpose logic input with 12V

tolerance. It can be programmed as an active high or active low input that sets bit 4

of the Interrupt Status Register. A voltage >2.2V on this pin, represents a logic “1”

while a floating condition is interpreted as logic “0”.

3

4

5

6

AUXRST

GND

Digital Input. This pin can be driven low as an input to reset the ADM1028.

GROUND. Power and signal ground.

V_CC3AUX

RST

POWER +3.3Vaux. Power source and voltage monitor input for power on reset.

Digital Input. T his pin can be pulled low externally to indicate to the ADM1028

that the main system power has been removed. T he ADM1028 will shut off the

FAN_SPD output and reset its R_OFF output.

7

8

R_RST

Digital Output (Open drain). T his pin is a remote reset output which pulses low

on receipt of a specific SMBus message.

FAN _SPD /T EST _IN

Analog Output/Test Input. An active-high input that enables NAND board-

level connectivity testing. Refer to section on NAND testing.

Used as an analog output for fan speed control when NAND test is not selected.

9

D -

Remote Thermal Diode Negative Input. This is the negative input (current sink)

from the remote thermal diode. This also serves as the negative input into the A/D.

10

11

D +

Remote Thermal Diode Positive Input. This is the positive input (current source)

from the remote thermal diode. This serves as the positive input into the A/D.

THERMA/T EST _OUT Digital Output (Open Drain with integrated V_CC3AUXpull-up). An active low thermal

overload output that indicates a violation of a temperature set point (over

-temperature). The fan is on full-speed whenever this pin is asserted low. Acts as the

output of the NAND Tree when the ADM1028 is in NAND Tree Test Mode.

12

13

THERMB

R_OFF

Digital Output (Open Drain). This pin is a second THERM signal. It can be used

to drive external circuitry with a different external pull-up supply rail.

Digital Output or Open Drain with integrated V_CC3AUXpull-up. Remote off (power

down) output. This pin is driven high on receipt of a specific SMBus message. The

pin (and its associated register bit) remain high until the RST input is asserted low.

14

INT

Digital Output (Open Drain), System Interrupt Output. This signal indicates a

violation of a set trip point. The output is enabled when Bit 1 of the Configuration

Register is set to 1. The default state is disabled.

15

16

SC L

SDA

Digital Input SMBus Clock

Digital I/O(Open Drain) SMBus bi-directional Data

REV. PrD

–5–

Preliminary Technical Data

ADM1028

AWAITING

DATA

Figure 5. Pentium III Tem perature Measurem ent vs.

ADM1028 Reading

Figure 2. Tem perature Error vs. PC Board Track Resistance

Figure 6. Tem perature Error vs. Capacitance Between D+

and D-

Figure 3. Tem perature Error vs. Power Supply Noise

Frequency

AWAITING

DATA

AWAITING

DATA

Figure 7. Standby Current vs. Clock Frequency

Figure 4. Tem perature Error vs. Com m on-Mode Noise

Frequency

–6–

REV. PrD

Preliminary Technical Data

ADM1028

AWAITING

DATA

Figure 10. Power-up Reset vs. Tem perature

Figure 8. Tem perature Error vs. Differential-Mode Noise

Frequency

AWAITING

DATA

Figure 9. Standby Supply Current vs. Supply Voltage

REV. PrD

–7–

Preliminary Technical Data

ADM1028

SCL remains high. T his indicates that an address/data

stream will follow. All slave peripherals connected to

the serial bus respond to the ST ART condition, and

shift in the next 8 bits, consisting of a 7-bit address

(MSB first) plus a R/W bit, which determines the direc-

tion of the data transfer, i.e. whether data will be writ-

ten to or read from the slave device.

F U NC T IO NAL D E S C R IP T IO N

G E NE R AL D E S C R IP T IO N

T he ADM1028 is a low-cost temperature monitor and

fan controller for microprocessor-based systems. T he

temperature of a remote sensor diode may be measured,

allowing monitoring of processor temperature in a single-

processor system. An on-chip temperature sensor allows

monitoring of system ambient temperature.

T he peripheral whose address corresponds to the trans-

mitted address responds by pulling the data line low

during the low period before the ninth clock pulse,

known as the Acknowledge Bit. All other devices on the

bus now remain idle whilst the selected device waits for

data to be read from or written to it. If the R/W bit is a

0 then the master will write to the slave device. If the

R/W bit is a 1 the master will read from the slave de-

vice.

Measured values can be read out via the serial System

Management Bus, and values for limit comparisons can be

programmed in over the same serial bus.

T he ADM1028 also contains a DAC for fan speed con-

trol. An automatic hardware temperature trip point is

provided for fault tolerant fan control and the fan will be

driven to full speed if this is exceeded. T wo interrupt

outputs are provided, which will be asserted if the software

or hardware limits are exceeded.

2. Data is sent over the serial bus in sequences of 9 clock

pulses, 8 bits of data followed by an Acknowledge Bit

from the slave device.T ransitions on the data line must

occur during the low period of the clock signal and

remain stable during the high period, as a low to high

transition when the clock is high may be interpreted as

a ST OP signal. T he number of data bytes that can be

transmitted over the serial bus in a single READ or

WRIT E operation is limited only by what the master

and slave devices can handle.

Finally, the chip has remote reset and shutdown

capabilities.

INT E RNAL RE GIST E RS O F T H E AD M1028

A brief description of the ADM1028's principal internal

registers is given below. More detailed information on the

function of each register is given in T ables 4 to 10.

3. When all data bytes have been read or written, stop

conditions are established. In WRIT E mode, the master

will pull the data line high during the 10th clock pulse

to assert a ST OP condition. In READ mode, the mas-

ter device will override the acknowledge bit by pulling

the data line high during the low period before the 9th

clock pulse. T his is known as No Acknowledge. T he

master will then take the data line low during the low

period before the 10th clock pulse, then high during the

10th clock pulse to assert a ST OP condition.

Configuration Register: Provides control and configuration.

Address Pointer Register: This register contains the address

that selects one of the other internal registers. When writing to

the ADM1028, the first byte of data is always a register ad-

dress, which is written to the Address Pointer Register.

Inter r upt (INT) Status Register: T his register provides

status of each Interrupt event.

Inter r upt (INT) Mask Register: Allows masking of indi-

vidual interrupt sources.

Any number of bytes of data may be transferred over the

serial bus in one operation, but it is not possible to mix

read and write in one operation, because the type of opera-

tion is determined at the beginning and cannot subse-

quently be changed without starting a new operation.

Value and Lim it Register s: T he results of temperature

measurements are stored in these registers, along with

their limit values.

Analog O utput Register : T he code controlling the analog

output DAC is stored in this register.

In the case of the ADM1028, write operations contain

either one or two bytes, and read operations contain one

byte, and perform the following functions:

Aler t Status Register: Indicates the status of the THERM

signal and GPI pin.

T o write data to one of the device data registers or read

data from it, the Address Pointer Register must be set so

that the correct data register is addressed, then data can be

written into that register or read from it. T he first byte of

a write operation always contains an address that is stored

in the Address Pointer Register. If data is to be written to

the device, then the write operation contains a second data

byte that is written to the register selected by the address

pointer register.

Rem ote Function Register : T his register allows control of

the R_RST and R_OFF outputs.

SE RIAL BUS INT E RF AC E

Control of the ADM1028 is carried out via the serial bus.

T he ADM1028 is connected to this bus as a slave device,

under the control of a master device, e.g. the 810 chipset.

T he ADM1028 has a 7-bit serial bus address. When the

device is powered up, it will do so with a default serial bus

address. T he SMBus address for the ADM1028 is

0101110 binary.

T his is illustrated in figure 11a. T he device address is sent

over the bus followed by R/W set to 0. T his is followed by

two data bytes.T he first data byte is the address of the

internal data register to be written to, which is stored in

the Address Pointer Register. T he second data byte is the

data to be written to the internal data register.

T he serial bus protocol operates as follows:

1. T he master initiates data transfer by establishing a

ST ART condition, defined as a high to low transition

on the serial data line SDA whilst the serial clock line

When reading data from a register there is only one

possibility:

–8–

REV. PrD

Preliminary Technical Data

ADM1028

output of this sensor and outputs the temperature data in

8-bit two's complement format. T he format of the tem-

perature data is shown in T able 2.

1. T he serial bus address is written to the device along

with the address pointer register value. T he ADM1028

should then acknowledge the write by pulling SDA low

during the 9th clock pulse. T he master does not

generate a ST OP condition but issues a new ST ART

condition. T he serial bus address is again sent but with

the R/W bit high indicating a READ operation. T he

ADM1028 will then return the data from the selected

register, and a No Acknowledge is generated to signify

the end of the read operation. T he master will then

initiate a ST OP condition to end the transaction and

release the SMBus.

E XT E RNAL T E M P E RAT U RE M E ASU RE M E NT

T he ADM1028 can measure the temperature of an exter-

nal diode sensor or diode-connected transistor, connected

to pins 9 and 10.

Pins 9 and 10 are a dedicated temperature input channel.

T he default functions of pins Pins 11 and 12 are as

THERM outputs to indicate overtemperature conditions.

T he forward voltage of a diode or diode-connected tran-

sistor, operated at a constant current, exhibits a negative

temperature coefficient of about -2mV/^oC.Unfortunately,

the absolute value of V_be, varies from device to device, and

individual calibration is required to null this out, so the

technique is unsuitable for mass-production.

In figures 11a & 11b, the serial bus address is shown as

the default value 01011(A1)(A0), where A1 and A0 are

the lowest two bits of the device SMBus address.

T E M P E R AT U R E M E ASU R E M E NT SYST E M

INT E R NAL T E M P E R AT U R E M E ASU R E M E NT

T he technique used in the ADM1028 is to measure the

change in V_bewhen the device is operated at two different

currents.

T he ADM1028 contains an on-chip bandgap temperature

sensor. T he on-chip ADC performs conversions on the

T his is given by:

1

9

1

9

SCL

D 6

D 2

0

1

0

1

A1

A0

D7

D 5

D 4

D 3

D 1

SDA

R/W

D 0

START BY

MASTER

ACK. BY

ADM1028

FRAM E

1

FRAM E

2

SERIAL BUS ADDRESS BYTE

ADDRESS POINTER REGISTER BYTE

1

9

SCL (CONTINUED)

SDA (CONTINUED)

D 4

D 3

D 2

D 1

D 7

D 5

D 0

D 6

ACK. BY

STOP BY

MASTER

ADM1028

FRAM E

3

DATA BYTE

Figure 11a. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register

1

9

1

9

SCL

D 6

D 2

SDA

0

1

0

1

A1

A0

R/W

D7

D 5

D 4

D 3

D 1

D 0

START BY

ACK. BY

MASTER

ADM1028

FRAM E

1

FRAM E

2

SERIAL BUS ADDRESS BYTE

ADDRESS POINTER REGISTER BYTE

9

1

0

9

1

SCL

SDA

D 6

D 0

D 5

D 2

1

0

1

A1

A0

R/W

D7

D 4

D 3

D 1

START BY

MASTER

ACK. BY

ADM1028

NO ACK.

STOP BY

BY M ASTER MASTER

FRAME 3

SERIAL BUS ADDRESS BYTE

FRAME 4

DATA BYTE FROM ADM1028

Figure 11b. Reading Data from the ADM1028

–9–

REV. PrD

Preliminary Technical Data

ADM1028

+100 °C

+125 °C

+127 °C

0110 0100

0111 1101

0111 1111

∆V_be= KT /q x ln(N)

where:

K is Boltzmann’s constant

q is charge on the carrier

T is absolute temperature in Kelvins

N is ratio of the two currents

T o prevent ground noise interfering with the measure-

ment, the more negative terminal of the sensor is not ref-

erenced to ground, but is biased above ground by an

internal diode at the D- input. If the sensor is used in a

very noisy environment, a capacitor of value up to 1000pF

may be placed between the D+ and D- inputs to filter the

noise.

Figure 12 shows the input signal conditioning used to

measure the output of an external temperature sensor.

T his figure shows the external sensor as a substrate tran-

sistor, provided for temperature monitoring on some mi-

croprocessors, but it could equally well be a discrete

transistor.

T o measure ∆V_be, the sensor is switched between operat-

ing currents of I and N x I. T he resulting waveform is

passed through a 65kHz lowpass filter to remove noise,

thence to a chopper-stabilized amplifier that performs the

functions of amplification and rectification of the wave-

form to produce a DC voltage proportional to ∆V_be. T his

voltage is measured by the ADC to give a temperature

output in 8-bit two’s complement format. T o further re-

duce the effects of noise, digital filtering is performed by

averaging the results of 16 measurement cycles. An exter-

nal temperature measurement takes nominally 9.6ms.

If a discrete transistor is used, the collector will not be

grounded, and should be linked to the base. If a PNP

transistor is used the base is connected to the D- input

and the emitter to the D+ input. If an NPN transistor is

used, the emitter is connected to the D- input and the

base to the D+ input.

TABLE 2. TE MP E RATURE D ATA FO RMAT

Tem per atur e

D igital O utput

LAYO U T C O NS ID E R AT IO NS

-128 °C

-125 °C

-100 °C

-75 °C

-50 °C

-25 °C

-1 °C

1000 0000

1000 0011

1001 1100

1011 0101

1100 1110

1110 0111

1111 1111

0000 0000

0000 0001

0000 1010

0001 1001

0011 0010

0100 1011

Digital boards can be electrically noisy environments, and

care must be taken to protect the analog inputs from

noise, particularly when measuring the very small voltages

from a remote diode sensor. T he following precautions

should be taken:

1. Place the ADM1028 as close as possible to the remote

sensing diode. Provided that the worst noise sources

such as clock generators, data/address buses and CRT s

are avoided, this distance can be 4 to 8 inches.

2. Route the D+ and D- tracks close together, in parallel,

with grounded guard tracks on each side. Provide a

ground plane under the tracks if possible.

0 °C

+1 °C

+10 °C

+25 °C

+50 °C

+75 °C

3. Use wide tracks to minimize inductance and reduce

noise pickup. 10 mil track minimum width and spacing

is recommended.

V

DD

I

BIAS

N x I

V

D+

D-

O UT+

TO ADC

REMOTE

SENSING

TRANSISTOR

V

O UT-

BIAS

DIODE

LOWPASS FILTER

f

= 65kHz

c

Figure 12. ADM1028 Signal Conditioning

–10–

REV. PrD

Preliminary Technical Data

ADM1028

4. T he op-amp may be powered from the +V rail alone.

If it is powered from +V then the input common-mode

range should include ground to accommodate the

minimum output voltage of the DAC, and the output

voltage should swing below 0.6V to ensure that the

transistor can be turned fully off.

GN D

10 mil

10 mil.

10 mil

10 mil.

10 mil

10 mil.

D+

D-

5. In all these circuits, the output transistor must have an

I_CMAXgreater than the maximum fan current, and be

capable of dissipating power due to the voltage

dropped across it when the fan is not operating at full-

speed.

GN D

Figure 13. Arrangem ent of Signal Tracks

6. If the fan motor produces a large back e.m.f when

switched off, it may be necessary to add clamp diodes

to protect the output transistors in the event that the

output goes from full-scale to zero very quickly.

4. T ry to minimize the number of copper/solder joints,

which can cause thermocouple effects. Where copper/

solder joints are used, make sure that they are in both

the D+ and D- path and at the same temperature.

T hermocouple effects should not be a major problem as

1^oC corresponds to about 200µV, and thermocouple

voltages are about 3µV/^oC of temperature difference.

Unless there are two thermocouples with a big tem-

perature differential between them, thermocouple volt-

ages should be much less than 200µV.

Figure 14c shows how the FAN_OFF signal may be used

(with any of the control circuits) to gate the fan on and off

independent of the value on the FAN_SPD/T EST _IN

pin.

F AULT T O LE RANT F AN C O NT RO L

5. Place 0.1µF bypass and 2200pF input filter capacitors

T he ADM1028 incorporates a fault tolerant fan control

capability that is tied to operation of the THERMA,

THERMB outputs. It can override the setting of the ana-

log output and force it to maximum to give full fan speed

in the event of a critical overtemperature problem, even if,

for some reason, this has not been handled by the system

software.

close to the ADM1028.

6. If the distance to the remote sensor is more than 8

inches, the use of twisted pair cable is recommended.

T his will work up to about 6 to 12 feet.

7. For really long distances (up to 100 feet) use shielded

twisted pair such as Belden # 8451 microphone cable.

Connect the twisted pair to D+ and D- and the shield

to GND close to the ADM1028. Leave the remote end

of the shield unconnected to avoid ground loops.

T here are two temperature set point registers that will

activate the fault tolerant fan control. One of these limits

is programmable by the user and one is a hardware (read-

only) register that will operate if the user does not pro-

gram any limit. T he fault tolerant fan control is activated

if a limit is exceeded for three or more consecutive read-

ings. T hese limits are separate from the normal high and

low temperature limits for the INT output, which do not

affect the fault tolerant fan control or THERM outputs.

A hardware limit of 100^oC is programmed in to the

register at address 18h, for the remote diode Default

THERM limit. T his is the default limit and the analog

output will be forced to full-scale if the remote sensor

reads more than 100^oC. T his makes the fault tolerant fan

control failsafe in that it will operate at this temperature

even if the user has programmed no other limit, or in the

event of a software malfunction. Similarly, the Default

Internal T emp THERM limit held in register 17h, forces

the analog output full-scale if the ambient temperature

measured is more than 70^oC.

Because the measurement technique uses switched current

sources, excessive cable and/or filter capacitance can affect

the measurement. When using long cables, the filter ca-

pacitor C1 may be reduced or removed. In any case the

total shunt capacitance should not exceed 1000pF.

Cable resistance can also introduce errors. 1Ω series resis-

tance introduces about 0.5^oC error.

ANALO G O U T P U T

T he ADM1028 has a single analog output (FAN_SPD)

from an unsigned 8 bit DAC which produces 0 - 2.5V.

T he analog output register defaults to 00 during power-on

reset, which produces minimum fan speed. T he analog

output may be amplified and buffered with external cir-

cuitry such as an op-amp and transistor to provide fan

speed control.

Suitable fan drive circuits are given in Figures 14a to 14e.

When using any of these circuits, the following points

should be noted:

T he user may override the default limits by programming

a new limit into register 14h for the remote sensor and a

new limit into register 13h for the internal sensor. T he

default value in register 14h is the same as for the read-

only register (100^oC), but it may be programmed with

higher or lower values.

1. All of these circuits will provide an output range from

zero to almost +V_FAN

.

2. T o amplify the 2.5V range of the analog output up to

+V_FAN, the gain of these circuits needs to be set as

shown.

Once registers 13h and 14h have been programmed, or if

the defaults are acceptable, bit 3 of the configuration

3. Care must be taken when choosing the op-amp to en-

sure that its input common-mode range and output

voltage swing are suitable.

REV. PrD

–11–

Preliminary Technical Data

ADM1028

+5 V

+12V

R3

R4

100k⍀

100k

⍀

Q3

F A N _ S P D

-

NDT452P

Q 1

N D T 45 2 P

A D 8 54 1

+

R2

R 2

3.9k⍀

FAN_SPD

1 5k ⍀

5 V

F A N

R 1

Q1/Q2

R1

R5

1 0k ⍀

MBT3904

DUAL

1k⍀

5k⍀

Figure 14d. Discrete 12V Fan Drive Circuit with P-Channel

MOSFET, SIngle Supply

Figure 14a. 5V Fan Circuit with Op-Amp

+12V

Q4

R4

FAN_SPD

BD132

TIP32A

1k⍀

-

R5

100k⍀

Q1

100k⍀

Q3

BC556

2N3906

AD8519

BD136

2SA968

R3

+

1k⍀

R2

39k⍀

3.9k⍀

FAN_SPD

R1

Q1/Q2

MBT3904

DUAL

10k⍀

R3

R6

R1

100⍀

5k⍀

1k⍀

Figure 14b. 12V Fan Circuit with Op-Am p and PNP Transistor

Figure 14e. Discrete 12V Fan Drive Circuit with Bipolar

Output Single Supply

+12V

R3

FAN_S PD

100k⍀

-

Q 1

AD8519

NDT452P

+

R2

39k⍀

+3.3V

R1

10k⍀

R4

1k⍀

Q 2

FAN_O FF

M M FT3055V

Figure 14c. 12V Fan Circuit with Op-Am p and P-Channel

MOSFET

–12–

REV. PrD

Preliminary Technical Data

register must be set to ‘1’. T his bit is a write-once bit that

can only be written to ‘1’ and it has two effects:

ADM1028

no longer generate an interrupt. However, the bits in the

status register will be set as normal.

1. it makes the values in registers 13h and 14h the active

limits, and disables read-only registers 17h and 18h.

INT E R R U P T C LE AR ING

2. it locks the data into registers 13h and 14h, so that it

cannot be changed until the lock bit is reset, either

when AUXRST or RST is asserted, or a Power On

Reset occurs.

T he Interrupt Status Register reflects out-of-limit

conditions. T he Status bits may be individually cleared by

writing a “1” to the appropriate status bits. Writing a “1”

to bits 1 & 2 cause software interrupts to be generated. Bit

4 (GPI) of the Interrupt Status Register reflects the

current status of the GPI pin, and so cannot be cleared by

writing to this bit.

Once the hardware override of the analog output is trig-

gered, it will only return to normal operation after three

consecutive measurements that are 5 degrees lower than

the set limit.

T he INT output is cleared with the INT_Enable bit,

which is Bit 1 of the Configuration Register, without

affecting the contents of the Interrupt (INT) Status

Registers.

Whenever FAN_SPD output is forced to full-scale, the

FAN_OFF output is negated.

T H E AD M 1028 INT E RRUP T SYST E M

T he ADM1028 has three interrupt outputs, INT,

THERMA and THERMB. T hese have different functions.

INT responds to violations of software programmed

temperature limits and its interrupt sources are maskable,

as described in more detail later. Interrupts and status bits

are only set if a limit is exceeded for at least 3 consecutive

conversions.

THERM O U T P U T S

T he THERMA, THERMB signals are functionally

identical. T hese system overtemperature outputs will

assert together when an overtemperature is detected.

THERMA (pin 11) is an open drain digital output which

has an integrated pullup resistor to V_CC3AUX. THERMB is

an open drain digital output, intended to drive external

circuitry operating at a different supply voltage level.

Operation of the INT output is illustrated in Figure 15.

Assuming that the temperature starts off within the pro-

grammed limits and that temperature interrupt sources are

not masked, INT will go low if the temperature measured

by the external sensor goes outside the programmed high

or low temperature limit for the sensor. INT also goes low

whenever THERM is low.

THERM O P E R AT ING M O D E

THERM only responds to the “hardware” temperature

limits at addresses 14h and 18h, not to the software pro-

grammed limits. T he function of these registers was

described earlier with regard to fault tolerant fan speed

control.

o

100

90

80

70

60

50

40

C

o

HARDW ARE

TRIP POINT

HIGH LIMIT

o

5

Temp.

TEMP

LOW LIMIT

THERM

*

PREVIOUS FAN

SPEED VALUE

PROGRAM M ED

VALUE

INT

FFh

*INT cleared by

software

ANALOG

OUTPUT

T

interrupt

HIGH

logic re-armed

here

Figure 16. Operation of THERM Outputs

Figure 15. Operation of INT Output

THERM will go low if the hardware temperature limit is

exceeded for three consecutive measurements. It will re-

main low until the temperature falls 5 degrees below the

limit for three consecutive measurements. While THERM

is low, the analog output will go to FFh to boost a con-

trolled fan to full speed and FAN_OFF will be negated.

Once the interrupt has been cleared, it will not be re-

asserted even if the temperature remains outside the limit

previously exceeded. H owever, INT will be re-armed if

the temperature falls back within the set limits for 3

consecutive conversions. Once the INT function has been

re-armed, it will then be re-asserted once a limit is

exceeded for 3 consecutive conversions.

When the Fault T olerant Fan Control state is exited, the

analog FAN_SPD output returns to its previously pro-

grammed value, which may have been changed during the

time that the FAN_SPD output was forced to FFh.

INT E R R U P T M AS KING

Any of the bits in the Interrupt Status Register can be

masked out by setting the corresponding mask bit in the

Interrupt Mask Register. T hat interrupt source will then

REV. PrD

–13–

Preliminary Technical Data

ADM1028

INT E R R U P T S T R U C T U R E

P O WE R - O N R E SE T

T he Interrupt Structure of the ADM1028 is shown in

more detail in Figure 17. As each measurement value is

obtained and stored in the appropriate value register, the

value and the limits from the corresponding limit registers

are fed to the high and low limit comparators. T he result

of each comparison (1 = out of limit, 0 = in limit) is

routed to the corresponding bit input of the Interrupt Sta-

tus Register via a data demultiplexer, and used to set that

bit high or low as appropriate.

When the ADM1028 is powered up, it will initiate a

power-on reset sequence when the supply voltage V_CC3AUX

rises above the power-on reset threshold, with registers

being reset to their power-on values. Normal operation

will begin when the supply voltage rises above the reset

threshold. Registers whose power on values are not shown

have power on conditions that are indeterminate (this

includes the Value and Limit Registers). In most applica-

tions, usually the first action after power on would be to

write limits into the Limit Registers.

T he Interrupt Mask Register has bits corresponding to

each of the Interrupt Status Register Bits. Setting an Inter-

rupt Mask Bit high forces the corresponding Status Bit

output low, whilst setting an Interrupt Mask Bit low al-

lows the corresponding Status Bit to be asserted. After

masking, the status bits are all OR'd together to produce

the INT output, which will pull low if any unmasked sta-

tus bit goes high, i.e. when any measured value goes out

of limit.

Power on reset clears or initializes the following registers

(the initialized values are shown in Table 4):

- C onfiguration Register

- Interrupt Status Register

- Interrupt Mask Register

- Analog Output Register

- Programmable T rip Point Registers

The INT output is enabled when Bit 1 of the Configuration

Register (INT_Enable) is high.

T he ADM1028 can also be reset by taking AUXRST low

as an input. T he above-mentioned registers will be reset

to their default values and the ADC will remain inactive

as long as AUXRST is below the reset threshold.

T aking the RST pin low will cause the following registers

to be reset.

G E NE RAL P URP O SE LO G IC INP UT (G P I)

Pin 2 is used as a general purpose logic input with 12V

tolerance. T he GPI input may be programmed to be

active high or active low by clearing or setting bit 6 of the

Configuration Register. T he default value is active high.

Bit 4 of the Interrupt Status register follows the state (or

inverted state) of GPI and will generate an interrupt when

it is set to 1, like any other input to the Interrupt Status

Register. However, the GPI bit is not latched in the Status

Register and always reflects the current state (or inverted

state) of the GPI input. If it is 1 it will not be cleared by

reading the Status Register.

-

Bit 3 of the Configuration Register (Programmable

THERM Limit Lock Bit)

-

DAC Output, Fan speed

INT. TEMP

0

1

2

3

4

5

6

7

FLAG1

HIGH

1 = OUT

LIMIT

FLAG2

INT. THERM

GPI

OF LIMIT

FROM VALUE

AND LIMIT

VALUE

EXT. TEMP

EXT. THERM

DIODE FAULT

REGISTERS

MASK GATING X 8

LOW

LIMIT

STATUS

BIT

INT

MASK

BIT

MASKING DATA

FROM BUS

INT ENABLE

8 MASK BITS

(SAME BIT ORDER AS

STATUS REGISTER)

CONFIGURATION

REGISTER

Figure 17. ADM1028 Interrupt Register Structure

–14–

REV. PrD

Preliminary Technical Data

ADM1028

INIT IALIZAT IO N (SO F T RE SE T )

TABLE 3. TE ST VE C TO RS

RST AUXRST GPI SDA

Soft reset performs a similar, but not identical, function to

power on reset. T he Limit Registers remain unchanged.

SCL

THERMA

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Soft reset is accomplished by setting Bit 4 of the Configu-

ration Register high. T his Bit automatically clears after

being set.

Unlike clearing INT , where the temperature must fall

back within the set limits for three conversions before the

INT function is rearmed, the soft reset allows INT to be

pulled low immediatey after the soft reset.

NAND T RE E T E ST

A NAND tree is provided in the ADM1028 for Automated

T est Equipment (AT E) board level connectivity testing.

T he device is placed into NAND tree test mode by

powering up with pin FAN_SPD/T EST _IN (pin 8) held

high. T his pin is sampled and its state at power-up is

latched. If it is connected high, then the NAND tree test

mode is invoked. NAND tree test mode will only be ex-

ited once the ADM1028 is powered down.

In NAND tree test mode, all digital inputs may be tested

as illustrated in T able 3. THERMA/T EST _OUT will

become the NAND tree output pin.

T he structure of the NAND T ree is shown in Figure 21.

T o perform a NAND T ree test, all pins are initially

driven low. T he test vectors set all inputs low, then one-

by-one toggles them high (keeping them high). Exercising

the test circuit with this “walking one” pattern, starting

with the input closest to the output of the tree, cycling

towards the farthest, causes the output of the tree to toggle

with each input change. Allow for a typical propagation

delay of 500ns.

PO W ER-O N

RESET

Clk

Q

FAN_SPD/

TEST_IN

D

LATCH

ENABLE

RST

AUXRST

G PI

THERM A/

SDA

TEST_O UT

SCL

Figure 21. NAND Tree

C O NF IG U R ING T H E INT E R R U P T

On power-up, the Interrupt functionality of the device is

disabled. T he Configuration register (0x40) must be writ-

ten to, in order to enable the Interrupt output. T he

INT_Enable bit (bit 1) of the Register should be set to 1.

REV. PrD

–15–

Preliminary Technical Data

ADM1028

TABLE 4. AD M1028 RE GISTE RS

Register Nam e

Addr ess A7 - A0 in hex

C om m ents

Value Registers

Company ID

0x14 – 0x38

0x3E

See T able 5

T his location will contain the company identification

number. T his register is read only.

Revision

0x3F

T his location will contain the revision number of the

part in the lower four bits of the register [3:0]. T he

upper four bits reflect the AD M 1028 Version N umber

[7:4]. T he first version is 1101. T he next version of

ADM1028 would be 1110, etc. For instance, if the

stepping were A0 and this part is a ADM1028, then

this register would read 1101 0000. T his register is

read only.

C onfiguration Register

Interrupt Status Register

Interrupt Mask Register

Manufacturer T est

0x40

See T able 6. Power on value = 0010 0001

See T able 7. Power on value = 0000 0000

See T able 8. Power on value = 0000 0000

0x41

0x43

0x44 - 0x4A

T est Registers for manufacturer’s use only. Do not

write to these registers.

Remote function

Alert Status

0x4B

0x4C

See T able 9. Power on value = 0000 0000

See T able 10. Power on value = 0000 0000

TABLE 5. RE GISTE RS 0X13- 0X3A VALUE RE GISTE RS

Address Read/Write D escription

0x13

Read/Write

Programmable Internal T herm Automatic T rip Point - default 127 degrees C.

T his register can only be written to if the write once bit in the configuration register

(0x40, bit 3) has not been set.

0x14

Read/Write

Programmable Remote T hermal Diode Automatic T rip Point - default 100 degrees C.

T his register can only be written to if the write once bit in the configuration register

(0x40, bit 3) has not been set.

0x15

0x17

Read/Write

Read Only

T est register for manufacturer’s use only. Do not write to this register

Default Internal T herm Automatic T rip Point - default 70 degrees C

Cannot be changed. Disabled when bit 3 of Config register is set

0x18

Read Only

Default Remote T hermal Diode Automatic T rip Point - default 100 degrees C

Cannot be changed. Disabled when bit 3 of Config register is set

0x19

0x26

0x27

0x37

0x38

0x39

0x3A

Read/Write

Read Only

Read/Write

Analog Output, FAN_SPD (defaults to 0x00h)

External Remote T emperature Value

Internal T emperature Value

External Remote T emperature H igh Limit

External Remote T emperature Low Limit

Internal T emperature High Limit - default 127 degrees C.

Internal T emperature Low Limit

–16–

REV. PrD

Preliminary Technical Data

ADM1028

P O WE R O N D E FAULT <7:0> = 21H

TABLE 6. RE GISTE R 0X40

C O NF IG U R AT IO N R E G IS T E R

BIT

Nam e

R/W

D escription

0

ST ART

Read/Write

Setting this bit to a “1” enables startup of ADM1028; clearing this bit

to “0” places ADM1028 in standby mode.

At startup temperature monitoring and limit checking functions begin.

Note, all limit values should be programmed into ADM1028 prior to

using the standard thermal interrupt mechanism based upon high and

low limits. (Powerup default=1)

1

INT Enable

Read/Write

Read Only

Setting this bit to a “1” enables the INT output.

1=Enabled 0=Disabled (Powerup Default = 0)

2

3

Reserved

Reserved (default = 0)

Program m able

T herm

Limit Lock

Bit

Read/Write Once Setting this bit to a “1” will lock in the value set into the Programmable

Remote T herm Limit Register (Value Register 0x14). Furthermore,

bit is set, the values in the Default Remote T herm Limit Register

(Value Register 0x18) will no longer have an effect on the THERM,

FAN_SPD, or FAN-OFF outputs. T his bit cannot be written again

until after RST has been asserted. (Power-up default = 0)

4

5

Soft Reset

Read/Write

Setting this bit to a “1”will restore powerup default values to the

Configuration Register, Interrupt Status Register and Interrupt Mask

Register. T his also rearms INT structure but not the T HERM

structure. T his bit automatically clears itself since the power on default

is zero.

FAN OFF

Read/Write

Setting this bit to a “1” will cause the FAN OFF pin to be floated.

Clearing this bit to “0” will cause the FAN OFF pin to be driven low

which requests that the fan be turned off. T his bit will be

unconditionally set if the THERM pin is ever asserted; once THERM

is negated this bit must be returned to its prior state (prior to THERM

assertion). Reading this bit reflects the state of the FAN-OFF output

buffer. Due to the open-drain nature of this pin the value read does not

represent the actual state of the external circuit connected to it.

(Power up default =1)

6

7

GPI Invert

Reserved

Read/Write

Read Only

Setting this bit to a “1” will invert the GPI input for the purpose of

level detection and interrupt generation. Clearing this bit to “0” leaves

the GPI input unmodified. (Powerup default=0)

Reserved. (Powerup default = 0).

REV. PrD

–17–

Preliminary Technical Data

TABLE 7. RE GISTE R 0X41. INTE RRUP T STATUS RE GISTE R. P O WE R O N D E FAULT <7:0> = 00H

ADM1028

B IT

N AM E

R E AD /W R IT E

D E S C R I P T I O N

0

Int. T emp Error

Read/Write

‘1’ to clear

A one indicates that one of the limits for the internal

temperature sensor has been exceeded.

1

2

Flag 1

Flag 2

Read/Write

T his bit can be used as a general purpose flag with the capability of

generating an interrupt. Writing a ‘1’ to this bit causes it to be set to

‘1’. Writing a ‘0’ clears this bit.

Read/Write

T his bit can be used as a general purpose flag with the capability of

generating an interrupt. Writing a ‘1’ to this bit causes it to be set to

‘1’. Writing a ‘0’ clears this bit.

3

4

Int. THERM

Read/Write

‘1’ to clear

A one indicates that the internal thermal overload (THERM) limit

has been exceeded.

GPI Input

Read Only

A “1” indicates that the GPI pin is asserted. T he polarity of the GPI

pin is determined by GPI Invert (bit 6) in the Configuration

Register. For example, if GPI Invert is cleared then this bit will be

“1” when the GPI pin is high (“1”); this bit will be “0” when the

GPI pin is low (“0”). If GPI Invert is set then this bit will be “1”

when the GPI pin is low (“0”); this bit will be “0” when the GPI pin

is high (“1”). Note that the state of GPI is not latched; this bit

simply reflects the state or inverted state of the GPI pin. Note: if this

bit is “1” reading this register will NOT clear it to “0.”

5

6

7

Ext. T emp Error Read/Write

‘1’ to clear

A one indicates that one of the limits for the external

temperature sensor has been exceeded.

Ext. THERM

Read/Write

‘1’ to clear

A one indicates that the external thermal overload (THERM) limit

has been exceeded.

Ext Diode Fault

Read/Write

‘1’ to clear

A one indicates either a short- or open-circuit fault on the remote

sensor diode.

TABLE 8. RE GISTE R 0X43

INTE RRUP T MASK RE GISTE R. P O WE R O N D E FAULT <7:0> = 00H

BIT

Nam e

Read/Write

D escription

0

Int T emp Error

Read/Write

A one disables the corresponding interrupt status bit for the INT

output.

1

2

3

4

5

6

7

Flag 1 Mask

Flag 2 Mask

Int THERM

G PI M ask

Read/Write

A one disables the corresponding interrupt status bit for the INT

output.

A one disables the corresponding interrupt status bit for the INT

output.

A one disables the corresponding interrupt status bit for the INT

output.

A one disables the corresponding interrupt status bit for the INT

output.

Ext T emp Error

Ext T H ERM

Ext Diode Fault

A one disables the corresponding interrupt status bit for the INT

output.

A one disables the corresponding interrupt status bit for the INT

output.

A one disables the corresponding interrupt status bit for the INT

output.

–18–

REV. PrD

Preliminary Technical Data

ADM1028

TABLE 9. RE GISTE R 0X4B

RE MO TE FUNC TIO N RE GISTE R. P O WE R O N D E FAULT <7:0> = 00 H

BIT

Nam e

Read/Write

D escription

0

R_RST

Read/Write

Writing a “1” to this bit causes the R_RST output to be pulsed low for

a minimum of 125µs. T his bit will self-clear to 0 when the R_RST

pulse is complete. Writing a “0” to this bit has no effect. Reading this

bit reflects the state of this register bit and not the state of the pin. T he

power-on default value is “0”.

1

R _O F F

Read/Write

Writing a “1” to this bit causes the R_OFF output to be driven high.

T his bit will be cleared, and the output driven low, when RST is

asserted. Writing a “0” to this bit has no effect. T he power-on default

value is “0”.

2

3

4

5

6

7

Reserved

Read/Write

Reserved (default = 0)

TABLE 10. RE GISTE R 0X4C

ALE RT STATUS RE GISTE R. P O WE R O N D E FAULT <7:0> = 00 H

BIT

Nam e

Read/Write

D escription

0

T H ERM Alert

Read Only

A one indicates that thee xternal thermal overload limit is currently

exceeded.

1

GPI Alert

Read Only

T his bit represents the logic level of the GPI pin if bit 6 of the

Configuration Register is “0”, or the inverse logic level of the GPI pin

if bit 6 of the Configuration Register is “1”.

2

3

4

5

6

7

Reserved

Read Only

U ndefined

REV. PrD

–19–

Preliminary Technical Data

ADM1028

O U T LINE D IM E NS IO NS

D imensions shown in inches and (mm).

16-Pin QSOP Package (RQ-16)

0.197 (5.00)

0.189 (4.80)

9

16

0.244 (6.20)

0.228 (5.79)

0.157 (3.99)

0.150 (3.81)

1

8

PIN 1

0.069 (1.75)

0.053 (1.35)

0.059 (1.50)

MAX

8؇

0.010 (0.25)

0.004 (0.10)

0.012 (0.30)

0.008 (0.20)

0.025

(0.64)

BSC

؇

0

0.050 (1.27)

0.016 (0.41)

SEATING 0.010 (0.20)

PLANE

0.007 (0.18)

REF: JEDEC 0.150” SSOP - DRAWING NUMBER MO-137

–20–

REV. PrD


型号：	ADM1028ARQ-REEL7
厂家：	ADI
描述：	IC SPECIALTY ANALOG CIRCUIT, PDSO16, MO-137AB, QSOP-16, Analog IC:Other 光电二极管
文件：	总20页 (文件大小：277K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADM1028ARQ-REEL7 [ADI]

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