ADM1022ARQZ [ADI]
IC 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16, MO-137AB, QSOP-16, Power Management Circuit;
| 型号： | ADM1022ARQZ |
| 厂家： | 
ADI |
| 描述： | IC 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16, MO-137AB, QSOP-16, Power Management Circuit 光电二极管 |
| 文件： | 总20页 (文件大小：335K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low-Cost PC Temperature
Monitor and Fan Control ASIC
a
ADM1022
FEATURES
GENERAL DESCRIPTION
External Temperature Measurement with Remote
Diode (Two Channels)
On-Chip Temperature Sensor
Interrupt and Over-Temperature Outputs
Fault Tolerant Fan Control
Brownout Detection
LDCM Support
System Management Bus (SMBus)
Standby Mode to Minimize Power Consumption
Limit Comparison of all Monitored Values
The ADM1022 is a low cost temperature monitor and fan con-
troller for microprocessor-based systems. The temperature of one
or two remote sensor diodes may be measured, allowing monitor-
ing of processor temperature in single- or dual-processor systems.
Measured values can be read out via a serial System Manage-
ment Bus, and values for limit comparisons can be programmed
in over the same serial bus.
The ADM1022 also contains a DAC for fan speed control.
Automatic hardware temperature trip points are provided and
the fan will be driven to full speed if they are exceeded.
APPLICATIONS
Finally, the chip has two supply voltage monitors for brownout
detection.
Network Servers and Personal Computers
Microprocessor-Based Office Equipment
Test Equipment and Measuring Instruments
The ADM1022’s 3.0 V to 5.5 V supply voltage range, low supply
current, and SMBus interface make it ideal for a wide range of
applications. These include hardware monitoring and protection
applications in personal computers, electronic test equipment
and office electronics.
FUNCTIONAL BLOCK DIAGRAM
V
V
MON
CC
ADD/NTEST_OUT
SERIAL BUS
INTERFACE
SDA
RESET
GENERATOR 1
RST1
ADM1022
SCL
ANALOG
OUTPUT
REGISTER
AND 8-BIT DAC
FAN_SPD/NTEST_IN
RESET
GENERATOR 2
RST2
MR
V
CC
ADDRESS
POINTER
REGISTER
20k⍀
VALUE AND
LIMIT
REGISTERS
BANDGAP
TEMPERATURE
SENSOR
LIMIT
COMPARATORS
ADC
ANALOG
MULTIPLEXER
INTERRUPT
STATUS
D1+
D1–
2.5V
BANDGAP
REFERENCE
REGISTERS
D2+/GPI
INT MASK
REGISTER
INT
D2–/THERM
MASK
GATING
CONFIGURATION
REGISTER
FAN_OFF
GND
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
(T = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.)
ADM1022–SPECIFICATIONS
A
Parameter
Min
Typ1
Max
Unit
Test Conditions
POWER SUPPLY
Supply Voltage, VCC
Supply Current, ICC
3.0
3.30
1.4
5.5
2.6
V
mA
Interface Inactive, ADC Active
TEMPERATURE-TO-DIGITAL CONVERTER
Internal Sensor Accuracy
±3
±2
∞C
∞C
∞C
∞C
∞C
∞C
mA
mA
ms
±1
TA = 85∞C, Tested at Wafer Sort
TA = 85∞C, Tested at Wafer Sort
Resolution
External Diode Sensor Accuracy
1
±5
±3
Resolution
Remote Sensor Source Current
1
90
5.5
60
3.5
130
7.5
200
High Level (D+ = D– +0.65 V)
Low Level (D+ = D– +0.65 V)
Total Monitoring Cycle Time, tC
ANALOG OUTPUT
Output Voltage Range
Total Unadjusted Error, TUE
Full-Scale Error
0
2.5
±5
±3
V
%
%
LSB
LSB
LSB
mA
mA
IL = 2 mA
±1
±2
Zero Error
No Load
Monotonic by Design
Differential Nonlinearity, DNL
Integral Nonlinearity
Output Source Current
Output Sink Current
±1
±1
2
1
VOLTAGE MONITOR THRESHOLDS
Reset Threshold, VMON, VCC
Hysteresis
2.85
2.925
50
3.00
V
mV
Measured with VCC Falling
MR INPUT
MR Minimum Pulsewidth, tMR
MR Glitch Immunity
MR to RST2 Propagation Delay, tMD
MR Pull-Up Resistance
10
10
ms
100
0.5
20
ns
ms
30
kW
RESET OUTPUTS, RST1, RST2
Reset Output Voltage, VOL
0.3
V
ISINK = 1.2 mA
CC = VTH(MAX)
V
Reset Active Timeout Period, tRP
VCC to Reset Delay, tD
DIGITAL OUTPUT ADD/NTEST_OUT2
Output High Voltage, VOH
140
2.4
180
20
560
ms
ms
V
V
IOUT = 3.0 mA
Output Low Voltage, VOL
0.4
OPEN-DRAIN DIGITAL OUTPUTS
(INT, THERM, RST2, RST1)
Output Low Voltage, VOL
0.4
1
V
mA
IOUT = –3.0 mA
VOUT = VCC
High Level Output Leakage Current, IOH
0.1
0.1
OPEN-DRAIN SERIAL DATA
BUS OUTPUT (SDA)
Output Low Voltage, VOL
High Level Output Leakage Current, IOH
0.4
1
V
mA
IOUT = –3.0 mA
VOUT = VCC
SERIAL BUS DIGITAL INPUTS
(SCL, SDA)
Input High Voltage, VIH
Input Low Voltage, VIL
Input Leakage Current
Hysteresis
2.1
V (min)
V (max)
mA
0.8
±5
500
mV
REV. B
–2–
ADM1022
Parameter
Min
2.2
–1
Typ
Max
Unit
Test Conditions
DIGITAL INPUT LOGIC LEVELS
(FAN_SPD/NTEST_IN,
ADD/NTEST_OUT, MR, GPI)
Input High Voltage, VIH
Input Low Voltage, VIL
V
V
0.8
DIGITAL INPUT LEAKAGE CURRENT
(ALL DIGITAL INPUTS)
Input High Current, IIH
–0.005
+0.005 +1
5
mA
mA
pF
VIN = VCC
VIN = 0
Input Low Current, IIL
Input Capacitance, CIN
SERIAL BUS TIMING3
Clock Frequency, fSCLK
Glitch Immunity, tSW
400
kHz
ns
ms
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
50
Bus Free Time, tBUF
1.3
600
600
600
1.3
0.6
Start Setup Time, tSU:STA
Start Hold Time, tHD:STA
Stop Condition Setup Time, tSU:STO
SCL Low Time, tLOW
SCL High Time, tHIGH
SCL, SDA Rise Time, tR
SCL, SDA Fall Time, tF
Data Setup Time, tSU:DAT
Data Hold Time, tHD:DAT
ns
ns
ns
ms
ms
300
300
ns
ns
ns
ns
100
300
NOTES
1Typicals are at TA = 25∞C and represent most likely parametric norm. Standby current typ is measured with VCC = 3.3 V.
2ADD is a three-state input that may be pulled high, low or left open-circuit.
3Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.2 V for a rising edge.
Specifications subject to change without notice.
tR
tF
tLOW
tHD;STA
SCLK
tSU;STA
tHIGH
tSU;STO
tHD;STA
tHD;DAT
tSU;DAT
SDATA
tBUF
P
S
P
S
Figure 1. Diagram for Serial Bus Timing
REV. B
–3–
ADM1022
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
Positive Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . 6.5 V
Voltage On Digital Inputs Except Therm . . –0.3 V to +6.5 V
Voltage On Therm Pin . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Voltage on Any Other Input
or Output Pin . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Input Current at Any Pin . . . . . . . . . . . . . . . . . . . . . . . ±5 mA
Package Input Current . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Maximum Junction Temperature (TJ max) . . . . . . . . . . 150∞C
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature, Soldering
THERMAL CHARACTERISTICS
16-Lead QSOP Package
q
q
JA = 105∞C/W
JA = 39∞C/W
ORDERING GUIDE
Vapor Phase 60 sec . . . . . . . . . . . . . . . . . . . . . . . . . . 215∞C
Infrared 15 sec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200∞C
ESD Rating (Human Body Model) . . . . . . . . . . . . . . . 4000 V
Temperature
Range
Package
Description
Package
Option
Model
ADM1022ARQ 0∞C to 85∞C
16-Lead QSOP RQ-16
PIN CONFIGURATION
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SDA
FAN_OFF
MR
SCL
INT
RST1
GND
ADM1022
ADD/NTEST_OUT
D2+/GPI
D2–/THERM
D1+
TOP VIEW
V
(Not to Scale)
CC
V
MON
RST2
D1–
FAN_SPD/NTEST_IN
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADM1022 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. B
–4–
ADM1022
PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic
Description
1
2
3
FAN_OFF
Digital Output (Open-Drain) Fan Off Request. When asserted low this indicates a request to shut
off the fan independent of the FAN_SPD output. When negated (output FET off) it indicates that
the fan may be turned on.
Digital Input, Manual Reset. A logic low on this input causes RST2 to be asserted. Once this input
is negated that output will remain asserted for tRP. This input has an internal 20 kW pull-up resistor.
Leave unconnected if not used.
Digital I/O (Open-Drain). This pin is asserted low while VCC remains below the reset threshold. It
remains asserted for tRP after the reset condition is terminated. It is bidirectional so the ADM1022 can
be optionally reset; external logic must be used to prevent system auxiliary reset from occurring
when used as an input.
MR
RST1
4
5
6
7
GND
VCC
VMON
RST2
GROUND. Power and Signal Ground.
POWER 3.3 V. Power source and voltage monitor input for first reset generator.
Analog Input. Voltage monitor input for second reset generator.
Digital Output (Open-Drain). This pin is asserted low under any of the following conditions:
– VMON or VCC remains below the reset threshold
– while MR is held low
– while RST1 is asserted.
It remains asserted for tRP after the reset conditions are terminated.
8
FAN_SPD/NTEST_IN
Analog Output/Test Input. An active-high input that enables NAND board-level connectivity testing.
Refer to section on NAND testing. Used as an analog output for fan speed control when NAND
test is not selected.
9
D1–
Remote Thermal Diode Negative Input. This is the negative input (current sink) from the remote
thermal diode. This also serves as the negative input into the A/D.
10
11
D1+
Remote Thermal Diode Positive Input. This is the positive input (current source) from the remote
thermal diode. This serves as the positive input into the A/D.
D2–/THERM
Analog Input/Digital I/O (Open-Drain). Can be programmed as negative input for a second diode
temperature sensor, or as a digital I/O pin. In this case it is an active low thermal overload output
that indicates a violation of a temperature set point (over-temperature). Also acts as an input to
provide external fan control. When this pin is pulled low by an external signal, a status bit is set and
the fan speed is set to full on.
12
D2+/GPI
Analog/Digital Input. Can be programmed as the positive input for a second diode sensor, or as a
general-purpose logic input. In this case it can be programmed as an active high or active low input
that sets Bit 4 of the Status Registers. This bit can only be reset by reading the status registers, pro-
vided GPI is in the inactive state.
13
14
ADD/NTEST_OUT
Digital I/O. The lowest order programmable bit of the SMBus Address. ADD is sampled at power-
up and changing it while powered on will have no immediate effect. This pin also functions as an
output when doing a NAND test.
Digital Output (Open Drain), System Interrupt Output. This signal indicates a violation of a set
trip point. The output is enabled when Bit 1 of the Configuration Register is set to 1. The default
state is disabled.
INT
15
16
SCL
SDA
Digital Input SMBus Clock.
Digital I/O (Open-Drain) SMBus Bidirectional Data.
REV. B
–5–
ADM1022–Typical Performance Characteristics
30
120
100
90
80
70
60
50
40
30
20
10
0
20
10
DXP TO GND
0
–10
DXP TO V (5V)
CC
–20
–30
–40
–50
–60
1
3.3
10
30
100
0
10
20
30
40
50
60
70
80
90 100 110
MEASURED TEMPERATURE
LEAKAGE RESISTANCE – M⍀
TPC 4. Pentium® III Temperature Measurement vs.
ADM1022 Reading
TPC 1. Temperature Error vs. PC Leakage Resistance
6
5
30
25
20
4
250mV p-p REMOTE
15
3
ERROR
2
10
5
1
100mV p-p REMOTE
0
0
–5
1.0
–1
50
500
5k
500k
FREQUENCY – Hz
5M
50M
50k
2.2
3.2
4.7
7.0
10.0
14.0
22.0
29.0
DXP-DXN CAPACITANCE – nF
TPC 2. Temperature Error vs. Power Supply Noise
Frequency
TPC 5. Temperature Error vs. Capacitance Between D+
and D–
25
80
70
60
50
40
20
100mV p-p
15
10
50mV p-p
V
= 5V
CC
30
20
10
0
5
25mV p-p
5M
0
V
= 3V
CC
–5
50
500
5k
50k
500k
50M
1k
5k 10k 25k 50k 75k 100k 250k 500k 750k 1M
SCLK FREQUENCY – Hz
0
FREQUENCY – Hz
TPC 3. Temperature Error vs. Common-Mode Noise
Frequency
TPC 6. Standby Current vs. Clock Frequency
Pentium is a registered trademark of Intel Corporation.
REV. B
–6–
ADM1022
10
9
8
7
6
5
4
3
2
1
0
GENERAL DESCRIPTION
The ADM1022 is a low-cost temperature monitor and fan con-
troller for microprocessor-based systems. The temperature of
one or two remote sensor diodes may be measured, allowing
monitoring of processor temperature in single- or dual-processor
systems. The chip also contains an on-chip sensor to allow
ambient temperature to be monitored.
10mV SQ. WAVE
Measured values can be read out via a serial System Manage-
ment Bus, and values for limit comparisons can be programmed
in over the same serial bus.
The ADM1022 also contains a DAC for fan speed control.
Automatic hardware temperature trip points are provided for
fault tolerant fan control and the fan will be driven to full speed
if they are exceeded. Two interrupt outputs are provided, which
will be asserted if the software or hardware limits are exceeded.
50
500
5k
50k
100k 500k
FREQUENCY – Hz
5M
25M 50M
TPC 7. Temperature Error vs. Differential-Mode Noise
Frequency
Finally, the chip has two supply voltage monitors for brownout
detection. These drive two reset pins, one of which is bidirec-
tional. A manual reset input is also provided.
2.3
2.2
INTERNAL REGISTERS OF THE ADM1022
A brief description of the ADM1022’s principal internal regis-
ters is given below. More detailed information on the function
of each register is given in Tables IV to IX.
V
= 5.5V
DD
2.1
2.0
1.9
Configuration Register: Provides control and configuration.
Address Pointer Register: This register contains the address that
selects one of the other internal registers. When writing to the
ADM1022, the first byte of data is always a register address, which
is written to the Address Pointer Register.
V
= 3.3V
DD
Interrupt (INT) Status Register: This register provides status
of each Interrupt event. It is also mirrored by a second register
at address 4Ch.
1.8
1.7
V
= 3.0V
10
DD
Interrupt (INT) Mask Register: Allows masking of individual
interrupt sources.
–30
–10
30
50
70
90
110
130
TEMPERATURE – ؇C
TPC 8. Standby Supply Current vs. Supply Voltage
Value and Limit Registers: The results of temperature measure-
ments are stored in these registers, along with their limit values.
Analog Output Register: The code controlling the analog out-
put DAC is stored in this register.
400
350
SERIAL BUS INTERFACE
RST2
Control of the ADM1022 is carried out via the serial bus. The
ADM1022 is connected to this bus as a slave device, under the
control of a master device, e.g., the PIIX4.
300
250
The ADM1022 has a 7-bit serial bus address. When the device is
powered up, it will do so with a default serial bus address. The five
MSBs of the address are set to 01011, the two LSBs are deter-
mined by the logical states of Pin 13 (ADD/NTEST_OUT).
This is a three-state input that can be grounded, connected to VCC
or left open-circuit to give three different addresses. The state of
the ADD pin is only sampled at power-up, so changing ADD
with power-on will have no effect until the device is powered
off then on again.
200
RST1
150
100
–30
–10
10
30
50
70
90
110
130
TEMPERATURE – ؇C
TPC 9. Power-up Reset vs. Temperature
REV. B
–7–
ADM1022
Table I. ADD Pin Truth Table
In the case of the ADM1022, write operations contain either
one or two bytes, and read operations contain one byte, and
perform the following functions:
ADD Pin
GND
No Connect
VCC
A1
A0
1
0
0
0
0
1
To write data to one of the device data registers or read data
from it, the Address Pointer Register must be set so that the
correct data register is addressed, then data can be written into
that register or read from it. The first byte of a write operation
always contains an address that is stored in the Address Pointer
Register. If data is to be written to the device, then the write
operation contains a second data byte that is written to the reg-
ister selected by the address pointer register.
If ADD is left open-circuit the default address will be 0101100.
The facility to make hardwired changes to A1 and A0 allows the
user to avoid conflicts with other devices sharing the same serial
bus; for example, if more than one ADM1022 is used in a system.
This is illustrated in Figure 2a. The device address is sent over
the bus followed by R/W set to 0. This is followed by two data
bytes. The first data byte is the address of the internal data
register to be written to, which is stored in the Address Pointer
Register. The second data byte is the data to be written to the
internal data register.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition, defined as a high-to-low transition on the serial
data line SDA while the serial clock line SCL remains high.
This indicates that an address/data stream will follow. All
slave peripherals connected to the serial bus respond to the
START condition, and shift in the next eight bits, consisting
of a 7-bit address (MSB first) plus an R/W bit, which deter-
mines the direction of the data transfer, i.e., whether data
will be written to or read from the slave device.
When reading data from a register there are two possibilities:
1. If the ADM1022’s Address Pointer Register value is unknown
or not the desired value, it is first necessary to set it to the cor-
rect value before data can be read from the desired data register.
This is done by performing a write to the ADM1022 as before,
but only the data byte containing the register address is sent,
as data is not to be written to the register. This is shown in
Figure 2b.
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the Acknowl-
edge Bit. All other devices on the bus now remain idle while
the selected device waits for data to be read from or written
to it. If the R/W bit is a 0, the master will write to the slave
device. If the R/W bit is a one, the master will read from the
slave device.
A read operation is then performed consisting of the serial bus
address, R/W bit set to 1, followed by the data byte read from
the data register. This is shown in Figure 2c.
2. If the Address Pointer Register is known to be already at the
desired address, data can be read from the corresponding
data register without first writing to the Address Pointer Reg-
ister, so Figure 2b can be omitted.
2. Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an Acknowledge Bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, as a low-to-high transition when
the clock is high may be interpreted as a STOP signal. The
number of data bytes that can be transmitted over the serial
bus in a single READ or WRITE operation is limited only by
what the master and slave devices can handle.
NOTES
1. Although it is possible to read a data byte from a data register
without first writing to the Address Pointer Register, if the
Address Pointer Register is already at the correct value, it is
not possible to write data to a register without writing to the
Address Pointer Register, because the first data byte of a
write is always written to the Address Pointer Register.
3. When all data bytes have been read or written, stop conditions
are established. In WRITE mode, the master will pull the
data line high during the 10th clock pulse to assert a STOP
condition. In READ mode, the master device will override
the acknowledge bit by pulling the data line high during the
low period before the 9th clock pulse. This is known as No
Acknowledge. The master will then take the data line low
during the low period before the 10th clock pulse, then high
during the 10th clock pulse to assert a STOP condition.
2. In Figures 2a to 2c, the serial bus address is shown as the
default value 01011(A1)(A0), where A1 and A0 are set by
the three-state ADD pin.
3. The ADM1022 also supports the Read Byte protocol, as
described in the System Management Bus specification.
Any number of bytes of data may be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation, because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.
REV. B
–8–
ADM1022
1
0
9
1
9
SCL
SDA
D6
D2
1
0
1
1
A1
A0
D7
D5
D4
D3
D1
D0
R/W
ACK. BY
ADM1022
START BY
MASTER
ACK. BY
ADM1022
FRAME 1
SERIAL BUS ADDRESS
BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
1
9
SCL
(CONTINUED)
D2
D1
D7
D6
D5
D4
D3
D0
SDA (CONTINUED)
ACK. BY STOP BY
ADM1022 MASTER
FRAME 3
DATA BYTE
Figure 2a. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
1
0
9
1
9
SCL
SDA
D6
D2
1
0
1
1
A1
A0
D7
D5
D4
D3
D1
D0
R/W
ACK. BY
ADM1022
ACK. BY
STOP BY
START BY
MASTER
ADM1022 MASTER
FRAME 1
SERIAL BUS ADDRESS
BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
Figure 2b. Writing to the Address Pointer Register Only
1
9
1
9
SCL
D6
D2
0
1
0
1
1
A1
A0
D7
D5
D4
D3
D1
SDA
START BY
D0
R/W
ACK. BY
ADM1022
NO ACK.
STOP BY
BY MASTER MASTER
MASTER
FRAME 1
SERIAL BUS ADDRESS
BYTE
FRAME 2
DATA BYTE FROM ADM1022
Figure 2c. Reading Data from a Previously Selected Register
TEMPERATURE MEASUREMENT SYSTEM
Internal Temperature Measurement
The forward voltage of a diode or diode-connected transistor,
operated at a constant current, exhibits a negative temperature
coefficient of about –2 mV/∞C. Unfortunately, the absolute value
of VBE, varies from device to device, and individual calibra-
tion is required to null this out, so the technique is unsuitable
for mass-production.
The ADM1022 contains an on-chip bandgap temperature
sensor. The on-chip ADC performs conversions on the out-
put of this sensor and outputs the temperature data in 8-bit
twos complement format. The format of the temperature data
is shown in Table II.
The technique used in the ADM1022 is to measure the change
in VBE when the device is operated at two different currents.
External Temperature Measurement
The ADM1022 can measure the temperature of two external
diode sensors or diode-connected transistors, connected to Pins
9 and 10 or 11 and 12.
This is given by:
DVBE = KT/q ¥ ln(N)
where:
Pins 9 and 10 are a dedicated temperature input channel. The
default function of Pins 11 and 12 is the THERM input/output
and a general purpose logic input (GPI), but they can be config-
ured to measure a diode sensor by setting Bit 7 of the Configu-
ration Register to 1.
K is Boltzmann’s constant
q is charge on the carrier
T is absolute temperature in Kelvins
N is ratio of the two currents
REV. B
–9–
ADM1022
Figure 3 shows the input signal conditioning used to measure
the output of an external temperature sensor. This figure
shows the external sensor as a substrate transistor, provided
for temperature monitoring on some microprocessors, but it
could equally well be a discrete transistor.
LAYOUT CONSIDERATIONS
Digital boards can be electrically noisy environments, and care
must be taken to protect the analog inputs from noise, particu-
larly when measuring the very small voltages from a remote
diode sensor. The following precautions should be taken:
1. Place the ADM1022 as close as possible to the remote sens-
ing diode. Provided that the worst noise sources such as
clock generators, data/address buses and CRTs are avoided,
this distance can be four to eight inches.
V
DD
I
N
؋
I I
BIAS
2. Route the D+ and D– tracks close together, in parallel, with
grounded guard tracks on each side. Provide a ground plane
under the tracks if possible.
V
V
D+
D–
OUT+
TO
ADC
REMOTE
SENSING
TRANSISTOR
3. Use wide tracks to minimize inductance and reduce noise
pickup. 10 mil track minimum width and spacing is
recommended.
BIAS
DIODE
OUT–
LOW-PASS
FILTER
C
f
= 65kHz
10MIL
10MIL
10MIL
10MIL
10MIL
10MIL
10MIL
GND
D+
Figure 3. Signal Conditioning
If a discrete transistor is used, the collector will not be grounded,
and should be linked to the base. If a PNP transistor is used the
base is connected to the D– input and the emitter to the D+ input.
If an NPN transistor is used, the emitter is connected to the D–
input and the base to the D+ input.
D–
GND
Table II. Temperature Data Format
Figure 4. Arrangement of Signal Tracks
Temperature
Digital Output
4. Try to minimize the number of copper/solder joints, which
can cause thermocouple effects. Where copper/solder joints
are used, make sure that they are in both the D+ and D–
path and at the same temperature.
–128∞C
–125∞C
–100∞C
–75∞C
–50∞C
–25∞C
–1∞C
1000 0000
1000 0011
1001 1100
1011 0101
1100 1110
1110 0111
1111 1111
0000 0000
0000 0001
0000 1010
0001 1001
0011 0010
0100 1011
0110 0100
0111 1101
0111 1111
Thermocouple effects should not be a major problem as 1∞C
corresponds to about 200 mV, and thermocouple voltages are
about 3 mV/oC of temperature difference. Unless there are
two thermocouples with a big temperature differential between
them, thermocouple voltages should be much less than 200 mV.
0∞C
+1∞C
+10∞C
+25∞C
+50∞C
+75∞C
+100∞C
+125∞C
+127∞C
5. Place 0.1 mF bypass and 1000 pF input filter capacitors close
to the ADM1022.
6. If the distance to the remote sensor is more than eight inches,
the use of twisted pair cable is recommended. This will work
up to about 6 to 12 feet.
7. For really long distances (up to 100 feet) use a shielded
twisted pair such as Belden #8451 microphone cable. Con-
nect the twisted pair to D+ and D– and the shield to GND
close to the ADM1022. Leave the remote end of the shield
unconnected to avoid ground loops.
To prevent ground noise interfering with the measurement, the
more negative terminal of the sensor is not referenced to ground,
but is biased above ground by an internal diode at the D– input.
If the sensor is used in a very noisy environment, a capacitor of
value up to 1000 pF may be placed between the D+ and D–
inputs to filter the noise.
Because the measurement technique uses switched current
sources, excessive cable and/or filter capacitance can affect the
measurement. When using long cables, the filter capacitor C1
may be reduced or removed. In any case, the total shunt capaci-
tance should not exceed 1000 pF.
To measure DVBE, the sensor is switched between operating
currents of I and N ¥ I. The resulting waveform is passed through
a 65 kHz low-pass filter to remove noise, thence to a chopper-
stabilized amplifier that performs the functions of amplification
and rectification of the waveform to produce a dc voltage pro-
portional to DVBE. This voltage is measured by the ADC to give
a temperature output in 8-bit twos complement format. To
further reduce the effects of noise, digital filtering is performed
by averaging the results of 16 measurement cycles. An external
temperature measurement takes nominally 9.6 ms.
Cable resistance can also introduce errors. 1 W series resistance
introduces about 0.5∞C error.
REV. B
–10–
ADM1022
ANALOG OUTPUT
12V
The ADM1022 has a single analog output (FAN_SPD) from an
unsigned 8-bit DAC that produces 0 V–2.5 V. The analog out-
put register defaults to 00 during power-on reset, which produces
minimum fan speed. The analog output may be amplified and
buffered with external circuitry such as an op amp and transistor
to provide fan speed control.
R4
1k⍀
FAN_SPD
Q1
BD136
2SA968
AD8519
+
R3
1k⍀
R2
39k⍀
Suitable fan drive circuits are given in Figures 5a to 5e. When
using any of these circuits, the following points should be noted:
R1
10k⍀
1. All of these circuits will provide an output range from zero to
almost +VFAN
.
Figure 5b. 12 V Fan Circuit with Op Amp and PNP
Transistor
2. To amplify the 2.5 V range of the analog output up to +VFAN
,
the gain of these circuits needs to be set as shown.
12V
3. Care must be taken when choosing the op amp to ensure that
its input common-mode range and output voltage swing are
suitable.
R3
100k⍀
FAN_SPD
Q1
4. The op amp may be powered from the +V rail alone. If it
is powered from +V then the input common-mode range
should include ground to accommodate the minimum output
voltage of the DAC, and the output voltage should swing below
0.6 V to ensure that the transistor can be turned fully off.
AD8519
+
NDT452 P
R2
39k⍀
3.3V
R1
10k⍀
R4
1k⍀
5. In all these circuits, the output transistor must have an ICMAX
greater than the maximum fan current, and be capable of dis-
sipating power due to the voltage dropped across it when the
fan is not operating at full speed.
Q2
NDT3055L
FAN_OFF
6. If the fan motor produces a large back ElectroMotive Force
(EMF) when switched off, it may be necessary to add clamp
diodes to protect the output transistors in the event that the
output goes from full-scale to zero very quickly.
Figure 5c. 12 V Fan Circuit with Op Amp and P-Channel
MOSFET
12V
7. Pulling FAN_SPD/NTEST_IN high externally on power-up
causes NAND Test Mode to be invoked on the ADM1022.
Therefore, a 4.7 kW pull-down resistor should be added
externally to the FAN_SPD pin to prevent ADM1022 inad-
vertently entering the NAND Tree Test Mode.
R3
100k⍀
R4
100k⍀
Q3
NDT452 P
Figure 5c shows how the FAN_OFF signal may be used (with
any of the control circuits) to gate the fan on and off indepen-
dent of the value on the FAN_SPD/NTEST_IN pin.
R2
3.9k⍀
Q1/Q2
MBT3904
DUAL
FAN_SPD
R5
5k⍀
R1
1k⍀
5V
Figure 5d. Discrete 12 V Fan Drive Circuit with
P-Channel MOSFET, Single Supply
FAN_SPD
Q1
AD8541
+
NDT452 P
12V
R2
15k⍀
R5
100k⍀
R4
100k⍀
Q4
BD132
TIP32A
5V
FAN
R1
10k⍀
Q3
BC556
2N3906
R2
Figure 5a. 5 V Fan Circuit with Op Amp
3.9k⍀
Q1/Q2
MBT3904
DUAL
FAN_SPD
R6
5k⍀
R3
100⍀
R1
1k⍀
Figure 5e. Discrete 12 V Fan Drive Circuit with Bipolar
Output Single Supply
REV. B
–11–
ADM1022
FAULT TOLERANT FAN CONTROL
Operation of the INT output is illustrated in Figure 6. Assum-
ing that the temperature starts off within the programmed limits
and that temperature interrupt sources are not masked, INT
will go low if the temperature measured by any of the internal or
external sensors goes outside the programmed high or low
temperature limit for that sensor. INT also goes low whenever
THERM is low.
The ADM1022 incorporates a fault tolerant fan control capabil-
ity that is tied to operation of the THERM output. It can over-
ride the setting of the analog output and force it to maximum to
give full fan speed in the event of a critical over-temperature
problem, even if, for some reason, this has not been handled by
the system software.
There are four temperature set point registers that will activate
the fault tolerant fan control. Two of these limits are program-
mable by the user and two are hardware (read-only) registers
that will operate if the user does not program any limits. The
fault tolerant fan control is activated if a limit is exceeded for
three or more consecutive readings. These limits are separate
from the normal high and low temperature limits for the INT
output, which do not affect the fault tolerant fan control or
THERM output.
100؇C
90؇C
*
80؇C
HIGH LIMIT
*
*
70؇C
TEMP
*
60؇C
LOW LIMIT
*
*
50؇C
40؇C
A hardware limit of 70∞C for the on-chip temperature sensor is
programmed into the register at address 13h. For the remote
sensors, a hardware limit of 100∞C is programmed in to the
register at address 17h. These are the default limits and the ana-
log output will be forced to full-scale if the on-chip sensor reads
more than 70∞C or either of the remote sensors reads more than
100∞C. This makes the fault tolerant fan control fail-safe in that it
will operate at these temperatures even if the user has programmed
no other limits, or in the event of a software malfunction.
INT
ACPI CONTROL
METHODS
CLEAR EVENT
*ACPI AND DEFAULT CONTROL METHODS
ADJUST TEMPERATURE LIMIT VALUES
Figure 6. Operation of INT Output
Once the interrupt has been cleared, it will not be reasserted
even if the temperature remains outside the limit previously
exceeded. However, INT will be reasserted if:
The user may override these default limits by programming new
limits into registers at address 14h for the on-chip sensor and
18h for the remote sensors. The default values in these registers
are the same as for the read-only registers (70∞C and 100∞C),
but they may be programmed with higher or lower values.
a) the temperature goes outside the other limit for the sensor
or
b) the previously exceeded limit is reprogrammed and the tem-
perature is then outside the new limit on the next conversion
cycle
Once registers 13h and 14h have been programmed, or if the
default is acceptable, Bit 1 of the configuration register must be
set to “1.” This bit is a write-once bit that can only be written to
“1” and it has two effects:
or
c) an interrupt is generated by another source.
1. It makes the values in registers 13h and 14h the active limits,
and disables read-only registers 17h and 18h.
INTERRUPT MASKING
2. It locks the data into registers 13h and 14h, so they cannot
be changed until the lock bit is reset, which is when RST2 is
asserted or a Power-On Reset occurs.
Any of the bits in the Interrupt Status Register can be masked out
by setting the corresponding mask bit in the Interrupt Mask Regis-
ter. That interrupt source will then no longer generate an interrupt.
However, the bits in the status register will be set as normal.
Once the hardware override of the analog output is triggered, it will
only return to normal operation after three consecutive measure-
ments that are five degrees lower than each of the above limits.
INTERRUPT CLEARING
Reading the Interrupt Status Register will output the contents of
the Register, then clear it. It will remain cleared until the moni-
toring cycle updates it, so the next read operation should not be
performed on the register until this has happened, or the result
will be invalid.
The analog output can also be forced to full-scale by pulling the
THERM pin (Pin 11) low. Bit 6 of the Status Register is also set.
Whenever FAN_SPD output is forced to full-scale, the FAN_OFF
output is negated.
THE ADM1022 INTERRUPT SYSTEM
The INT output is cleared with the INT_Clear bit, which is Bit
2 of the Configuration Register, without affecting the contents
of the Interrupt (INT) Status Registers.
The ADM1022 has two interrupt outputs, INT and THERM.
These have different functions. INT responds to violations of
software programmed temperature limits and its interrupt sources
are maskable, as described in more detail later. THERM is
intended as a “fail-safe” interrupt output that cannot be masked.
Interrupts and status bits are only set if a limit is exceeded for at
least three consecutive conversions.
INTERRUPT STATUS MIRROR REGISTER
Whenever a bit in the Interrupt Status Register is set, the corre-
sponding bit is also set in the mirror register at address 4Ch.
This register allows a second management system to access the
status data without worrying about clearing the data. The data
in this register is for reading only and has no effect on the inter-
rupt output. The contents of this register are cleared when read.
REV. B
–12–
ADM1022
THERM INPUT/OUTPUT
THERM will go low if the hardware temperature limit is exceeded
for three consecutive measurements. It will remain low until the
temperature falls five degrees below the limit for three consecu-
tive measurements. While THERM is low, the analog output
will go to FFh to boost a controlled fan to full speed and
FAN_OFF will be negated.
Pin 11 may be configured as an input for a second temperature
sensor by setting Bit 7 of the Configuration Register, or it may
be used as an interrupt output by clearing Bit 7 of the Configu-
ration Register, which is its default condition. The Thermal
Management Input/Output (THERM) is a logic input/open-
drain output. It can also function as a logic input. If THERM is
taken low by an external source, the analog output will be forced
to FFh to switch a controlled fan to maximum speed and
FAN_OFF will be negated.
When the Fault Tolerant Fan Control state is exited, the analog
FAN_SPD output returns to its previously programmed value,
which may have been changed during the time that the FAN_SPD
output was forced to FFh.
THERM OPERATING MODE
INTERRUPT STRUCTURE
THERM responds only to the “hardware” temperature limits
at addresses 13h, 14h, 17h and 18h, not to the software pro-
grammed limits. The function of these registers was described
earlier with regard to fault tolerant fan speed control.
The Interrupt Structure of the ADM1022 is shown in more
detail in Figure 8. As each measurement value is obtained and
stored in the appropriate value register, the value and the limits
from the corresponding limit registers are fed to the high and
low limit comparators. The result of each comparison (1 = out
of limit, 0 = in limit) is routed to the corresponding bit input of
the Interrupt Status Register via a data demultiplexer, and used
to set that bit high or low as appropriate.
HARDWARE
TRIP POINT
5؇
The Interrupt Mask Register has bits corresponding to each of
the Interrupt Status Register Bits. Setting an Interrupt Mask Bit
high forces the corresponding Status Bit output low, while set-
ting an Interrupt Mask Bit low allows the corresponding Status
Bit to be asserted. After masking, the status bits are all OR’d
together to produce the INT output, which will pull low if any
unmasked status bit goes high, i.e., when any measured value
goes out of limit.
TEMP
THERM
PROGRAMMED
EXT
VALUE
FF
FF
H
ANALOG
OUTPUT
H
THERM
INPUT
The INT output is enabled when Bit 1 of the Configuration Register
(INT_Enable) is high, and Bit 2 (INT_Clear) is low.
Figure 7. Operation of THERM Output
The THERM output cannot be cleared nor its interrupt
sources masked.
GPI
INT. TEMP
0
1
EXT. TEMP2
DIODE 2 FAULT
RESERVED
GPI
HIGH
LIMIT
1 = OUT
OF
LIMIT
2
3
4
5
6
7
DATA
DEMULTI-
PLEXER
INTERRUPT
HIGH
AND
STATUS
FROM
VALUE
REGISTER
LOW
EXT. TEMP1
THERM
VALUE
LIMIT
AND LIMIT
REGISTERS
COMPARA-
TORS
MASK GATING
؋
8 DIODE 1 FAULT
STATUS
BIT
MASK
BIT
LOW
LIMIT
INT
INTERRUPT
MASK
REGISTER
MASKING
DATA
FROM BUS
INT_ENABLE
INT_CLEAR
8 MASK BITS
(SAME BIT
ORDER AS
STATUS
CONFIGURATION
REGISTER
REGISTER)
THIS CONNECTION ONLY RELEVANT IF
THERM IS PULLED LOW EXTERNALLY.
D2–/THERM
Figure 8. Interrupt Register Structure
REV. B
–13–
ADM1022
GENERAL-PURPOSE LOGIC INPUT (GPI)
Operation of the reset outputs at power-up, and for a manual reset
input, is shown in Figure 9. It should be noted that the resets will
only be asserted once VCC rises above 1 V. Below this voltage there
is insufficient gate drive voltage to turn on the output FETs. If the
device being reset and its pull-up resistor is supplied from VCC, the
reset voltage will rise with VCC to 1 V before being pulled low. If
the device being reset and its pull-up resistor use a separate
supply voltage, the reset output will follow that voltage until
reset is asserted.
Pin 12 may be configured as an input for a second temperature
sensor input by setting Bit 7 of the Configuration Register, or it
may be used as a general-purpose logic input by clearing Bit 7 of
the Configuration Register, which is its default condition. The
GPI input may be programmed to be active high or active low by
clearing or setting Bit 6 of the Configuration Register. The default
value is active high. Bit 4 of the Interrupt Status Register follows
the state (or inverted state) of GPI and will generate an interrupt
when it is set to one, like any other input to the Interrupt Status
Register. However, the GPI bit is not latched in the Status Register
and always reflects the current state (or inverted state) of the
GPI input. If it is one it will not be cleared by reading the
Status Register.
The ADM1022 can also be reset by taking RST1 low as an input.
The above-mentioned registers will be reset to their default
values and the ADC will remain inactive as long as RST1 is
below the reset threshold.
V
CC
–1V
RESETS
The ADM1022 has a manual reset input, (Pin 2 – MR), a bidi-
rectional reset pin, (Pin 3 – RST1) and a reset output (Pin 7 –
RST2). These operate as follows:
RST1
RST2
Taking MR low forces a system reset and takes the RST2 output
low. It will remain low for tRP after MR goes high again. The
MR input has a 20 kW pull-up resistor, and may be left uncon-
nected if not used. MR is typically used to generate a system
reset from a front-panel push-button.
tRP
tRP
POWER-ON RESET
The RST1 pin is a bidirectional I/O. It is asserted low as an out-
put if VCC falls below the reset threshold. It can also operate as a
reset input to the ADM1022 in the same way as MR. At power-
up, RST2 will remain asserted for tRP after RST1 goes high.
MR
RST2
tRP
t
The RST2 output is asserted low under any of the following
MANUAL RESET (FOR EXAMPLE)
conditions:
£ the MR input is low, as previously described,
– RST1 is asserted low as an output or pulled low as an input,
£ VMON is below the reset threshold.
Figure 9. Operation of Reset Outputs
RST1 AS I/O
If RST1 is used as a reset input to the ADM1022 while also
being used as a system reset output, it will be necessary to sepa-
rate the two functions so that a reset from the system to the
ADM1022 does not also reset the system.
POWER-ON RESET
When the ADM1022 is powered up, it will initiate a power-on
reset sequence when the supply voltage VCC rises above the
power-on reset threshold, with registers being reset to their
power-on values. Normal operation will begin when the supply
voltage rises above the reset threshold. Registers whose power-
on values are not shown have power on conditions that are
indeterminate (this includes the Value and Limit Registers). In
most applications, usually the first action after power-on would
be to write limits into the Limit Registers.
This can be achieved using the circuit of Figure 10. If ALT_RST
is high, then reset outputs from the ADM1022 can pass through
N2 to reset the system.
If, however, ALT_RST is low, the ADM1022 will be reset, but
SYS_RST will be held high by the high input from N1 to N2.
Power-on reset clears or initializes the following registers (the ini-
tialized values are shown in Table IV):
V
CC
ADM1022
– Configuration Register
– Interrupt Status Register
– Interrupt Status Mirror Register
– Interrupt Mask Register
– Test Register
100k⍀
RST1
N2
SYS_RST
– Analog Output Register
– Programmable Trip Point Registers
N1
ALT_RST
Figure 10. Separation of RST1 Input from RST1 Output
REV. B
–14–
ADM1022
5 V OPERATION
In NAND tree test mode, all digital inputs may be tested as illus-
trated in Table III. ADD/NTEST_OUT will become the NAND
tree output pin.
The ADM1022 may be operated with VCC and/or VMON con-
nected to any supply voltage between 3.0 V and 5.5 V, but it
should be noted that the reset threshold voltages are fixed and
optimized for 3.3 V operation. If the VCC supply voltage is 5 V,
for example, the VMON input can still be used to monitor another
3.3 V supply without problems. However, the reset threshold for
the 5 V, VCC supply, may be below that at which 5 V logic will
operate reliably and may not give a reliable indication of brown-
out on the 5 V supply.
The structure of the NAND Tree is shown in Figure 12. To
perform a NAND Tree test, all pins are initially driven low. The
test vectors set all inputs low, then one-by-one toggles them
high (keeping them high). Exercising the test circuit with this
“walking one” pattern, starting with the input closest to the out-
put of the tree, cycling towards the farthest, causes the output of
the tree to toggle with each input change. Allow for a typical
propagation delay of 500 ns.
Alternatively, VMON may be configured to monitor a supply volt-
age higher than 3.3 V by adding an input attenuator.
POWER-ON
RESET
The ratio of R1 to R2 is given by:
CLK
R1/R2 = (VR – 2.93)/2.93
Q
D
FAN_SPD/
NTEST_IN
LATCH
Where VR is the desired reset voltage and 2.93 V is the nominal
ENABLE
reset voltage of the VMON input.
GPI
SCL
SDA
MR
V
ADD/NTEST_OUT
MON
R1
V
IN
R2
Figure 12. NAND Tree
Table III. Test Vectors
Figure 11. Scaling VMON to a Higher Reset Voltage
GPI
SCL
SDA
MR
ADD/NTEST_OUT
The input resistance of the VMON input is approximately 100 kW,
with a tolerance of around ±30%, so the parallel combination of
R1 and R2 should be much lower than 100 kW to minimize
errors due to variations in this input resistance.
0
0
0
0
1
0
0
0
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
0
1
INITIALIZATION (SOFT RESET)
Soft reset performs a similar, but not identical, function to
power-on reset. The Test Register and Analog Output register
are not initialized.
CONFIGURING THE INTERRUPT
On power-up, the Interrupt functionality of the device is disabled.
The Configuration Register (0x40) must be written to, in order
to enable the Interrupt output. The INT_Clear bit (Bit 2) should
be cleared to 0 and the INT_Enable bit (Bit 1) of the Register
should be set to 1.
Soft reset is accomplished by setting Bit 4 of the Configuration
Register high. This bit automatically clears after being set.
NAND TREE TEST
A NAND tree is provided in the ADM1022 for Automated Test
Equipment (ATE) board level connectivity testing. The device
is placed into NAND tree test mode by powering up with pin
FAN_SPD/NTEST_IN (Pin 8) held high. This pin is sampled
and its state at power-up is latched. If it is connected high, the
NAND tree test mode is invoked. NAND tree test mode will
only be exited once the ADM1022 is powered down.
If the INT_Enable bit is set, and the INT_Clear bit is not
cleared to 0, then any interrupts generated will be reflected in
the Interrupt Status Register, but will not toggle the Interrupt
pin externally.
REV. B
–15–
ADM1022
Table IV. Registers
Address A7–A0
in Hex
Register Name
Comments
Value Registers
Company ID
0x13–0x3A
0x3E
See Table V.
This location will contain the company identification number. This
register is read only.
Revision
0x3F
This location will contain the revision number of the part in the lower
four bits of the register [3:0]. The upper four bits reflect the ADM1022
Version Number [7:4]. The first version is 1100. The next version of
ADM1022 would be 1101, etc. For instance, if the stepping were A0
and this part is an ADM1022, this register would read 1100 0000.
This register is read only.
Configuration Register
0x40
0x41
0x42
0x43
0x44
0x47
0x4A
0x4C
See Table VI. Power-On Value = 0010 0101.
See Table VII. Power-On Value = 0000 0000.
Interrupt Status Register
Reserved for Future Use
Interrupt Mask Register
Reserved for Future Use
Reserved for Future Use
Reserved for Future Use
Interrupt Status Register Mirror
See Table VIII. Power-On Value = 0000 0000.
See Table IX. Power-On Value = 0000 0000.
Table V. Registers 0x13–0x3A Value Registers
Description
Address
Read/Write
0x13
Read/Write
Programmable Local Temp Sensor Automatic Trip Point—Default 70∞C. This register can only be
written to if the write once bit in the configuration register (0x40, Bit 3) has not been set.
Programmable Remote Thermal Diode Automatic Trip Point—Default 100∞C. This register can
only be written to if the write once bit in the configuration register (0x40, Bit 3) has not been set.
Test Register for manufacturer’s use only. Do not write to this register.
Default Local Temp Sensor Automatic Trip Point—Default 70∞C. Cannot be changed. Disabled
when Bit 3 of Configuration Register is set.
0x14
Read/Write
0x15
0x17
Read/Write
Read Only
0x18
Read Only
Default Remote Thermal Diode Automatic Trip Point—Default 100∞C. Cannot be changed. Disabled
when Bit 3 of Configuration Register is set.
0x19
0x20
0x26
0x27
0x2B
0x2C
0x37
0x38
0x39
0x3A
Read/Write
Read Only
Read Only
Read Only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Analog Output, FAN_SPD (Defaults to 0x00h).
External Temperature Value Diode 2
External Temperature Value Diode 1
Internal Temperature
External Temperature Diode 2 High Limit
External Temperature Diode 2 Low Limit
External Temperature Diode 1 High Limit
External Temperature Diode 1 Low Limit
Internal Temperature High Limit
Internal Temperature Low Limit
REV. B
–16–
ADM1022
Table VI. Register 0x40 Configuration Register
Description
Bit
Name
Read/Write
0
START
Read/Write
Setting this bit to a “1” enables startup of ADM1022; clearing this bit to a “0” places ADM1022
in standby mode. Caution: The INT output will not be cleared if the user clears this bit after an
interrupt has occurred (see “INT Clear” bit). At startup temperature monitoring and limit
checking functions begin. Note, all limit values should be programmed into ADM1022 prior to
using the standard thermal interrupt mechanism based upon high and low limits. (Power-Up
Default = 1.)
1
2
3
INT Enable
INT Clear
Read/Write
Read/Write
Read/Write
Setting this bit to a “1” enables the INT output. 1 = Enabled 0 = Disabled
(Power-Up Default = 0).
This bit clears the INT output when set (1) without affecting the contents of the Interrupt Status
Register. (Power-Up Default = 1.)
Setting this bit to a “1” will lock in the value set into the Programmable Local and Remote
Automatic Trip Point Registers (Value Register locations 0x13 and 0x14). Furthermore,
when this bit is set, the values in the Default Local and Remote Automatic Trip Point
Registers (Value Register locations 0x17 and 0x18) will no longer have an effect on the
THERM, FAN_SPD or FAN-OFF outputs. This bit cannot be written again until after RST2
has been asserted or Power-On Reset occurs. (Power-Up Default = 0.)
Programmable
Automatic Trip Once
Point Lock Bit
4
5
Soft Reset
Read/Write
Setting this bit to a “1” will restore power-up default values to the Configuration Register,
Interrupt Status Register, Interrupt Status Register Mirror, Interrupt Mask Register.
This bit automatically clears itself since the power-on default is zero.
FAN OFF
Read/Write
Setting this bit to a “1” will cause the FAN OFF pin to be floated. Clearing this bit to “0” will
cause the FAN OFF pin to be driven low, which requests that the fan be turned off. This bit will
be unconditionally set if the THERM pin is ever asserted. Reading this bit reflects the state of
the FAN-OFF output buffer. Due to the open-drain nature of this pin the value read does not
represent the actual state of the external circuit connected to it. (Power-Up Default = 1.)
Setting this bit to a “1” will invert the GPI input for the purpose of level detection and interrupt
generation. Clearing this bit to a “0” leaves the GPI input unmodified. (Power-Up Default = 0.)
Setting this bit configures Pins 11 and 12 as inputs for a second diode temperature sensor. Clearing
this bit configures Pin 11 as THERM output and Pin 12 as general purpose logic input (GPI).
(Power-Up Default = 0.)
6
7
GPI Invert
D2
Read/Write
Read/Write
Table VII. Register 0x41 Interrupt Status Register. Power-On Default <7:0> = 00h
Bit Name
Read/Write
Description
0
1
Int. Temp Error
Ext. Temp2 Error
Read Only
Read Only
A one indicates that one of the internal temperature sensor limits has been exceeded.
A one indicates that one of the limits for the second external temperature sensor has
been exceeded.
2
3
4
Diode 2 Fault
Reserved
GPI Input
Read Only
Read Only
Read Only
A one indicates either a short- or open-circuit fault on remote sensor diode 2.
Undefined
A “1” indicates that the GPI pin is asserted. The polarity of the GPI pin is determined
by GPI Invert (Bit 6) in the Configuration Register. For example, if GPI Invert is cleared,
this bit will be “1” when the GPI pin is high (“1”); this bit will be “0” when the GPI
pin is low (“0”). If GPI Invert is set, this bit will be “1” when the GPI pin is low (“0”);
this bit will be “0” when the GPI pin is high (“1”). Note that the state of GPI is not
latched; this bit simply reflects the state or inverted state of the GPI pin. Note: if this
bit is “1” reading this register will NOT clear it to “0.”
5
Ext. Temp1 Error
Read Only
A one indicates that one of the limits for the first external temperature sensor has been
exceeded.
6
7
THERM Input
Diode 1 Fault
Read Only
Read Only
A one indicates that the thermal overload (THERM) line has been asserted externally.
A one indicates either a short- or open-circuit fault on remote sensor diode 1.
NOTE: An error that causes continuous interrupts to be generated may be masked in its respective mask register until the error can be alleviated.
REV. B
–17–
ADM1022
Table VIII. 0x43 Interrupt Mask Register. Power-On Default <7:0> = 00h
Bit
Name
Read/Write
Description
0
1
2
3
4
5
6
7
Int. Temp Error
Ext. Temp2 Error
Diode 2 Fault
Reserved
Read Only
Read Only
Read Only
Read Only
Read/Write
Read/Write
Read/Write
Read/Write
A one disables the corresponding interrupt status bit for the INT output.
A one disables the corresponding interrupt status bit for the INT output.
A one disables the corresponding interrupt status bit for the INT output.
Undefined
A one disables the corresponding interrupt status bit for the INT output.
A one disables the corresponding interrupt status bit for the INT output.
A one disables the corresponding interrupt status bit for the INT output.
A one disables the corresponding interrupt status bit for the INT output.
GPI Input
Ext. Temp1 Error
THERM Input
Diode 1 Fault
Table IX. Register 0x4C Interrupt Status Register Mirror. Power-On Default <7:0> = 00h
Bit
Name
Read/Write
Description
0
1
Int. Temp Error
Ext. Temp2 Error
Read Only
Read Only
A one indicates that one of the internal temperature sensor limits has been exceeded.
A one indicates that one of the limits for the second external temperature sensor
has been exceeded.
2
3
4
Diode 2 Fault
Reserved
GPI Input
Read Only
Read Only
Read Only
A one indicates either a short- or open-circuit fault on remote sensor diode 2.
Undefined
A “1” indicates that the GPI pin is asserted. The polarity of the GPI pin is
determined by GPI Invert (Bit 6) in the Configuration Register. For example, if GPI
Invert is cleared, this bit will be “1” when the GPI pin is high (“1”); this bit will be
“0” when the GPI pin is low (“0.”) If GPI Invert is set, this bit will be “1” when
the GPI pin is low (“0”); this bit will be “0” when the GPI pin is high (“1”). Note
that the state of GPI is not latched; this bit simply reflects the state or inverted
state of the GPI pin. Note: if this bit is “1” reading this register will NOT clear
it to “0.”
5
Ext. Temp1 Error
Read Only
A one indicates that one of the limits for the first external temperature sensor has
been exceeded.
6
7
THERM Input
Diode 1 Fault
Read Only
Read Only
A one indicates that the thermal overload (THERM) line has been asserted externally.
A one indicates either a short- or open-circuit fault on remote sensor diode 1.
REV. B
–18–
ADM1022
OUTLINE DIMENSIONS
16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions shown in inches
0.193
BSC
16
1
9
8
0.154
BSC
0.236
BSC
PIN 1
0.069
0.053
0.065
0.049
8؇
0؇
0.010
0.004
0.012
0.008
0.025
BSC
0.050
0.016
SEATING
PLANE
0.010
0.006
COPLANARITY
0.004
COMPLIANT TO JEDEC STANDARDS MO-137AB
Revision History
Location
Page
4/03—Data Sheet changed from REV. A to REV. B.
Added ESD Caution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7/01—Data Sheet changed from REV. 0 to REV. A.
Figure 1 replaced with new figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
REV. B
–19–
–20–
相关型号：
ADM1022ARQZ-REEL7
IC 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16, MO-137AB, QSOP-16, Power Management Circuit
ADI
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