ADL5521_08 [ADI]
400 MHz - 4000 MHz Low Noise Amplifier; 400兆赫 - 4000 MHz低噪声放大器
| 型号： | ADL5521_08 |
| 厂家： | 
ADI |
| 描述： | 400 MHz - 4000 MHz Low Noise Amplifier |
| 文件： | 总45页 (文件大小：2874K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
400 MHz – 4000 MHz
Low Noise Amplifier
ADL5521
Preliminary Technical Data
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Operation from 400 MHz to 4000 MHz
Noise figure of 0.8 dB at 900 MHz
Including external input match
Gain of 20.0 dB at 900 MHz
ACTIVE
BIAS
VBIAS 1
8 VPOS
OIP3 of 37.7 dBm at 900 MHz
RFIN 2
NC 3
7 RFOUT
6 NC
P1dB of 22.0 dBm at 900 MHz
Integrated bias control circuit
Single supply operation from 3 V to 5 V
Operating current of 26 mA at 3 V
Small footprint LFCSP package
Pin compatible with 17.5 dB gain ADL5523
ADL5521
NC 4
5 NC
Figure 1.
GENERAL DESCRIPTION
The ADL5521 is a high performance GaAs pHEMT low-noise
amplifier. It provides high gain and low noise figure for single down-
conversion IF sampling receiver architectures as well as direct down
conversion receivers. The ADL5521 also has low power
consumption at 3 V.
The ADL5521 allows optimal noise matching without sacrificing
significant gain matching. S11 of better then 6 dB can typically be
achieved when matching for optimal noise.
The ADL5521 amplifier comes in a compact, thermally enhanced,
3mm x 3mm LFCSP package and operates over the temperature
range of −40°C to +85°C.
The ADL5523 is a companion part that offers a gain of 17.5 dB in a
pin compatible package. A fully populated evaluation board is also
available.
Rev. PrC
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2008 Analog Devices, Inc. All rights reserved.
ADL5521
Preliminary Technical Data
AC Specifications................................................................................................................................................................................................................4
AC Specifications................................................................................................................................................................................................................5
AC Specifications (cont.)...................................................................................................................................................................................................6
AC Specifications (cont.)...................................................................................................................................................................................................7
De-Embedded S-Parameters, VPOS = 5V .........................................................................................................................................................................8
De-Embedded S-Parameters, VPOS = 5V (Cont.) ...........................................................................................................................................................9
De-Embedded S-Parameters, VPOS = 3V ...................................................................................................................................................................... 10
De-Embedded S-Parameters, VPOS = 3V (Cont.) ........................................................................................................................................................ 11
Absolute Maximum Ratings........................................................................................................................................................................................... 12
ESD Caution................................................................................................................................................................................................................. 12
Pin Configuration And Functional Descriptions........................................................................................................................................................ 13
Typical Performance Characteristics, 500MHz, VPOS = 5V .................................................................................................................................... 14
Typical Performance Characteristics, 900MHz, VPOS = 5V .................................................................................................................................... 15
Typical Performance Characteristics, 1300MHz, VPOS = 5V.................................................................................................................................. 16
Typical Performance Characteristics, 1950MHz, VPOS = 5V.................................................................................................................................. 17
Typical Performance Characteristics, 2140MHz, VPOS = 5V.................................................................................................................................. 18
Typical Performance Characteristics, 2600MHz, VPOS = 5V.................................................................................................................................. 19
Typical Performance Characteristics, 3500MHz, VPOS = 5V.................................................................................................................................. 20
Typical Performance Characteristics, 500MHz, VPOS = 3V .................................................................................................................................... 21
Typical Performance Characteristics, 900MHz, VPOS = 3V .................................................................................................................................... 22
Typical Performance Characteristics, 1300MHz, VPOS = 3V.................................................................................................................................. 23
Typical Performance Characteristics, 1950MHz, VPOS = 3V.................................................................................................................................. 24
Typical Performance Characteristics, 2140MHz, VPOS = 3V.................................................................................................................................. 25
Typical Performance Characteristics, 2600MHz, VPOS = 3V.................................................................................................................................. 26
Typical Performance Characteristics, 3500MHz, VPOS = 3V.................................................................................................................................. 27
Typical DC Performance Characteristics..................................................................................................................................................................... 28
Source Pull Circles, Gain and Noise Figure, VPOS = 5V.............................................................................................................................................. 30
LOAD Pull Circles, Gain and IP3, VPOS = 5V .............................................................................................................................................................. 31
Source Pull Circles, Noise Figure, VPOS = 3V............................................................................................................................................................... 32
LOAD Pull Circles, Gain and IP3, VPOS = 3V .............................................................................................................................................................. 33
Tuning the ADL5521/23 Eval Board for Optimal Noise Figure................................................................................................................................ 34
Tuning S22................................................................................................................................................................................................................ 34
Rev. PrC| Page 2 of 45
Preliminary Technical Data
ADL5521
Tuning the LNA Input for Optimal Gain............................................................................................................................................................. 37
Tuning the LNA Input for Optimal Noise Figure............................................................................................................................................... 37
S11 Parameters of ADL5521,23 with S22 Matched ............................................................................................................................................ 38
Example of Optimal Noise Matching at 850MHz............................................................................................................................................... 41
Outline Dimensions ........................................................................................................................................................................................................ 45
Ordering Guide............................................................................................................................................................................................................ 45
Rev. PrC| Page 3 of 45
ADL5521
Preliminary Technical Data
AC SPECIFICATIONS
T = 25°C, RBIAS = 3.3KΩ, parameters include matching circuit, matched for optimal noise, unless otherwise noted
Table 1.
Parameter
Conditions
3V
5V
Min
Typ
Max
Min
Typ
Max
Unit
Frequency = 500MHz
Gain (S21)
21.6
TBD
22.5
TBD
dB
Gain Flatness
In the [450 – 550]
frequency band
dB/MHz
Gain vs. Temperature
-40° to +85 C°
TBD
TBD
dB/degC
dB
Noise Figure
1.0
1.0
RBIAS = 3.3KΩ
RBIAS = 5.2KΩ
0.9
0.9
Output IP3
Two tones, each 0dBm
out
29.0
37.8
dBm
dBm
Output 1 dB Compression
Point
16.8
22.0
Input return loss (S11)
Output return loss (S22)
-7.5
-8.6
dB
dB
dB
-16.9
-26.9
-16.4
-27.9
Isolation (S12)
Frequency = 900MHz
Gain (S21)
19.7
TBD
20
dB
Gain Flatness
In the [850 – 950]
frequency band
TBD
dB/MHz
Gain vs. Temperature
-40° to +85 C°
TBD
TBD
dB/degC
dB
Noise Figure
0.9
0.9
RBIAS = 3.3KΩ
RBIAS = 5.2KΩ
0.9
0.8
Output IP3
Two tones, each 0dBm
out
27.8
37.7
dBm
dBm
Output 1 dB Compression
Point
16.8
22.0
Input return loss (S11)
Output return loss (S22)
-7.6
-8.5
dB
dB
-16.3
17.1
Isolation (S12)
-24.4
25.5
dB
Rev. PrC| Page 4 of 45
Preliminary Technical Data
ADL5521
AC SPECIFICATIONS
T = 25°C, RBIAS = 3.3KΩ, parameters include matching circuit, matched for optimal noise, unless otherwise noted
Table 2.
Parameter
Conditions
3V
5V
Min
Typ
Max
Min
Typ
Max
Unit
Frequency = 1300MHz
Gain (S21)
18.1
TBD
18.4
TBD
dB
Gain Flatness
In the [1200 – 1300]
frequency band
dB/MHz
Gain vs. Temperature
40° to +85 C°
-
TBD
TBD
dB/degC
dB
Noise Figure
0.9
0.9
RBIAS = 3.3KΩ
RBIAS = 5.2KΩ
0.8
0.8
Output IP3
Two tones, each 0dBm
out
29.7
35.6
dBm
dBm
Output 1 dB Compression
Point
16.2
21.9
Input return loss (S11)
Output return loss (S22)
Isolation (S12)
-6.3
-7.9
dB
dB
dB
-16.8
-22.3
-16.2
-23.3
Frequency = 1950MHz
Gain (S21)
14.9
TBD
15.4
dB
Gain Flatness
In the [1920 – 1980]
frequency band
0.015
dB/MHz
Gain vs. Temperature
40° to +85 C°
-
TBD
0.018
dB/degC
dB
Noise Figure
0.9
0.9
RBIAS = 3.3KΩ
RBIAS = 5.2KΩ
0.8
0.8
Output IP3
Two tones, each 0dBm
out
29.4
35.5
dBm
dBm
21.6
Output 1 dB Compression
Point
16.0
Input return loss (S11)
Output return loss (S22)
-8.1
-8.9
dB
dB
-25.7
-29.9
Isolation (S12)
-21.2
-21.7
dB
Rev. PrC| Page 5 of 45
ADL5521
Preliminary Technical Data
AC SPECIFICATIONS (CONT.)
T = 25°C, RBIAS = 3.3KΩ, parameters include matching circuit, matched for optimal noise, unless otherwise noted
Table 3.
Parameter
Conditions
3V
5V
Min
Typ
Max
Min
Typ
Max
Unit
Frequency = 2140MHz
Gain (S21)
14.4
TBD
14.8
TBD
dB
Gain Flatness
In the [2110 – 2170]
frequency band
dB/MHz
Gain vs. Temperature
40° to +85 C°
-
TBD
TBD
dB/degC
dB
Noise Figure
0.9
0.9
RBIAS = 3.3KΩ
RBIAS = 5.2KΩ
0.8
0.8
Output IP3
Two tones, each 0dBm
out
31.1
35.8
dB
dBm
Output 1 dB Compression
Point
16.1
21.5
Input return loss (S11)
Output return loss (S22)
-7.8
-8.5
dB
dB
-32.1
-35.6
Isolation (S12)
Frequency = 2600MHz
Gain (S21)
-20.6
-21.1
dB
12.1
TBD
12.5
TBD
dB
Gain Flatness
In the [2500 – 2700]
frequency band
dB/MHz
Gain vs. Temperature
40° to +85 C°
-
TBD
TBD
dB/degC
dB
Noise Figure
0.9
0.9
RBIAS = 3.3KΩ
RBIAS = 5.2KΩ
0.8
0.8
Output IP3
Two tones, each 0dBm
out
31.0
35.5
dBm
dBm
Output 1 dB Compression
Point
16.0
21.1
Input return loss (S11)
Output return loss (S22)
-6.1
-6.4
dB
dB
-15.7
-15.8
Isolation (S12)
-20.2
-20.6
dB
Rev. PrC| Page 6 of 45
Preliminary Technical Data
ADL5521
AC SPECIFICATIONS (CONT.)
T = 25°C, RBIAS = 3.3KΩ, parameters include matching circuit, matched for optimal noise, unless otherwise noted
Table 4.
Parameter
Conditions
3V
5V
Min
Typ
Max
Min
Typ
Max
Unit
Frequency = 3500MHz
Gain (S21)
10.0
TBD
10.5
TBD
dB
Gain Flatness
In the [3400 – 3600]
frequency band
dB/MHz
Gain vs. Temperature
40° to +85 C°
-
TBD
TBD
dB/degC
dB
Noise Figure
1.1
1.1
1.1
33
RBIAS = 3.3KΩ
RBIAS = 5.2KΩ
1.1
Output IP3
Two tones, each 0dBm
out
28.1
dBm
dBm
Output 1 dB Compression
Point
15.0
20.2
Input return loss (S11)
Output return loss (S22)
Isolation (S12)
-8.6
-9.1
dB
dB
dB
-17.1
-18.0
-17.1
-18.3
DC Specifications
Parameter
Conditions
3V
5V
Typ
Min
Typ
Max
Min
Max
Unit
Current Consumption
36
65
48
ma
RBIAS = 3.3KΩ
RBIAS = 5.2KΩ
TBD
Rev. PrC| Page 7 of 45
ADL5521
Preliminary Technical Data
DE-EMBEDDED S-PARAMETERS, VPOS = 5V
Frequency (GHz)
S11
S11
S12
S12
S21
S21
S22
S22
K
(Mag) (Angle) (Mag) (Angle) (Mag) (Angle) (Mag) (Angle)
0.05
0.125
0.25
0.375
0.5
0.625
0.75
0.875
1.0
1.125
1.25
1.375
1.5
1.625
1.75
1.875
2.0
2.125
2.25
2.375
2.5
2.625
2.75
2.875
3.0
3.125
Rev. PrC| Page 8 of 45
Preliminary Technical Data
ADL5521
DE-EMBEDDED S-PARAMETERS, VPOS = 5V (CONT.)
Frequency (GHz)
S11
S11
S12
S12
S21
S21
S22
S22
K
(Mag) (Angle) (Mag) (Angle) (Mag) (Angle) (Mag) (Angle)
3.125
3.25
3.375
3.5
3.625
3.75
3.875
4.0
Rev. PrC| Page 9 of 45
ADL5521
Preliminary Technical Data
DE-EMBEDDED S-PARAMETERS, VPOS = 3V
Frequency (GHz)
S11
S11
S12
S12
S21
S21
S22
S22
K
(Mag) (Angle) (Mag) (Angle) (Mag) (Angle) (Mag) (Angle)
0.05
0.125
0.25
0.375
0.5
0.625
0.75
0.875
1.0
1.125
1.25
1.375
1.5
1.625
1.75
1.875
2.0
2.125
2.25
2.375
2.5
2.625
2.75
2.875
3.0
3.125
Rev. PrC| Page 10 of 45
Preliminary Technical Data
ADL5521
DE-EMBEDDED S-PARAMETERS, VPOS = 3V (CONT.)
Frequency (GHz)
S11
S11
S12
S12
S21
S21
S22
S22
K
(Mag) (Angle) (Mag) (Angle) (Mag) (Angle) (Mag) (Angle)
3.125
3.25
3.375
3.5
3.625
3.75
3.875
4.0
Rev. PrC| Page 11 of 45
ADL5521
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 5
Parameter
Rating
5.5 V
Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those
listed in the operational sections of this specification is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Supply Voltage, VPOS
Max RF Input Level
+20dBm
TBD mW
TBD mW
Internal Power Dissipation
θJA (Exposed paddle soldered down)
θJA (Exposed paddle not soldered down) TBD°C/W
θJC (At exposed paddle)
TBD°C/W
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
TBD°C/W
TBD°C
–40°C to +85°C
–65°C to +150°C
Lead Temperature Range
(Soldering 60 sec)
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrC| Page 12 of 45
Preliminary Technical Data
ADL5521
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
Top View
(not to scale)
VBIAS 1
8 VPOS
RFIN 2
NC 3
7 RFOUT
6 NC
Exposed Pad
NC 4
5 NC
ADL5521
Figure 2. 8-Lead LFCSP
Table 3. Pin Function Descriptions- 8Lead CSP
Pin No.
Mnemonic
Description
1
VBIAS
Bias: Internal DC bias. This pin should be connected to VPOS
through a 3.3KΩ resistor for optimum performance
2
RFIN
NC
RF Input: Input to LNA
3,4,5,6
NC: No internal connection
7
8
RFOUT
VPOS
RF Output: Must be AC-coupled.
Supply: VDD bias needs to be bypassed to ground using
low-inductance capacitors. The recommended
configuration is for the output matching to be done on this
pin. See schematics in applications section.
Exposed pad
EP
Exposed Paddle: Connect to a low impedance ground plane
Rev. PrC| Page 13 of 45
ADL5521
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS, 500MHZ, VPOS = 5V
Matched for optimal noise figure, external matching circuit included.
Figure 3. Typical S Parameters, Log magnitude
Figure 5.Gain, P1dB, OIP3 vs. Frequency
Figure 4. S11 and S22, Smith Chart
Figure 6. Distribution of Noise Figure for Five Parts
Figure 7. Output Power and Gain vs. Temperature
Figure 8. O IP3 vs. Output Power, Temperature and Frequency
Rev. PrC| Page 14 of 45
Preliminary Technical Data
ADL5521
TYPICAL PERFORMANCE CHARACTERISTICS, 900MHZ, VPOS = 5V
Matched for optimal noise figure, external matching circuit included.
Figure 9. Typical S Parameters, Log magnitude
Figure 11.Gain, P1dB, OIP3 vs. Frequency
Figure 10. S11 and S22, Smith Chart
Figure 12. Distribution of Noise Figure for Five Parts
Figure 13. Output Power and Gain vs. Temperature
Figure 14. O IP3 vs. Output Power, Temperature and Frequency
Rev. PrC| Page 15 of 45
ADL5521
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS, 1300MHZ, VPOS = 5V
Matched for optimal noise figure, external matching circuit included.
Figure 15. Typical S Parameters, Log magnitude
Figure 17.Gain, P1dB, OIP3 vs. Frequency
Figure 16. S11 and S22, Smith Chart
Figure 18. Distribution of Noise Figure for Five Parts
Figure 19. Output Power and Gain vs. Temperature
Figure 20. O IP3 vs. Output Power, Temperature and Frequency
Rev. PrC| Page 16 of 45
Preliminary Technical Data
ADL5521
TYPICAL PERFORMANCE CHARACTERISTICS, 1950MHZ, VPOS = 5V
Matched for optimal noise figure, external matching circuit included.
Figure 21. Typical S Parameters, Log magnitude
Figure 22. S11 and S22, Smith Chart
3.5
3
30
28
26
24
22
20
18
16
14
40
35
30
25
20
15
10
5
OIP3 (-40°C
+25°C
+85°C)
2.5
2
P1dB (-40°C
+25°C
+85°C)
1.5
1
Gain (-40°C
+25°C
0.5
+85°C)
0
0
1920
1930
1940
1950
1960
1970
1980
1920
1930
1940
1950
1960
1970
1980
Frequency (MHz)
Freq - MHz
Figure 23.Gain, P1dB, OIP3 vs. Frequency
Figure 24. Distribution of Noise Figure for Five Parts
30
38
-40°C (1920MHz
1950MHz
37
36
35
34
33
32
31
30
29
28
27
26
25
25
20
15
10
5
1980MHz)
+85°C (1920MHz
Gain (-40°C
1950MHz
1980MHz)
+25°C (1920MHz
1950MHz
+25°C
+85°C)
Output Power (-40°C
+25°C
1980MHz)
+85°C)
0
-5
-8
-6
-4
-2
0
2
4
6
8
10
12
14
16
18
20
-10
-25
-20
-15
-10
Pin - dBm
-5
0
5
10
Pout - dBm
Figure 25. Output Power and Gain vs. Temperature
Figure 26. O IP3 vs. Output Power, Temperature and Frequency
Rev. PrC| Page 17 of 45
ADL5521
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS, 2140MHZ, VPOS = 5V
Matched for optimal noise figure, external matching circuit included.
Figure 27. Typical S Parameters, Log magnitude
Figure 29.Gain, P1dB, OIP3 vs. Frequency
Figure 28. S11 and S22, Smith Chart
Figure 30. Distribution of Noise Figure for Five Parts
Figure 31. Output Power and Gain vs. Temperature
Figure 32. O IP3 vs. Output Power, Temperature and Frequency
Rev. PrC| Page 18 of 45
Preliminary Technical Data
ADL5521
TYPICAL PERFORMANCE CHARACTERISTICS, 2600MHZ, VPOS = 5V
Matched for optimal noise figure, external matching circuit included.
Figure 33. Typical S Parameters, Log magnitude
Figure 35.Gain, P1dB, OIP3 vs. Frequency
Figure 34. S11 and S22, Smith Chart
Figure 36. Distribution of Noise Figure for Five Parts
Figure 37. Output Power and Gain vs. Temperature
Figure 38. O IP3 vs. Output Power, Temperature and Frequency
Rev. PrC| Page 19 of 45
ADL5521
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS, 3500MHZ, VPOS = 5V
Matched for optimal noise figure, external matching circuit included.
Figure 39. Typical S Parameters, Log magnitude
Figure 41.Gain, P1dB, OIP3 vs. Frequency
Figure 40. S11 and S22, Smith Chart
Figure 42. Distribution of Noise Figure for Five Parts
Figure 43. Output Power and Gain vs. Temperature
Figure 44. O IP3 vs. Output Power, Temperature and Frequency
Rev. PrC| Page 20 of 45
Preliminary Technical Data
ADL5521
TYPICAL PERFORMANCE CHARACTERISTICS, 500MHZ, VPOS = 3V
Matched for optimal noise figure, external matching circuit included.
Figure 45. Typical S Parameters, Log magnitude
Figure 47.Gain, P1dB, OIP3 vs. Frequency
Figure 46. S11 and S22, Smith Chart
Figure 48. Distribution of Noise Figure for Five Parts
Figure 49. Output Power and Gain vs. Temperature
Figure 50. O IP3 vs. Output Power, Temperature and Frequency
Rev. PrC| Page 21 of 45
ADL5521
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS, 900MHZ, VPOS = 3V
Matched for optimal noise figure, external matching circuit included.
Figure 51. Typical S Parameters, Log magnitude
Figure 53.Gain, P1dB, OIP3 vs. Frequency
Figure 52. S11 and S22, Smith Chart
Figure 54. Distribution of Noise Figure for Five Parts
Figure 55. Output Power and Gain vs. Temperature
Figure 56. O IP3 vs. Output Power, Temperature and Frequency
Rev. PrC| Page 22 of 45
Preliminary Technical Data
ADL5521
TYPICAL PERFORMANCE CHARACTERISTICS, 1300MHZ, VPOS = 3V
Matched for optimal noise figure, external matching circuit included.
Figure 57. Typical S Parameters, Log magnitude
Figure 59.Gain, P1dB, OIP3 vs. Frequency
Figure 58. S11 and S22, Smith Chart
Figure 60. Distribution of Noise Figure for Five Parts
Figure 61. Output Power and Gain vs. Temperature
Figure 62. O IP3 vs. Output Power, Temperature and Frequency
Rev. PrC| Page 23 of 45
ADL5521
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS, 1950MHZ, VPOS = 3V
Matched for optimal noise figure, external matching circuit included.
Figure 63. Typical S Parameters, Log magnitude
Figure 65.Gain, P1dB, OIP3 vs. Frequency
Figure 64. S11 and S22, Smith Chart
Figure 66. Distribution of Noise Figure for Five Parts
Figure 67. Output Power and Gain vs. Temperature
Figure 68. O IP3 vs. Output Power, Temperature and Frequency
Rev. PrC| Page 24 of 45
Preliminary Technical Data
ADL5521
TYPICAL PERFORMANCE CHARACTERISTICS, 2140MHZ, VPOS = 3V
Matched for optimal noise figure, external matching circuit included.
Figure 69. Typical S Parameters, Log magnitude
Figure 71.Gain, P1dB, OIP3 vs. Frequency
Figure 70. S11 and S22, Smith Chart
Figure 72. Distribution of Noise Figure for Five Parts
Figure 73. Output Power and Gain vs. Temperature
Figure 74. O IP3 vs. Output Power, Temperature and Frequency
Rev. PrC| Page 25 of 45
ADL5521
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS, 2600MHZ, VPOS = 3V
Matched for optimal noise figure, external matching circuit included.
Figure 75. Typical S Parameters, Log magnitude
Figure 77.Gain, P1dB, OIP3 vs. Frequency
Figure 76. S11 and S22, Smith Chart
Figure 78. Distribution of Noise Figure for Five Parts
Figure 79. Output Power and Gain vs. Temperature
Figure 80. O IP3 vs. Output Power, Temperature and Frequency
Rev. PrC| Page 26 of 45
Preliminary Technical Data
ADL5521
TYPICAL PERFORMANCE CHARACTERISTICS, 3500MHZ, VPOS = 3V
Matched for optimal noise figure, external matching circuit included.
Figure 81. Typical S Parameters, Log magnitude
Figure 83.Gain, P1dB, OIP3 vs. Frequency
Figure 82. S11 and S22, Smith Chart
Figure 84. Distribution of Noise Figure for Five Parts
Figure 85. Output Power and Gain vs. Temperature
Figure 86. O IP3 vs. Output Power, Temperature and Frequency
Rev. PrC| Page 27 of 45
ADL5521
Preliminary Technical Data
TYPICAL DC PERFORMANCE CHARACTERISTICS
70
69
68
67
66
65
64
63
62
61
60
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
Temperature - degC
Figure 87. ADL5521 Current vs. Temperature, VPOS = 5V
Rev. PrC| Page 28 of 45
Preliminary Technical Data
ADL5521
VPOS
C5 (1nF)
a
L2
C3 (1nF)
R1 (3.3KΩ)
VBIAS
VDD
1
8
L1**
C2 (82pF)
2
7
6
5
Input
RFIN
RFOUT
3
4
C1*
NC
NC
NC
NC
note - ground is through thermal pad
*Murata-Erie multilayer ceramic cap
**Coilcraft High Q Surface Mount Inductor
Figure 88. LNA Eval Board Schematic.
Table 6. Recommended Components and Positions of Matching Components for Basic Connections, Tuned for Optimal Noise
Frequency
500MHz
900 MHz
1300 MHz
C1
C2
C3
C4
C5
L1
9nH
8.2nH 3.4nH
3.4nH
L2
12nH
TR1(mm) TR2(mm)
R1
open
2.4pF
2.7pF
0
0
0
0
0
open
150pf
7.5 x 0.5
0Ω
1950 MHz
2140 MHz
2600 MHz
3500 MHz
1.3pF
1.3pf
1.3pf
0.5pf
1.1nH
4 x 0.5
4.5 x 0.5
5 x 0.5
3.5 x 0.5
3.0 x 0.5
2.5 x 0.5
1x 0.5
0Ω
10nF 220pF 82pF
3.3KΩ
1.1nH
1nF
0Ω
1.3nH
0Ω
1.2nf 2.4pf*
6.5 x 0.5
0Ω
*Capacitor, not inductor, used to match at 3500MHz
Rev. PrC| Page 29 of 45
ADL5521
Preliminary Technical Data
SOURCE PULL CIRCLES, GAIN AND NOISE FIGURE, VPOS = 5V
Figure 89. Noise Contours for
500MHz Matching Components
Figure 90. Noise Contours for
2140MHz Matching Components
Figure 91. Noise Contours for
900MHz Matching Components
Figure 92. Noise Contours for
2600MHz Matching Components
Figure 93. Noise Contours for
Figure 94. Noise Contours for
1300MHz Matching Components
3500MHz Matching Components
Figure 95. Noise Contours for
1950MHz Matching Components
Rev. PrC| Page 30 of 45
Preliminary Technical Data
ADL5521
LOAD PULL CIRCLES, GAIN AND IP3, VPOS = 5V
Figure 96. IP3 and Gain Contours for
500MHz Matching Components
Figure 97. IP3 and Gain Contours
for 2140MHz Matching Components
Figure 98. IP3 and Gain Contours for
900MHz Matching Components
Figure 99. IP3 and Gain Contours for
2600MHz Matching Components
Figure 100. IP3 and Gain Contours
Figure 101. IP3 and Gain Contours
for 1300MHz Matching Components for 3500MHz Matching Components
Figure 102. IP3 and Gain Contours
for 1950MHz Matching Components
Rev. PrC| Page 31 of 45
ADL5521
Preliminary Technical Data
SOURCE PULL CIRCLES, NOISE FIGURE, VPOS = 3V
Figure 103. Noise Contours for
500MHz Matching Components
Figure 104. Noise Contours for
2140MHz Matching Components
Figure 105. Noise Contours for
900MHz Matching Components
Figure 106. Noise Contours for
2600MHz Matching Components
Figure 107. Noise Contours for
Figure 108. Noise Contours for
1300MHz Matching Components
3500MHz Matching Components
Figure 109. Noise Contours for
1950MHz Matching Components
Rev. PrC| Page 32 of 45
Preliminary Technical Data
ADL5521
LOAD PULL CIRCLES, GAIN AND IP3, VPOS = 3V
Figure 110. IP3 and Gain Contours
for 500MHz Matching Components
Figure 111. IP3 and Gain Contours
for 2140MHz Matching Components
Figure 112. IP3 and Gain Contours
for 900MHz Matching Components
Figure 113. IP3 and Gain Contours
for 2600MHz Matching Components
Figure 114. IP3 and Gain Contours
Figure 115. IP3 and Gain Contours
for 1300MHz Matching Components for 3500MHz Matching Components
Figure 116. IP3 and Gain Contours
for 1950MHz Matching Components
Rev. PrC| Page 33 of 45
ADL5521
Preliminary Technical Data
TUNING THE ADL5521/23 EVAL BOARD FOR OPTIMAL NOISE FIGURE
The ADL5521 and ADL5523 are monolithic LNAs in a 3x3mm
LFCSP package. The eval board, as shipped from the factory,
should give a noise figure of 0.9dB over a bandwidth of several
hundred MHz. The specific frequency where optimal noise is
reached depends on the tuning.
The slider can be seen in the LNA PCB layout in Figure 117 as the
red area to the right of the bias line. With a 0 Ω jumper in place of
L2, moving a 1nF capacitor from the top to the bottom effectively
tunes S22 from 1400 MHz to 3500MHz. Table 7 shows the
component values and placement required for S22 tuning from
800MHz to 3200MHz. For lower frequencies, higher values of L2
can be used to tune S22, and for frequencies from 3.2GHx to
4.0GHz, smaller values of capacitors can be used on the slider.
The bandwidth of the ADL5521 is 400MHz to 4GHz, although
noise figure will degrade above 2.5GHz as the gain begins to roll
off.
The results for S22 tuned for different frequencies are shown in
Figure 118 to Figure 123.
Note – The factory eval board has a bias resistor on the LNA of
3.3K Ω. If this bias resistor is increased to 5.2K Ω, the optimal
noise figure will drop to 0.8dB, but the tradeoff is that the OIP3
will typically drop from 35 to 33dB. The change in S parameters
will be insignificant when changing bias resistors, so this section
will only take into account measurements done with 3.3K Ω bias
resistor.
Frequency
(MHz)
L2 (nH)
C3 (nF)
C3
Placement
800
3.4
0 Ω
0 Ω
0 Ω
0 Ω
0 Ω
Open
Open
1nF
Contents of this note are based completely on lab measurements.
Although there are plots in which the Agilent ADS environment is
used, the data in these plots comes completely from lab
measurements.
1400
2000
2400
2800
3200
A
B
1nF
1nf
Tuning S22
Tuning of the LNA begins with S22 (output tuning). Tuning of the
LNA output is done by placing reactive components on the bias
line, referred to in the schematics in Figure 88 as VPOS.
C
D
1nf
Table 7. Capacitor and Inductor Tuning and Placement for LNA S22 Tuning
On the LNA eval board, S22 tuning is achieved by either the use of
an inductor (L2) on the bias line, or a shunt cap C3) on the bias
line to ground. Typically, either L2 is required, or C3, but not
both.
The evaluation board uses a ‘slider’ on the bias line in order to
make tuning for S22 as easy as possible. The slider is an area of
ground etch adjacent to the bias line that is clear of solder mask.
The bias line in this area is also free of solder mask. This allows a
capacitor (C3) to be placed anywhere on the bias line to ground
and so provides easy, very accurate tuning for S22.
Note that the PCB layout shows two capacitors, C3 and C4.
Typically only one of these is needed for good S22 tuning.
Rev. PrC| Page 34 of 45
Preliminary Technical Data
ADL5521
Figure 117. PCB Layout for LNA Eval Board, Note 'Slider' on Bias Line
Rev. PrC| Page 35 of 45
ADL5521
Preliminary Technical Data
Figure 118. S22 tuned for 800MHz
Figure 119. S22 tuned for 2.4GHz
Figure 120. S22 tuned for 1400MHz
Figure 121. S22 tuned for 2.8GHz
Figure 122. S22 tuned for 2.0GHz
Figure 123. S22 tuned for 3.2GHz
Rev. PrC| Page 36 of 45
Preliminary Technical Data
ADL5521
Tuning the LNA Input for Optimal Gain
LNAs are generally tuned for either gain or noise optimization, or
some tradeoff between the two. One figure of merit of an LNA is
how much tradeoff must be made for one of these parameters to
optimize the other. With the ADL5521 and ADL5523, S11 of 6 to
8dB at the input to the matching network can still be typically
achieved when optimizing for noise.
S11*
For optimal gain matching, the goal is to use a matching network
that converts the input impedance of the LNA to the characteristic
impedance of the system, typically 50 Ω. Correct tuning for gain
matching results in a conjugate match. That is, the impedance of
the matching network at the LNA input, looking back toward the
generator, will always be the complex conjugate of the LNA input
impedance when matched for gain.
S11
Once the conjugate of S11 is known, a matching circuit must be
found which transforms the 50 Ω system impedance into the
conjugate S11 impedance. To do this, the designer starts at the
origin of the circle and finds components that move the 50
Ω match to S11*.
Figure 125. Smith Chart Representation of Conjugate Match
Tuning the LNA Input for Optimal Noise Figure
The related impedances for gain matching are shown in Figure
124. A Smith Chart representation of the conjugate match is
shown in Figure 125.
The point in the Smith Chart at which matching for optimal noise
occurs is typically referred to as Gamma Optimal, or ΓOPT. It’s
often different than the gain matching point. Finding ΓOPT is not
as obvious as the gain match. ΓOPT is a function of the
semiconductor structure and characteristics of the LNA. Typically,
the fabrication facility that produces the LNA will have this
information. ΓOPT can also be determined by doing source pull
testing in the lab.
50 Ω
S11
Matching
LNA
Network
50 Ω
S11*
Noise matching for the ADL5521 and 23 is actually very easy, as
the area of the Smith Chart where the noise figure is optimal or
near optimal is not confined to a narrow area around ΓOPT. This is
very advantageous as it means that component variations will play
a smaller part in board to board variation of noise figure.
Figure 124. Matching LNA Input for Gain
The matching area for optimal noise for the ADL5523 and
ADL5521 is shown in Figure 126. Note that textbooks usually
define noise circles as a conjugate match. However, for the
purpose of this note this circle is a direct match, we will do things
slightly differently. In our case to find the correct matching circuit,
the designer must start with the S11 of the LNA, then select
components which move the S11 to within this circle.
One important aspect of the overall ADL5521 and 23 ease of
tuning is that as long as S22 is matched for a particular frequency,
this noise matching area remains very consistent in its placement
for that frequency. Said another way, if S22 is matched, we simply
have to take the measured S11 and move it into the black circle for
optimal noise matching.
Rev. PrC| Page 37 of 45
ADL5521
Preliminary Technical Data
Frequency
500MHz
750MHz
900 MHz
1400 MHz
1950 MHz
2150 MHz
2400 MHz
C1
na
C2
C3
C5
L1
9nH
L2
12nH
3.4nH
3.4nH
0 Ω
2.0pf
2.4pF
2.4pF
1.3pF
1.3pf
1.3pf
11nH
8.2nH
5.1nH
1.1nH
1.1nH
1.3nH
na
82pf
1nf
0 Ω
1nF
0 Ω
0 Ω
Table 8. L and C Values for ADL5521 Matching Circuits at Various Frequencies
Figure 126. Area of Optimal Noise Matching for ADL5521, 23
S11 Parameters of ADL5521,23 with S22 Matched
To determine the correct matching circuit for optimal noise, the
next step is to look at the results of S11 for the various frequencies
at which S22 was tuned earlier in this note. Once the S11 is
determined for a particular frequency, all that needs to be done is
to find the matching components that provide that match.
Figure 127 to Figure 132 show S11 for the various frequencies.
Again, these measurements are all based on S22 being matched at
that particular frequency.
Note that the S11 for every example shown in Figure 127 to Figure
132 is either in the lower left quadrant of the Smith Chart or
slightly into the upper left. To move this impedance in the given
noise circle first requires a series L component at the LNA input.
The values for L in all of the examples will differ, but a correct
value of L will move the match along the constant R circle up into
upper left quadrant of the Smith Chart.
A shunt capacitor can then be added to move the match along a
constant admittance line, down and to the right, hopefully right
into the center of the noise circle given in Figure 126.
The solution for the structure of the match for all of the examples
in Figure 127 to Figure 132 is a series L to the input of the LNA,
and a shunt capacitor at the generator end of this inductor.
An example of the effect of the series L, shunt C match, based on
the 800MHz example, is given in Figure 133. This example uses
the output from the Agilent ADS Smith Chart tool.
Rev. PrC| Page 38 of 45
Preliminary Technical Data
ADL5521
Figure 127. S11 of ADL5521 with S22 Matched at 800MHz
Figure 128. S11 of ADL5521 with S22 Matched at 1.4 GHz
Figure 129. S11 of ADL5521 with S22 Matched at 2.0 GHz
Rev. PrC| Page 39 of 45
ADL5521
Preliminary Technical Data
Figure 130. S11 of ADL5521 with S22 Matched at 2.4 GHz
Figure 131. S11 of ADL5521 with S22 Matched at 2.8 GHz
Figure 132. S11 of ADL5521 with S22 Matched at 3.2 GHz
Rev. PrC| Page 40 of 45
Preliminary Technical Data
ADL5521
Figure 133. Example of Series L, Shunt C Matching Network for ΓOPT (800MHz Example)
Example of Optimal Noise Matching at 2.4GHz
Example of Optimal Noise Matching at 850MHz
Based on the S11 information given in Figure 127, a value of L of
9.0nH and a value of C of 2.2pf were experimentally determined
in the lab. The measured results of Noise Figure and S parameters
are given in Figure 134, Figure 135, and Figure 136
Based on the S11 information given in Figure 1275, a value of L of
1.3nH and a value of C of 1.3pf were experimentally determined
in the lab. The measured results of Noise Figure and S parameters
are given in Figure 137, Figure 138, and Figure 139.
Optimal matching component values for several other frequencies
are given in Table 8.
Rev. PrC| Page 41 of 45
ADL5521
Preliminary Technical Data
25
20
15
10
5
Noise Figure
Gain
0
5E+08 7E+08 9E+08 1.1E+09 1.3E+09 1.5E+09 1.7E+09 1.9E+09
Figure 134. Noise Figure of ADL5521 When Tuned for 850MHz
Figure 135. S22 and S11 Matching for ADL5521, 850MHz Example
Rev. PrC| Page 42 of 45
Preliminary Technical Data
ADL5521
Figure 136. Log-Log Plot of S Parameters, ADL5521 850MHz Example
18
16
14
12
10
8
noise figure
gain
6
4
2
0
1.50E+09 1.70E+09 1.90E+09 2.10E+09 2.30E+09 2.50E+09
Figure 137. Noise Figure of ADL5521 When Tuned for 2.4GHz
Rev. PrC| Page 43 of 45
ADL5521
Preliminary Technical Data
Figure 138. S22 and S11 Matching for ADL5521, 2.4GHz Example
Figure 139. Log-Log Plot of S Parameters, ADL5521 2.4GHz Example
Rev. PrC| Page 44 of 45
Preliminary Technical Data
OUTLINE DIMENSIONS
ADL5521
3.25
3.00 SQ
2.75
0.60 MAX
5
0.50
BSC
0.60 MAX
8
2.95
2.75 SQ
2.55
1.60
1.45
1.30
EXPOSED
PAD
TOP
VIEW
PIN 1
INDICATOR
(BOTTOM VIEW)
4
1
PIN 1
INDICATOR
0.50
0.40
0.30
1.89
1.74
1.59
12° MAX
0.90 MAX
0.85 NOM
0.70 MAX
0.65TYP
0.05 MAX
0.01 NOM
0.30
0.23
0.18
SEATING
PLANE
0.20 REF
Figure 140. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
3mm × 3 mm Body, Very Thin, Dual Lead CP-8-2
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADL5521ACPZ-R71
ADL5521ACPZ-WP1
ADL5521-EVALZ
Temperature Range
Package Description
7” Tape and Reel
Waffle Pack
Package Option
–40°C to +85°C
–40°C to +85°C
CP-8-2
CP-8-2
Evaluation Board
ADL5521 is qualified to the reflow profile in JEDEC standard J-STD-020 at a peak temp of 260C. Moisture sensitivity level
per JEDEC standard J-STD-20 is MSL3.
1 Z = Pb free part
Rev. PrC| Page 45 of 45
PR06828-0-2/08(PrC)
相关型号：
ADL5530ACPZ-R2
DC to 1000 MHz IF Gain Block; Package: LFCSP (2x3x.85mm); No of Pins: 8; Temperature Range: Industrial
ADI
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