ADL5306ACP-REEL7 [ADI]

60 dB Range (100 nA to 100 UA) Low Cost Logarithmic Converter; 60分贝范围( 100 nA至100 UA )低成本对数转换器
ADL5306ACP-REEL7
型号: ADL5306ACP-REEL7
厂家: ADI    ADI
描述:

60 dB Range (100 nA to 100 UA) Low Cost Logarithmic Converter
60分贝范围( 100 nA至100 UA )低成本对数转换器

转换器
文件: 总16页 (文件大小:801K)
中文:  中文翻译
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60 dB Range (100 nA to 100 µA)  
Low Cost Logarithmic Converter  
ADL5306  
FEATURES  
Optimized for fiber optic photodiode interfacing  
FUNCTIONAL BLOCK DIAGRAM  
VPOS +5V  
NC  
Measures current over 3 decades  
I
PD  
0.2 log  
10  
(
)
VOUT  
Law conformance 0.1 dB from 100 nA to 100 μA  
Single- or dual-supply operation (3 V to 5.5 V total)  
Full log-ratio capabilities  
VREF  
1nA  
BIAS  
2.5V  
GENERATOR  
80k  
R
20kΩ  
COMM  
REF  
200kΩ  
Temperature stable  
0.5V  
Nominal slope of 10 mV/dB (200 mV/decade)  
Nominal intercept of 1 nA (set by external resistor)  
Optional adjustment of slope and intercept  
Rapid response time for a given current level  
Miniature 16-lead chip scale package (LFCSP 3 mm × 3 mm)  
Low power: ~5 mA quiescent current  
SCAL  
BFIN  
IREF  
V
14.2kΩ  
BIAS  
V
BE2  
1kΩ  
Q2  
Q1  
I
LOG  
TEMPERATURE  
COMPENSATION  
1nF  
VLOG  
451Ω  
V
BE1  
I
PD INPT  
VSUM  
1nF  
6.69kΩ  
COMM  
APPLICATIONS  
1kΩ  
Low cost optical power measurement  
Wide range baseband logarithmic compression  
Measurement of current and voltage ratios  
Optical absorbance measurement  
0.5V  
1nF  
VNEG  
COMM  
03727-0-001  
Figure 1. Functional Block Diagram  
The logarithmic intercept (reference current) is nominally  
GENERAL DESCRIPTION  
positioned at 1 nA by using the externally generated, 100 µA IREF  
current provided by a 200 kΩ resistor connected between VREF, at  
2.5 V, and IREF, at 0.5 V. The intercept can be adjusted over a  
narrow range by varying this resistor. The part can also operate in a  
log-ratio mode, with limited accuracy, where the numerator and  
denominator currents are applied to INPT and IREF, respectively.  
The ADL5306is a low cost microminiature logarithmic converter  
optimized for determining optical power in fiber optic systems. The  
ADL5306 is derived from the AD8304 and AD8305 translinear  
logarithmic converters. This family of devices provides wide  
measurement dynamic range in a versatile and easy-to-use form. A  
single-supply voltage between 3 V and 5.5 V is adequate; dual  
supplies may optionally be used. Low quiescent current (5 mA  
typical) permits use in battery-operated applications.  
A buffer amplifier is provided to drive substantial loads, raise the  
basic 10 mV/dB slope, serve as a precision comparator (threshold  
detector), or implement low-pass filters. Its rail-to-rail output stage  
can swing to within 100 mV of the positive and negative supply  
rails, and its peak current-sourcing capacity is 25 mA.  
IPD, the 100 nA to 100 µA input current applied to the INPT pin, is  
the collector current of an optimally scaled NPN transistor that  
converts this current to a voltage (VBE) with a precise logarithmic  
relationship. A second converter is used to handle the reference  
current, IREF, applied to IREF. These input nodes are biased slightly  
above ground (0.5 V). This is generally acceptable for photodiode  
applications where the anode does not need to be grounded.  
Similarly, this bias voltage is easily accounted for in generating IREF  
The logarithmic front end’s output is available at VLOG.  
A fundamental aspect of translinear logarithmic converters is that  
small-signal bandwidth falls as current level diminishes, and low  
frequency noise-spectral density increases. At the 100 nA level, the  
ADL5306s bandwidth is about 100 kHz; it increases in proportion  
to IPD up to a maximum of about 10 MHz. The increase in noise  
level at low currents can be addressed by using a buffer amplifier to  
realize low-pass filters of up to three poles.  
.
The basic logarithmic slope at this output is 200 mV/decade  
(10 mV/dB) nominal; a 60 dB range corresponds to a 600 mV  
output change. When this voltage (or the buffer output) is applied  
to an ADC that permits an external reference voltage to be  
employed, the ADL5306s 2.5 V voltage reference output at VREF  
can be used to improve scaling accuracy.  
The ADL5306 is available in a 16-lead LFCSP package and is  
specified for operation from–40°C to +85°C.  
Protected by US Patents 4,604,532 and 5,519,308; other patents pending.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective companies.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2003 Analog Devices, Inc. All rights reserved.  
ADL5306  
TABLE OF CONTENTS  
Specifications..................................................................................... 3  
Response Time and Noise Considerations ............................. 10  
Applications..................................................................................... 11  
Using a Negative Supply ............................................................ 11  
Characterization Methods ........................................................ 12  
Evaluation Board ............................................................................ 14  
Outline Dimensions....................................................................... 16  
Ordering Guide .......................................................................... 16  
Absolute Maximum Ratings............................................................ 4  
Pin Configuration and Pin Function Descriptions...................... 5  
Typical Performance Characteristics ............................................. 6  
General Structure.............................................................................. 9  
Theory............................................................................................ 9  
Managing Intercept and Slope.................................................. 10  
REVISION HISTORY  
Rev. 0: Initial Version  
Rev. 0 | Page 2 of 16  
ADL5306  
SPECIFICATIONS  
Table 1. VP = 5 V, VN = 0, TA = 25°C, RREF = 200 kΩ, unless otherwise noted  
Parameter  
Conditions  
Min1  
Typ  
Max1  
Unit  
INPUT INTERFACE  
INPT (Pin 4), IREF (Pin 3)  
Flows toward INPT pin  
Flows toward INPT pin  
Flows toward IREF pin  
Internally preset; may be altered by user  
–40°C < TA < +85°C  
Specified Current Range, IPD  
Input Current Min/Max Limits  
Reference Current, IREF, Range  
Summing Node Voltage  
Temperature Drift  
100n  
100µ  
1
100µ  
0.54  
A
mA  
A
100n  
0.46  
0.5  
V
0.015  
mV/°C  
mV  
Input Offset Voltage  
LOGARITHMIC OUTPUT  
Logarithmic Slope  
VIN – VSUM , VIREF – VSUM  
VLOG (Pin 9)  
–20  
+20  
190  
185  
0.3  
200  
1
210  
215  
1.7  
2.5  
0.4  
mV/dec  
mV/dec  
nA  
–40°C < TA < +85°C  
Logarithmic Intercept2  
0.1  
nA  
–40°C < TA < +85°C  
100 nA < IPD < 100 µA  
IPD > 1 µA  
Law Conformance Error  
Wideband Noise3  
Small-Signal Bandwidth3  
Maximum Output Voltage  
Minimum Output Voltage  
Output Resistance  
0.1  
0.7  
0.7  
1.7  
0.01  
5
dB  
µV/√Hz  
MHz  
V
V
kΩ  
IPD > 1 µA  
Limited by VN = 0 V  
VREF (Pin 2)  
4.375  
5.625  
REFERENCE OUTPUT  
Voltage wrt Ground  
2.435  
2.4  
2.5  
2.565  
2.6  
V
V
–40°C < TA < +85°C  
Maximum Output Current  
Incremental Output Resistance  
OUTPUT BUFFER  
Sourcing (grounded load)  
Load current < 10 mA  
20  
2
mA  
BFIN (Pin 10); SCAL (Pin 11); VOUT (Pin 12)  
Input Offset Voltage  
Input Bias Current  
–20  
+20  
mV  
µA  
MΩ  
V
Flowing out of Pin 10 or Pin 11  
0.4  
35  
V – 0.1  
P
Incremental Input Resistance  
Output Range  
RL = 1 kΩ to ground  
Incremental Output Resistance  
Peak Source/Sink Current  
Small-Signal Bandwidth  
Slew Rate  
Load current < 10 mA  
0.5  
50  
15  
15  
mA  
MHz  
V/µs  
GAIN = 1  
0.2 V to 4.8 V output swing  
VPOS (Pin 8); VNEG (Pin 6)  
(VP – VN ) 11 V  
POWER SUPPLY  
Positive Supply Voltage  
Quiescent Current  
3
5
5.5  
6.6  
V
5.4  
0
mA  
V
Negative Supply Voltage (Optional)  
–5.5  
(VP – VN ) 11 V  
1 Minimum and maximum specified limits on parameters that are guaranteed but not tested are six sigma values.  
2 Other values of logarithmic intercept can be achieved by adjusting RREF  
3 Output noise and incremental bandwidth are functions of input current measured using the output buffer connected for GAIN = 1.  
.
Rev. 0 | Page 3 of 16  
 
 
 
 
 
ADL5306  
ABSOLUTE MAXIMUM RATINGS  
Table 2. ADL5306 Absolute Maximum Ratings  
Stresses above those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. This is a stress  
rating only; functional operation of the device at these or any  
other conditions above those indicated in the operational  
section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
Parameter  
Rating  
Supply Voltage VP – VN  
Input Current  
12 V  
20 mA  
Internal Power Dissipation  
θJA  
Maximum Junction Temperature  
Operating Temperature Range  
Storage Temperature Range  
500 mW  
135°C/W  
125°C  
–40°C to +85°C  
–65°C to +150°C  
Lead Temperature Range (Soldering 60 sec) 300°C  
Rev. 0 | Page 4 of 16  
 
ADL5306  
PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS  
COMM COMM COMM COMM  
16 15 14 13  
VOUT  
SCAL  
NC  
VREF  
IREF  
INPT  
1
2
3
4
12  
11  
ADL5306  
10 BFIN  
9
VLOG  
5
6
7
8
VSUM VNEG VNEG VPOS  
03727-0-002  
Figure 2. 16-Lead Leadframe Chip Scale Package (LFCSP)  
Table 3. Pin Function Descriptions  
Pin No. Mnemonic Function  
1
2
3
4
NC  
N/A  
VREF  
IREF  
INPT  
Reference Output Voltage of 2.5 V.  
Accepts (Sinks) Reference Current IREF  
Accepts (Sinks) Photodiode Current IPD. Usually connected to photodiode anode such that photocurrent flows  
into INPT.  
.
5
6, 7  
8
VSUM  
VNEG  
VPOS  
VLOG  
BFIN  
SCAL  
VOUT  
COMM  
Guard Pin. Used to shield the INPT current line and for optional adjustment of the INPT and IREF node potential.  
Optional Negative Supply, VN. This pin is usually grounded; for details of usage, see the Applications section.  
Positive Supply, ( VP – VN ) ≤ 11 V.  
Output of the Logarithmic Front End.  
Buffer Amplifier Noninverting Input.  
Buffer Amplifier Inverting Input.  
Buffer Output.  
9
10  
11  
12  
13–16  
Analog Ground.  
Rev. 0 | Page 5 of 16  
 
ADL5306  
TYPICAL PERFORMANCE CHARACTERISTICS  
(VP = 5 V, VN = 0 V, RREF = 200 kΩ, TA = 25°C, unless otherwise noted.)  
1.2  
1.5  
1.0  
T
= –40°C, 0°C, +25°C, +70°C, +85°C  
= 0V  
T
= –40°C, 0°C, +25°C, +70°C, +85°C  
V = 0V  
N
A
A
V
N
1.0  
0.8  
0.6  
0.4  
0.2  
0
+85°C  
+70°C  
0.5  
0
+25°C  
0°C  
–0.5  
–1.0  
–1.5  
–40°C  
10n  
100n  
1µ  
10µ  
100µ  
1m  
10n  
100n  
1µ  
10µ  
100µ  
1m  
I
(A)  
I
(A)  
PD  
03727-0-003  
03727-0-006  
PD  
Figure 3. VLOG vs. IPD for Multiple Temperatures  
Figure 6. Law Conformance Error vs. IPD (IREF = 10 µA) for Multiple  
Temperatures, Normalized to 25°C  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
1.5  
T
= –40°C, 0°C, +25°C, +70°C, +85°C  
= 0V  
T
= –40°C, 0°C, +25°C, +70°C, +85°C  
V = 0V  
N
A
A
V
N
1.0  
0.5  
+85°C  
+70°C  
0
+25°C  
–0.5  
–1.0  
–1.5  
–40°C  
0°C  
10n  
100n  
1µ  
10µ  
100µ  
1m  
10n  
100n  
1µ  
10µ  
100µ  
1m  
I
(A)  
I
(A)  
03727-0-004  
03727-0-007  
REF  
REF  
Figure 4. VLOG vs. IREF for Multiple Temperatures  
Figure 7. Law Conformance Error vs. IREF (IPD = 10 µA) for Multiple  
Temperatures, Normalized to 25°C  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
0.3  
0.2  
100µA  
0.1  
100nA  
100nA  
1µA  
10µA  
0
10µA  
100µA  
1µA  
–0.1  
–0.2  
–0.3  
10n  
100n  
1µ  
10µ  
100µ  
1m  
10n  
100n  
1µ  
10µ  
100µ  
1m  
I
(A)  
I
(A)  
PD  
03727-0-005  
03727-0-008  
PD  
Figure 5. VLOG vs. IPD for Multiple Values of IREF  
(Decade Steps from 10 nA to 1 mA)  
Figure 8. Law Conformance Error vs. IPD for Multiple Values of IREF  
(Decade Steps from 10 nA to 1 mA)  
Rev. 0 | Page 6 of 16  
 
 
ADL5306  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
0.3  
0.2  
100nA  
0.1  
100µA  
10µA  
1µA  
100nA  
100µA  
0
1µA  
10µA  
–0.1  
–0.2  
–0.3  
10n  
100n  
1µ  
10µ  
100µ  
1m  
10n  
100n  
1µ  
10µ  
100µ  
1m  
I
(A)  
I
(A)  
REF  
03727-0-009  
03727-0-012  
REF  
Figure 9. VLOG vs. IREF for Multiple Values of IPD  
(Decade Steps from 10 nA to 1 mA)  
Figure 12. Law Conformance Error vs. IREF for Multiple Values of IPD  
(Decade Steps from 10 nA to 1 mA)  
0.3  
0.2  
1.2  
1.0  
10µA TO 100µA: tRISE < 1µs,  
tFALL < 1µs  
0.1  
0.8  
+5V, 0V  
1µA TO 10µA: tRISE < 1µs,  
tFALL < 5µs  
+3V, –0.5V  
0
0.6  
100nA TO 1µA: tRISE < 5µs,  
tFALL < 20µs  
+3V, 0V  
+5V, –5V  
–0.1  
–0.2  
–0.3  
0.4  
0.2  
0
–20  
0
20  
40  
60  
80  
100 120 140 160 180  
10n  
100n  
1µ  
10µ  
100µ  
1m  
03727-0-010  
TIME (µs)  
I
(A)  
03727-0-013  
PD  
Figure 13. Pulse Response: IPD to VOUT (G = 1)  
Figure 10. Law Conformance Error vs. IPD for Various Supply Conditions  
1.4  
4
T
= –40°C, +85°C  
A
3
2
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
100nA TO 1µA: tRISE = 30µs,  
tFALL = 5µs  
MEAN + 3 @ –40°C  
MEAN ±3 @ +85°C  
1µA TO 10µA: tRISE = 5µs,  
tFALL < 1µs  
1
10µA TO 100µA: tRISE = 1µs,  
tFALL < 1µs  
0
–1  
–2  
–3  
–4  
MEAN – 3 @ –40°C  
–20  
0
20  
40  
60  
80  
100 120 140 160 180  
10n  
100n  
1µ  
10µ  
100µ  
1m  
I
(A)  
03727-0-011  
TIME (µs)  
03727-0-014  
PD  
Figure 14. Pulse Response: IREF to VOUT (G = 1)  
Figure 11. VINPT – VSUM vs. IPD  
Rev. 0 | Page 7 of 16  
ADL5306  
5
0
10  
5
100nA  
0
100µA  
Av = 1  
–5  
–5  
Av = 5  
–10  
–15  
–20  
–25  
–30  
–35  
–10  
–15  
–20  
–25  
10µA  
1µA  
Av = 2  
Av = 2.5  
10M  
–40  
100  
10k  
100k  
1M  
FREQUENCY (Hz)  
100M  
1k  
10k  
100k  
FREQUENCY (Hz)  
1M  
10M  
100M  
03727-0-015  
03727-0-018  
Figure 15. Small-Signal AC Response (5% Sine Modulation), from IPD to VOUT  
(G = 1) for IPD in Decade Steps from 10 nA to 1 mA  
Figure 18. Small-Signal AC Response of the Buffer for Various  
Closed-Loop Gains (RL = 1 k, CL < 2 pF)  
10  
2.0  
5
0
100nA  
1.5  
1.0  
100µA  
–5  
MEAN + 3σ  
MEAN – 3σ  
0.5  
–10  
–15  
–20  
–25  
–30  
–35  
–40  
0
10µA  
1µA  
–0.5  
–1.0  
–1.5  
–2.0  
–40 –30 –20 –10  
0
10 20 30 40 50 60 70 80 90  
100  
1k  
10k  
100k  
FREQUENCY (Hz)  
1M  
10M  
100M  
03727-0-016  
03727-0-019  
TEMPERATURE (°C)  
Figure 16. Small-Signal AC Response (5% Sine Modulation), from IREF to VOUT  
(G = 1) for IREF in Decade Steps from 10 nA to 1 mA  
Figure 19. Buffer Input Offset Drift vs. Temperature  
(3σ to Either Side of Mean)  
100  
6
5
4
3
2
1
0
10  
1
100nA  
1µA  
10µA  
0.1  
0.01  
100µA  
100  
1k  
10k  
100k  
1M  
10M  
10n  
100n  
1µ  
10µ  
100µ  
1m  
03727-0-017  
FREQUENCY (Hz)  
I
(A)  
03727-0-020  
PD  
Figure 17. Spot Noise Spectral Density at VOUT (G = 1) vs. Frequency  
for IPD in Decade Steps from 10 nA to 1 mA  
Figure 20. Total Wideband Noise Voltage at VOUT vs. IPD (G = 1)  
Rev. 0 | Page 8 of 16  
ADL5306  
GENERAL STRUCTURE  
The ADL5306 addresses a wide variety of interfacing conditions  
to meet the needs of fiber optic supervisory systems, and is  
useful in many nonoptical applications. This section explains  
the structure of this unique style of translinear log amp. The  
simplified schematic in Figure 21 shows the key elements.  
THEORY  
The base-emitter voltage of a BJT (bipolar junction transistor)  
can be expressed by the following equation, which immediately  
shows its basic logarithmic nature:  
V
BE = kT/q ln(IC / IS)  
(1)  
BIAS  
GENERATOR  
where:  
IREF  
PHOTODIODE  
INPUT  
V
V
BE1  
BE2  
TEMPERATURE  
COMPENSATION  
(SUBTRACT AND  
DIVIDE BY T°K)  
IC is the collector current  
2.5V  
VREF  
IS is a scaling current, typically only 10–17  
A
CURRENT  
I
REF  
80kΩ  
0.5V  
20kΩ  
COMM  
kT/q is the thermal voltage, proportional to absolute  
temperature (PTAT), and is 25.85 mV at 300 K.  
I
PD  
VSUM  
44µA/dec  
INPT  
0.5V  
14.2k451Ω  
IS is never precisely defined and exhibits an even stronger  
temperature dependence, varying by a factor of roughly a  
2.5V  
VLOG  
0.5V  
Q1  
billion between –35°C and +85°C. Thus, to make use of the BJT  
as an accurate logarithmic element, both of these temperature-  
dependencies must be eliminated.  
V
V
Q2  
BE2  
6.69kΩ  
BE1  
COMM  
03727-0-021  
VNEG (NORMALLY GROUNDED)  
The difference between the base-emitter voltages of a matched  
pair of BJTs, one operating at the photodiode current IPD and  
the other operating at a reference current IREF, can be written as  
Figure 21. Simplified Schematic  
The photodiode current IPD is received at Pin INPT. The voltage  
at this node is essentially equal to the voltage on the two  
adjacent guard pins, VSUM and IREF, due to the low offset  
voltage of the JFET op amp. Transistor Q1 converts IPD to a  
corresponding logarithmic voltage, as shown in Equation 1. A  
finite positive value of VSUM is needed to bias the collector of Q1  
for the usual case of a single-supply voltage. This is internally  
set to 0.5 V, one fifth of the 2.5 V reference voltage appearing on  
Pin VREF. The resistance at the VSUM pin is nominally 16 kΩ;  
this voltage is not intended as a general bias source.  
VBE1 VBE2 = kT/q ln(IPD / IS) – kT/q ln(IREF / IS)  
= ln(10) kT/q log10(IPD /IREF  
)
(2)  
= 59.5 mV log10(IPD /IREF) (T = 300 K)  
The uncertain, temperature-dependent saturation current, IS,  
that appears in Equation 1 has therefore been eliminated. To  
eliminate the temperature variation of kT/q, this difference  
voltage is processed by what is essentially an analog divider.  
Effectively, it puts a variable under Equation 2. The output of  
this process, which also involves a conversion from voltage  
mode to current mode, is an intermediate, temperature-  
corrected current:  
The ADL5306 also supports the use of an optional negative  
supply voltage, VN , at Pin VNEG. When VN is –0.5 V or more  
negative, VSUM may be connected to ground; thus, INPT and  
IREF assume this potential. This allows operation as a voltage-  
input logarithmic converter by the inclusion of a series resistor  
at either or both inputs. Note that the resistor setting, IREF, will  
need to be adjusted to maintain the intercept value. It should  
also be noted that the collector-emitter voltages of Q1 and Q2  
are now the full VN, and effects due to self-heating will cause  
errors at large input currents.  
I
LOG = IY log10(IPD IREF  
)
(3)  
/
where IY is an accurate, temperature-stable scaling current that  
determines the slope of the function (change in current per  
decade). For the ADL5306, IY is 44 µA, resulting in a  
temperature-independent slope of 44 µA/decade for all values  
of IPD and IREF . This current is subsequently converted back to a  
voltage-mode output, VLOG, scaled 200 mV/decade.  
The input-dependent VBE1 of Q1 is compared with the reference  
VBE2 of a second transistor, Q2, operating at IREF. This is  
generated externally to a recommended value of 10 µA.  
However, other values over a several-decade range can be used  
with a slight degradation in law conformance (see Figure 8).  
Rev. 0 | Page 9 of 16  
 
 
ADL5306  
It is apparent that this output should be zero for IPD = IREF, and  
would need to swing negative for smaller values of input  
current. To avoid this, IREF would need to be as small as the  
smallest value of IPD. In the ADL5306, an internal offset voltage  
is added to VLOG to shift it upward by 0.8 V. This moves the  
intercept to the left by four decades, from 10 µA to 1 nA:  
MANAGING INTERCEPT AND SLOPE  
As previously noted, the internally generated 2.5 V bias  
combines with the on-chip resistors to introduce an accurate  
offset voltage of 0.8 V at the VLOG pin, equivalent to four  
decades. This results in a logarithmic transfer function that can  
be written as  
LOG = VY log10 (104 × IPD  
I
REF)= VY log10 (IPD IINTC  
)
(6)  
I
LOG = IY log10(IPD / IINTC  
)
(4)  
V
/
/
where IINTC is the operational / value of the intercept current.  
Since values of IPD < IINTC result in a negative VLOG, a negative  
supply of sufficient value is required to accommodate this  
situation (discussed later).  
where IINTC = IREF /104  
Thus, the effective intercept current, IINTC, is only one ten-  
thousandth of IREF, corresponding to 10 nA when using the  
recommended value of IREF = 100 µA.  
The voltage VLOG is generated by applying ILOG to an internal  
resistance of 4.55 kΩ, formed by the parallel combination of a  
6.69 kΩ resistor to ground and the 14.2 kΩ resistor to the  
internal 2.5 V reference. At the VLOG pin, the output current  
The slope can be reduced by attaching a resistor to the VLOG  
pin. This is strongly discouraged because the on-chip resistors  
will not ratio correctly to the added resistance. Also, it is rare  
that one would wish to lower the basic slope of 10 mV/dB; if  
this is necessary, it should be done at the low impedance output  
of the buffer, which is provided to avoid such miscalibration  
and allow higher slopes to be used.  
I
LOG generates a voltage of  
LOG = ILOG × 4.55 kΩ  
= 44 µA × 4.55 kΩ × log10 (IPD IREF  
V
)
(5)  
/
The ADL5306 buffer is essentially an uncommitted op amp  
with rail-to-rail output swing, good load driving capabilities,  
and a unity-gain bandwidth of >20 MHz. In addition to  
allowing the introduction of gain using standard feedback  
networks, thereby increasing the slope voltage, VY, the buffer  
can be used to implement multipole low-pass filters, threshold  
detectors, and a variety of other functions. For more details, see  
the AD8304 Data Sheet.  
= VY log10 (IPD IREF  
)
/
where VY = 200 mV/decade or 10 mV/dB. Note that any  
resistive loading on VLOG will lower this slope and will result  
in an overall scaling uncertainty due to the variability of the on-  
chip resistors. Consequently, this practice is not recommended.  
VLOG may also swing below ground when dual supplies (VP and  
VN) are used. When VN = -0.5 V or more negative, the input  
pins INPT and IREF may be positioned at ground level simply  
by grounding VSUM.  
RESPONSE TIME AND NOISE CONSIDERATIONS  
The response time and output noise of the ADL5306 are  
fundamentally a function of the signal current IPD. For small  
currents, the bandwidth is proportional to IPD. The output’s low  
frequency voltage-noise spectral density is a function of IPD, and  
increases for small values of IREF. For details of noise and  
bandwidth performance of translinear log amps, see the  
AD8304 Data Sheet.  
Rev. 0 | Page 10 of 16  
 
ADL5306  
APPLICATIONS  
frequency is 3.2 kHz. Such filtering is useful in minimizing the  
output noise, particularly when IPD is small. Multipole filters are  
more effective in reducing the total noise. For examples, see the  
AD8304 Data Sheet.  
The ADL5306 is easy to use in optical supervisory systems and  
in similar situations where a wide-ranging current is to be  
converted to its logarithmic equivalent (i.e., represented in  
decibel terms). Basic connections for measuring a single current  
input are shown in Figure 22, which includes various  
nonessential components, as will be explained.  
The dynamic response of this overall input system is influenced  
by the external RC networks connected from the two inputs  
(INPT, IREF) to ground. These are required to stabilize the  
input systems over the full current range. The bandwidth  
changes with the input current due to the widely varying pole  
frequency. The RC network adds a zero to the input system to  
ensure stability over the full range of input current levels. The  
network values shown in Figure 22 will usually suffice, but some  
experimentation may be necessary when the photodiodes  
capacitance is high.  
VPOS +5V  
NC  
I
PD  
0.5 log  
10  
(
)
VREF  
1nA  
VOUT  
BIAS  
GENERATOR  
2.5V  
80kΩ  
COMM  
20kΩ  
R
REF  
12kΩ  
200kΩ  
0.5V  
IREF  
INPT  
SCAL  
BFIN  
14.2kΩ  
V
BIAS  
1kΩ  
Although the two current inputs are similar, some care is  
needed to operate the reference input at extremes of current  
(<100 nA) and temperature (<0°C). Modifying the RC network  
to 4.7 nF and 2 kΩ will allow operation to –40°C at 10 nA. By  
inspecting the transient response to perturbations in IREF at  
representative current levels, the capacitor value can be adjusted  
to provide fast rise and fall times with acceptable settling. To  
fine-tune the network zero, the resistor value should be  
adjusted.  
V
V
BE2  
BE1  
Q2  
Q1  
I
VLOG  
451Ω  
LOG  
TEMPERATURE  
COMPENSATION  
1nF  
C
FLT  
I
PD  
10nF  
6.69kΩ  
COMM  
1kΩ  
VSUM  
8kΩ  
0.5V  
1nF  
1nF  
VNEG  
COMM  
03727-0-022  
Figure 22. Basic Connections for Fixed Intercept Use  
USING A NEGATIVE SUPPLY  
The 2 V difference in voltage between VREF and INPT, in  
conjunction with the external 200 kΩ resistor RREF, provides a  
reference current IREF of 100 µA into Pin IREF. The internal  
reference raises the voltage at VLOG by 0.8 V, effectively  
lowering the intercept current IINTC by a factor of 104 to position  
it at 1 nA. Any temperature variation in RREF must be taken into  
account when estimating the stability of the intercept. Also, the  
overall noise will increase when using very low values of IREF. In  
fixed-intercept applications, there is little benefit in using a large  
reference current, since this only compresses the low current  
end of the dynamic range when operated from a single supply,  
shown here as 5 V. The capacitor between VSUM and ground is  
recommended to minimize the noise on this node and to help  
provide a clean reference current.  
Most applications of the ADL5306 require only a single supply  
of 3.0 V to 5.5 V. However, to provide further versatility, dual  
supplies may be employed, as illustrated in Figure 23.  
VPOS +5V  
NC  
I
PD  
0.5 log  
10  
(
)
VREF  
1nA  
VOUT  
BIAS  
GENERATOR  
2.5V  
80kΩ  
COMM  
20kΩ  
R
REF  
12kΩ  
200kΩ  
0.5V  
IREF  
INPT  
SCAL  
BFIN  
14.2kΩ  
V
BIAS  
1kΩ  
V
V
BE2  
Q2  
Q1  
I
VLOG  
451Ω  
LOG  
TEMPERATURE  
COMPENSATION  
1nF  
Since the basic scaling at VLOG is 0.2 V/dec and a swing of 4 V  
at the buffer output would therefore correspond to 20 decades,  
it will often be useful to raise the slope to make better use of the  
rail-to-rail voltage range. For illustrative purposes, the circuit in  
Figure 22 provides an overall slope of 0.5 V/dec (25 mV/dB).  
Thus, using IREF = 100 µA, VLOG runs from 0.2 V at IPD = 100 nA  
to 0.8 V at IPD = 100 µA. The buffer output runs from 0.5 V to  
2.0 V, corresponding to a dynamic range of 60 dB electrical  
(30 dB optical) power.  
BE1  
C
FLT  
I
PD  
10nF  
6.69kΩ  
COMM  
1kΩ  
VSUM  
8kΩ  
0.5V  
1nF  
VNEG  
REF  
COMM  
V
F
I
+ I  
sig  
q
V
– V –0.5V  
F
SUM  
I
= I + I  
PD  
sig  
V
– V  
F
sigmax  
N
R
S
C
I
+ I  
1
q
V
03727-0-023  
N
The optional capacitor from VLOG to ground forms a single-  
pole low-pass filter in combination with the 4.55 kΩ resistance  
at this pin. For example, using a CFLT of 10 nF, the –3 dB corner  
Figure 23. Negative Supply Application  
Rev. 0 | Page 11 of 16  
 
 
 
ADL5306  
The use of a negative supply, VN, allows the summing node to be  
placed at ground level whenever the input transistor (Q1 in  
Figure 1) has a sufficiently negative bias on its emitter. When  
VN = –0.5 V, the VCE of Q1 and Q2 will be the same value as in  
the default case when VSUM is grounded. This bias need not be  
accurate, and a poorly defined source can be used. However, the  
source must be able to support the quiescent current as well as  
the INPT and IREF signal current. For example, it may be  
convenient to utilize a forward-biased junction voltage of about  
0.7 V or a Schottky barrier voltage of a little over 0.5 V. With the  
summing node at ground, the ADL5306 may now be used as a  
voltage-input log amp, at either the numerator input INPT or  
the denominator input IREF by inserting a suitably scaled  
resistor from the voltage source to the relevant pin. The overall  
accuracy for small input voltages is limited by the voltage offset  
at the inputs of the JFET op amps.  
VREF  
IREF  
VNEG  
VPOS  
VOUT  
KEITHLEY 236  
KEITHLEY 236  
ADL5306  
BFIN  
CHARACTERIZATION  
BOARD  
VLOG  
INPT  
VSUM  
RIBBON  
CABLE  
TRIAX CONNECTORS  
(SIGNAL – INPT AND IREF  
GUARD – VSUM  
SHIELD – GROUND)  
DC MATRIX / DC SUPPLIES / DMM  
03727-0-024  
Figure 24. Primary Characterization Setup  
The primary characterization setup shown in Figure 24 is used  
to measure VREF, the static (dc) performance, logarithmic  
conformance, slope and intercept, the voltages appearing at Pins  
VSUM, INPT, and IREF, and the buffer offset and VREF drift  
with temperature. In some cases, a fixed resistor between Pins  
VREF and IREF was used in place of a precision current source.  
For the dynamic tests, including noise and bandwidth  
measurements, more specialized setups are required. This  
includes close attention to the input stabilizing networks; for  
example, to ensure stable operation over the full current range  
of IREF and temperature extremes, filter components C1 = 4.7 nF  
and R13 = 2 kare used at Pin IREF to ground.  
The use of a negative supply also allows the output to swing  
below ground, thereby allowing the intercept to correspond to a  
midrange value of IPD. However, the voltage VLOG remains  
referenced to the ACOM pin, and while VLOG does not swing  
negative for default operating conditions, it is free to do so.  
Thus, adding a resistor from VLOG to the negative supply  
lowers all values of VLOG, which raises the intercept. The  
disadvantage of this method is that the slope is reduced by the  
shunting of the external resistor, and the poorly defined ratio of  
on-chip and off-chip resistance causes errors in both the slope  
and intercept. A more accurate method for repositioning the  
intercept follows.  
HP3577A  
NETWORK ANALYZER  
OUTPUT INPUT R INPUT A INPUT B  
CHARACTERIZATION METHODS  
During the characterization of the ADL5306, the device was  
treated as a precision current-input logarithmic converter,  
because it is impractical to generate accurate photocurrents by  
illuminating a photodiode. The test currents were generated by  
using either a well-calibrated current source, such as the  
Keithley 236, or a high value resistor from a voltage source to  
the input pin. Great care is needed when using very small input  
currents. For example, the triax output connection from the  
current generator was used with the guard tied to VSUM. The  
input trace on the PC board was guarded by connecting  
adjacent traces to VSUM.  
16  
15  
14  
13  
COMM COMM COMM COMM  
B
A
+INAD8138  
EVALUATION  
BOARD  
VOUT  
SCAL  
BFIN  
NC  
12  
11  
10  
9
1
2
3
4
BNC-T  
VREF  
IREF  
INPT  
ADL5306  
AD8138 PROVIDES DC OFFSET  
VLOG  
VSUM VNEG VNEG VPOS  
5
6
7
8
+V  
S
0.1µF  
These measures are needed to minimize the risk of leakage  
current paths. With 0.5 V as the nominal bias on the INPT pin,  
a leakage-path resistance of 1 GΩ to ground would subtract  
0.5 nA from the input, which amounts to a –0.44 dB error for a  
10 nA source current. Additionally, the very high output  
resistance at the input pins and the long cables commonly  
needed during characterization allow 60 Hz and RF emissions  
to introduce substantial measurement errors. Careful guarding  
techniques are essential to reducing the pickup of these  
spurious signals.  
03727-0-025  
Figure 25. Configuration for Buffer Amplifier Bandwidth Measurement  
Figure 25 shows the configuration used to measure the buffer  
amplifier bandwidth. The AD8138 evaluation board includes  
provisions to offset VLOG at the buffer input, allowing  
measurements over the full range of IPD using a single supply.  
The network analyzer input impedances are set to 1 MΩ.  
Rev. 0 | Page 12 of 16  
 
 
 
ADL5306  
The configuration of Figure 27 is used to measure the noise  
HP3577A  
NETWORK ANALYZER  
performance. Batteries provide both the supply voltage and the  
input current in order to minimize the introduction of spurious  
noise and ground loop effects. The entire evaluation system,  
including the current setting resistors, is mounted in a closed  
aluminum enclosure to provide additional shielding to external  
noise sources.  
OUTPUT INPUT R INPUT A INPUT B  
16  
15  
14  
13  
POWER  
COMM COMM COMM COMM  
SPLITTER  
VOUT  
SCAL  
BFIN  
NC  
12  
11  
10  
9
1
2
3
4
LeCROY 9210  
TDS5104  
CH A  
VREF  
IREF  
INPT  
R2  
B
+INAD8138  
EVALUATION  
BOARD  
9213  
ADL5306  
CH 1  
R1  
A
VLOG  
VSUM VNEG VNEG VPOS  
5
6
7
8
1k  
1kΩ  
1nF  
16  
15  
14  
13  
+V  
S
F
COMM COMM COMM COMM  
1nF  
0.1  
µ
VOUT  
SCAL  
BFIN  
NC  
12  
11  
10  
9
1
2
3
4
03727-0-026  
VREF  
IREF  
INPT  
200k  
Figure 26. Configuration for Logarithmic Amplifier Bandwidth Measurement  
ADL5306  
R1  
VLOG  
Figure 26 shows the configuration used for frequency response  
measurements of the logarithmic amplifier section. The  
AD8138 output is offset to 1.5 V dc and modulated to a depth  
of 5% at frequency. R1 is chosen (over a wide range of values up  
to 1.0 GΩ) to provide IPD. The buffer is used to deload VLOG.  
VSUM VNEG VNEG VPOS  
5
6
7
8
50k1kΩ  
1kΩ  
+V  
0.1µF  
S
1nF  
1nF  
03727-0-028  
Figure 28. Configuration for Logarithmic Amplifier Pulse Response  
Measurement  
HP89410A  
Figure 28 shows the setup used to make the pulse response  
measurements. As with the bandwidth measurement, VLOG is  
connected directly to BFIN and the buffer amplifier is  
configured for a gain of 1. The buffers output is connected  
through a short cable to the TDS5104 scope, with the input  
impedance set to 1 MΩ. The LeCroys output is offset to create  
the initial pedestal current for a given R1 value. The pulse then  
creates a 1-decade current step.  
SOURCE TRIGGER CHANNEL 1 CHANNEL 2  
16  
15  
14  
13  
COMM COMM COMM COMM  
VOUT  
SCAL  
BFIN  
NC  
12  
11  
10  
9
1
2
3
4
VREF  
IREF  
INPT  
200k  
ADL5306  
R1  
VLOG  
VSUM VNEG VNEG VPOS  
5
6
7
8
1k  
1k  
ALKALINE  
"D" CELL  
1nF  
1nF  
0.1  
µ
F
ALKALINE  
"D" CELL  
03727-0-027  
Figure 27. Configuration for Noise Spectral Density Measurement  
Rev. 0 | Page 13 of 16  
 
 
 
ADL5306  
EVALUATION BOARD  
a slope of 200 mV/dec, and the intercept is set to 1 nA. Table 4  
describes the various configuration options.  
An evaluation board is available for the ADL5306, the schematic  
of which is shown in 29. It can be configured for a wide variety  
of experiments. The buffer gain is factory-set to unity, providing  
Table 4. Evaluation Board Configuration Options  
Component  
Function  
Default Conditions  
P1  
P1 = Installed  
Supply Interface. Provides access to supply pins VNEG,  
COMM, and VPOS.  
P2, R8, R9, R10, R18  
P2 = Not Installed  
Monitor Interface. By adding 0 Ω resistors to R8, R9, R10,  
and R18, the VREF, VSUM, VOUT, and VLOG pin voltages  
can be monitored using a high impedance probe.  
R8 = R9 = R10 = Open (Size 0603)  
R18 = Open (Size 0603)  
R2 = R6 = 0 Ω (Size 0603)  
R3 = R4 = Open (Size 0603)  
R11 = R14 = 0 Ω (Size 0603)  
C2 = C7 = Open (Size 0603)  
C9 = C10 = Open (Size 0603)  
VLOG = VOUT = Installed  
R1 = 200 kΩ (Size 0603)  
R19 = 0 Ω (Size 0603)  
R2, R3, R4, R6, R11, R14, C2, C7, C9, C10  
Buffer Amplifier/Output Interface. The logarithmic slope  
of the ADL5306 can be altered using the buffer’s gain-  
setting resistors, R2 and R3. R4, R6, R11, R14, C2, C7, C9, and  
C10 are provided for a variety of filtering applications.  
R1, R19  
Intercept Adjustment. The voltage dropped across  
resistor R1 determines the intercept reference current,  
nominally set to 10 µA using a 200 kΩ 1% resistor.  
R12, R15, C3, C4, C5, C6  
Supply Decoupling  
C3 = C4 = 0.01 µF (Size 0603)  
C5 = C6 = 0.1 µF (Size 0603)  
R12 = R15 = 0 Ω (Size 0603)  
C11 = 1 nF (Size 0603)  
R13 = R16 = 1 kΩ (Size 0603)  
C1 = C8 = 1 nF (Size 0603)  
IREF = INPT = Installed  
PD = Not Installed  
C11  
Filtering VSUM  
Input Compensation. Provides essential HF compensation  
at the input pins, INPT and IREF.  
R13, R16, C1, C8  
IREF, INPT, PD, LK1, R5  
Input Interface. The test board is configured to accept a  
current through the SMA connector labeled INPT. An SC  
style packaged photodiode can be used in place of the  
INPT SMA for optical interfacing. By removing R1 and  
adding a 0 Ω short for R5, a second current can be applied  
to the IREF input (also SMA) for evaluating the ADL5306 in  
log-ratio applications.  
LK1 = Installed  
R5 = Open (Size 0603)  
J1  
J1 = Open  
SC Style Photodiode  
Rev. 0 | Page 14 of 16  
 
 
ADL5306  
R10  
OPEN  
VOUT  
VOUT  
16  
15  
14  
13  
COMM COMM COMM COMM  
R14  
VOUT  
SCAL  
BFIN  
NC  
12  
11  
10  
9
1
2
3
4
0
R2  
C9  
C2  
R4  
0
R18  
OPEN  
R19  
OPEN  
OPEN  
R3  
OPEN  
R6  
0
OPEN  
VREF  
IREF  
INPT  
VREF  
IREF  
R1  
0
200k  
1%  
ADL5306  
I
R8  
OPEN  
R11  
R5  
OPEN  
REF  
VLOG  
VLOG  
R13  
I
PD  
1k  
VLOG  
SC-STYLE  
PD  
0
C7  
C10  
VSUM VNEG VNEG VPOS  
C1  
1nF  
1
OPEN OPEN  
5
6
7
8
2
3
C3  
0.01  
C4  
0.01  
1
2
3
4
AGND  
µ
F
µ
F
INPT  
VOUT  
VREF  
VSUM  
VLOG  
LK1  
C11 1nF  
R16 1k  
R9 OPEN  
C6  
0.1  
C5  
0.1  
1nF  
C8  
µ
F
µ
F
AGND  
2
VSUM  
5
VNEG  
1
3
VPOS  
P1  
P2  
03727-0-029  
Figure 29. Evaluation Board Schematic  
03727-0-031  
03727-0-030  
Figure 31. Component Side Silkscreen  
Figure 30. Component Side Layout  
Rev. 0 | Page 15 of 16  
ADL5306  
OUTLINE DIMENSIONS  
0.50  
0.40  
0.30  
3.00  
0.60 MAX  
BSC SQ  
PIN 1 INDICATOR  
1
2
0.45  
PIN 1  
INDICATOR  
1.45  
1.30 SQ  
1.15  
2.75  
TOP  
BOTTOM  
VIEW  
VIEW  
BSC SQ  
0.50  
BSC  
0.25 MIN  
1.50 REF  
12°MAX  
0.80 MAX  
0.65 NOM  
1.00  
0.90  
0.80  
0.05 MAX  
0.01 NOM  
SEATING  
PLANE  
0.30  
0.23  
0.18  
0.20 REF  
COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2  
Figure 32. 16-Lead Leadframe Chip Scale Package [LFCSP]  
(CP-16)  
Dimensions shown in millimeters  
ESD CAUTION  
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the  
human body and test equipment and can discharge without detection. Although this product features  
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy  
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance  
degradation or loss of functionality.  
ORDERING GUIDE  
ADL5306 Products  
ADL5306ACP2  
Temperature Package  
–40°C to +85°C  
Package Description  
16-Lead LFCSP  
Package Outline  
CP-16  
Branding1  
JSA  
ADL5306ACP-R2  
ADL5306ACP-REEL7  
ADL5306-EVAL  
–40°C to +85°C  
–40°C to +85°C  
Tape and Reel  
7” Tape and Reel  
Evaluation Board  
CP-16  
CP-16  
JSA  
JSA  
1 Branding is as follows:  
Line 1—Logo  
Line 2—JSA  
Line 3—K (Date Code). Date code is in YWW format.  
2 Contact factory for availability.  
© 2003 Analog Devices, Inc. All rights reserved. Trademarks and  
registered trademarks are the property of their respective companies.  
C03727–0–7/03(0)  
Rev. 0 | Page 16 of 16  
 
 

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