ADIS16495 [ADI]
Tactical Grade, Six Degrees of Freedom Inertial Sensor;
| 型号： | ADIS16495 |
| 厂家： | 
ADI |
| 描述： | Tactical Grade, Six Degrees of Freedom Inertial Sensor |
| 文件： | 总42页 (文件大小：986K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Tactical Grade, Six Degrees of Freedom
Inertial Sensor
Data Sheet
ADIS16495
FEATURES
GENERAL DESCRIPTION
Triaxial, digital gyroscope
The ADIS16495 is a complete inertial system that includes a
triaxis gyroscope and a triaxis accelerometer. Each inertial sensor
in the ADIS16495 combines industry leading iMEMS® technology
125°/sec, 450°/sec, 2000°/sec range options
0.05° axis to axis misalignment error
0.25° (maximum) axis to package misalignment error
0.8°/hr in-run bias stability (ADIS16495-1)
0.09°/√hr angular random walk (ADIS16495-1)
Triaxial, digital accelerometer, 8 g
with signal conditioning that optimizes dynamic performance.
The factory calibration characterizes each sensor for sensitivity,
bias, alignment, and linear acceleration (gyroscope bias). As a
result, each sensor has its own dynamic compensation formulas that
provide accurate sensor measurements.
3.2 μg in run bias stability
Triaxial, delta angle and delta velocity outputs
Factory calibrated sensitivity, bias, and axial alignment
Calibration temperature range: −40°C to +85°C
SPI compatible
Programmable operation and control
Automatic and manual bias correction controls
Configurable FIR filters
Digital I/O: data ready, external clock
Sample clock options: internal, external, or scaled
On demand self test of inertial sensors
Single-supply operation: 3.0 V to 3.6 V
1500 g mechanical shock survivability
Operating temperature range: −40°C to +105°C
The ADIS16495 provides a simple, cost effective method for
integrating accurate, multiaxis inertial sensing into industrial
systems, especially when compared with the complexity and
investment associated with discrete designs. All necessary motion
testing and calibration are part of the production process at
the factory, greatly reducing system integration time. Tight
orthogonal alignment simplifies inertial frame alignment in
navigation systems. The serial peripheral interface (SPI) and
register structure provide a simple interface for data collection
and configuration control.
The footprint and connector system of the ADIS16495 enable a
simple upgrade from the ADIS16375, ADIS16480, ADIS16485,
ADIS16488A, and ADIS16490. The ADIS16495 is available in an
aluminum package that is approximately 47 mm × 44 mm ×
14 mm and includes a standard connector interface.
APPLICATIONS
Precision instrumentation, stabilization
Guidance, navigation, control
Avionics, unmanned vehicles
Precision autonomous machines, robotics
FUNCTIONAL BLOCK DIAGRAM
DIO1 DIO2 DIO3 DIO4 RST
VDD
POWER
MANAGEMENT
GND
SELF TEST
I/O
OUTPUT
DATA
CS
TRIAXIAL
GYROSCOPE
REGISTERS
SCLK
DIN
CALIBRATION
AND
FILTERS
TRIAXIAL
ACCELEROMETER
SPI
CONTROLLER
USER
CONTROL
REGISTERS
TEMPERATURE
SENSOR
DOUT
CLOCK
ADIS16495
Figure 1.
Rev. C
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©2017-2020 Analog Devices, Inc. All rights reserved.
Technical Support
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ADIS16495
Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Time Stamp................................................................................. 24
Cyclical Redundancy Check (CRC-32)................................... 24
Delta Angles................................................................................ 25
Delta Velocity ............................................................................. 26
User Bias/Scale Adjustment...................................................... 29
Scratch Registers, USER_SCR_x.............................................. 31
Applications ...................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications .................................................................................... 4
Timing Specifications .................................................................. 6
Absolute Maximum Ratings ........................................................... 8
Thermal Resistance...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions ............................ 9
Typical Performance Characteristics........................................... 10
Theory of Operation ...................................................................... 12
Binertial Sensor Signal Chain................................................... 12
Register Structure....................................................................... 13
Serial Peripheral Interface......................................................... 14
Data Ready .................................................................................. 14
Reading Sensor Data.................................................................. 15
Device Configuration ................................................................ 16
User Register Memory Map.......................................................... 17
User Register Defintions ............................................................... 20
Page Number (PAGE_ID) ........................................................ 20
Data/Sample Counter (DATA_CNT)..................................... 20
Status/Error Flag Indicators (SYS_E_FLAG)......................... 20
Self Test Error Flags (DIAG_STS) ........................................... 21
Internal Temperature (TEMP_OUT) ..................................... 21
Gyroscope Data .......................................................................... 21
Acceleration Data....................................................................... 23
Flash Memory Endurance Counter, FLSHCNT_LOW,
FLSHCNT_HIGH...................................................................... 32
Global Commands, GLOB_CMD ........................................... 32
Auxiliary I/O Line Configuration, FNCTIO_CTRL............. 33
General-Purpose I/O Control, GPIO_CTRL......................... 34
Miscellaneous Configuration, CONFIG................................. 34
Linear Acceleration on Effect on Gyroscope Bias ................. 35
Decimation Filter, DEC_RATE ............................................... 35
Continuous Bias Estimation (CBE), NULL_CNFG.............. 35
Scaling the Input Clock (PPS Mode), SYNC_SCALE........... 36
FIR Filters.................................................................................... 36
Firmware Revision, FIRM_REV .............................................. 38
Applications Information ............................................................. 40
Mounting Best Practices ........................................................... 40
Preventing Misinsertion............................................................ 40
Evaluation Tools......................................................................... 40
Power Supply Considerations .................................................. 40
CRC32 Coding Example ........................................................... 41
Outline Dimensions....................................................................... 42
Ordering Guide .......................................................................... 42
REVISION HISTORY
7/2019—Rev. B to Rev. C
Changes to Figure 5 and Figure 6 ...................................................7
Changes to Table 6............................................................................9
Changes to Figure 12 ..................................................................... 10
Added Figure 13 and Figure 14; Renumbered Sequentially..... 10
Added Figure 15 and Figure 16.................................................... 11
Changes to Burst Read Function Section, Table 10, and
Table 11............................................................................................ 15
Changes to Table 12....................................................................... 17
Changes to Model Column, Table 24.......................................... 21
Changes to Cyclical Redundancy Check (CRC-32) Section .... 24
Changes to Delta Angle Measurement Range and Model
Changes to Table 1 ........................................................................... 5
Changes to tSTALL Parameter and Endnote 2, Table 2 .................. 6
Changes to Flash Memory Update Section and On Demand Self
Test (ODST) Section...................................................................... 33
Changes to Data Ready Indicator Section .................................. 34
Changes to Scaling the Input Clock (PPS Mode),
SYNC_SCALE Section................................................................... 36
5/2019—Rev. A to Rev. B
Changes to Features Section ........................................................... 1
Changes to Specifications Section and Table 1 ............................ 4
Column, Table 60........................................................................... 25
Rev. C | Page 2 of 42
Data Sheet
ADIS16495
Changes to Delta Velocity Section................................................26
Changes to Accelerometer Scale Adjustment, X_ACCL_SCALE
Section...............................................................................................29
Changes to Table 150 and Continuous Bias Estimation (CBE),
NULL_CNFG Section ....................................................................35
Changes to Description Column, Table 156 ...............................36
Added CRC32 Coding Example Section .....................................41
Updated Outline Dimensions .......................................................42
11/2017—Rev. 0 to Rev. A
Changes to Table 1............................................................................3
Added Endnote 2, Table 1; Renumbered Sequentially................4
Changes to t2 Parameter, Table 2 ...................................................5
Changes to Table 3............................................................................5
10/2017—Revision 0: Initial Version
Rev. C | Page 3 of 42
ADIS16495
Data Sheet
SPECIFICATIONS
TC = 25°C, VDD = 3.3 V, angular rate = 0°/sec, ADIS16495-1 model, 1 g, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
125
Typ
Max
Unit
GYROSCOPES
Dynamic Range
ADIS16495-1
°/sec
ADIS16495-2
450
480
°/sec
ADIS16495-3
2000
°/sec
Sensitivity
ADIS16495-1, 32-bit
ADIS16495-2, 32-bit
ADIS16495-3, 32-bit
−40°C ≤ TC ≤ +85°C, 1 σ
−40°C ≤ TC ≤ +85°C, 1 σ
Axis to axis, −40°C ≤ TC ≤+85°C, 1 σ
Axis to package, −40°C ≤ TC ≤+85°C
1 σ, ADIS16495-1, FS = 125°/sec
1 σ, ADIS16495-2, FS = 450°/sec
1 σ, ADIS16495-3, FS = 2000°/sec
10485760
2621440
655360
0.2
0.2
0.05
LSB/°/sec
LSB/°/sec
LSB/°/sec
%
Error Over Temperature
Repeatability1
Misalignment
%
Degrees
Degrees
% FS
% FS
% FS
0.25
Nonlinearity2
0.2
0.2
0.25
Bias
Repeatability3
In Run Bas Stability
−40°C ≤ TC ≤+85°C, 1 σ
1 σ, ADIS16495-1
0.07
0.8
°/sec
°/hr
1 σ, ADIS16495-2
1.6
°/hr
1 σ, ADIS16495-3
3.3
°/hr
Angular Random Walk
1 σ, ADIS16495-1
1 σ, ADIS16495-2
1 σ, ADIS16495-3
−40°C ≤ TC ≤ +85°C, 1 σ
Any axis, 1 σ (CONFIG register, Bit 7 = 1)
Any axis, 1 σ (CONFIG register, Bit 7 = 0)
1 σ, ADIS16495-1
0.09
0.1
0.18
0.1
0.006
0.015
0.0003
°/√hr
°/√hr
°/√hr
°/sec
°/sec/g
°/sec/g
°/sec/g2
Error over Temperature
Linear Acceleration Effect
Vibration Rectification Error
Noise
Output Noise
No filtering, ADIS16495-1
No filtering, ADIS16495-2
No filtering, ADIS16495-3
1 σ, ADIS16495-1
1 σ, ADIS16495-2
1 σ, ADIS16495-3
0.051
0.058
0.112
0.002
0.0022
0.0042
480
°/sec rms
°/sec rms
°/sec rms
°/sec/√Hz rms
°/sec/√Hz rms
°/sec/√Hz rms
Hz
Rate Noise Density4
−3 dB Bandwidth
ADIS16495-1
ADIS16495-2, ADIS16495-3
550
Hz
Sensor Resonant Frequency
ACCELEROMETERS5
Dynamic Range
65
kHz
Each axis
8
g
Sensitivity
Error Over Temperature
Repeatability
x_ACCL_OUT and x_ACCL_LOW (32-bit)
−40°C ≤ TC ≤ +85°C, 1 σ
−40°C ≤ TC ≤ +85°C, 1 σ
262144000
0.01
0.05
LSB/g
%
%
Misalignment
Axis to axis, −40°C ≤ TC ≤+85°C, 1 σ
Axis to package, −40°C ≤ TC ≤+85°C
Best fit straight line, 2 g, FS = 8 g
Best fit straight line, 4 g, FS = 8 g
Best fit straight line, 8 g, FS = 8 g
0.035
Degrees
Degrees
% FS
% FS
% FS
0.25
Nonlinearity
0.25
0.5
1.5
Bias
In Run Stability
Velocity Random Walk
1 σ
1 σ
3.2
0.008
μg
m/sec/√hr
Rev. C | Page 4 of 42
Data Sheet
ADIS16495
Parameter
Test Conditions/Comments
−40°C ≤ TC ≤ +85°C, 1 σ
−40°C ≤ TC ≤ +85°C, 1 σ
Min
Typ
0.5
1
Max
Unit
mg
mg
Error over Temperature
Repeatability
Noise
Output Noise
Noise Density
−3 dB Bandwidth
Sensor Resonant Frequency
TEMPERATURE SENSOR
Scale Factor
No filtering
10 Hz to 40 Hz, no filtering
0.5
17
750
2.5
mg rms
μg/√Hz rms
Hz
kHz
Output = 0x0000 at 25°C ( 5°C)
0.0125
°C/LSB
LOGIC INPUTS6
Input Voltage
High, VIH
2.0
V
Low, VIL
0.8
V
RST Pulse Width
CS Wake-Up Pulse Width
Input Current
1
µs
µs
20
Logic 1, IIH
Logic 0, IIL
All Pins Except RST, CS
RST, CS Pins7
VIH = 3.3 V
VIL = 0 V
10
10
µA
µA
mA
pF
0.33
10
Input Capacitance, CIN
DIGITAL OUTPUTS6
Output Voltage
High, VOH
ISOURCE = 0.5 mA
2.4
V
Low, VOL
ISINK = 2.0 mA
Endurance8
TJ = 85°C
0.4
V
FLASH MEMORY
Data Retention9
FUNCTIONAL TIMES10
Power-On Start-Up Time
Reset Recovery Time11
100,000
20
Cycles
Years
Time until data is available, −40°C ≤ TC ≤ +85°C, 1 σ
265
225
265
ms
ms
ms
GLOB_CMD register, Bit 7 = 1 (see Table 142)
RST pulled low, then restored to high
Flash Memory
Update Time
Clear User Calibration
Self Test Time12
GLOB_CMD register, Bit 3 = 1 (see Table 142)
GLOB_CMD register, Bit 6 = 1 (see Table 142)
GLOB_CMD register, Bit 1 = 1 (see Table 142)
1300
350
30
ms
µs
ms
CONVERSION RATE
Initial Clock Accuracy
Temperature Coefficient
Sync Input Clock
Pulse Per Second (PPS) Mode
POWER SUPPLY, VDD
Power Supply Current13
4.25
0.02
40
kSPS
%
ppm/°C
kHz
Hz
3.0
1
4.5
128
3.6
Operating voltage range
Normal mode, VDD = 3.3 V, µ + σ
3.0
V
mA
89
1 Bias repeatability provides an estimate for long-term drift in the bias, as observed during 500 hours of High-Temperature Operating Life (HTOL) at +105°C.
2 FS means full scale, FS = 125°/sec (ADIS16495-1), FS = 450°/sec (ADIS16495-2), FS = 2000°/sec (ADIS16495-3).
3 Bias repeatability provides an estimate for long-term drift in the bias, as observed during 500 hours of High-Temperature Operating Life (HTOL) at +105°C.
4 Magnitude between 10 Hz and 40 Hz, sample rate is 4250 SPS (nominal), no digital filtering.
5 All specifications associated with the accelerometers relate to the full-scale range of 8 g.
6 The digital I/O signals use a 3.3 V system.
7 RST
CS
and
pins are connected to the VDD pin through 10kΩ pull-up resistors.
8 Endurance is qualified as per JEDEC Standard 22, Method A117, measured at −40°C, +25°C, +85°C, and +125°C.
9 The data retention specification assumes a junction temperature (TJ) of 85°C per JEDEC Standard 22, Method A117. Data retention lifetime decreases with TJ.
10 These times do not include thermal settling and internal filter response times, which can affect overall accuracy.
11
RST
The
line must be in a low state for at least 10 μs to ensure a proper reset initiation and recovery.
12 Self test time can extend when using external clock rates that are lower than 4000 Hz.
13 Supply current transients can reach 250 mA during initial startup or reset recovery.
Rev. C | Page 5 of 42
ADIS16495
Data Sheet
TIMING SPECIFICATIONS
TC = 25°C, VDD = 3.3 V, unless otherwise noted.
Table 2.
Normal Mode
Burst Read Function
Parameter
Description
Min1
0.01
5
Typ
Max1
Min
Typ
Max1
Unit
MHz
µs
ns
ns
fSCLK
tSTALL
SCLK frequency
15
6.5
2
Stall period between data
SCLK low period
SCLK high period
CS to SCLK edge
N/A
tCLS
tCHS
tCS
31
31
32
31
31
32
ns
tDAV
tDSU
tDHD
tDR, tDF
tDSOE
tHD
tSFS
tDSHI
tNV
DOUT valid after SCLK edge
DIN setup time before SCLK rising edge
DIN hold time after SCLK rising edge
DOUT rise/fall times, ≤100 pF loading
CS assertion to DOUT active
SCLK edge to DOUT invalid
Last SCLK edge to CS deassertion
CS deassertion to DOUT high impedance
Data invalid time
10
10
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
2
2
2
2
3
8
11
3
8
11
0
0
0
32
0
0
32
0
9
9
20
20
t1
t2
t3
Input sync pulse width
Input sync to data invalid
Input sync period3
5
5
306
306
222.2
222.2
1 Guaranteed by design and characterization, but not tested in production.
2 See Table 3 for exceptions to the stall time rating. An insufficient stall time results in reading all 0s for the register attempting to be read.
3 This measurement represents the inverse of the maximum frequency for the input sample clock: 4500 Hz.
Register Specific Stall Times
Table 3.
Parameter
Description
Min1
Typ
Max
Unit
STALL TIME
FNCTIO_CTRL
FILTR_BNK_0
FILTR_BNK_1
NULL_CNFG
SYNC_SCALE
DEC_RATE
GPIO_CTRL
CONFIG
GLOB_CMD, Bit 1
GLOB_CMD, Bit 3
GLOB_CMD, Bit 6
GLOB_CMD, Bit 7
Configure the DIOx functions
Enable/select finite impulse response (FIR) filter banks
Enable/select FIR filter banks
Configure autonull bias function
Configure input clock scale factor
Configure decimation rate
Configure general-purpose input/output (I/O) lines
Configure miscellaneous functions
On demand self test
340
65
65
μs
μs
μs
μs
μs
μs
μs
μs
ms
ms
μs
ms
71
340
340
45
45
20
1120
350
210
Flash memory update
Factory calibration restore
Software reset
1 Monitoring the data ready signal (see Table 144 for FNCTIO_CTRL configuration) for the return of regular pulsing can help minimize system wait times.
Rev. C | Page 6 of 42
Data Sheet
ADIS16495
Timing Diagrams
CS
tCHS
tCLS
tCS
tSFS
1
2
3
4
5
6
15
16
SCLK
DOUT
tDSOE
tDAV
tHD
tDR
tDSHI
MSB
DB14
tDSU
DB13
DB12
DB11
DB10
DB2
DB1
tDF
LSB
LSB
tDHD
DIN
R/W
A6
A5
A4
A3
A2
D2
D1
Figure 2. SPI Timing and Sequence
tSTALL
CS
SCLK
Figure 3. Stall Time and Data Rate
t3
t2
DIO4
(SYNC CLOCK)
t1
DATA
READY
tNV
OUTPUT
REGISTERS
DATA VALID
DATA VALID
Figure 4. Input Clock Timing Diagram, FNCTIO_CTRL, Bits[7:4] = 0xFD
CS
SCLK
DIN
7C00
DOUT
0000
1
BURST_ID
2
X_GYRO_LOW
3
CRC_UPR
19
0
Figure 5. Burst Read Function Sequence Diagram, 19 Segments
CS
SCLK
DIN
7C00
CRC_UPR
20
0000
1
BURST_ID
2
BURST_ID
3
X_GYRO_LOW
4
DOUT
Figure 6. Burst Read Function Sequence Diagram, 20 Segments
Rev. C | Page 7 of 42
ADIS16495
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 4.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Pay careful attention
to PCB thermal design.
Parameter
Rating
Mechanical Shock Survivability
Any Axis, Unpowered
Any Axis, Powered
1500 g
1500 g
θ
JA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure.
JC is the junction to case thermal resistance.
VDD to GND
−0.3 V to +3.6 V
−0.3 V to VDD + 0.2 V
−0.3 V to VDD + 0.2 V
−40°C to +105°C
−55°C to +150°C
2 bar
Digital Input Voltage to GND
Digital Output Voltage to GND
Operating Temperature Range
Storage Temperature Range1
Barometric Pressure
θ
The ADIS16495 is a multichip module, which includes many
active components. The values in Table 5 identify the thermal
response of the hottest component inside of the ADIS16495,
with respect to the overall power dissipation of the module.
This approach enables a simple method for predicting the
temperature of the hottest junction, based on either ambient or
case temperature.
1 Extended exposure to temperatures that are lower than −40°C or higher
than +105°C can adversely affect the accuracy of the factory calibration.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
For example, when the TA = 70°C, the hottest junction inside of
the ADIS16495 is 76.7°C.
TJ = θJA × VDD × IDD + 70°C
TJ = 22.8°C/W × 3.3 V × 0.089 A + 70°C
TJ = 76.7°C
Table 5. Package Characteristics
Package Type
θJA
θJC
Device Weight
ML-24-91
30.7°C/W
20.9°C/W
42 g
1 Thermal impedance simulated values come from a case when 4 M2 × 0.4 mm
machine screws (torque = 20 inch ounces) secure the ADIS16495 to the PCB.
ESD CAUTION
Rev. C | Page 8 of 42
Data Sheet
ADIS16495
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADIS16495
TOP VIEW
(Not to Scale)
24 22 20 18 16 14 12 10
8
7
6
5
4
3
2
1
PIN 23
PIN 1
23 21 19 17 15 13 11
9
NOTES
1. THIS REPRESENTATION DISPLAYS THE TOP VIEW PINOUT
FOR THE MATING SOCKET CONNECTOR.
2. THE ACTUAL CONNECTOR PINS ARE NOT VISIBLE FROM
THE TOP VIEW.
3. MATING CONNECTOR: SAMTEC CLM-112-02 OR EQUIVALENT.
4. DNC = DO NOT CONNECT.
5. PIN 12 AND PIN 15 ARE NOT PHYSICALLY PRESENT.
PIN 1 PIN 2
Figure 8. Axial Orientation (Top Side Facing Up)
Figure 7. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
DIO3
DIO4
SCLK
DOUT
DIN
Type
Description
1
2
3
4
5
6
Input/output
Input/output
Input
Output
Input
Configurable Digital Input/Output 3.
Configurable Digital Input/Output 4.
SPI Serial Clock.
SPI Data Output. Clocks output on the SCLK falling edge.
SPI Data Input. Clocks input on the SCLK rising edge.
SPI Chip Select.
CS
Input
7
8
DIO1
RST
Input/output
Input
Configurable Digital Input/Output 1.
Reset.
9
DIO2
VDD
NO PIN
GND
DNC
DNC
Input/output
Supply
Not applicable
Supply
Not applicable
Not applicable
Configurable Digital Input/Output 2.
Power Supply.
No Pin. These pins are not physically present.
Power Ground.
Do Not Connect. Do not connect to these pins.
Do Not Connect. Do not connect to this pin. This pin can tolerate connection to 3.3 V.
10, 11
12, 15
13, 14
16 to 22, 24
23
Rev. C | Page 9 of 42
ADIS16495
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
1000
X-AXIS
X-AXIS
Y-AXIS
Z-AXIS
Y-AXIS
Z-AXIS
100
10
1
0.1
0.001
0.01
0.1
1
10
100
1000 10000 100000
10000
100000
0.001
0.01
0.1
1
10
100
1000
INTEGRATION PERIOD (Seconds)
INTEGRATION PERIOD (Seconds)
Figure 9. Gyroscope Allan Deviation, ADIS16495-1
Figure 12. Accelerometer Allan Deviation
1000
0
X-AXIS
Y-AXIS
Z-AXIS
MEAN + 1σ
–0.02
MEAN
100
10
1
–0.04
–0.06
–0.08
–0.10
–0.12
MEAN – 1σ
0.1
0.001
0.01
0.1
1
10
100
1000 10000 100000
–40
–20
20
40
0
60
80
INTEGRATION PERIOD (Seconds)
TEMPERATURE (°C)
Figure 10. Gyroscope Allan Deviation, ADIS16495-2
Figure 13. Gyroscope Sensitivity Error vs. Temperature, Cold to Hot,
ADIS16495-1
1000
100
10
0
X-AXIS
Y-AXIS
Z-AXIS
–0.02
MEAN + 1σ
–0.04
MEAN
–0.06
MEAN – 1σ
–0.08
1
–0.10
0.1
0.001
–0.12
0.01
0.1
1
10
100
1000 10000 100000
–40
–20
20
40
0
60
80
INTEGRATION PERIOD (Seconds)
TEMPERATURE (°C)
Figure 11. Gyroscope Allan Deviation, ADIS16495-3
Figure 14. Gyroscope Sensitivity Error vs. Temperature, Hot to Cold,
ADIS16495-1
Rev. C | Page 10 of 42
Data Sheet
ADIS16495
0.010
0.008
0.006
0.004
0.002
0
0.010
0.008
0.006
0.004
0.002
0
MEAN + 1σ
MEAN + 1σ
MEAN
MEAN
MEAN – 1σ
–0.002
–0.004
–0.006
–0.008
–0.010
–0.002
–0.004
–0.006
–0.008
–0.010
MEAN – 1σ
–40
–20
20
40
0
60
80
–40
–20
20
40
0
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. Accelerometer Sensitivity Error vs. Temperature, Cold to Hot,
ADIS16495-1
Figure 16. Accelerometer Sensitivity Error vs. Temperature, Hot to Cold,
ADIS16495-1
Rev. C | Page 11 of 42
ADIS16495
Data Sheet
THEORY OF OPERATION
The ADIS16495 is an autonomous sensor system that starts up
on its own when it has a valid power supply. After running
through its initialization process, it begins sampling, processing,
and loading calibrated sensor data into the output registers,
which are accessible using the SPI port.
External Clock Options
The ADIS16495 offers two modes of operation to control data
production with an external clock: sync mode and PPS mode.
In sync mode, the external clock directly controls the data
sampling and production clock (fSM in Figure 18 and Figure 19).
In PPS mode the user can provide a lower input clock rate (1 Hz
to 128 Hz) and use a scale factor (SYNC_SCALE register, see
Table 154) to establish a data collection and processing rate that
is between 3000 Hz and 4250 Hz for best performance.
BINERTIAL SENSOR SIGNAL CHAIN
Figure 17 shows the basic signal chain for the inertial sensors in
the ADIS16495, which processes data at a rate of 4250 SPS
when using the internal sample clock. Using one of the external
clock options in FNCTIO_CTRL, Bits[7:4] (see Table 144) can
provide some flexibility in selecting this rate.
Inertial Sensor Calibration
The calibration function for the gyroscopes and the
accelerometers has two components: factory calibration and
user calibration (see Figure 20).
OUTPUT
MEMS
SENSORS
CALIBRATION
FILTERING
DATA
REGISTERS
FROM
SENSORS
FACTORY
CALIBRATION
USER
CALIBRATION
TO
FILTERING
Figure 17. Signal Processing Diagram, Inertial Sensors
Figure 20. Gyroscope Calibration Processing
Gyroscope Data Sampling
The ADIS16495 produces angular rate measurements around
three orthogonal axes (x, y, and z). Figure 18 shows the basic
signal flow for the production of x-axis gyroscope data (same as
y-axis and z-axis). This signal chain contains two digital MEMS
gyroscopes (XG1 and XG2), which have their own ADC and sample
clocks (fSGX1 and fSGX2 = 4100 Hz) that produce data independently
from each other. The sensor to sensor tolerance on this sample rate
is 200 samples per second (SPS). Processing this data starts with
combining (summation and rescale) the most recent sample from
each gyroscope together by using an independent sample master
frequency (fSM) clock (fSM = 4250 Hz, see Figure 18), which drives
the rest of the digital signal processing (calibration, alignment, and
filtering) for the gyroscopes and accelerometers.
Gyroscope Factory Calibration
Gyroscope factory calibration applies the following correction
formula to the data of each gyroscope:
XC
X
b
m
m11 m12
ω
ω
ω
ω
X
13
=
m21 m22 m23
m31 m32 m33
×
+
bY
+
YC
Y
ω ZC
ω Z
bZ
(1)
a'
g11 g12
g
X
13
g21 g22 g23 × a'Y
g31 g32 g33
a'Z
where:
MEMS
X-AXIS
ωXC, ωYC, and ωZC are the postcalibration gyroscope data.
m11, m12, m13, m21, m22, m23, m31, m32, and m33 are the scale and
alignment correction factors.
ωX, ωY, and ωZ are the precalibration gyroscope data.
bX, bY, and bZ are the bias correction factors.
GYROSCOPE
RATE DATA
SAMPLE 1
ADC
X
G1
X-AXIS
ANGULAR RATE
DATA PROCESSING
fSGX1 = 4100Hz
X-AXIS
RATE DATA
SAMPLE 2
MEMS
GYROSCOPE
ADC
X
G2
g11, g12, g13, g21, g22, g23, g31, g32, and g33 are the linear g correction
factors.
fSGX2 = 4100Hz
fSM = 4250Hz
a'X, a'Y, and a'Z are the postcalibration accelerometer data.
Figure 18. Gyroscope Data Sampling
All the correction factors in each matrix/array are derived from
direct observation of the response of each gyroscope to a variety
of rotation rates at multiple temperatures across the calibration
temperature range (−40°C ≤ TC ≤ +85°C). These correction
factors are stored in the flash memory bank, but they are not
available for observation. Bit 7 in the CONFIG register provides an
on/off control for the linear g compensation (see Table 148). See
Figure 41 for more details on the user calibration options that
are available for the gyroscopes.
Accelerometer Data Sampling
The ADIS16495 produces linear acceleration measurements
along the same orthogonal axes (x, y, and z) as the gyroscopes,
using the same clock (fSM, see Figure 18 and Figure 19) that
triggers data acquisition and subsequent processing of the
gyroscope data.
X-AXIS
X-AXIS
MEMS
ACCELEROMETER
ADC
ACCELERATION
DATA PROCESSING
fSM = 4250SPS
Figure 19. Accelerometer Data Sampling
Rev. C | Page 12 of 42
Data Sheet
ADIS16495
The decimation filter averages multiple samples together to
Accelerometer Factory Calibration
produce each register update. In this type of filter structure, the
number of samples in the average is equal to the reduction in the
update rate for the output data registers. See the DEC_RATE
register for the user controls for this filter (see Table 150).
The accelerometer factory calibration applies the following
correction formulas to the data of each accelerometer:
b
a'
m11 m12
m
a
X
13
X
X
a'Y = m21 m22 m23 × aY + bY
+
REGISTER STRUCTURE
a'Z
m31 m32 m33
aZ
bZ
All communication with the ADIS16495 involves accessing its
user registers. The register structure contains both output data
and control registers. The output data registers include the
latest sensor data, error flags, and identification data. The
control registers include sample rate, filtering, I/O, calibration,
and diagnostic configuration options. All com-munication
between the ADIS16495 and an external processor involves
either reading or writing to one of the user registers.
(2)
2
0
p21
p12
0
p
ω
13
XC
p23 × ωY2C
2
p31 p32
0
ωZC
where:
a'X, a'Y, and a'Z are the postcalibration accelerometer data.
m11, m12, m13, m21, m22, m23, m31, m32, and m33 are the scale and
alignment correction factors.
aX, aY, and aZ are the precalibration accelerometer data.
bX, bY, and bZ are the bias correction factors.
0, p12, p13, p21, p23, p31, and p32 are the point of percussion
correction factors
TRIAXIAL
OUTPUT
GYROSCOPE
ADC
DSP
REGISTERS
TRIAXIAL
ACCELEROMETER
CONTROL
REGISTERS
TEMPERATURE
SENSOR
CONTROLLER
ω2XC, ω2YC, and ω2ZC are the postcalibration gyroscope data
(squared).
Figure 22. Basic Operation
All the correction factors in each matrix/array are derived from
direct observation of the response of each accelerometer to a
variety of inertial test conditions at multiple temperatures
across the calibration temperature range (−40°C ≤ TC ≤ +85°C).
These correction factors are stored in the flash memory bank,
but they are not available for observation. Bit 6 in the CONFIG
register provides an on/off control for the point of percussion
alignment (see Table 148). See Figure 42 for more details on the
user calibration options that are available for the
The register structure uses a paged addressing scheme that
contains 13 pages, with each page containing 64 register
locations. Each register is 16 bits wide, with each byte having its
own unique address within the memory map of that page. The SPI
port has access to one page at a time, using the bit sequence in
Figure 23. Select the page to activate for SPI access by writing its
code to the PAGE_ID register. Read the PAGE_ID register to
determine which page is currently active. Table 7 displays the
PAGE_ID contents for each page and their basic functions. The
PAGE_ID register is located at Address 0x00 on every page.
accelerometers.
Filtering
After calibration, the data of each inertial sensor passes through
two digital filters, both of which have user configurable
attributes: FIR and decimation (see Figure 21).
Table 7. User Register Page Assignments
Page PAGE_ID Function
0
1
2
3
4
0x00
0x01
0x02
0x03
0x04
Output data, clock, identification
Reserved
Calibration
Control: sample rate, filtering, I/O
Serial number, cyclic redundancy check (CRC)
values
TO
FROM
CALIBRATION
FIR
FILTER
DECIMATION
FILTER
DATA
REGISTERS
Figure 21. Inertial Sensor Filtering
The FIR filter includes four banks of coefficients that have
120 taps each. Register FILTR_BNK_0 (see Table 158) and
Register FILTR_BNK_1 (see Table 160) provide the
configuration options for the use of the FIR filters of each inertial
sensor. Each FIR filter bank includes a preconfigured filter, but
the user can design their own filters and write over these values
using the register of each coefficient. For example, Table 163
provides the details for the FIR_COEF_A071 register, which
contains Coefficient 71 in FIR Bank A. Refer to Figure 45 for
the frequency response of the factory default filters. These
filters do not represent any specific application environment;
they are only examples.
5
6
7
8
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
FIR Filter Bank A, Coefficient 0 to Coefficient 59
FIR Filter Bank A, Coefficient 60 to Coefficient 119
FIR Filter Bank B, Coefficient 0 to Coefficient 59
FIR Filter Bank B, Coefficient 60 to Coefficient 119
FIR Filter Bank C, Coefficient 0 to Coefficient 59
FIR Filter Bank C, Coefficient 60 to Coefficient 119
FIR Filter Bank D, Coefficient 0 to Coefficient 59
FIR Filter Bank D, Coefficient 60 to Coefficient 119
9
10
11
12
Rev. C | Page 13 of 42
ADIS16495
Data Sheet
CS
SCLK
DIN
R/W A6
A5
R/W A6
A5
A4
A3
A2
A1
D9
A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0
D8 D7 D6 D5 D4 D3 D2 D1 D0
DOUT
D15 D14 D13 D12 D11 D10
D15 D14 D13
NOTES
1. DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0.
2. WHEN CS IS HIGH, DOUT IS IN A THREE-STATE, HIGH IMPEDANCE MODE, WHICH ALLOWS MULTIFUNCTIONAL USE OF THE LINE
FOR OTHER DEVICES.
Figure 23. SPI Communication Bit Sequence
SERIAL PERIPHERAL INTERFACE
DATA READY
The SPI provides access to all of the user accessible registers
(see Table 8) and typically connects to a compatible port on an
embedded processor platform. See Figure 24 for a diagram that
provides the most common connections between the
ADIS16495 and an embedded processor.
The factory default configuration provides users with a data ready
(DR) signal on the DIO2 pin, which pulses low when the output
data registers are updating (see Figure 25). In this configuration,
connect DIO2 to an interrupt service pin on the embedded
processor, which triggers data collection, when this signal pulses
high. Register FNCTIO_CTRL, Bits[3:0] (see Table 144) provide
some user configuration options for this function.
I/O LINES ARE COMPATIBLE WITH
3.3V LOGIC LEVELS
3.3V
VDD
10
11
DIO2
INACTIVE
ACTIVE
SYSTEM
PROCESSOR
SPI MASTER
6
3
SS
CS
ADIS16495
Figure 25. Data Ready, when FNCTIO_CTRL, Bits[3:0] = 1101 (Default)
SCLK
DIN
SCLK
MOSI
During the start-up and reset recovery processes, the DR signal
can exhibit some transient behavior before data production
begins. Figure 26 provides an example of the DR behavior
during startup, and Figure 27 and Figure 28 provide examples
of the DR behavior during recovery from reset commands.
5
4
9
MISO
IRQ
DOUT
DIO2
13
14
TIME THAT VDD > 3V
Figure 24. Electrical Connection Diagram
VDD
Table 8. Generic Master Processor Pin Names and Functions
PULSING INDICATES
DATA PRODUCTION
Mnemonic
Function
SS
Slave select
DR
IRQ
Interrupt request
Master output, slave input
Master input, slave output
Serial clock
MOSI
MISO
SCLK
START-UP TIME
Figure 26. Data Ready Response During Startup
SOFTWARE RESET COMMAND
GLOB_CMD[7] = 1
Embedded processors typically use control registers to
configure their serial ports for communicating with SPI slave
devices such as the ADIS16495. Table 9 provides a list of settings
that describe the SPI protocol of the ADIS16495. The
initialization routine of the master processor typically
establishes these settings using firmware commands to write
them into its serial control registers.
DR PULSING
RESUMES
DR
RESET RECOVERY TIME
Figure 27. Data Ready Response During Reset
(Register GLOB_CMD, Bit 7 = 1) Recovery
Table 9. Generic Master Processor SPI Settings
Processor Setting Description
RST PIN
RELEASED
Master
ADIS16495 operates as slave
Maximum serial clock rate
CPOL = 1 (polarity), CPHA = 1 (phase)
Bit sequence, see Figure 23 for coding
Shift register/data length
RST
SCLK ≤ 15 MHz
SPI Mode 3
MSB First Mode
16-Bit Mode
DR PULSING
RESUMES
DR
RESET RECOVERY TIME
RST
Figure 28. Data Ready Response During Reset (
= 0) Recovery
Rev. C | Page 14 of 42
Data Sheet
ADIS16495
SYS_E_FLAG register, which will not be equal to 0xA5A5, as
an identifier for when the ADIS16495 BRF response is starting.
READING SENSOR DATA
Reading a single register requires two 16-bit cycles on the SPI:
one to request the contents of a register and another to receive
those contents. The 16-bit command code (see Figure 23) for a
Table 10. BRF Data Format (fSCLK < 3 MHz)1
Segment DIN
DOUT
R
read request on the SPI has three parts: the read bit ( /W = 0),
0
0x7C00 N/A
the 7-bit address code for either address (upper or lower) of the
register, Bits[A6:A0], and eight don’t care bits, Bits[DC7:DC0].
Figure 29 provides an example that includes two register reads
in succession. This example starts with DIN = 0x1A00, to
request the contents of the Z_GYRO_OUT register, and follows
with 0x1800, to request the contents of the Z_GYRO_LOW
register (assuming PAGE_ID already equals 0x0000). The
sequence in Figure 29 also shows full duplex mode of
operation, which means that the ADIS16495 can receive
requests on DIN while also transmitting data out on DOUT
within the same 16-bit SPI cycle.
1
2
3
4
5
6
7
8
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0x0000
0xA5A5 (BURST_ID)
SYS_E_FLAG
TEMP_OUT
X_GYRO_LOW
X_GYRO_OUT
Y_GYRO_LOW
Y_GYRO_OUT
Z_GYRO_LOW
Z_GYRO_OUT
X_ACCL_LOW
X_ACCL_OUT
Y_ACCL_LOW
Y_ACCL_OUT
Z_ACCL_LOW
Z_ACCL_OUT
DATA_CNT (FNCTIO_CTRL, Bits[8:7] ≠ 11)
TIME_STAMP (FNCTIO_CTRL, Bits[8:7] = 11)
CRC_LWR
9
10
11
12
13
14
15
16
17
NEXT
ADDRESS
DIN
0x1A00
0x1800
DOUT
Z_GYRO_OUT
Z_GYRO_LOW
Figure 29. SPI Read Example
Figure 30 provides an example of the four SPI signals when
reading the PROD_ID register (see Table 92) in a repeating
pattern. This pattern can be helpful when troubleshooting the
SPI interface setup and communications.
18
19
N/A
N/A
CRC_UPR
CS
1 N/A means not applicable.
SCLK
Table 11. BRF Data Format (fSCLK > 3.6 MHz)1
DIN
DIN = 0111 1110 0000 0000 = 0x7E00
Segment DIN
DOUT
0
0x7C00
N/A
DOUT
1
2
3
4
5
6
7
8
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0x0000
DOUT = 0100 0000 0110 1111 = 0x406F = 16495 (PROD_ID)
0xA5A5 (BURST_ID)
0xA5A5 (BURST_ID)
SYS_E_FLAG
Figure 30. SPI Read Example, Second 16-Bit Sequence
Burst Read Function
TEMP_OUT
The burst read function (BRF) provides a method for reading a
batch of data (status, temperature, gyroscopes, accelerometers,
time stamp/data counter, and CRC code), which does not require a
stall time between each 16-bit segment and only requires one
command on the DIN line to initiate. System processors can
execute the BRF by reading the BURST_CMD register (DIN =
0x7C00) and then reading each segment of data in the response,
X_GYRO_LOW
X_GYRO_OUT
Y_GYRO_LOW
Y_GYRO_OUT
Z_GYRO_LOW
Z_GYRO_OUT
X_ACCL_LOW
X_ACCL_OUT
Y_ACCL_LOW
Y_ACCL_OUT
Z_ACCL_LOW
Z_ACCL_OUT
9
10
11
12
13
14
15
16
17
18
CS
while holding the
line in a low state, until after reading the
CS
last 16-bit segment of data. If the
line goes high before the
completion of all data acquisition, the data from that read request
is lost.
The BRF response on the DOUT line contains either 19 or 20 data
segments (16-bits each) after the BRF request (DIN = 0x7C00),
depending on the SCLK rate. Figure 5 and Table 10 illustrate
the 19-segment case, while Figure 6 and Table 11 illustrate the
20-segment case.
DATA_CNT (FNCTIO_CTRL, Bits[8:7] ≠ 11)
TIME_STAMP (FNCTIO_CTRL, Bits[8:7] = 11)
CRC_LWR
19
20
N/A
N/A
CRC_UPR
To manage that variation, use the transition from the
BURST_ID code (0xA5A5 in Table 10 and Table 11) to the
1 N/A means not applicable.
Rev. C | Page 15 of 42
ADIS16495
Data Sheet
This portion of the flash memory bank has two independent banks
that operate in a ping pong manner, alternating with every flash
update. During power-on or reset recovery, the ADIS16495
performs a CRC on the SRAM and compares it to a CRC
computation from the same memory locations in flash memory.
If this memory test fails, the ADIS16495 resets and boots up
from the other flash memory location. SYS_E_FLAG, Bit 2 (see
Table 18) provides an error flag for detecting when the backup
flash memory supported the last power-on or reset recovery.
Table 12 provides a memory map for the user registers in the
ADIS16495, which includes flash backup support (indicated by
yes or no in the flash column).
DEVICE CONFIGURATION
Each register contains 16 bits (two bytes); Bits[7:0] contain the
low byte and Bits[15:8] contain the high byte. Each byte has its
own unique address in the user register map (see Table 12).
Updating the contents of a register requires writing to its low
byte first and its high byte second. There are three parts to coding
a SPI command (see Figure 23), which writes a new byte of data
R
to a register: the write bit ( /W = 1), the 7-bit address code for
the byte that this command is updating, and the new data for
that location, Bits[DC7:DC0]. Figure 31 provides a coding
example for writing 0xFEDC to the XG_BIAS_LOW register
(see Table 106), assuming that PAGE_ID already equals 0x0002.
MANUAL
FLASH
BACKUP
CS
SCLK
NONVOLATILE
FLASH MEMORY
VOLATILE
SRAM
DIN
0x90DC
0x91FE
SPI ACCESS
(NO SPI ACCESS)
Figure 31. SPI Sequence for Writing 0xFEDC to XG_BIAS_LOW
START-UP
RESET
Dual Memory Structure
The ADIS16495 uses a dual memory structure (see Figure 32),
with static random access memory (SRAM) supporting real-
time operation and flash memory storing operational code,
calibration coefficients, and user configurable register settings.
The manual flash update command (GLOB_CMD, Bit 3, see
Table 142) provides a single-command method for storing user
configuration settings into flash memory, for automatic recall
during the next power-on or reset recovery process.
Figure 32. SRAM and Flash Memory Diagram
Rev. C | Page 16 of 42
Data Sheet
ADIS16495
USER REGISTER MEMORY MAP
Table 12. User Register Memory Map1
Flash
Register Name
PAGE_ID
Reserved
DATA_CNT
Reserved
SYS_E_FLAG
DIAG_STS
Reserved
R/W Backup
PAGE_ID
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
Address
Default Register Description
R/W No
N/A N/A
0x00, 0x01
0x02, 0x03
0x04, 0x05
0x06, 0x07
0x08, 0x09
0x0A, 0x0B
0x0C, 0x0D
0x0E, 0x0F
0x10, 0x11
0x12, 0x13
0x14, 0x15
0x16, 0x17
0x18, 0x19
0x1A, 0x1B
0x1C, 0x1D
0x1E, 0x1F
0x20, 0x21
0x22, 0x23
0x24, 0x25
0x26, 0x27
0x28, 0x29
0x2A, 0x2B
0x2C, 0x2D
0x2E to 0x3F
0x40, 0x41
0x42, 0x43
0x44, 0x45
0x46, 0x47
0x48, 0x49
0x4A, 0x4B
0x4C, 0x4D
0x4E, 0x4F
0x50, 0x51
0x52, 0x53
0x54, 0x55
0x56, 0x57
0x58 to 0x7B
0x7C, 0x7D
0x7E, 0x7F
0x00 to 0x7F
0x00, 0x01
0x02, 0x03
0x04, 0x05
0x06, 0x07
0x08, 0x09
0x0A, 0x0B
0x0C, 0x0D
0x0E, 0x0F
0x10, 0x11
0x0000
N/A
Page identifier
Reserved
R
No
N/A
N/A
Data counter
Reserved
N/A N/A
R
R
No
No
N/A
N/A
N/A
Output, system error flags (0x0000 if no errors)
Output, self test error flags (0x0000 if no errors)
Reserved
N/A N/A
TEMP_OUT
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
N/A
Output, temperature
X_GYRO_LOW
X_GYRO_OUT
Y_GYRO_LOW
Y_GYRO_OUT
Z_GYRO_LOW
Z_GYRO_OUT
X_ACCL_LOW
X_ACCL_OUT
Y_ACCL_LOW
Y_ACCL_OUT
Z_ACCL_LOW
Z_ACCL_OUT
TIME_STAMP
CRC_LWR
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Output, x-axis gyroscope, low word
Output, x-axis gyroscope, high word
Output, y-axis gyroscope, low word
Output, y-axis gyroscope, high word
Output, z-axis gyroscope, low word
Output, z-axis gyroscope, high word
Output, x-axis accelerometer, low word
Output, x-axis accelerometer, high word
Output, y-axis accelerometer, low word
Output, y-axis accelerometer, high word
Output, z-axis accelerometer, low word
Output, z-axis accelerometer, high word
Output, time stamp
N/A
N/A
N/A
Output, CRC-32 (32 bits), lower word
Output, CRC-32, upper word
CRC_UPR
Reserved
N/A N/A
N/A
Reserved
X_DELTANG_LOW
X_DELTANG_OUT
Y_DELTANG_LOW
Y_DELTANG_OUT
Z_DELTANG_LOW
Z_DELTANG_OUT
X_DELTVEL_LOW
X_DELTVEL_OUT
Y_DELTVEL_LOW
Y_DELTVEL_OUT
Z_DELTVEL_LOW
Z_DELTVEL_OUT
Reserved
BURST_CMD
PROD_ID
Reserved
PAGE_ID
Reserved
X_GYRO_SCALE
Y_GYRO_SCALE
Z_GYRO_SCALE
X_ACCL_SCALE
Y_ACCL_SCALE
Z_ACCL_SCALE
XG_BIAS_LOW
R
R
R
R
R
R
R
R
R
R
R
R
No
No
No
No
No
No
No
No
No
No
No
No
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Output, x-axis delta angle, low word
Output, x-axis delta angle, high word
Output, y-axis delta angle, low word
Output, y-axis delta angle, high word
Output, z-axis delta angle, low word
Output, z-axis delta angle, high word
Output, x-axis delta velocity, low word
Output, x-axis delta velocity, high word
Output, y-axis delta velocity, low word
Output, y-axis delta velocity, high word
Output, z-axis delta velocity, low word
Output, z-axis delta velocity, high word
Reserved
N/A N/A
N/A
R
R
No
Yes
N/A
Burst read command
0x4071
N/A
Output, product identification (16495d)
Reserved
N/A N/A
R/W No
N/A N/A
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
0x0000
N/A
Page identifier
Reserved
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
Calibration, scale, x-axis gyroscope
Calibration, scale, y-axis gyroscope
Calibration, scale, z-axis gyroscope
Calibration, scale, x-axis accelerometer
Calibration, scale, y-axis accelerometer
Calibration, scale, z-axis accelerometer
Calibration, bias, gyroscope, x-axis, low word
Rev. C | Page 17 of 42
ADIS16495
Data Sheet
Flash
R/W Backup
Register Name
XG_BIAS_HIGH
YG_BIAS_LOW
YG_BIAS_HIGH
ZG_BIAS_LOW
ZG_BIAS_HIGH
XA_BIAS_LOW
XA_BIAS_HIGH
YA_BIAS_LOW
YA_BIAS_HIGH
ZA_BIAS_LOW
ZA_BIAS_HIGH
Reserved
USER_SCR_1
USER_SCR_2
USER_SCR_3
USER_SCR_4
FLSHCNT_LOW
FLSHCNT_HIGH
PAGE_ID
PAGE_ID
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x05
0x05
0x05
Address
Default Register Description
Calibration, bias, gyroscope, x-axis, high word
Calibration, bias, gyroscope, y-axis, low word
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
N/A N/A
R/W Yes
R/W Yes
R/W Yes
R/W Yes
Yes
Yes
R/W No
No
N/A N/A
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
0x12, 0x13
0x14, 0x15
0x16, 0x17
0x18, 0x19
0x1A, 0x1B
0x1C, 0x1D
0x1E, 0x1F
0x20, 0x21
0x22, 0x23
0x24, 0x25
0x26, 0x27
0x28 to 0x73
0x74, 0x75
0x76, 0x77
0x78, 0x79
0x7A, 0x7B
0x7C, 0x7D
0x7E, 07F
0x00, 0x01
0x02, 0x03
0x04, 0x05
0x06, 0x07
0x08, 0x09
0x0A, 0x0B
0x0C, 0x0D
0x0E, 0x0F
0x10, 0x11
0x12, 0x13
0x14, 0x15
0x16, 0x17
0x18, 0x19
0x1A to 0x77
0x78, 0x79
0x7A, 0x7B
0x7C, 0x7D
0x7E, 0x7F
0x00, 0x01
0x02, 0x03
0x04, 0x05
0x06, 0x07
0x08, 0x09
0x0A, 0x0B
0x0C, 0x0D
0x0E, 0x0F
0x10, 0x11
0x12, 0x13
0x1C to 0x1F
0x20, 0x21
0x22 to 0x7F
0x00, 0x01
0x02 to 0x07
0x08 to 0x7F
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
N/A
Calibration, bias, gyroscope, y-axis, high word
Calibration, bias, gyroscope, z-axis, low word
Calibration, bias, gyroscope, z-axis, high word
Calibration, bias, accelerometer, x-axis, low word
Calibration, bias, accelerometer, x-axis, high word
Calibration, bias, accelerometer, y-axis, low word
Calibration, bias, accelerometer, y-axis, high word
Calibration, bias, accelerometer, z-axis, low word
Calibration, bias, accelerometer, z-axis, high word
Reserved
User Scratch Register 1
User Scratch Register 2
User Scratch Register 3
User Scratch Register 4
R
R
Diagnostic, flash memory count, low word
Diagnostic, flash memory count, high word
Page identifier
N/A
0x0000
N/A
GLOB_CMD
Reserved
FNCTIO_CTRL
GPIO_CTRL
CONFIG
W
Control, global commands
N/A
Reserved
0x000D Control, I/O pins, functional definitions
0x00X02 Control, I/O pins, general-purpose
0x00C0
0x0000
0x070A
0x109A
N/A
Control, clock, and miscellaneous correction
Control, output sample rate decimation
Control, automatic bias correction configuration
Control, input clock scaling (PPS mode)
Measurement range (model-specific) Identifier
Reserved
DEC_RATE
NULL_CNFG
SYNC_SCALE
RANG_MDL
R
N/A
Reserved
N/A N/A
R/W Yes
R/W Yes
N/A N/A
N/A
FILTR_BNK_0
FILTR_BNK_1
Reserved
FIRM_REV
FIRM_DM
FIRM_Y
BOOT_REV
PAGE_ID
Reserved
CAL_SIGTR_LWR
CAL_SIGTR_UPR
CAL_DRVTN_LWR
CAL_DRVTN_UPR
CODE_SIGTR_LWR
CODE_SIGTR_UPR
CODE_DRVTN_LWR
CODE_DRVTN_UPR
Reserved
SERIAL_NUM
Reserved
PAGE_ID
Reserved
FIR_COEF_Axxx3
0x0000
0x0000
N/A
Filter selection
Filter selection
Reserved
R
R
R
R
Yes
Yes
Yes
Yes
N/A
Firmware revision
N/A
N/A
N/A
Firmware programming date (day/month)
Firmware programming date (year)
Boot loader revision
R/W No
N/A N/A
0x0000
N/A
Page identifier
Reserved
R
R
R
R
R
R
R
R
Yes
Yes
No
No
Yes
Yes
No
No
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Signature CRC, calibration coefficients, low word
Signature CRC, calibration coefficients, high word
Real-time CRC, calibration coefficients, low word
Real-time CRC, calibration coefficients, high word
Signature CRC, program code, low word
Signature CRC, program code, high word
Real-time CRC, program code, low word
Real-time CRC, program code, high word
Reserved
N/A N/A
Yes
N/A N/A
R/W No
N/A N/A
R/W Yes
N/A
R
N/A
Serial number
N/A
Reserved
0x0000
N/A
Page identifier
Reserved
N/A
FIR Filter Bank A: Coefficient 0 through Coefficient 59
Rev. C | Page 18 of 42
Data Sheet
ADIS16495
Flash
R/W Backup
Register Name
PAGE_ID
Reserved
FIR_COEF_Axxx3
PAGE_ID
Reserved
FIR_COEF_Bxxx4
PAGE_ID
Reserved
FIR_COEF_Bxxx4
PAGE_ID
Reserved
FIR_COEF_Cxxx5
PAGE_ID
Reserved
FIR_COEF_Cxxx5
PAGE_ID
0x06
0x06
0x06
0x07
0x07
0x07
0x08
0x08
0x08
0x09
0x09
0x09
0x0A
0x0A
0x0A
0x0B
0x0B
0x0B
0x0C
0x0C
0x0C
Address
Default Register Description
R/W No
N/A N/A
R/W Yes
R/W No
N/A N/A
R/W Yes
R/W No
N/A N/A
R/W Yes
R/W No
N/A N/A
R/W Yes
R/W No
N/A N/A
R/W Yes
R/W No
N/A N/A
R/W Yes
R/W No
N/A N/A
R/W Yes
0x00, 0x01
0x0000
N/A
Page identifier
Reserved
0x02 to 0x07
0x08 to 0x7F
0x00, 0x01
0x02 to 0x07
0x08 to 0x7F
0x00, 0x01
0x02 to 0x07
0x08 to 0x7F
0x00, 0x01
0x02 to 0x07
0x08 to 0x7F
0x00, 0x01
0x02 to 0x07
0x08 to 0x7F
0x00, 0x01
0x02 to 0x07
0x08 to 0x7F
0x00, 0x01
N/A
FIR Filter Bank A: Coefficient 60 through Coefficient 119
0x0000
N/A
Page identifier
Reserved
N/A
FIR Filter Bank B: Coefficient 0 through Coefficient 59
0x0000
N/A
Page identifier
Reserved
N/A
FIR Filter Bank B: Coefficient 60 through Coefficient 119
0x0000
N/A
Page identifier
Reserved
N/A
FIR Filter Bank C: Coefficient 0 through Coefficient 59
0x0000
N/A
Page identifier
Reserved
N/A
FIR Filter Bank C: Coefficient 60 through Coefficient 119
PAGE_ID
Reserved
FIR_COEF_Dxxx6
PAGE_ID
Reserved
FIR_COEF_Dxxx6
0x0000
N/A
Page identifier
Reserved
N/A
0x0000
N/A
FIR Filter Bank D: Coefficient 0 through Coefficient 59
Page identifier
Reserved
0x02 to 0x07
0x08 to 0x7F
N/A
FIR Filter Bank D: Coefficient 60 through Coefficient 119
1 N/A means not applicable.
2 The GPIO_CTRL[7:4] bits reflect the logic levels on the DIOx lines and do not have a default setting.
3 See the FIR Filter Bank A, FIR_COEF_A000 to FIR_COEF_A119 section for additional information.
4 See the FIR Filter Bank B, FIR_COEF_B000 to FIR_COEF_B119 section for additional information.
5 See the FIR Filter Bank C, FIR_COEF_C000 to FIR_COEF_C119 section for additional information.
6 See the FIR Filter Bank D, FIR_COEF_D000 to FIR_COEF_D119 section for additional information.
Rev. C | Page 19 of 42
ADIS16495
Data Sheet
USER REGISTER DEFINTIONS
PAGE NUMBER (PAGE_ID)
Table 18. SYS_E_FLAG Bit Descriptions
The contents in the PAGE_ID register (see Table 13 and Table 14)
contain the current page setting, and provide a control for selecting
another page for SPI access. For example, set DIN = 0x8002 to
select Page 2 for SPI-based user access. See Table 12 for the
page assignments associated with each user accessible register.
Bits
Description
15
Watchdog timer flag. A 1 indicates the ADIS16495
automatically resets itself to clear an issue.
[14:9] Not used.
8
Sync error. A 1 indicates the sample timing is not scaling
correctly, when operating in PPS mode (FNCTIO_CTRL,
Bit 8 = 1, see Table 144). When this error occurs, verify
that the input sync frequency is correct and that
SYNC_SCALE (see Table 154) has the correct value.
Table 13. PAGE_ID Register Definition
Page
Addresses Default Access Flash Backup
0x00
0x00, 0x01 0x0000 R/W No
7
6
Processing overrun. A 1 indicates the occurrence of a
processing overrun. Initiate a reset to recover. Replace
the ADIS16495 if this error persists.
Table 14. PAGE_ID Bit Descriptions
Flash memory update failure. A 1 indicates that the most
recent flash memory update failed (GLOB_CMD, Bit 3, see
Table 142). Repeat the test and replace the ADIS16495 if
this error persists.
Bits
Description
[15:0]
Page number, binary numerical format
DATA/SAMPLE COUNTER (DATA_CNT)
5
Sensor failure. A 1 indicates failure in at least one of the
inertial sensors. Read the DIAG_STS register (see Table 20)
to determine which sensor is failing. Replace the
ADIS16495 if the error persists, when it is operating in
static inertial conditions.
The DATA_CNT register (see Table 15 and Table 16) is a
continuous, real-time, sample counter. It starts at 0x0000,
increments every time the output data registers update, and
wraps around from 0xFFFF (65,535 decimal) to 0x0000
(0 decimal).
4
3
Not used.
SPI communication error. A 1 indicates that the total
number of SCLK cycles is not equal to an integer multiple
of 16. Repeat the previous communication sequence to
recover. Persistence in this error can indicate a weakness in
the SPI service from the master processor.
Table 15. DATA_CNT Register Definition
Page Addresses Default
Access Flash Backup
0x00 0x04, 0x05 Not applicable
R No
2
SRAM error condition. A 1 indicates a failure in the CRC
(period = 20 ms) between the SRAM and flash memory.
Initiate a reset to recover. Replace the ADIS16495 if this
error persists.
Table 16. DATA_CNT Bit Descriptions
Bits Description
[15:0] Data counter, binary format
1
0
Boot memory failure. A 1 indicates that the device
booted up using code from the backup memory bank.
Replace the ADIS16495 if this error occurs.
STATUS/ERROR FLAG INDICATORS (SYS_E_FLAG)
Not used.
The SYS_E_FLAG register (see Table 17 and Table 18) provides
various error flags. Reading this register causes all of its bits to
return to 0, with the exception of Bit 7. If an error condition
persists, its flag (bit) automatically returns to an alarm value of 1.
Table 17. SYS_E_FLAG Register Definition
Page
Addresses Default Access Flash Backup
0x00
0x08, 0x09 0x0000 No
R
Rev. C | Page 20 of 42
Data Sheet
ADIS16495
Table 23. TEMP_OUT Data Format Examples
Temperature (°C) Decimal Hex Binary
SELF TEST ERROR FLAGS (DIAG_STS)
SYS_E_FLAG, Bit 5 (see Table 18) contains the pass/fail result
(0 = pass) for the on demand self test (ODST) operations,
whereas the DIAG_STS register (see Table 19 and Table 20)
contains pass/fail flags (0 = pass) for each inertial sensor. Reading
the DIAG_STS register causes all of its bits to restore to 0. The
bits in DIAG_STS return to 1 if the error conditions persists.
+85
+4800
+2
0x12C0 0001 0010 1100 0000
0x0002 0000 0000 0000 0010
0x0001 0000 0000 0000 0001
0x0000 0000 0000 0000 0000
0xFFFF 1111 1111 1111 1111
0xFFFE 1111 1111 1111 1110
0xEBB0 1110 1011 1011 0000
+25 + 2/80
+25 + 1/80
+25
+1
0
+25 – 1/80
+25 – 2/80
−40
−1
−2
−5200
Table 19. DIAG_STS Register Definition
Page
Addresses
Default Access Flash Backup
GYROSCOPE DATA
0x00
0x0A, 0x0B
0x0000 No
R
The gyroscopes in the ADIS16495 measure the angular rate of
rotation around three orthogonal axes (x, y, and z). Figure 34
shows the orientation of each gyroscope axis, which defines the
direction of rotation that produces a positive response in each
of the angular rate measurements.
Table 20. DIAG_STS Bit Descriptions
Bits Description (Default = 0x0000)
[15:6] Not used
5
4
3
2
1
0
Self test failure, z-axis accelerometer (1 means failure)
Self test failure, y-axis accelerometer (1 means failure)
Self test failure, x-axis accelerometer (1 means failure)
Self test failure, z-axis gyroscope (1 means failure)
Self test failure, y-axis gyroscope (1 means failure)
Self test failure, x-axis gyroscope (1 means failure)
Each gyroscope has two output data registers. Figure 33 shows
how these two registers combine to support a 32-bit, twos
complement data format for the x-axis gyroscope measurements.
This format also applies to the y-axis and z-axis as well.
X_GYRO_OUT
X_GYRO_LOW
INTERNAL TEMPERATURE (TEMP_OUT)
BIT 15
BIT 0 BIT 15
X-AXIS GYROSCOPE DATA
BIT 0
The TEMP_OUT register (see Table 21 and Table 22) provides
a coarse measurement of the temperature inside of the ADIS16495.
This data is useful for monitoring relative changes in the
thermal environment. Table 23 provides several examples of
the data format for the TEMP_OUT register.
Figure 33. Gyroscope Output Data Structure
Gyroscope Measurement Range/Scale Factor
Table 24 provides the range and scale factor (KG) for the
angular rate (gyroscope) measurements in each ADIS16495
model.
Table 21. TEMP_OUT Register Definition
Page Addresses Default
Access Flash Backup
Table 24. Gyroscope Measurement Range and Scale Factors
0x00 0x0E, 0x0F Not applicable
R
No
Model
Range
Scale Factor, KG
0.00625°/sec/LSB
0.025°/sec/LSB
0.1°/sec/LSB
ADIS16495-1
ADIS16495-2
ADIS16495-3
125°/sec
450°/sec
2000°/sec
Table 22. TEMP_OUT Bit Descriptions
Bits
Description
[15:0]
Temperature data; twos complement, 1°C per 80 LSB,
25°C = 0x0000
Z-AXIS
ω
Z
X-AXIS
Y-AXIS
ω
X
ω
Y
PIN 23
PIN 1
Figure 34. Gyroscope Axis and Polarity Assignments
Rev. C | Page 21 of 42
ADIS16495
Data Sheet
Gyroscope Data Formatting
Y-Axis Gyroscope (Y_GYRO_LOW, Y_GYRO_OUT)
Table 25 and Table 26 offer various numerical examples that
demonstrate the format of the rotation rate data in both 16-bit
and 32-bit formats. See Table 24 for the scale factor (KG)
associated with each ADIS16495 model.
The Y_GYRO_LOW (see Table 31 and Table 32) and
Y_GRYO_OUT (see Table 33 and Table 34) registers contain
the gyroscope data for the y-axis.
Table 31. Y_GYRO_LOW Register Definition
Table 25. 16-Bit Gyroscope Data Format Examples
Page Addresses Default
Access Flash Backup
Rotation Rate
0x00 0x14, 0x15 Not applicable
R
No
(°/sec)
+10000 KG
+2 KG
+KG
0°/sec
−KG
Decimal Hex
Binary
+10,000
+2
+1
0
0x2710 0010 0111 0001 0000
0x0002 0000 0000 0000 0010
0x0001 0000 0000 0000 0001
0x0000 0000 0000 0000 0000
Table 32. Y_GYRO_LOW Bit Descriptions
Bits
Description
[15:0]
Y-axis gyroscope data; low word
−1
−2
0xFFFF
0xFFFE
1111 1111 1111 1111
1111 1111 1111 1110
−2 KG
Table 33. Y_GYRO_OUT Register Definition
−10000 KG
−10,000
0xD8F0 1101 1000 1111 0000
Page Addresses Default
Access Flash Backup
0x00 0x16, 0x17 Not applicable
R
No
Table 26. 32-Bit Gyroscope Data Format Examples
Rotation Rate (°/sec)
+10000 KG
+KG/215
Decimal
Hexadecimal
0x27100000
0x00000002
0x00000001
0x0000000
0xFFFFFFFF
0xFFFFFFFE
0xD8F00000
Table 34. Y_GYRO_OUT Bit Descriptions
+655,360,000
+2
+1
0
−1
−2
Bits
Description
[15:0]
Y-axis gyroscope data; high word; twos complement,
0°/sec = 0x0000, see Table 24 for scale factor
+KG/216
0
−KG /216
Z-Axis Gyroscope (Z_GYRO_LOW, Z_GYRO_OUT)
−KG /215
The Z_GYRO_LOW (see Table 35 and Table 36) and
Z_GRYO_
−10000 KG
−655,360,000
OUT (see Table 37 and Table 38) registers contain the gyroscope
data for the z-axis.
X-Axis Gyroscope (X_GYRO_LOW, X_GRYO_OUT)
The X_GYRO_LOW (see Table 27 and Table 28) and X_GRYO_
OUT (see Table 29 and Table 30) registers contain the gyroscope
data for the x-axis.
Table 35. Z_GYRO_LOW Register Definition
Page Addresses Default
Access Flash Backup
0x00 0x18, 0x19 Not applicable
R
No
Table 27. X_GYRO_LOW Register Definition
Page Addresses Default
Access Flash Backup
Table 36. Z_GYRO_LOW Bit Descriptions
0x00 0x10, 0x11 Not applicable
R No
Bits
Description
[15:0]
Z-axis gyroscope data; additional resolution bits
Table 28. X_GYRO_LOW Bit Descriptions
Bits
Description
Table 37. Z_GYRO_OUT Register Definition
[15:0]
X-axis gyroscope data; low word
Page Addresses Default
Access Flash Backup
0x00 0x1A, 0x1B Not applicable
R No
Table 29. X_GYRO_OUT Register Definition
Page Addresses Default
Access Flash Backup
Table 38. Z_GYRO_OUT Bit Descriptions
0x00 0x12, 0x13 Not applicable
R No
Bits
Description
[15:0]
Z-axis gyroscope data; high word; twos complement,
0°/sec = 0x0000, see Table 24 for scale factor
Table 30. X_GYRO_OUT Bit Descriptions
Bits
Description
[15:0]
X-axis gyroscope data; high word; twos complement,
0°/sec = 0x0000, see Table 24 for scale factor
Rev. C | Page 22 of 42
Data Sheet
ADIS16495
Z-AXIS
aZ
X-AXIS
Y-AXIS
aX
aY
PIN 23
PIN 1
Figure 35. Accelerometer Axis and Polarity Assignments
Y-Axis Accelerometer (Y_ACCL_LOW, Y_ACCL_OUT)
ACCELERATION DATA
The Y_ACCL_LOW (see Table 43 and Table 44) and
Y_ACCL_OUT (see Table 45 and Table 46) registers contain
the accelerometer data for the y-axis.
The accelerometers in the ADIS16495 measure both dynamic
and static (response to gravity) acceleration along three orthogonal
axes (x, y, and z). Figure 35 shows the orientation of each
accelerometer axis, which defines the direction of linear
acceleration that produces a positive response in each of the
angular rate measurements.
Table 43. Y_ACCL_LOW Register Definition
Page Addresses Default
Access Flash Backup
0x00 0x20, 0x21 Not applicable
R
No
Each accelerometer has two output data registers. Figure 36
shows how these two registers combine to support a 32-bit,
twos complement data format for the x-axis accelerometer
measurements. This format also applies to the y-axis and z-axis.
Table 44. Y_ACCL_LOW Bit Descriptions
Bits Description
[15:0] Y-axis accelerometer data; low word
X_ACCL_OUT
X_ACCL_LOW
BIT 15
BIT 0 BIT 15
X-AXIS ACCELEROMETER DATA
BIT 0
Table 45. Y_ACCL_OUT Register Definition
Page Addresses Default
Access Flash Backup
Figure 36. Accelerometer Output Data Structure
0x00 0x22, 0x23 Not applicable
R
No
X-Axis Accelerometer (X_ACCL_LOW, X_ACCL_OUT)
The X_ACCL_LOW (see Table 39 and Table 40) and
X_ACCL_
OUT (see Table 41 and Table 42) registers contain the
Table 46. Y_ACCL_OUT Bit Descriptions
Bits Description
[15:0] Y-axis accelerometer data, high word; twos
accelerometer data for the x-axis.
complement, 8 g range, 0 g = 0x0000, 1 LSB = 0.25 mg
Table 39. X_ACCL_LOW Register Definition
Z-Axis Accelerometer (Z_ACCL_LOW, Z_ACCL_OUT)
Page Addresses Default
Access Flash Backup
The Z_ACCL_LOW (see Table 47 and Table 48) and Z_ACCL_
OUT (see Table 49 and Table 50) registers contain the accelerome-
ter data for the z-axis.
0x00 0x1C, 0x1D Not applicable
R No
Table 40. X_ACCL_LOW Bit Descriptions
Bits Description
Table 47. Z_ACCL_LOW Register Definition
Page Addresses Default
Access Flash Backup
[15:0] X-axis accelerometer data; low word
0x00 0x24, 0x25 Not applicable
R
No
Table 41. X_ACCL_OUT Register Definition
Table 48. Z_ACCL_LOW Bit Descriptions
Bits Description
Page Addresses Default
Access Flash Backup
0x00 0x1E, 0x1F Not applicable
R
No
[15:0] Z-axis accelerometer data; low word
Table 42. X_ACCL_OUT Descriptions
Bits Description
Table 49. Z_ACCL_OUT Register Definition
Page Addresses Default
Access Flash Backup
[15:0] X-axis accelerometer data, high word; twos
complement, 8 g range; 0 g = 0x0000, 1 LSB = 0.25 mg
0x00 0x26, 0x27 Not applicable
R No
Rev. C | Page 23 of 42
ADIS16495
Data Sheet
Table 50. Z_ACCL_OUT Bit Descriptions
to 5 on the second update, 9 on the third update, for example,
until the next clock signal pulse.
Bits
Description
[15:0] Z-axis accelerometer data, high word; twos
CYCLICAL REDUNDANCY CHECK (CRC-32)
complement, 8 g range, 0 g = 0x0000, 1 LSB = 0.25 mg
The ADIS16495 performs a CRC-32 computation, using the
output data registers (see Table 55).
Accelerometer Resolution
Table 51 and Table 52 offer various numerical examples that
demonstrate the format of the linear acceleration data in both
16-bit and 32-bit formats.
Table 55. CRC-32 Source Data and Example Values
Register
Example Value
0x0000
0x083A
0x0000
0xFFF7
SYS_E_FLAG
TEMP_OUT
Table 51. 16-Bit Accelerometer Data Format Examples
X_GYRO_LOW
X_GYRO_OUT
Y_GYRO_LOW
Y_GYRO_OUT
Z_GYRO_LOW
Z_GYRO_OUT
X_ACCL_LOW
X_ACCL_OUT
Y_ACCL_LOW
Y_ACCL_OUT
Z_ACCL_LOW
Z_ACCL_OUT
TIME_STAMP
Acceleration
Decimal
+32,000
+2
+1
0
−1
−2
−32,000
Hex
Binary
+8 g
0x7D00 0111 1101 0000 0000
0x0000
0xFFFE
+0.5 mg
+0.25 mg
0 mg
−0.25 mg
−0.5 mg
−8 g
0x0002
0x0001
0x0000
0xFFFF
0xFFFE
0x8300
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
1000 0011 0000 0000
0x0000
0x0001
0x5001
0x0003
0xE00A
0x0015
0xC009
0x0320
0x8A54
Table 52. 32-Bit Accelerometer Data Format Examples
Acceleration
Decimal
Hexadecimal
0x7D000000
0x00000002
0x00000001
0x00000000
0xFFFFFFFF
0xFFFFFFFE
0x83000000
+8 g
+2,097,152,000
+2
+1
0
−1
−2
+0.25/215 mg
+0.25/216 mg
0 mg
The CRC_LWR (see Table 56 and Table 57) and CRC_UPR
(see Table 58 and Table 59) registers contain the result of the
CRC-32 computation. For the example, the register values from
Table 55 are,
−0.25/216 mg
−0.25/215 mg
−8 g
−2,097,152,000
CRC_LWR = 0x15B4
CRC_UPR = 0xB6C8
TIME STAMP
When using PPS mode (FNCTIO_CTRL, Bits[8:7] = 11 (binary),
see Table 144), the TIME_STAMP register (see Table 53 and
Table 54) provides the time between the most recent pulse on
the input clock signal and the most recent data update.
Table 56. CRC_LWR Register Definition
Page Addresses Default
Access Flash Backup
0x00 0x2A, 0x2B Not applicable
R No
Table 53. TIME_STAMP Register Definition
Table 57. CRC_LWR Bit Definitions
Page Addresses Default
Access Flash Backup
Bits
Description
0x00 0x28, 0x29 Not applicable
R
No
[15:0] CRC-32 code from most recent BRF, lower word
Table 54. TIME_STAMP Bit Descriptions
Bits Description
[15:0] Time stamp, binary format.
Table 58. CRC_UPR Register Definition
Page Addresses Default
Access Flash Backup
1 LSB = 1/fSM (see Figure 18, Figure 19, and Table 154).
The leading edge of the input clock pulse resets the
value in this register to 0x0000.
0x00 0x2C, 0x2D Not applicable
R
No
Table 59. CRC_UPR Bit Definitions
Bits Description
[15:0] CRC-32 code from most recent BRF, upper word
When using the decimation filter (DEC_RATE > 0x0000), the
value in the TIME_STAMP register represents the time of the first
sample (taken at the rate of fSM, per Figure 18 and Figure 19).
For example, when DEC_RATE = 0x0003, the decimation filter
reduces the update by a factor of four and the TIME_STAMP
register updates to 1 (decimal) during the first data update, then
Rev. C | Page 24 of 42
Data Sheet
ADIS16495
Z-AXIS
Δθ
Z
X-AXIS
Y-AXIS
Δθ
X
Δθ
Y
PIN 23
PIN 1
Figure 37. Delta Angle Axis and Polarity Assignments
Delta Angle Measurement Range
DELTA ANGLES
Table 60 offers the measurement range and scale factor for each
ADIS16495 model.
In addition to the angular rate of rotation (gyroscope) measure-
ments around each axis (x, y, and z), the ADIS16495 also provides
delta angle measurements that represent a computation of angular
displacement between each sample update. Figure 37 shows the
orientation of each delta angle output, which defines the
direction of rotation that produces a positive response in each
of the angular displacement (delta angle) measurements.
Table 60. Delta Angle Measurement Range and Scale Factor
Model
Measurement Range, ΔθMAX
ADIS16495-1
ADIS16495-2
ADIS16495-3
360°
720°
2160°
The delta angle outputs represent an integration of the gyro-
scope measurements and use the following formula for all three
axes (x-axis displayed):
X-Axis Delta Angle (X_DELTANG_LOW,
X_DELTANG_OUT)
D − 1
1
The X_DELTANG_LOW (see Table 61 and Table 62) and
X_DELTANG_OUT (see Table 63 and Table 64) registers
contain the delta angle data for the x-axis.
∆θx,n D
=
×
ω
+ωx,n D +d − 1
x,n D + d
∑
(
)
2 fS
d =0
where:
Δθx is the delta angle measurement for the x-axis.
D is the decimation rate = DEC_RATE + 1 (see Table 150).
fS is the sample rate.
Table 61. X_DELTANG_LOW Register Definitions
Page Addresses Default
Access Flash Backup
0x00 0x40, 0x41 Not applicable
R
No
d is the incremental variable in the summation formula.
ωx is the x-axis rate of rotation (gyroscope).
n is the sample time, prior to the decimation filter.
Table 62. X_DELTANG_LOW Bit Descriptions
Bits
Description
When using the internal sample clock, fS is equal to 4250 SPS.
When using the external clock option, fS is equal to the frequency
of the external clock. The range in the delta angle registers
accommodates the maximum rate of rotation (100°/sec), the
nominal sample rate (4250 SPS), and an update rate of 1 Hz
(DEC_RATE = 0x1099; divide by 4249 plus 1, see Table 150),
all at the same time. When using an external clock that is higher
than 4250 SPS, reduce the DEC_RATE setting to avoid over-
ranging the delta angle registers.
[15:0]
X-axis delta angle data; low word
Table 63. X_DELTANG_OUT Register Definitions
Page Addresses Default
Access Flash Backup
0x00 0x42, 0x43 Not applicable
R
No
Table 64. X_DELTANG_OUT Bit Descriptions
Bits Description
[15:0] X-axis delta angle data; twos complement, 0° = 0x0000,
1 LSB = ΔθMAX/215 (see Table 60 for ΔθMAX
Each axis of the delta angle measurements has two output data
registers. Figure 38 shows how these two registers combine to
support a 32-bit, twos complement data format for the x-axis
delta angle measurements. This format also applies to the y-axis
and z-axis.
)
X_DELTANG_OUT
BIT 0 BIT 15
X-AXIS DELTA ANGLE DATA
X_DELTANG_LOW
BIT 15
BIT 0
Figure 38. Delta Angle Output Data Structure
Rev. C | Page 25 of 42
ADIS16495
Data Sheet
Delta Angle Resolution
Y-Axis Delta Angle (Y_DELTANG_LOW, Y_DELTANG_OUT)
Table 73 and Table 74 shows various numerical examples that
demonstrate the format of the delta angle data in both 16-bit
and 32-bit formats.
The Y_DELTANG_LOW (see Table 65 and Table 66) and
Y_DELTANG_OUT (see Table 67 and Table 68) registers
contain the delta angle data for the y-axis.
Table 73. 16-Bit Delta Angle Data Format Examples
Table 65. Y_DELTANG_LOW Register Definitions
Delta Angle (°)
ΔθMAX × (215−1)/215 +32,767
Decimal Hex
Binary
Page Addresses Default
Access Flash Backup
0x7FFF 0111 1111 1110 1111
0x0002 0000 0000 0000 0010
0x0001 0000 0000 0000 0001
0x0000 0000 0000 0000 0000
0xFFFF 1111 1111 1111 1111
0xFFFE 1111 1111 1111 1110
0x8000 1000 0000 0000 0000
0x00 0x44, 0x45 Not applicable
R No
+ΔθMAX/214
+ΔθMAX/215
0
+2
+1
0
Table 66. Y_DELTANG_LOW Bit Descriptions
Bits
Description
−ΔθMAX/215
−ΔθMAX/214
−ΔθMAX
−1
−2
−32,768
[15:0]
Y-axis delta angle data; low word
Table 67. Y_DELTANG_OUT Register Definitions
Page Addresses Default
Access Flash Backup
Table 74. 32-Bit Delta Angle Data Format Examples
0x00 0x46, 0x47 Not applicable
R No
Delta Angle (°)
+ΔθMAX × (231 − 1)/231
+ΔθMAX/230
+ΔθMAX2000/231
0
−ΔθMAX/231
−ΔθMAX/230
−ΔθMAX
Decimal
Hex
+2,147,483,647 0x7FFFFFFF
+2
+1
0
−1
−2
0x00000002
0x00000001
0x00000000
0xFFFFFFFF
0xFFFFFFFE
Table 68. Y_DELTANG_OUT Bit Descriptions
Bits Description
[15:0] Y-axis delta angle data; twos complement, 0° = 0x0000,
1 LSB = ΔθMAX/215 (see Table 60 for ΔθMAX
)
−2,147,483,648 0x80000000
Z-Axis Delta Angle (Z_DELTANG_LOW,
Z_DELTANG_OUT)
DELTA VELOCITY
The Z_DELTANG_LOW (see Table 69 and Table 70) and
Z_DELTANG_OUT (see Table 71 and Table 72) registers
contain the delta angle data for the z-axis.
In addition to the linear acceleration measurements along each
axis (x, y, and z), the ADIS16495 also provides delta velocity
measurements that represent a computation of linear velocity
change between each sample update. Figure 40 shows the
orientation of each delta-velocity measurement, which defines
the direction of linear velocity increase that produces a positive
response in each of the delta velocity rate measurements.
Table 69. Z_DELTANG_LOW Register Definitions
Page Addresses Default
Access Flash Backup
0x00 0x48, 0x49 Not applicable
R No
Table 70. Z_DELTANG_LOW Bit Descriptions
The delta velocity outputs represent an integration of the accelera-
tion measurements and use the following formula for all three
axes (x-axis displayed):
Bits
Description
[15:0]
Z-axis delta angle data; low word
D−1
1
2 fS
∆Vx,nD
=
×
(
a
+ ax,nD+d−1
)
∑
x,nD+d
Table 71. Z_DELTANG_OUT Register Definitions
d=0
Page Addresses Default
Access Flash Backup
where:
0x00 0x4A, 0x4B Not applicable
R No
ΔVX is the delta velocity measurement for the x-axis.
D is the decimation rate = DEC_RATE + 1 (see Table 150).
fS is the sample rate.
d is the incremental variable in the summation formula.
ax is the x-axis rate of acceleration (accelerometer).
n is the sample time, prior to the decimation filter.
Table 72. Z_DELTANG_OUT Bit Descriptions
Bits Description
[15:0] Z-axis delta angle data; twos complement, 0° = 0x0000,
1 LSB = ΔθMAX/215 (see Table 60 for ΔθMAX
)
Rev. C | Page 26 of 42
Data Sheet
ADIS16495
When using the internal sample clock, fS is equal to 4250 SPS.
When using the external clock option, fS is equal to the frequency
of the external clock. The range in the delta velocity registers
accommodates the maximum linear acceleration (8 g), the
nominal sample rate (4250 SPS), and an update rate of 1 Hz
(DEC_RATE = 0x1099; divide by 4249 plus 1, see Table 150),
all at the same time. When using an external clock that is higher
than 4250 SPS, reduce the DEC_RATE setting to avoid
overranging the delta velocity registers.
Y-Axis Delta Velocity (Y_DELTVEL_LOW,
Y_DELTVEL_OUT)
The Y_DELTVEL_LOW (see Table 79 and Table 80) and
Y_DELTVEL_OUT (see Table 81 and Table 82) registers contain
the delta velocity data for the y-axis.
Table 79. Y_DELTVEL_LOW Register Definitions
Page Addresses Default
Access Flash Backup
0x00 0x50, 0x51 Not applicable
R
No
Each axis of the delta velocity measurements has two output
data registers. Figure 39 shows how these two registers combine
to support 32-bit, twos complement data format for the delta
velocity measurements along the x-axis. This format also
applies to the y-axis and x-axis.
Table 80. Y_DELTVEL_LOW Bit Definitions
Bits
Description
[15:0]
Y-axis delta angle data; low word
X_DELTVEL_OUT
BIT 0 BIT 15
X-AXIS DELTA ANGLE DATA
X_DELTVEL_LOW
Table 81. Y_DELTVEL_OUT Register Definitions
BIT 15
BIT 0
Page Addresses Default
Access Flash Backup
0x00 0x52, 0x53 Not applicable
R
No
Figure 39. Delta Angle Output Data Structure
Table 82. Y_DELTVEL_OUT Bit Definitions
Bits Description
X-Axis Delta Velocity (X_DELTVEL_LOW,
X_DELTVEL_OUT)
[15:0] Y-axis delta velocity data, high word; twos complement,
100 m/sec range, 0 m/sec = 0x0000;
The X_DELTVEL_LOW (see Table 75 and Table 76) and
X_DELTVEL_OUT (see Table 77 and Table 78) registers
contain the delta velocity data for the x-axis.
1 LSB = 100 m/sec ÷ 215 = ~3.052 mm/sec
Z-Axis Delta Velocity (Z_DELTVEL_LOW,
Z_DELTVEL_OUT)
Table 75. X_DELTVEL_LOW Register Definitions
Page Addresses Default
Access Flash Backup
The Z_DELTVEL_LOW (see Table 83 and Table 84) and
Z_DELTVEL_OUT (see Table 85 and Table 86) registers
contain the delta velocity data for the z-axis.
0x00 0x4C, 0x4D Not applicable
R No
Table 76. X_DELTVEL_LOW Bit Definitions
Bits
Description
Table 83. Z_DELTVEL_LOW Register Definitions
[15:0]
X-axis delta angle data; low word
Page Addresses Default
Access Flash Backup
0x00 0x54, 0x55 Not applicable
R
No
Table 77. X_DELTVEL_OUT Register Definitions
Page Addresses Default Access Flash Backup
0x00 0x4E, 0x4F Not applicable No
Table 84. Z_DELTVEL_LOW Bit Definitions
R
Bits
Description
[15:0]
Z-axis delta angle data; low word
Table 78. X_DELTVEL_OUT Bit Definitions
Bits Description
Table 85. Z_DELTVEL_OUT Register Definitions
[15:0] X-axis delta velocity data, high word; twos complement,
100 m/sec range, 0 m/sec = 0x0000;
Page Addresses Default
Access Flash Backup
0x00 0x56, 0x57 Not applicable
R
No
1 LSB = 100 m/sec ÷ 215 = ~3.052 mm/sec
Table 86. Z_DELTVEL_OUT Bit Definitions
Bits Description
[15:0] Z-axis delta velocity data, high word; twos complement,
100 m/sec range, 0 m/sec = 0x0000;
1 LSB = 100 m/sec ÷ 215 = ~3.052 mm/sec
Rev. C | Page 27 of 42
ADIS16495
Data Sheet
Z-AXIS
ΔV
Z
X-AXIS
Y-AXIS
ΔV
X
ΔV
Y
PIN 23
PIN 1
Figure 40. Delta Velocity Axis and Polarity Assignments
Burst Read Command, BURST_CMD
Delta Velocity Resolution
Reading the BURST_CMD register (see Table 89 and Table 90)
starts the BRF. See Table 10, Table 11, Figure 5, and Figure 6
for more information on the BRF function.
Table 87 and Table 88 offer various numerical examples that
demonstrate the format of the delta angle data in both 16-bit
and 32-bit formats.
Table 89. BURST_CMD Register Definitions
Table 87. 16-Bit Delta Velocity Data Format Examples
Page Addresses Default
Access Flash Backup
Velocity (m/sec)
Decimal Hex
Binary
0x00 0x7C, 0x7D Not Applicable
R
No
+100 × (215 − 1)/215 +32,767
0x7FFF 0111 1111 1110 1111
0x0002 0000 0000 0000 0010
0x0001 0000 0000 0000 0001
0x0000 0000 0000 0000 0000
0xFFFF 1111 1111 1111 1111
0xFFFE 1111 1111 1111 1110
0x8000 1000 0000 0000 0000
+100/214
+100/215
0
+2
+1
0
Table 90. BURST_CMD Bit Definitions
Bits
Description
−100/215
−100/214
−100
−1
−2
−32,768
[15:0]
Burst read command register
Product Identification, PROD_ID
The PROD_ID register (see Table 91 and Table 92) contains
the numerical portion of the device number (16,495). See
Figure 30 for an example of how to use a looping read of this
register to validate the integrity of the communication.
Table 88. 32-Bit Delta Angle Data Format Examples
Velocity (m/sec)
+100 × (231 − 1)/231
+100/230
+100/231
0
Decimal
Hex
+2,147,483,647
+2
+1
0
0x7FFFFFFF
0x00000002
0x00000001
0x00000000
0xFFFFFFFF
0xFFFFFFFE
0x80000000
Table 91. PROD_ID Register Definitions
Page
Addresses
Default Access Flash Backup
0x00
0x7E, 0x7F
0x406F Yes
R
−100/231
−100/230
−100
−1
−2
−2,147,483,648
Table 92. PROD_ID Bit Definitions
Bits
Description
[15:0]
Product identification = 0x406F
Rev. C | Page 28 of 42
Data Sheet
ADIS16495
USER BIAS/SCALE ADJUSTMENT
Gyroscope Scale Adjustment, Z_GYRO_SCALE
The signal chain of each inertial sensor (accelerometers, gyro-
scopes) includes application of unique correction formulas that
come from extensive characterization of bias, sensitivity, align-
ment, and response to linear acceleration (gyroscopes) over a
temperature range of −40°C to +85°C for the ADIS16495. These
correction formulas are not accessible, but the user does have the
opportunity to adjust the bias and the scale factor, for each sensor
individually, through user accessible registers. These correction
factors follow immediately after the factory derived correction
formulas in the signal chain, which processes at a rate of 4250
Hz when using the internal sample clock (see fSM in Figure 18
and Figure 19).
The Z_GYRO_SCALE register (see Table 97 and Table 98)
allows the user to adjust the scale factor for the z-axis
gyroscopes. This register influences the z-axis gyroscope
measurements in the same manner that X_GYRO_SCALE
influences the x-axis gyroscope measurements (see Figure 41).
Table 97. Z_GYRO_SCALE Register Definitions
Page
Addresses
Default Access Flash Backup
0x02
0x08, 0x09
0x0000 R/W Yes
Table 98. Z_GYRO_SCALE Bit Definitions
Bits Description
Gyroscope Scale Adjustment, X_GYRO_SCALE
[15:0] Z-axis gyroscope scale correction; twos complement,
0x0000 = unity gain, 1 LSB = 1 ÷ 215 = ~0.003052%
The X_GYRO_SCALE register (see Table 93 and Table 94)
provides the user with the opportunity to adjust the scale factor
for the x-axis gyroscopes. See Figure 41 for an illustration of
how this scale factor influences the x-axis gyroscope data.
Accelerometer Scale Adjustment, X_ACCL_SCALE
The X_ACCL_SCALE register (see Table 99 and Table 100)
allows users to adjust the scale factor for the x-axis
accelerometers. See Figure 42 for an illustration of how this
scale factor influences the x-axis accelerometer data.
Table 93. X_GYRO_SCALE Register Definitions
Page
Addresses
Default Access Flash Backup
0x02
0x04, 0x05
0x0000 R/W Yes
Table 99. X_ACCL_SCALE Register Definitions
Page
Addresses
Default Access Flash Backup
Table 94. X_GYRO_SCALE Bit Definitions
Bits Description
0x02
0x0A, 0x0B
0x0000 R/W Yes
[15:0] X-axis gyroscope scale correction; twos complement,
0x0000 = unity gain, 1 LSB = 1 ÷ 215 = ~0.003052%
Table 100. X_ACCL_SCALE Bit Definitions
Bits Description
1 + X_GYRO_SCALE
[15:0] X-axis accelerometer scale correction; twos complement,
0x0000 = unity gain, 1 LSB = 1 ÷ 215 = ~0.003052%
FACTORY
X-AXIS
GYRO
CALIBRATION
AND
X_GYRO_OUT X_GYRO_LOW
FILTERING
1 + X_ACCL_SCALE
XG_BIAS_HIGH XG_BIAS_LOW
FACTORY
X-AXIS
ACCL
CALIBRATION
AND
X_ACCL_OUT X_ACCL_LOW
Figure 41. User Bias/Scale Adjustment Registers in Gyroscope Signal Path
FILTERING
Gyroscope Scale Adjustment, Y_GYRO_SCALE
XA_BIAS_HIGH
XA_BIAS_LOW
The Y_GYRO_SCALE register (see Table 95 and Table 96) allows
the user to adjust the scale factor for the y-axis gyroscopes. This
register influences the y-axis gyroscope measurements in the
same manner that X_GYRO_SCALE influences the x-axis
gyroscope measurements (see Figure 41).
Figure 42. User Bias/Scale Adjustment Registers in Accelerometer Signal Path
Accelerometer Scale Adjustment, Y_ACCL_SCALE
The Y_ACCL_SCALE register (see Table 101 and Table 102)
allows the user to adjust the scale factor for the y-axis
accelerometers. This register influences the y-axis accelerometer
measurements in the same manner that X_ACCL_SCALE
influences the x-axis accelerometer measurements (see Figure 42).
Table 95. Y_GYRO_SCALE Register Definitions
Page
Addresses
Default Access Flash Backup
0x02
0x06, 0x07
0x0000 R/W Yes
Table 101. Y_ACCL_SCALE Register Definitions
Page
Addresses
Default Access Flash Backup
Table 96. Y_GYRO_SCALE Bit Definitions
Bits Description
0x02
0x0C, 0x0D
0x0000 R/W Yes
[15:0] Y-axis gyroscope scale correction; twos complement,
0x0000 = unity gain, 1 LSB = 1 ÷ 215 = ~0.003052%
Table 102. Y_ACCL_SCALE Bit Definitions
Bits Description
[15:0] Y-axis accelerometer scale correction; twos complement,
0x0000 = unity gain, 1 LSB = 1 ÷ 215 = ~0.003052%
Rev. C | Page 29 of 42
ADIS16495
Data Sheet
YG_BIAS_HIGH register, and the digital format examples in
Accelerometer Scale Adjustment, Z_ACCL_SCALE
Table 26 apply to the number that comes from combining the
YG_BIAS_LOW and YG_BIAS_HIGH registers. These registers
influence the y-axis gyroscope measurements in the same manner
that the XG_BIAS_ LOW and XG_BIAS_HIGH registers
influence the x-axis gyroscope measurements (see Figure 41).
The Z_ACCL_SCALE register (see Table 103 and Table 104)
allows the user to adjust the scale factor for the z-axis
accelerometers. This register influences the z-axis accelerometer
measurements in the same manner that X_ACCL_SCALE
influences the x-axis accelerometer measurements (see Figure 42).
Table 109. YG_BIAS_LOW Register Definitions
Table 103. Z_ACCL_SCALE Register Definitions
Page
Addresses
Default Access Flash Backup
Page
Addresses
Default Access Flash Backup
0x02
0x14, 0x15
0x0000 R/W Yes
0x02
0x0E, 0x0F
0x0000 R/W Yes
Table 110. YG_BIAS_LOW Bit Definitions
Bits Description
Table 104. Z_ACCL_SCALE Bit Definitions
Bits Description
[15:0] Y-axis gyroscope offset correction, low word; twos comp-
lement, 0°/sec = 0x0000, 1 LSB = KG ÷ 216 (see Table 24)
[15:0] Z-axis accelerometer scale correction; twos complement,
0x0000 = unity gain, 1 LSB = 1 ÷ 215 = ~0.003052%
Table 111. YG_BIAS_HIGH Register Definitions
Gyroscope Bias Adjustment, XG_BIAS_LOW,
XG_BIAS_HIGH
Page
Addresses
Default Access Flash Backup
0x02
0x16, 0x17
0x0000 R/W Yes
The XG_BIAS_LOW (see Table 105 and Table 106) and XG_
BIAS_HIGH (see Table 107 and Table 108) registers combine
to allow the user to adjust the bias of the x-axis gyroscopes. The
digital format examples in Table 25 also apply to the XG_BIAS_
HIGH register, and the digital format examples in Table 26 apply
to the number that comes from combining the XG_BIAS_LOW
and XG_BIAS_HIGH registers. See Figure 41 for an illustration
of how these two registers combine and influence the x-axis
gyroscope measurements.
Table 112. YG_BIAS_HIGH Bit Definitions
Bits Description
[15:0] Y-axis gyroscope offset correction, high word twos
complement, 0°/sec = 0x0000, 1 LSB = KG (See Table 24)
Gyroscope Bias Adjustment, ZG_BIAS_LOW,
ZG_BIAS_HIGH
The ZG_BIAS_LOW (see Table 113 and Table 114) and ZG_
BIAS_HIGH (see Table 115 and Table 116) registers combine
to allow users to adjust the bias of the z-axis gyroscopes. The
digital format examples in Table 25 also apply to the ZG_BIAS_
HIGH register, and the digital format examples in Table 26 apply
to the number that comes from combining the ZG_BIAS_LOW
and ZG_BIAS_HIGH registers. These registers influence the
z-axis gyroscope measurements in the same manner that the
XG_BIAS_ LOW and XG_BIAS_HIGH registers influence the x-
axis gyroscope measurements (see Figure 41).
Table 105. XG_BIAS_LOW Register Definitions
Page
Addresses
Default Access Flash Backup
0x02
0x10, 0x11
0x0000 R/W Yes
Table 106. XG_BIAS_LOW Bit Definitions
Bits
Description
[15:0]
X-axis gyroscope offset correction, low word;
twos complement, 0°/sec = 0x0000, 1 LSB = KG ÷ 216
(see Table 24)
Table 113. ZG_BIAS_LOW Register Definitions
Table 107. XG_BIAS_HIGH Register Definitions
Page
Addresses
Default Access Flash Backup
Page
Addresses
Default Access Flash Backup
0x02
0x18, 0x19
0x0000 R/W Yes
0x02
0x12, 0x13
0x0000 R/W Yes
Table 114. ZG_BIAS_LOW Bit Definitions
Bits Description
[15:0] Z-axis gyroscope offset correction, low word; twos comp-
lement, 0°/sec = 0x0000, 1 LSB = KG ÷ 216 (see Table 24)
Table 108. XG_BIAS_HIGH Bit Definitions
Bits Description
[15:0] X-axis gyroscope offset correction, high word twos
complement, 0°/sec = 0x0000, 1 LSB = KG (see Table 24)
Table 115. ZG_BIAS_HIGH Register Definitions
Gyroscope Bias Adjustment, YG_BIAS_LOW,
YG_BIAS_HIGH
Page
Addresses
Default Access Flash Backup
0x02
0x1A, 0x1B
0x0000 R/W Yes
The YG_BIAS_LOW (see Table 109 and Table 110) and YG_
BIAS_HIGH (see Table 111 and Table 112) registers combine
to allow users to adjust the bias of the y-axis gyroscopes. The
digital format examples in Table 25 also apply to the
Rev. C | Page 30 of 42
Data Sheet
ADIS16495
Table 116. ZG_BIAS_HIGH Bit Definitions
Table 122. YA_BIAS_LOW Bit Definitions
Bits
Description
Bits
Description
[15:0] Z-axis gyroscope offset correction, high word twos
complement, 0°/sec = 0x0000, 1 LSB = KG (See Table 24)
[15:0]
Y-axis accelerometer offset correction, low word, twos
complement, 0 g = 0x0000, 1 LSB = 0.25 mg ÷ 216
Accelerometer Bias Adjustment, XA_BIAS_LOW,
XA_BIAS_HIGH
Table 123. YA_BIAS_HIGH Register Definitions
Page
Addresses
Default Access Flash Backup
The XA_BIAS_LOW (see Table 117 and Table 118) and XA_
BIAS_HIGH (see Table 119 and Table 120) registers combine
to allow the user to adjust the bias of the x-axis accelerometers.
The digital format examples in Table 51 also apply to the
XA_BIAS_ HIGH register and the digital format examples in
Table 52 apply to the number that comes from combining the
XA_BIAS_LOW and XA_BIAS_HIGH registers. See Figure 42
for an illustration of how these two registers combine and
influence the x-axis gyroscope measurements.
0x02
0x22, 0x23
0x0000 R/W Yes
Table 124. YA_BIAS_HIGH Bit Definitions
Bits Description
[15:0] Y-axis accelerometer offset correction, high word, twos
complement, 0 g = 0x0000, 1 LSB = 0.25 mg
Accelerometer Bias Adjustment, ZA_BIAS_LOW,
ZA_BIAS_HIGH
Table 117. XA_BIAS_LOW Register Definitions
The ZA_BIAS_LOW (see Table 125 and Table 126) and ZA_
BIAS_HIGH (see Table 127 and Table 128) registers combine
to allow users to adjust the bias of the z-axis accelerometers.
The digital format examples in Table 51 also apply to the
ZA_BIAS_HIGH register and the digital format examples in
Table 52 apply to the number that comes from combining the
ZA_BIAS_LOW and ZA_BIAS_HIGH registers. These registers
influence the z-axis accelerometer measurements in the same
manner that the XA_BIAS_LOW and XA_BIAS_HIGH
registers influence the x-axis accelerometer measurements (see
Figure 42).
Page
Addresses
Default Access Flash Backup
0x02
0x1C, 0x1D
0x0000 R/W Yes
Table 118. XA_BIAS_LOW Bit Definitions
Bits
Description
[15:0]
X-axis accelerometer offset correction, low word, twos
complement, 0 g = 0x0000, 1 LSB = 0.25 mg ÷ 216
Table 119. XA_BIAS_HIGH Register Definitions
Page
Addresses
Default Access Flash Backup
Table 125. ZA_BIAS_LOW Register Definitions
0x02
0x1E, 0x1F
0x0000 R/W Yes
Page
Addresses
Default Access Flash Backup
0x02
0x24, 0x25
0x0000 R/W Yes
Table 120. XA_BIAS_HIGH Bit Definitions
Bits Description
Table 126. ZA_BIAS_LOW Bit Definitions
Bits Description
[15:0] X-axis accelerometer offset correction, high word,
twos complement, 0 g = 0x0000, 1 LSB = 0.25 mg
[15:0] Z-axis accelerometer offset correction, low word,
Accelerometer Bias Adjustment, YA_BIAS_LOW,
YA_BIAS_HIGH
twos complement, 0 g = 0x0000, 1 LSB = 0.25 mg ÷ 216
The YA_BIAS_LOW (see Table 121 and Table 122) and YA_
BIAS_HIGH (see Table 123 and Table 124) registers combine
to allow the user to adjust the bias of the y-axis accelerometers.
The digital format examples in Table 51 also apply to the
YA_BIAS_ HIGH register, and the digital format examples in
Table 52 apply to the number that comes from combining the
YA_BIAS_LOW and YA_BIAS_HIGH registers. These registers
influence the y-axis accelerometer measurements in the same
manner that the XA_BIAS_LOW and XA_BIAS_HIGH registers
influence the x-axis accelerometer measurements (see Figure 42).
Table 127. ZA_BIAS_HIGH Register Definitions
Page
Addresses
Default Access Flash Backup
0x02
0x26, 0x27
0x0000 R/W Yes
Table 128. ZA_BIAS_HIGH Bit Definitions
Bits Description
[15:0] Z-axis accelerometer offset correction, high word,
twos complement, 0 g = 0x0000, 1 LSB = 0.25 mg
SCRATCH REGISTERS, USER_SCR_X
Table 121. YA_BIAS_LOW Register Definitions
The USER_SCR_1 (see Table 129 and Table 130), USER_SCR_2
(see Table 131 and Table 132), USER_SCR_3 (see Table 133
and Table 134), and USER_SCR_4 (see Table 135 and Table 136)
registers provide four locations for the user to store information.
Page
Addresses
Default Access Flash Backup
0x02
0x20, 0x21
0x0000 R/W Yes
Rev. C | Page 31 of 42
ADIS16495
Data Sheet
Table 129. USER_SCR_1 Register Definitions
Table 138. FLSHCNT_LOW Bit Definitions
Bits Description
[15:0] Flash memory write counter, low word
Page
Addresses
Default Access Flash Backup
0x02
0x74, 0x75
0x0000 R/W Yes
Table 130. USER_SCR_1 Bit Definitions
Bits Description
[15:0] User defined
Table 139. FLSHCNT_HIGH Register Definitions
Page Addresses Default Access Flash Backup
0x02 0x7E, 0x7F Not applicable
R
Yes
Table 131. USER_SCR_2 Register Definitions
Table 140. FLSHCNT_HIGH Bit Definitions
Bits Description
Page
Addresses
Default Access Flash Backup
0x02
0x76, 0x77
0x0000 R/W Yes
[15:0] Flash memory write counter, high word
Table 132. USER_SCR_2 Bit Definitions
Bits Description
[15:0] User defined
600
450
300
Table 133. USER_SCR_3 Register Definitions
Page
Addresses
Default Access Flash Backup
0x02
0x78, 0x79
0x0000 R/W Yes
150
0
Table 134. USER_SCR_3 Bit Definitions
Bits Description
[15:0] User defined
30
40
55
70
85
100
125
135
150
JUNCTION TEMPERATURE (°C)
Figure 43. Flash Memory Retention
Table 135. USER_SCR_4 Register Definitions
GLOBAL COMMANDS, GLOB_CMD
Page
Addresses
Default Access Flash Backup
The GLOB_CMD register (see Table 141 and Table 142) provides
trigger bits for several operations. Write a 1 to the appropriate bit
in GLOB_CMD to start a particular function.
0x02
0x7A, 0x7B
0x0000 R/W Yes
Table 136. USER_SCR_4 Bit Definitions
Bits Description
[15:0] User defined
Table 141. GLOB_CMD Register Definitions
Page Addresses Default
Access Flash Backup
0x03 0x02, 0x03 Not applicable
W
No
FLASH MEMORY ENDURANCE COUNTER,
FLSHCNT_LOW, FLSHCNT_HIGH
Table 142. GLOB_CMD Bit Definitions
The FLSHCNT_LOW (see Table 137 and Table 138) and
FLSHCNT_HIGH (see Table 139 and Table 140) registers
combine to provide a 32-bit, binary counter that tracks the
number of flash memory write cycles. In addition to the
number of write cycles, the flash memory has a finite service
lifetime, which depends on the junction temperature. Figure 43
provides guidance for estimating the retention life for the flash
memory at specific junction temperatures. The junction
temperature is approximately 7°C above the case temperature.
Bits
Description
[15:8]
7
6
[5:4]
3
2
1
0
Not used
Software reset
Clear user calibration
Not used
Flash memory update
Not used
Self test
Bias correction update
Table 137. FLSHCNT_LOW Register Definitions
Software Reset
Page Addresses Default
Access Flash Backup
Turn to Page 3 (DIN = 0x8003) and then set GLOB_CMD, Bit 7 =
1 (DIN = 0x8280, then DIN = 0x8300) to initiate a reset in the
operation of the ADIS16495. This reset removes all data, initializes
all registers from their flash settings, and restarts data sampling
and processing. This function provides a firmware alternative
0x02 0x7C, 0x7D Not applicable
R
Yes
RST
to providing a low pulse on the
Rev. C | Page 32 of 42
pin (see Table 6, Pin 8).
Data Sheet
ADIS16495
Clear User Calibration
AUXILIARY I/O LINE CONFIGURATION,
FNCTIO_CTRL
Turn to Page 3 (DIN = 0x8003) and then set GLOB_CMD, Bit 6 =
1 (DIN = 0x8240, then DIN = 0x8300) to clear all user bias/scale
adjustments for each accelerometer and gyroscope. This command
writes 0x0000 to the following registers: X_GYRO_SCALE,
Y_GYRO_ SCALE, Z_GYRO_SCALE, X_ACCL_SCALE, Y_
ACCL_SCALE, Z_ACCL_SCALE, XG_BIAS_LOW,
XG_BIAS_HIGH, YG_BIAS_ LOW, YG_BIAS_HIGH,
ZG_BIAS_LOW, ZG_BIAS_HIGH, XA_BIAS_LOW,
XA_BIAS_HIGH, YA_BIAS_LOW, YA_BIAS_ HIGH,
ZA_BIAS_LOW, and ZA_BIAS_HIGH.
The FNCTIO_CTRL register (see Table 143 and Table 144)
provides configuration control for each I/O pin (DIO1, DIO2,
DIO3, and DIO4). Each DIOx pin supports only one function at
a time. When a single pin has two assignments, the enable bit for
the lower priority function automatically resets to zero (disabling
the lower priority function). The order of priority is as follows,
from highest priority to lowest priority: data ready, sync clock
input, and general-purpose. The ADIS16495 can take up to 20 ms
to execute a write command to the FNCTIO_CTRL register.
During this time, the operational state and the contents of the
register remain unchanged, but the SPI interface supports normal
communication (for accessing other registers).
Flash Memory Update
Turn to Page 3 (DIN = 0x8003) and then set GLOB_CMD, Bit 3 =
1 (DIN = 0x8208, then DIN = 0x8300) to initiate a manual flash
update. SYS_E_FLAG, Bit 6 (see Table 18) identifies success (0)
or failure (1) in completing this process.
Table 143. FNCTIO_CTRL Register Definitions
Page
Addresses
Default Access Flash Backup
The user must not poll the status registers while waiting for the
update to complete because the serial port is disabled during
the update. Rather, the user must either wait the prescribed
amount of time found in Table 3 or wait for the data ready
indicator pin to begin toggling.
0x03
0x06, 0x07
0x000D R/W Yes
Table 144. FNCTIO_CTRL Bit Definitions
Bits
[15:9]
8
Description
Not used
On Demand Self Test (ODST)
Sync clock mode:
1 = PPS
0 = sync
Turn to Page 3 (DIN = 0x8003) and then set GLOB_CMD, Bit 1 =
1 (DIN = 0x8202, then DIN = 0x8300) to run the ODST
routine, which executes the following steps:
7
Sync clock input enable
1 = enabled
0 = disabled
1. Measure the output on each sensor.
2. Activate an internal force on the mechanical elements of
each sensor, which simulates the force associated with
actual inertial motion.
3. Measure the output response on each sensor.
4. Deactivate the internal force on each sensor.
5. Calculate the difference between the force on and normal
operating conditions (force off).
6. Compare the difference with internal pass/fail criteria.
7. Report the pass/fail results for each sensor in DIAG_STS
(see Table 20) and the overall pass/fail flag in SYS_E_FLAG,
Bit 5 (see Table 18).
6
Sync clock input polarity
1 = rising edge
0 = falling edge
Sync clock input line selection
00 = DIO1
01 = DIO2
10 = DIO3
11 = DIO4
[5:4]
3
Data ready enable
1 = enabled
0 = disabled
False positive results are possible when the executing the ODST
while the device is in motion. The user must not poll the status
registers while waiting for the test to complete. Rather, the user
must either wait the prescribed amount of time found in Table 3 or
wait for the data ready indicator pin to begin toggling.
2
Data ready polarity
1 = positive
0 = negative
[1:0]
Data ready line selection
00 = DIO1
Bias Correction Update
01 = DIO2
10 = DIO3
11 = DIO4
Turn to Page 3 (DIN = 0x8003) and set GLOB_CMD, Bit 0 = 1
(DIN = 0x8201, then DIN = 0x8300) to update the user offset
registers with the correction factors of the continuous bias
estimation (CBE) (see Table 152). Ensure that the inertial platform
is stable during the entire average time for optimal bias estimates.
Rev. C | Page 33 of 42
ADIS16495
Data Sheet
For example, use the following sequence to set DIO1 and DIO3
as high and low output lines, respectively, and set DIO2 and DIO4
as input lines:
Data Ready Indicator
The FNCTIO_CTRL, Bits[3:0] provide three configuration
options for the data ready function: on/off, polarity, and DIOx line.
The primary purpose this signal is to drive the interrupt control
line of an embedded processor, which can synchronize data
collection and minimize latency. The data ready indicator is useful
to determine if the controller inside the ADIS16495 is busy with a
task (for example, a flash memory update) because data ready stops
togging while these tasks are performed and resumes upon
completion. The factory default assigns DIO2 as a positive
polarity, data ready signal, which means the data in the output
registers is valid when the DIO2 line is high (see Figure 25).
This configuration works well when DIO2 drives an interrupt
service pin that activates on a low to high pulse.
1. Turn to Page 3 (DIN = 0x8003).
2. Set GPIO_CTRL, Bits[7:0] = 0x15 (DIN = 0x8815, then
DIN = 0x8900).
Table 145. GPIO_CTRL Register Definitions1
Page
Addresses
Default Access Flash Backup
0x03
0x08, 0x09
0x00X0 R/W Yes
1 GPIO_CTRL, Bits[7:4] reflect the logic levels on the DIOx lines and do not
have a default setting.
Table 146. GPIO_CTRL Bit Definitions1
Bits
Description
Use the following sequence to change this assignment to DIO3
with negative polarity:
[15:8]
Don’t care
7
6
5
4
3
General-Purpose I/O Line 4 (DIO4) data level
General-Purpose I/O Line 3 (DIO3) data level
General-Purpose I/O Line 2 (DIO2) data level
General-Purpose I/O Line 1 (DIO1) data level
General-Purpose I/O Line 4 (DIO4) direction control
(1 = output, 0 = input)
1. Turn to Page 3 (DIN = 0x8003).
2. Set FNCTIO_CTRL, Bits[3:0] = 1000 (DIN = 0x860A, then
DIN = 0x8700).
The timing jitter on the data ready signal is typically within
1.4 µs. When using DIO1 to support the data ready function,
this signal can experience some premature pulses, which do not
indicate the start of data production, during its start-up process. If
it is necessary to use DIO1 for this function, use it in conjunction
with a delay or other control mechanism to prevent premature
data acquisition activity during the start-up process.
2
1
0
General-Purpose I/O Line 3 (DIO3) direction control
(1 = output, 0 = input)
General-Purpose I/O Line 2 (DIO2) direction control
(1 = output, 0 = input)
General-Purpose I/O Line 1 (DIO1) direction control
(1 = output, 0 = input)
1 GPIO_CTRL, Bits[7:4] reflect the logic levels on the DIOx lines and do not
have a default setting.
Input Sync/Clock Control
The FNCTIO_CTRL, Bits[8:4] provide several configuration
options for using one of the DIOx lines as an external clock signal
and for controlling inertial sensor data collection and processing.
For example, use the following sequence to establish DIO4 as a
positive polarity, input clock pin that operates in sync mode and
preserves the factory default setting for the data ready function:
MISCELLANEOUS CONFIGURATION, CONFIG
The CONFIG register (see Table 147 and Table 148) provides
configuration options for the linear g compensation in the
gyroscopes (on/off) and the point of percussion alignment for
the accelerometers (on/off).
1. Turn to Page 3 (DIN = 0x8003).
2. Set FNCTIO_CTRL, Bits[7:0] = 0xFD (DIN = 0x86FD).
3. Set FNCTIO_CTRL, Bits[15:8] = 0x00 (DIN = 0x8700).
Table 147. CONFIG Register Definitions
Page
Addresses
Default Access Flash Backup
0x03
0x0A, 0x0B
0x00C0 R/W Yes
In sync mode, the ADIS16495 disables its internal sample clock,
and the frequency of the external clock signal establishes the rate of
data collection and processing (fSM in Figure 18 and Figure 19).
When using the PPS mode (FNCTIO_CTRL, Bit 8 = 1), the rate of
data collection and production (fSM) is equal to the product of the
external clock frequency and scale factor (KECSF) in the
SYNC_SCALE register (see Table 154).
Table 148. CONFIG Bit Definitions
Bits Description
[15:8] Not used
7
Linear g compensation for gyroscopes (1 = enabled)
Point of percussion alignment (1 = enabled)
Not used
6
[5:0]
GENERAL-PURPOSE I/O CONTROL, GPIO_CTRL
When FNCTIO_CTRL does not configure a DIOx pin, the
GPIO_CTRL register (see Table 145 and Table 146) provides
user controls for general-purpose use of the DIOx pins.
GPIO_CTRL, Bits[3:0] provide I/O assignment controls for
each line. When the DIOx lines are inputs, monitor their level
by reading GPIO_CTRL, Bits[7:4]. When the DIOx lines are
used as outputs, set their level by writing to GPIO_CTRL, Bits[7:4].
Point of Percussion
CONFIG, Bit 6 offers a point of percussion alignment function
that maps the accelerometer sensors to the corner of the
package identified in Figure 44. To activate this feature, turn to
Rev. C | Page 34 of 42
Data Sheet
ADIS16495
Page 3 (DIN = 0x8003), then set CONFIG, Bit 6 = 1 (DIN =
0x8A40, then DIN = 0x8B00).
CONTINUOUS BIAS ESTIMATION (CBE),
NULL_CNFG
The NULL_CNFG register (see Table 151 and Table 152) provides
the configuration controls for the CBE, which associates with the
bias correction update command in GLOB_CMD, Bit 0 (see
Table 142). NULL_CNFG, Bits[3:0] establishes the total average
time (tA) for the bias estimates and NULL_CNFG, Bits[13:8]
provide on/off controls for each sensor. The factory default
configuration for NULL_CNFG enables the bias null command
for the gyroscopes, disables the bias null command for the
accelerometers, and sets the average time to ~15.42 seconds.
PIN 23
PIN 1
POINT OF PERCUSSION
ALIGNMENT REFERENCE POINT.
SEE CONFIG[6].
tB = 2TBC/4250 = 210/4250 = ~0.241 seconds
Figure 44. Point of Percussion Reference Point
LINEAR ACCELERATION ON EFFECT ON
GYROSCOPE BIAS
tA = 64 × tB = 64 × 0.241 = 15.42 seconds
where:
tB is the time base.
tA is the averaging time.
The ADIS16495 includes first-order compensation for the linear g
effect in the gyroscopes, which uses the following model:
When a sensor bit in NULL_CNFG is active (equal to 1),
setting GLOB_CMD, Bit 0 = 1 (DIN sequence: 0x8003, 0x8201,
0x8300) causes its bias correction register to automatically
update with a value that corrects for its present bias error (from
the CBE).
XC
XPC
LG11 LG12 LG13
A
ω
ω
ω
ω
ω
ω
X
= LG
LG22 LG23 × AY
+
21
YC
YPC
LG31 LG32 LG33
AZ
ZC
ZPC
The linear g correction factors, LGXY, apply correction for linear
acceleration in all three directions to the data path of each gyro-
scope (ωXPC, ωYPC, and ωZPC) at the rate of the data samples
(4250 SPS when using the internal clock). CONFIG, Bit 7 provides
an on/off control for this compensation. The factory default value
for this bit activates this compensation. To turn it off, turn to Page
3 (DIN = 0x8003) and set CONFIG, Bit 7 = 0 (DIN = 0x8A40, then
DIN = 0x8B00). This command sequence also preserves the
default setting for the point of percussion alignment function (on).
For example, setting NULL_CNFG, Bit 8 equal to 1 causes an
update in the XG_BIAS_LOW (see Table 106) and
XG_BIAS_HIGH (see Table 108) registers.
Table 151. NULL_CNFG Register Definitions
Page
Addresses
Default Access Flash Backup
0x03
0x0E, 0x0F
0x070A R/W Yes
Table 152. NULL_CNFG Bit Definitions
Bits Description
[15:14] Not used
DECIMATION FILTER, DEC_RATE
The DEC_RATE register (see Table 149 and Table 150)
provides user control for the final filter stage (see Figure 21),
which averages and decimates the accelerometers and
gyroscopes data, and extends the time that the delta angle and
delta velocity track between each update. The output sample
rate is equal to 4250/(DEC_RATE + 1). For example, turn to
Page 3 (DIN = 0x8003), and set DEC_RATE = 0x2A (DIN =
0x8C2A, then DIN = 0x8D00) to reduce the output sample rate to
~98.8 SPS (4250 ÷ 43).
13
12
11
10
9
8
[7:4]
[3:0]
Z-axis acceleration bias correction enable (1 = enabled)
Y-axis acceleration bias correction enable (1 = enabled)
X-axis acceleration bias correction enable (1 = enabled)
Z-axis gyroscope bias correction enable (1 = enabled)
Y-axis gyroscope bias correction enable (1 = enabled)
X-axis gyroscope bias correction enable (1 = enabled)
Not used
Time base control (TBC), range: 0 to 13 (default = 10);
tB = 2TBC/4250, time base; tA = 64 × tB, average time
Table 149. DEC_RATE Register Definitions
Page
Addresses
Default Access Flash Backup
0x03
0x0C, 0x0D
0x0000 R/W Yes
Table 150. DEC_RATE Bit Definitions
Bits
Description
[15:0]
Decimation rate, binary format
Rev. C | Page 35 of 42
ADIS16495
Data Sheet
chain of each sensor (see Figure 21). These registers provide
on/off control for the FIR bank for each inertial sensor, along
with the FIR bank (A, B, C, or D) that each sensor uses.
Table 157. FILTR_BNK_0 Register Definitions
SCALING THE INPUT CLOCK (PPS MODE),
SYNC_SCALE
The PPS mode (FNCTIO_CTRL, Bit 8 = 1, see Table 144) supports
the use of an input sync frequency that is slower than the data
sample rates of the inertial sensors. This mode supports a
frequency range of 1 Hz to 128 Hz for the input sync mode. In
this mode, the data sample rate is equal to the product of the
value in the SYNC_SCALE register (see Table 153 and Table 154)
and the input sync frequency.
Page
0x03
Addresses
0x16, 0x17
Default Access Flash Backup
0x0000 R/W Yes
Table 158. FILTR_BNK_0 Bit Definitions
Bits
15
Description (Default = 0x0000)
Don’t care
For example, the following command sequence sets the data
collection and processing rate (fSM in Figure 18 and Figure 19)
to 4000 Hz (SYNC_SCALE = 0x0FA0) when using a 1 Hz
signal on the DIO3 line as the external clock input, and
preserves the factory default configuration for the data ready
signal:
14
[13:12]
Y-axis accelerometer filter enable (1 = enabled)
Y-axis accelerometer filter bank selection
00 = Bank A
01 = Bank B
10 = Bank C
11 = Bank D
X-axis accelerometer filter enable (1 = enabled)
X-axis accelerometer filter bank selection:
00 = Bank A
11
[10:9]
1. Turn to Page 3 (DIN = 0x8003).
2. Set SYNC_SCALE, Bits[7:0] = 0xA0 (DIN = 0x90A0).
3. Set SYNC_SCALE, Bits[15:8] = 0x0F (DIN = 0x910F).
4. Set FNCTIO_CTRL, Bits[7:0] = 0xFD (DIN = 0x86ED).
5. Set FNCTIO_CTRL, Bits[15:8] = 0x00 (DIN = 0x8701).
01 = Bank B
10 = Bank C
11 = Bank D
8
[7:6]
Z-axis gyroscope filter enable (1 = enabled)
Z-axis gyroscope filter bank selection:
00 = Bank A
The data ready indicator pin does not begin to toggle until at
least two external clock edges (with valid time period between
them) are detected by the ADIS16495.
01 = Bank B
10 = Bank C
11 = Bank D
Y-axis gyroscope filter enable (1 = enabled)
Table 153. SYNC_SCALE Register Definitions
Page
Addresses
Default
Access
Flash Backup
5
0x03
0x10, 0x11
0x109A
R/W
Yes
[4:3]
Y-axis gyroscope filter bank selection:
00 = Bank A
01 = Bank B
10 = Bank C
11 = Bank D
Table 154. SYNC_SCALE Bit Definitions
Bits
Description
[15:0]
External clock scale factor (KECSF), binary format
2
X-axis gyroscope filter enable (1 = enabled)
X-axis gyroscope filter bank selection:
00 = Bank A
01 = Bank B
10 = Bank C
Measurement Range Identifier, RANG_MDL
[1:0]
The RANG_MDL register (see Table 155 and Table 156)
provides a convenient method for identifying the model (and
gyroscope measurement range) of the ADIS16495.
Table 155. RANG_MDL Register Definitions1
11 = Bank D
Page
Addresses
Default
Access
Flash Backup
0x03
0x12, 0x13
N/A
R
N/A
Table 159. FILTR_BNK_1 Register Definitions
1 N/A means not applicable.
Page
Addresses
Default Access Flash Backup
Table 156. RANG_MDL Bit Definitions
Bits
0x03
0x18, 0x19
0x0000 R/W Yes
Description
[15:3]
[3:0]
Not used
Table 160. FILTR_BNK_1 Bit Definitions
0011 = ADIS16495-1 ( 125°/sec)
0111 = ADIS16495-2 ( 450°/sec)
1111 = ADIS16495-3 ( 2000°/sec)
Bits
[15:3]
2
Description
Don’t care
Z-axis accelerometer filter enable (1 = enabled)
[1:0]
Z-axis accelerometer filter bank selection:
FIR FILTERS
00 = Bank A
01 = Bank B
10 = Bank C
11 = Bank D
FIR Filters Control, FILTR_BNK_0, FILTR_BNK_1
The FILTR_BNK_0 (see Table 157 and Table 158) and
FILTR_BNK_1 (see Table 159 and Table 160) registers provide
the configuration controls for the FIR filter bank in the signal
Rev. C | Page 36 of 42
Data Sheet
ADIS16495
FIR Filter Bank Memory Maps
FIR Filter Bank B, FIR_COEF_B000 to FIR_COEF_B119
Table 165. Filter Bank B Memory Map
The ADIS16495 provides four FIR filter banks to configure and
select for each individual inertial sensor using the FILTR_BNK_0
(see Table 158) and FILTR_BNK_1 (see Table 160) registers.
Each FIR filter bank (A, B, C, and D) has 120 taps that consume
two pages of memory. The coefficient associated with each tap,
in each filter bank, has its own dedicated register that uses a 16-
bit, twos complement format. The FIR filter has unity gain when
the sum of all of the coefficients is equal to 32,768. For filter
designs that require less than 120 taps, write 0x0000 to all unused
registers to eliminate the latency associated with that particular tap.
Page PAGE_ID Addresses
Register
7
7
7
7
7
0x07
0x07
0x07
0x07
0x07
0x00, 0x01
0x02 to 0x07
0x08, 0x09
0x0A, 0x0B
0x0C to 0x7D FIR_COEF_B002 to
FIR_COEF_B058
PAGE_ID
Not used
FIR_COEF_B000
FIR_COEF_B001
7
8
8
8
8
8
0x07
0x08
0x08
0x08
0x08
0x08
0x7E, 0x07F
0x00, 0x01
0x02 to 0x07
0x08, 0x09
0x0A, 0x0B
FIR_COEF_B059
PAGE_ID
Not used
FIR_COEF_B060
FIR_COEF_B061
FIR Filter Bank A, FIR_COEF_A000 to FIR_COEF_A119
Table 161. FIR Filter Bank A Memory Map
Page PAGE_ID Addresses
0x0C to 0x7D FIR_COEF_B062 to
FIR_COEF_B118
Register
5
5
5
5
5
0x05
0x05
0x05
0x05
0x05
0x00, 0x01
0x02 to 0x07
0x08, 0x09
0x0A, 0x0B
0x0C to 0x7D
PAGE_ID
Not used
FIR_COEF_A000
FIR_COEF_A001
FIR_COEF_A002 to
FIR_COEF_A058
8
0x08
0x7E, 0x7F
FIR_COEF_B119
FIR Filter Bank C, FIR_COEF_C000 to FIR_COEF_C119
Table 166. Filter Bank C Memory Map
Page PAGE_ID Addresses
Register
5
6
6
6
6
6
0x05
0x06
0x06
0x06
0x06
0x06
0x7E, 0x07F
0x00, 0x01
0x02 to 0x07
0x08, 0x09
0x0A, 0x0B
0x0C to 0x7D
FIR_COEF_A059
PAGE_ID
Not used
FIR_COEF_A060
FIR_COEF_A061
FIR_COEF_A062 to
FIR_COEF_A118
9
9
9
9
9
0x09
0x09
0x09
0x09
0x09
0x00, 0x01
0x02 to 0x07
0x08, 0x09
0x0A, 0x0B
0x0C to 0x7D FIR_COEF_C002 to
FIR_COEF_C058
0x7E, 0x07F
0x00, 0x01
0x02 to 0x07
0x08, 0x09
0x0A, 0x0B
PAGE_ID
Not used
FIR_COEF_C000
FIR_COEF_C001
9
0x09
0x0A
0x0A
0x0A
0x0A
0x0A
FIR_COEF_C059
PAGE_ID
Not used
FIR_COEF_C060
FIR_COEF_C061
6
0x06
0x7E, 0x7F
FIR_COEF_A119
10
10
10
10
10
Table 162 and Table 163 provide detailed register and bit
definitions for one of the FIR coefficient registers in Bank A,
FIR_COEF_A071. Table 164 provides a configuration example,
which sets this register to a decimal value of −169 (0xFF57).
0x0C to 0x7D FIR_COEF_C062 to
FIR_COEF_C118
10
0x0A
0x7E, 0x7F
FIR_COEF_C119
Table 162. FIR_COEF_A071 Register Definitions
Page Addresses Default
Access Flash Backup
FIR Filter Bank D, FIR_COEF_D000 to FIR_COEF_D119
Table 167. Filter Bank D Memory Map
0x06 0x1E, 0x1F
Not applicable R/W
Yes
Table 163. FIR_COEF_A071 Bit Definitions
Page PAGE_ID Addresses
Register
Bits
Description
11
11
11
11
11
0x0B
0x0B
0x0B
0x0B
0x0B
0x00, 0x01
0x02 to 0x07
0x08, 0x09
0x0A, 0x0B
0x0C to 0x7D FIR_COEF_D002 to
FIR_COEF_D058
PAGE_ID
Not used
FIR_COEF_D000
FIR_COEF_D001
[15:0]
FIR Bank A, Coefficient 71, twos complement
Table 164. Configuration Example, FIR Coefficient
DIN Command
Description
0x8006
Turn to Page 6
0x9E57
0x9FFF
FIR_COEF_A071, Bits[7:0] = 0x57
FIR_COEF_A071, Bits[15:8] = 0xFF
11
12
12
12
12
12
0x0B
0x0C
0x0C
0x0C
0x0C
0x0C
0x7E, 0x07F
0x00, 0x01
0x02 to 0x07
0x08, 0x09
0x0A, 0x0B
FIR_COEF_D059
PAGE_ID
Not used
FIR_COEF_D060
FIR_COEF_D061
0x0C to 0x7D FIR_COEF_D062 to
FIR_COEF_D118
12
0x0C
0x7E, 0x7F
FIR_COEF_D119
Rev. C | Page 37 of 42
ADIS16495
Data Sheet
Table 171. FIRM_DM Register Definitions
Default Filter Performance
Page Addresses Default
Access Flash Backup
The FIR filter banks have factory programmed filter designs that
are all low-pass filters that have unity dc gain. Table 168 provides a
summary of each filter design, and Figure 45 shows the frequency
response characteristics. The phase delay is equal to ½ of the total
number of taps.
0x03 0x7A, 0x7B Not applicable
R Yes
Table 172. FIRM_DM Bit Definitions
Bits
Description
[15:12]
Factory configuration month BCD code, tens digit,
numerical format = 4-bit binary, range = 0 to 2
Table 168. FIR Filter Descriptions, Default Configuration
[11:8]
[7:4]
[3:0]
Factory configuration month BCD code, ones digit,
numerical format = 4-bit binary, range = 0 to 9
FIR Filter Bank
Taps
120
120
32
−3 dB Frequency (Hz)
A
B
C
D
300
100
300
100
Factory configuration day BCD code, tens digit,
numerical format = 4-bit binary, range = 0 to 3
Factory configuration day BCD code, ones digit,
numerical format = 4-bit binary, range = 0 to 9
32
0
Firmware Revision Year, FIRM_Y
–10
NO FIR
FILTERING
The FIRM_Y register (see Table 173 and Table 174) contains
the year of the factory configuration date. For example, the year
2013 is represented by FIRM_Y = 0x2013.
–20
B
D
A
C
–30
–40
–50
–60
–70
–80
–90
Table 173. FIRM_Y Register Definitions
Page Addresses Default
Access Flash Backup
0x03 0x7C, 0x7D Not applicable
R Yes
Table 174. FIRM_Y Bit Definitions
–100
0
Bits
Description
200
400
600
800
1000
1200
[15:12]
Factory configuration year BCD code, thousands digit,
numerical format = 4-bit binary, range = 0 to 9
Factory configuration year BCD code, hundreds digit,
numerical format = 4-bit binary, range = 0 to 9
Factory configuration year BCD code, tens digit,
numerical format = 4-bit binary, range = 0 to 3
Factory configuration year BCD code, ones digit,
numerical format = 4-bit binary, range = 0 to 9
FREQUENCY (Hz)
Figure 45. FIR Filter Frequency Response Curves
[11:8]
[7:4]
[3:0]
FIRMWARE REVISION, FIRM_REV
The FIRM_DM register (see Table 169 and Table 170) contains
the month and day of the factory configuration date. FIRM_DM,
Bits[15:12] and FIRM_DM, Bits[11:8] contain digits that represent
the month of the factory configuration in a binary coded decimal
(BCD) format. For example, November is the 11th month in a year
and is represented by FIRM_DM, Bits[15:8] = 0x11. FIRM_DM,
Bits[7:4], and FIRM_DM, Bits[3:0], contain digits that represent
the day of factory configuration in a BCD format. For example,
the 27th day of the month is represented by FIRM_DM, Bits[7:0] =
0x27.
Boot Revision Number, BOOT_REV
The BOOT_REV register (see Table 175 and Table 176) contains
the revision of the boot code in the ADIS16495 processor core.
Table 175. BOOT_REV Register Definitions
Page Addresses Default
Access Flash Backup
0x03 0x7E, 0x7F Not applicable
R
Yes
Table 169. FIRM_REV Register Definitions
Page Addresses Default
Access Flash Backup
Table 176. BOOT_REV Bit Definitions
0x03 0x78, 0x79 Not applicable
R Yes
Bits
Description
[15:8]
[7:0]
Binary, major revision number
Binary, minor revision number
Table 170. FIRM_REV Bit Definitions
Bits Description
[15:12] Firmware revision BCD code, tens digit, numerical
format = 4-bit binary, range = 0 to 9
Continuous SRAM Testing
This device employs a CRC function on the SRAM memory blocks
that contain the program code (CODE_SIGTR_xxx) and the
calibration coefficients (CAL_DRVTN_xxx). This process operates
in the background and generates real-time, 32-bit CRC values
for the program code and calibration coefficients, respectively. At
the conclusion of each cycle, the processor writes these calculated
[11:8]
[7:4]
[3:0]
Firmware revision BCD code, ones digit, numerical
format = 4-bit binary, range = 0 to 9
Firmware revision BCD code, tenths digit, numerical
format = 4-bit binary, range = 0 to 9
Firmware revision BCD code, hundredths digit,
numerical format = 4-bit binary, range = 0 to 9
Rev. C | Page 38 of 42
Data Sheet
ADIS16495
values in the CAL_DRVTN_xxx and CODE_DRVTN_xxx
registers (see Table 182, Table 184, Table 190, and Table 192) and
compares them with the signature values, which reflect the state
of these memory locations at the time of factory configuration.
When the calculation results do not match the signature values,
SYS_E_FLAG, Bit 2 increases to a 1. The respective signature
values are available for user access through the CAL_SIGTR_xxx
and CODE_SIGTR_xxx registers (see Table 178, Table 180,
Table 186, and Table 188). The following conditions must be
met for SYS_E_FLAG, Bit 2 to remain at the zero level:
Signature CRC, Program Code, CODE_SIGTR_LWR
Table 185. CODE_SIGTR_LWR Register Definitions
Page Addresses Default
Access Flash Backup
0x04 0x0C, 0x0D Not applicable
R Yes
Table 186. CODE_SIGTR_LWR Bit Definitions
Bits Description
[15:0] Factory programmed CRC value for the calibration
coefficients, low word
Signature CRC, Program Code, CODE_SIGTR_UPR
Table 187. CODE_SIGTR_UPR Register Definitions
•
•
•
•
CAL_SIGTR_LWR = CAL_DRVTN_LWR
CAL_SIGTR_UPR = CAL_DRVTN_UPR
CODE_SIGTR_LWR = CODE_DRVTN_LWR
CODE_SIGTR_UPR = CODE_DRVTN_UPR
Page Addresses Default
Access Flash Backup
0x04 0x0E, 0x0F Not applicable
R
Yes
Table 188. CODE_SIGTR_UPR Bit Definitions
Bits Description
Signature CRC, Calibration Values, CAL_SIGTR_LWR
Table 177. CAL_SIGTR_LWR Register Definitions
[15:0] Factory programmed CRC value for the calibration
coefficients, high word
Page Addresses Default
Access Flash Backup
0x04 0x04, 0x05 Not applicable
R Yes
Derived CRC, Program Code, CODE_DRVTN_LWR
Table 189. CODE_DRVTN_LWR Register Definitions
Table 178. CAL_SIGTR_LWR Bit Definitions
Bits Description
Page Addresses Default
Access Flash Backup
[15:0] Factory programmed CRC value for the program code,
low word
0x04 0x10, 0x11 Not applicable
R No
Table 190. CODE_DRVTN_LWR Bit Definitions
Bits Description
[15:0] Calculated CRC value for the calibration coefficients, low
word
Signature CRC, Calibration Values, CAL_SIGTR_UPR
Table 179. CAL_SIGTR_UPR Register Definitions
Page Addresses Default
Access Flash Backup
0x04 0x06, 0x07 Not applicable
R Yes
Derived CRC, Program Code, CODE_DRVTN_UPR
Table 191. CODE_DRVTN_LWR Register Definitions
Table 180. CAL_SIGTR_UPR Bit Definitions
Bits Description
Page Addresses Default
Access Flash Backup
[15:0] Factory programmed CRC value for the program code,
high word
0x04 0x12, 0x13 Not applicable
R No
Table 192. CODE_DRVTN_UPR Bit Definitions
Bits Description
Derived CRC, Calibration Values, CAL_DRVTN_LWR
Table 181. CAL_DRVTN_LWR Register Definitions
[15:0] Calculated CRC value for the calibration coefficients,
high word
Page Addresses Default
Access Flash Backup
0x04 0x08, 0x09 Not applicable
R No
Lot Specific Serial Number, SERIAL_NUM
Table 193. SERIAL_NUM Register Definitions
Table 182. CAL_DRVTN_LWR Bit Definitions
Bits Description
[15:0] Calculated CRC value for the program code, low word
Derived CRC, Calibration Values, CAL_DRVTN_UPR
Table 183. CAL_DRVTN_UPR Register Definitions
Page Addresses Default
Access Flash Backup
0x04 0x20, 0x21 Not applicable
R Yes
Table 194. SERIAL_NUM Bit Definitions
Page Addresses Default
Access Flash Backup
Bits
Description
0x04 0x0A, 0x0B Not applicable
R No
[15:0]
Lot specific serial number
Table 184. CAL_DRVTN_UPR Bit Definitions
Bits Description
[15:0] Calculated CRC value for the program code, high word
Rev. C | Page 39 of 42
ADIS16495
Data Sheet
APPLICATIONS INFORMATION
MOUNTING BEST PRACTICES
PREVENTING MISINSERTION
For the best performance, follow these guidelines when
installing the ADIS16495 into a system:
The ADIS16495 connector uses the same pattern as the
ADIS16485, but with Pin 12 and Pin 15 missing. This pin
configuration enables a mating connector to plug these holes,
which helps prevent misconnection of the ADIS16495. Samtec
has a custom part number that provides this type of mating
socket: ASP-193371-04.
•
Eliminate opportunity for translational force (x- and y-axis
direction, per Figure 35) application on the electrical
connector.
•
•
Use uniform mounting forces on all four corners. The
suggested torque setting is 40 inch ounces (0.285 Nm).
When the ADIS16495 rests on the PCB, which contains
the mating connector (see Figure 46), use a diameter of at
least 2.85 mm for the passthrough holes.
EVALUATION TOOLS
Breakout Board, ADIS16IMU1/PCBZ
The ADIS16IMU1/PCBZ (sold separately) provides a breakout
board function for the ADIS16495, which means that it provides
access to the ADIS16495 through larger connectors that support
standard 1 mm ribbon cabling. It also provides four mounting
holes for attachment of the ADIS16495 to the breakout board.
These guidelines help prevent irregular force profiles, which
can warp the package and introduce bias errors in the sensors.
Figure 46 and Figure 47 provide details for mounting hole and
connector alignment pin drill locations.
39.600 BSC
PC-Based Evaluation, EVAL-ADIS2
Use the EVAL-ADIS2 and ADIS16IMU1/PCBZ to evaluate the
ADIS16495 on a PC-based platform.
19.800 BSC
PASSTHROUGH HOLE
FOR MOUNTING SCREWS
POWER SUPPLY CONSIDERATIONS
DIAMETER OF THE HOLE
MUST ACCOMODATE
DIMENSIONAL TOLERANCE
BETWEEN THE CONNECTOR
AND HOLES
The VDD power supply must charge 46 µF of capacitance (inside
of the ADIS16495, across the VDD and GND pins) during its
initial ramp and settling process. When VDD reaches 2.85 V,
the ADIS16495 begins its internal start-up process, which gener-
ates additional transient current demand. See Figure 48 for a
typical current profile during the start-up process. The first
peak in Figure 48 relates to charging the 46 µF capacitor bank,
whereas the other transient activity relates to numerous
functions turning on during the initialization process of the
ADIS16495.
DEVICE
OUTLINE
0.560 BSC 2×
ALIGNMENT HOLES
FOR MATING SOCKET
5 BSC
5 BSC
NOTES
a
b
T
a
b
1.608ms
159.8ms
Δ158.2ms Δ60.00mA
92.00mA
152.0mA
1. ALL DIMENSIONS IN UNITS OF MILLIMETERS (mm).
2. IN THIS CONFIGURATION, THE CONNECTOR IS FACING DOWN AND
ITS PINSARE NOT VISIBLE.
Figure 46. Suggested PCB Layout Pattern, Connector Down
0.4334 [11.0]
0.019685
[0.5000]
(TYP)
0.0240 [0.610]
VDD
3
0.054 [1.37]
DR
2
4
0.1800
[4.57]
0.0394 [1.00]
0.0394 [1.00]
CURRENT
0.022±
DIA (TYP)
B
CH2 2.0V
M40.0ms
20.10%
A
CH3
3.00V
W
NONPLATED
THROUGH HOLE 2×
0.022 DIA THROUGH HOLE (TYP)
NONPLATED THROUGH HOLE
B
B
CH4 100mA
CH3 2.0V
T
12.5MS/s 5M pts
W
W
Figure 48. Transient Current Demand, Startup (DR Means Data Ready)
Figure 47. Suggested Layout and Mechanical Design when Using Samtec
CLM-112-02-G-D-A for the Mating Connector
Rev. C | Page 40 of 42
Data Sheet
ADIS16495
unsigned long crc32_block( unsigned long crc,
const unsigned short data[], int n )
CRC32 CODING EXAMPLE
This section contains sample code and values for computing
the cyclic redundancy check (CRC) for the ADIS16495 register
readback values.
{
unsigned long long_c;
int i;
In this coding example, the 32-bit CRC is first initialized with
0xFFFFFFFF. Next, each 16-bit word passes through the CRC
computation in ascending order. Finally, the CRC is XOR’ed
with 0xFFFFFFFF.
/* cycle through memory */
for ( i=0; i<n; i++ )
{
/* Get lower byte */
long_c = 0x000000ff &
(unsigned long)data[i];
/* Process with CRC */
crc = ((crc>>8) & 0x00ffffff) ^
crc_tab32[(crc^long_c)&0xff];
/* Get upper byte */
long_c = (0x000000ff &
((unsigned long)data[i]>>8);
/* Process with CRC */
crc = ((crc>>8) & 0x00ffffff) ^
crc_tab32[(crc^long_c)&0xff];
}
The ADIS16495 updates the CRC value for each data ready
cycle. The registers listed in Table 195 are used as inputs for
computing the CRC32 checksum. The registers can either be
read individually in normal SPI mode or in burst mode,
provided that all registers are all read during the same data
ready cycle.
Table 195. Sample Input Data for CRC Computation1
Register Number
Register
Input Value
0x0000
0x083A
0x0000
0xFFF7
0x0000
0xFFFE
0x0000
0x0001
0x5001
0x0003
0xE00A
0x0015
0xC009
0x0320
0x8A54
1
2
3
4
5
6
7
8
STATUS
TEMP_OUT
return crc;
}
X_GYRO_LOW
X_GYRO_OUT
Y_GYRO_LOW
Y_GYRO_OUT
Z_GYRO_LOW
Z_GYRO_OUT
X_ACCL_LOW
X_ACCL_OUT
Y_ACCL_LOW
Y_ACCL_OUT
Z_ACCL_LOW
Z_ACCL_OUT
TIME_STAMP
The CRC table (crc_tab32) is computed with the following
function:
void init_crc32_table( void )
{
9
unsigned long P_32;
int i, j;
unsigned long crc;
10
11
12
13
14
15
/* CRC32 polynomial defined by IEEE-802.3 */
P_32 = 0xEDB88320
/* 8 bits require 256 entries in Table */
for (i=0; i<256; i++)
1 This information is contained in the array data in the coding example.
{
Table 196. Output Results for CRC Sample Computation1
/* start with table entry number */
crc = (unsigned long) i;
Register Number
Register
CRC_LWR
CRC_UPR
Output Value
1
2
0x15B4
0xB6C8
/* cycle through all bits in entry number */
for (j=0; j<8; j++)
{
1 Based on the input shown in Table 195.
/* LSBit set? */
if ((crc&(unsigned
The following is the CRC initialization code:
long)0x00000001)!=(unsigned long)0)
{
/* Initialize CRC */
crc = 0xFFFFFFFFU;
/* process for bit set */
crc = (crc>>1) ^ P_32;
/* Compute CRC in the order of bytes low-high
starting at 0-14, BurstID, STATUS - TIME_STAMP */
crc = crc32_block(crc, DATA, 15);
}
else
{
/* Final operation per IEEE-802.3 */
crc ^= 0xFFFFFFFFU;
/* process for bit clear */
crc = (crc>>1);
}
}
The crc32_block function accepts an array of 16-bit numbers
and computes the CRC byte-by-byte:
/* Store calculated value into table */
crc_tab32[i] = crc;
}
}
Rev. C | Page 41 of 42
ADIS16495
Data Sheet
OUTLINE DIMENSIONS
44.254
44.000
43.746
39.800
34.600
34.575
34.550
39.600
39.400
7.350
7.225
7.100
20.00
19.80
19.60
2.20 BSC
2.20 BSC
2.065
Ø 2.040
2.015
2.325
2.200
2.075
1.142 BSC
42.800
42.600
42.400
37.598
37.573
37.548
47.254
47.000
46.746
3.70
3.50
3.30
Ø 2.40
BSC
2.065
2.040
2.015
BOTTOM VIEW
TOP VIEW
°
47.479
47.379
47.279
DETAIL A
13.750 REF
0.250 BSC
DETAIL A
FRONT VIEW
14.200
14.000
13.800
2.84 BSC
3.454
3.200
2.946
0.250 BSC
5.50
BSC
5.50
BSC
1.00 BSC
PITCH
0.30 SQ BSC
Figure 49. 24-Lead Module with Connector Interface [MODULE]
(ML-24-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Description
Package Option
ML-24-9
ML-24-9
ADIS16495-1BMLZ
ADIS16495-2BMLZ
ADIS16495-3BMLZ
24-Lead Module with Connector Interface [MODULE]
24-Lead Module with Connector Interface [MODULE]
24-Lead Module with Connector Interface [MODULE]
ML-24-9
1 Z = RoHS Compliant Part.
©2017-2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15062-7/20(C)
Rev. C | Page 42 of 42
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