ADG507AKP [ADI]
CMOS 8-/16-Channel Analog Multiplexers; CMOS 8位/ 16通道模拟多路复用器
| 型号： | ADG507AKP |
| 厂家： | 
ADI |
| 描述： | CMOS 8-/16-Channel Analog Multiplexers |
| 文件： | 总8页 (文件大小：138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS
a
8-/16-Channel Analog Multiplexers
ADG506A/ADG507A
FUNCTIONAL BLOCK DIAGRAM
FEATURES
44 V Supply Maximum Rating
VSS to VDD Analog Signal Range
Single/Dual Supply Specifications
Wide Supply Ranges (10.8 V to 16.5 V)
Extended Plastic Temperature Range
(–40؇C to +85؇C)
Low Power Dissipation (28 mW max)
Low Leakage (20 pA typ)
Available in 28-Lead DIP, SOIC, PLCC, TSSOP and LCCC
Packages
Superior Alternative to:
DG506A, Hl-506
DG507A, Hl-507
GENERAL DESCRIPTION
ORDERING GUIDE
The ADG506A and ADG507A are CMOS monolithic analog
multiplexers with 16 channels and dual 8 channels, respectively.
The ADG506A switches one of 16 inputs to a common output,
depending on the state of four binary addresses and an enable
input. The ADG507A switches one of eight differential inputs to
a common differential output, depending on the state of three
binary addresses and an enable input. Both devices have TTL
and 5 V CMOS logic compatible digital inputs.
Temperature
Range
Package
Option2
Model1
ADG506AKN
ADG506AKR
ADG506AKP
ADG506ABQ
ADG506ATQ
ADG506ATE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–55°C to +125°C
N-28
R-28
P-28A
Q-28
Q-28
E-28A
The ADG506A and ADG507A are designed on an enhanced
LC2MOS process, which gives an increased signal capability of
VSS to VDD and enables operation over a wide range of supply
voltages. The devices can operate comfortably anywhere in the
10.8 V to 16.5 V single or dual supply range. These multiplexers
ADG507AKN
ADG507AKR
ADG507AKP
ADG507AKRU
ADG507ABQ
ADG507ATQ
ADG507ATE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–55°C to +125°C
N-28
R-28
P-28A
RU-28
Q-28
Q-28
E-28A
also feature high switching speeds and low RON
.
PRODUCT HIGHLIGHTS
1. Single/Dual Supply Specifications with a Wide Tolerance
The devices are specified in the 10.8 V to 16.5 V range for
both single and dual supplies.
NOTES
1To order MIL-STD-883, Class B processed parts, add /883B to part number.
See Analog Devices’ Military/Aerospace Reference Manual (1994) for military
data sheet.
2. Extended Signal Range
The enhanced LC2MOS processing results in a high break-
2E = Leadless Ceramic Chip Carrier (LCCC); N = Plastic DIP; P = Plastic
Leaded Chip Carrier (PLCC); Q = Cerdip; R = 0.3" Small Outline IC (SOIC);
RU = Thin Shrink Small Outline Package (TSSOP).
down and an increased analog signal range of VSS to VDD
.
3. Break-Before-Make Switching
Switches are guaranteed break-before-make so input signals
are protected against momentary shorting.
4. Low Leakage
Leakage currents in the range of 20 pA make these multiplexers
suitable for high precision circuits.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1998
ADG506A/ADG507A–SPECIFICATIONS
(V = +10.8 V to +16.5 V, V = –10.8 V to –16.5 V unless otherwise noted)
Dual Supply
DD
SS
ADG506A
ADG507A
K Version
–40؇C to
+25؇C +85؇C
ADG506A
ADG507A
B Version
ADG506A
ADG507A
T Version
–55؇C to
+25؇C +125؇C
–40؇C to
Parameter
+25؇C
+85؇C
Units
Comments
ANALOG SWITCH
Analog Signal Range
VSS
VSS
VDD
VSS
VSS
VDD
VSS
VSS
VDD
V min
V max
Ω typ
Ω max
Ω max
Ω max
VDD
280
450
300
VDD
280
450
300
VDD
280
450
RON
–10 V ≤ VS ≤ +10 V, IDS = 1 mA; Test Circuit 1
600
400
600
400
600
400
VDD = 15 V (±10%), VSS = –15 V (±10%)
VDD = 15 V (±5%), VSS = –15 V (±5%)
300
0.6
5
RON Drift
RON Match
0.6
5
0.6
5
%/°C typ –10 V ≤ VS ≤ +10 V, IDS = 1 mA
% typ
–10 V ≤ VS ≤ +10 V, IDS = 1 mA
IS (OFF), Off Input Leakage
0.02
1
0.04
1
1
0.04
1
0.02
1
0.04
1
1
0.04
1
0.02
1
0.04
1
1
0.04
1
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
V1 = ±10 V, V2 = ϯ10 V; Test Circuit 2
50
50
50
ID (OFF), Off Output Leakage
ADG506A
V1 = ±10 V, V2 = ϯ10 V; Test Circuit 3
200
100
200
100
200
100
ADG507A
D (ON), On Channel Leakage
ADG506A
I
V1 = ±10 V, V2 = ϯ10 V; Test Circuit 4
200
100
200
100
200
100
ADG507A
1
1
1
IDIFF, Differential Off Output
Leakage (ADG507A Only)
25
25
25
nA max V1 = ±10 V, V2 = ϯ10 V; Test Circuit 5
DIGITAL CONTROL
VINH, Input High Voltage
VINL, Input Low Voltage
IINL or IINH
2.4
0.8
1
2.4
0.8
1
2.4
0.8
1
V min
V max
µA max VIN = 0 to VDD
pF max
CIN Digital Input Capacitance
8
8
8
DYNAMIC CHARACTERISTICS
tTRANSITION
1
200
300
50
200
300
50
200
300
50
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
V1 = ±10 V, V2 = +10 V; Test Circuit 6
Test Circuit 7
400
10
400
10
400
10
1
tOPEN
25
25
25
tON (EN)1
tOFF (EN)1
200
300
200
300
200
300
200
300
200
300
200
300
Test Circuit 8
400
400
400
400
400
400
Test Circuit 8
OFF Isolation
68
50
5
68
50
5
68
50
5
dB typ
dB min
pF typ
VEN = 0.8 V, RL = 1 kΩ, CL = 15 pF,
VS = 7 V rms, f = 100 kHz
VEN = 0.8 V
CS (OFF)
CD (OFF)
ADG506A
ADG507A
QINJ, Charge Injection
44
22
4
44
22
4
44
22
4
pF typ
pF typ
pC typ
VEN = 0.8 V
RS = 0 Ω, VS = 0 V; Test Circuit 9
POWER SUPPLY
IDD
0.6
20
10
0.6
20
10
0.6
20
10
mA typ
mA max
µA typ
mA max
mW typ
mW max
VIN = VINL or VlNH
VIN = VIN or VINH
1.5
0.2
28
1.5
0.2
28
1.5
0.2
28
ISS
Power Dissipation
NOTES
1Sample tested at +25°C to ensure compliance.
Specifications subject to change without notice.
REV. C
–2–
ADG506A/ADG507A
(V = +10.8 V to +16.5 V, V = GND = 0 V unless otherwise noted)
Single Supply
DD
SS
ADG506A
ADG507A
K Version
ADG506A
ADG507A
B Version
ADG506A
ADG507A
T Version
–40؇C to
+25؇C +85؇C
–40؇C to
+85؇C
–55؇C to
+25؇C +125؇C
Parameter
+25؇C
Units
Comments
ANALOG SWITCH
Analog Signal Range
VSS
VDD
500
700
0.6
5
VSS
VDD
VSS
VDD
500
700
0.6
5
VSS
VDD
VSS
VDD
500
700
0.6
5
VSS
VDD
V min
V max
Ω typ
RON
0 V ≤ VS ≤ +10 V, IDS = 0.5 mA; Test Circuit 1
1000
1000
1000
Ω max
RON Drift
RON Match
%/°C typ 0 V ≤ VS ≤ +10 V, IDS = 0.5 mA
% typ
0 V ≤ VS ≤ +10 V, IDS = 0.5 mA
IS (OFF), Off Input Leakage
0.02
1
0.02
1
0.02
1
nA typ
nA max Test Circuit 2
V1 = +10 V/0 V, V2 = 0 V/ +10 V;
50
50
50
ID (OFF), Off Output Leakage
ADG506A
ADG507A
0.04
1
1
0.04
1
1
0.04
1
1
nA typ
nA max Test Circuit 3
nA max
V1 = +10 V/0 V, V2 = 0 V/ +10 V;
200
100
200
100
200
100
ID (ON), On Channel Leakage
ADG506A
ADG507A
0.04
1
1
0.04
1
1
0.04
1
1
nA typ
nA max Test Circuit 4
nA max
V1 = +10 V/0 V, V2 = 0 V/ +10 V;
200
100
200
100
200
100
IDIFF, Differential Off Output
Leakage (ADG507A Only)
V1 = +10 V/0 V, V2 = 0 V/ +10 V;
nA max Test Circuit 5
25
25
25
DIGITAL CONTROL
V
INH, Input High Voltage
2.4
0.8
1
2.4
0.8
1
2.4
0.8
1
V min
V max
VINL, Input Low Voltage
IINL or IINH
µA max VIN = 0 to VDD
CIN Digital Input Capacitance
8
8
8
pF max
DYNAMIC CHARACTERISTICS
tTRANSITION
1
300
450
50
300
450
50
300
450
50
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
V1 = +10 V/0 V, V2 = +10 V; Test Circuit 6
600
10
600
10
600
10
1
tOPEN
Test Circuit 7
Test Circuit 8
Test Circuit 8
25
25
25
tON (EN)1
tOFF (EN)1
250
450
250
450
250
450
250
450
250
450
250
450
600
600
600
600
600
600
OFF Isolation
68
50
5
68
50
5
68
50
5
dB typ
dB min
pF typ
VEN = 0.8 V, RL = 1 kΩ, CL = 15 pF,
VS = 3.5 V rms, f = 100 kHz
VEN = 0.8 V
CS (OFF)
CD (OFF)
ADG506A
ADG507A
QINJ, Charge Injection
44
22
4
44
22
4
44
22
4
pF typ
pF typ
pC typ
VEN = 0.8 V
RS = 0 Ω, VS = 0 V; Test Circuit 9
POWER SUPPLY
IDD
0.6
10
0.6
10
0.6
10
mA typ
VIN = VINL or VlNH
1.5
25
1.5
25
1.5
25
mA max
mW typ
mW max
Power Dissipation
NOTES
1Sample tested at +25°C to ensure compliance.
Truth Table (ADG507A)
Truth Table (ADG506A)
Specifications subject to change without notice.
A2 A1 A0 EN On Switch Pair
A3 A2 A1 A0 EN On Switch
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
NONE
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
NONE
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
8
9
10
11
12
13
14
15
16
X = Don’t Care
REV. C
–3–
ADG506A/ADG507A
ABSOLUTE MAXIMUM RATINGS1
Power Dissipation (Any Package)
Up to +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature
Commercial (K Version) . . . . . . . . . . . . . . –40°C to +85°C
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C
(TA = 25°C unless otherwise noted)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 V
Analog Inputs2
Voltage at S, D . . . . . . . . . . . . . . . . . . . . . . . VSS – 2 V to VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . + 2 V or
. . . . . . . . . . . . . . . . . . . . . . 20 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 20 mA
Pulsed Current S or D
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Overvoltage at A, EN, S or D will be clamped by diodes. Current should be limited
to the Maximum Rating above.
1 ms Duration, 10% Duty Cycle . . . . . . . . . . . . . . . . 40 mA
Digital Inputs2
Voltage at A, EN . . . . . . . . . . . . . . . . . . . . . . . . . . VSS – 4 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . to VDD + 4 V or
. . . . . . . . . . . . . . . . . . . . . . 20 mA, Whichever Occurs First
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG506A/ADG507A feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATIONS
DIP, SOIC
LCCC
PLCC
D
V
V
1
2
28
27
DD
NC
NC
SS
3
4
3
1
28 27 26
26 S8
2
4
3
2
1
28 27 26
S16
S15
S14
S13
S7
25
4
25
5
6
7
8
9
S7
S15
S14
S13
S12
S11
PIN 1
IDENTIFIER
S6
24
5
S15
S14
S13
S12
S11
S10
S9
5
6
25 S7
24 S6
ADG506A
24 S6
6
23
22
21
20
19
18
17
16
15
S5
S4
S3
TOP VIEW
(Not to Scale)
23
22
21
20
S5
S4
S3
S2
ADG506A
TOP VIEW
(Not to Scale)
7
ADG506A
23
7
S5
8
S12
S11
S10
TOP VIEW
(Not to Scale)
8
22 S4
21 S3
20 S2
19 S1
9
S2
S1
EN
A0
S10 10
9
19 S1
10
11
12
13
14
S9
11
10
11
S9
GND
NC
12
13 14 15 16 17 18
NC = NO CONNECT
12
14 15 16 17 18
13
A1
A2
A3
NC = NO CONNECT
NC = NO CONNECT
DIP, SOIC, TSSOP
PLCC
LCCC
DA
V
V
1
2
28
27
DD
DB
NC
SS
3
26 S8A
4
3
1
28 27 26
2
4
3
2
1
28 27 26
S8B
S7B
S6B
S5B
S7A
25
4
25
5
6
7
8
9
S7A
S6A
S5A
S4A
S3A
S2A
S1A
S7B
PIN 1
IDENTIFIER
S7B
S6A
24
5
25 S7A
24 S6A
5
ADG507A
24
23
22
21
20
19
S6B
S5B
S4B
S3B
S2B
S1B
6
S6B
S5B
S4B
S3B
S2B
S1B
23
22
21
20
19
18
17
16
15
6
7
S5A
S4A
S3A
TOP VIEW
(Not to Scale)
ADG507A
TOP VIEW
(Not to Scale)
7
ADG507A
23
S5A
8
TOP VIEW
(Not to Scale)
S4B
S3B
S2B
8
22 S4A
21 S3A
20 S2A
19 S1A
9
S2A
S1A
EN
9
10
11
10
11
12
13
14
10
11
S1B
GND
NC
12
13 14 15 16 17 18
NC = NO CONNECT
A0
12
14 15 16 17 18
13
A1
A2
NC
NC = NO CONNECT
NC = NO CONNECT
–4–
REV. C
Typical Performance Characteristics–ADG506A/ADG507A
The multiplexers are guaranteed functional with reduced single or dual supplies down to 4.5 V.
Figure 1. RON as a Function of VD (VS): Dual Supply
Figure 4. RON as a Function of VD (VS) Single Supply
Voltage, TA = +25°C
Voltage, TA = +25°C
Figure 2. Leakage Current as a Function of Temperature
(Note: Leakage Currents Reduce as the Supply Voltages
Reduce)
Figure 5. Trigger Levels vs. Power Supply Voltage, Dual
or Single Supply, TA = +25°C
Figure 3. tTRANSITION vs. Supply Voltage: Dual and Single
Supplies, TA = + 25°C (Note: For VDD and /VSS/ < 10 V; V1 =
Figure 6. IDD vs. Supply Voltage: Dual or Single Supply,
TA = +25°C
VDD/VSS, V2 = VSS/VDD. See Test Circuit 6)
REV. C
–5–
ADG506A/ADG507A
–Test Circuits
Note: All Digital Input Signal Rise and Fall Times Measured from 10% to 90% of 3 V. tR = tF = 20 ns.
Test Circuit 1. RON
Test Circuit 2. IS (OFF)
Test Circuit 3. ID (OFF)
Test Circuit 5. IDIFF
Test Circuit 4. ID (ON)
Test Circuit 6. Switching Time of Multiplexer, tTRANSITION
Test Circuit 7. Break-Before-Make Delay, tOPEN
–6–
REV. C
ADG506A/ADG507A
Test Circuit 8. Enable Delay, tON (EN), tOFF (EN)
Test Circuit 9. Charge Injection
The AD7580 is a 10-bit successive approximation ADC, which
has an on-chip sample-hold amplifier and provides a conversion
result in 20 µs. The ADC has differential analog inputs and is
configured in the application circuit for a span of 2.5 V over a
common-mode range 0 V to + 5 V. Wider common-mode ranges
can be accommodated. See the AD7579/AD7580 data sheet for
more details. The complete system operates from +12 V (+10%)
and +5 V supplies. The analog input signals to the ADG507A
contain information such as temperature, pressure, speed etc.
SINGLE SUPPLY AUTOMOTIVE APPLICATION
The excellent performance of the multiplexers under single
supply conditions makes the ADG506A/ADG507A suitable in
applications such as automotive and disc drives where only
positive power supply voltages are normally available. The fol-
lowing application circuit shows the ADG507A connected as an
8-channel differential multiplexer in an automotive, data acqui-
sition application circuit.
Figure 7. ADG507A in a Single Supply Automotive Data Acquisition Application
–7–
REV. C
ADG506A/ADG507A
TERMINOLOGY
tOFF (EN)
Delay time between the 50% and 10% points of
the digital input and switch “OFF” condition
RON
Ohmic resistance between terminals D and S
R
ON Match Difference between the RON of any two channels
tTRANSITION Delay time between the 50% and 90% points of
the digital inputs and switch “ON” condition
when switching from one address state to
another
RON Drift
IS (OFF)
Change in RON versus temperature
Source terminal leakage current when the switch
is off
ID (OFF)
Drain terminal leakage current when the switch
is off
tOPEN
“OFF” time measured between 50% points of
both switches when switching from one address
state to another
Maximum input voltage for Logic “0”
Minimum input voltage for Logic “1”
Input current of the digital input
Most positive voltage supply
Most negative voltage supply
Positive supply current
Negative supply current
I
D (ON)
Leakage current that flows from the closed switch
into the body
VINL
VINH
IINL (IINH
VDD
VS (VD)
CS (OFF)
CD (OFF)
CIN
Analog voltage on terminal S or D
Channel input capacitance for “OFF” condition
Channel output capacitance for “OFF” condition
Digital input capacitance
)
VSS
IDD
ISS
t
ON (EN)
Delay time between the 50% and 90% points of
the digital input and switch “ON” condition
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Cerdip (Suffix Q)
28-Lead Plastic DIP (Suffix N)
1.490 (37.84) MAX
0.550 (13.97)
0.53 (13.47)
0.525 (13.33)
0.515 (13.08)
1.45(36.83)
1.44 (36.58)
0.16 (4.07)
0.14 (3.56)
0.18(4.57)
MAX
0.606 (15.4)
0.594 (15.09)
0.62 (15.74)
0.59 (14.93)
GLASS
SEALANT
0.06 (1.52)
0.05 (1.27)
0.22 (5.59)
MAX
0.2
(5.08)
MAX
0.125
(3.175)
MIN
15؇
0
0.012 (0.305)
0.008 (0.203)
0.065 (1.66)
0.045 (1.15)
0.105 (2.67)
0.095 (2.42)
0.020 (0.508)
0.015 (0.381)
0.175 (4.45)
0.12 (3.05)
0.012 (0.305)
0.008 (0.203)
0.11 (2.79)
0.099 (2.28)
0.02 (0.5)
0.016 (0.406)
15°
0°
LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH
LEADS ARE SOLDER OR TIN PLATED KOVAR OR ALLOY 42
LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH
LEADS ARE SOLDER OR TIN PLATED KOVAR OR ALLOY 42
28-Lead SOIC (Suffix R)
28-Lead TSSOP (Suffix RU)
0.386 (9.80)
0.378 (9.60)
0.7125 (18.10)
0.6969 (17.70)
28
15
14
28
15
14
1
1
PIN 1
0.006 (0.15)
0.002 (0.05)
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
x 45°
0.0098 (0.25)
0.0433
(1.10)
MAX
0.028 (0.70)
0.020 (0.50)
8°
0°
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0256 (0.65)
BSC
0.0118 (0.30)
0.0075 (0.19)
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
28-Terminal Leadless Ceramic Chip Carrier (Suffix E)
28-Terminal Plastic Leaded Chip Carrier (Suffix P)
0.300 (7.62)
4
26
25
BSC
0.075
(1.91)
REF
0.050 ؎0.005
01.27 ؎0.13
5
0.100 (2.54)
0.064 (1.63)
PIN 1
IDENTIFIER
0.150
(3.51)
BSC
0.015 (0.38)
MIN
0.021 (0.533)
0.013 (0.331)
0.430 (10.5)
0.390 (9.9)
TOP VIEW
(PINS DOWN)
0.095 (2.41)
0.075 (1.90)
4
26
2
5
28
5
0.032 (0.812)
0.026 (0.661)
0.028 (0.71)
0.022 (0.56)
0.458 (11.63)
0.442 (11.23)
SQ
1
11
12
19
18
0.458
(11.63)
MAX
0.011 (0.28)
0.007 (0.18)
R TYP
BOTTOM
VIEW
0.120 (3.04)
0.090 (2.29)
0.456 (11.582)
0.450 (11.430)
0.050
(1.27)
BSC
SQ
SQ
SQ
0.498 (12.57)
0.485 (12.32)
0.075
(1.91)
REF
12
19
18
0.180 (4.51)
0.165 (4.20)
11
45° TYP
0.200
(5.08)
BSC
0.055 (1.40)
0.045 (1.14)
0.088 (2.24)
0.054 (1.37)
–8–
REV. C
相关型号：
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