ADF4355 [ADI]
Microwave Wideband Synthesizer with Integrated VCO;
| 型号： | ADF4355 |
| 厂家： | 
ADI |
| 描述： | Microwave Wideband Synthesizer with Integrated VCO |
| 文件： | 总35页 (文件大小：848K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Microwave Wideband Synthesizer
with Integrated VCO
Data Sheet
ADF4355
FEATURES
GENERAL DESCRIPTION
RF output frequency range: 54 MHz to 6800 MHz
Fractional-N synthesizer and integer-N synthesizer
High resolution 38-bit modulus
Low phase noise, voltage controlled oscillator (VCO)
Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output
Analog and digital power supplies: 3.3 V
Charge pump and VCO power supplies: 5.0 V typical
Logic compatibility: 1.8 V
Programmable dual modulus prescaler of 4/5 or 8/9
Programmable output power level
RF output mute function
3-wire serial interface
Analog and digital lock detect
The ADF4355 allows implementation of fractional-N or
integer-N phase-locked loop (PLL) frequency synthesizers
when used with an external loop filter and an external reference
frequency. A series of frequency dividers permits operation
from 54 MHz to 6800 MHz.
The ADF4355 has an integrated VCO with a fundamental
output frequency ranging from 3400 MHz to 6800 MHz. In
addition, the VCO frequency is connected to divide by 1, 2, 4, 8,
16, 32, or 64 circuits that allow the user to generate radio frequency
(RF) output frequencies as low as 54 MHz. For applications that
require isolation, the RF output stage can be muted. The mute
function is both pin and software controllable.
Control of all on-chip registers is through a simple 3-wire interface.
The ADF4355 operates with analog and digital power supplies
ranging from 3.15 V to 3.45 V, with charge pump and VCO
supplies from 4.75 V to 5.25 V. The ADF4355 also contains
hardware and software power-down modes.
APPLICATIONS
Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM,
PCS, DCS, DECT)
Point to point/point to multipoint microwave links
Satellites/VSATs
Test equipment/instrumentation
Clock generation
FUNCTIONAL BLOCK DIAGRAM
AV
DV
V
R
V
VCO
V
AV
DD
CE
DD
DD
P
SET
RF
MULTIPLEXER
MUXOUT
10-BIT R
COUNTER
÷2
DIVIDER
REF
REF
A
B
IN
×2
DOUBLER
LOCK
DETECT
C
1
IN
REG
REG
C
2
CLK
DATA
LE
DATA REGISTER
FUNCTION
LATCH
CHARGE
PUMP
CP
OUT
PHASE
COMPARATOR
V
V
TUNE
REF
V
VCO
CORE
BIAS
INTEGER
REGISTER
FRACTION
REGISTER
MODULUS
REGISTER
V
REGVCO
RF
RF
A+
A–
OUT
OUT
1/2/4/8
16/32/64
OUTPUT
STAGE
THIRD-ORDER
÷
FRACTIONAL
INTERPOLATOR
PDB
RF
RF
B+
B–
OUTPUT
STAGE
OUT
N COUNTER
RF
OUT
MULTIPLEXER
SD
ADF4355
A
CP
A
GNDVCO
A
GND
GND
GND
GNDRF
Figure 1.
Rev. B
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ADF4355
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Register 4 ..................................................................................... 22
Register 5 ..................................................................................... 23
Register 6 ..................................................................................... 24
Register 7 ..................................................................................... 26
Register 8 ..................................................................................... 27
Register 9 ..................................................................................... 27
Register 10................................................................................... 28
Register 11................................................................................... 28
Register 12................................................................................... 29
Register Initialization Sequence ............................................... 29
Frequency Update Sequence..................................................... 29
RF Synthesizer—A Worked Example ...................................... 30
Reference Doubler and Reference Divider ............................. 30
Spurious Optimization and Fast Lock..................................... 30
Optimizing Jitter......................................................................... 31
Spur Mechanisms ....................................................................... 31
Lock Time.................................................................................... 31
Applications Information .............................................................. 32
Direct Conversion Modulator .................................................. 32
Power Supplies............................................................................ 33
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
Transistor Count........................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 9
Circuit Description......................................................................... 12
Reference Input Section............................................................. 12
RF N Divider............................................................................... 12
Phase Frequency Detector (PFD) and Charge Pump............ 13
MUXOUT and Lock Detect...................................................... 13
Input Shift Registers................................................................... 13
Program Modes .......................................................................... 13
VCO.............................................................................................. 14
Output Stage................................................................................ 14
Register Maps.................................................................................. 16
Register 0 ..................................................................................... 18
Register 1 ..................................................................................... 19
Register 2 ..................................................................................... 20
Register 3 ..................................................................................... 21
Printed Circuit Board (PCB) Design Guidelines for a Chip-
Scale Package .............................................................................. 33
Output Matching........................................................................ 34
Outline Dimensions....................................................................... 35
Ordering Guide .......................................................................... 35
REVISION HISTORY
8/2017—Rev. A to Rev. B
Changes to Phase Resync Section ................................................ 21
Changes to Negative Bleed Section.............................................. 24
Change to Figure 36 ....................................................................... 24
Change to Reserved Section.......................................................... 25
Changes to Loss of Lock (LOL) Mode Section........................... 26
Changes to ADC Clock Divider (ADC_CLK_DIV) Section ... 28
Changes to Register Initialization Sequence Section and
Changes to Frequency Update Sequence Section ...................... 29
Changes to RF Synthesizer—A Worked Example Section........ 30
Change to Figure 44 ....................................................................... 32
Changes to Power Supplies Section and Figure 45 .................... 33
Changes to Frequency Update Sequence Section ...................... 29
Updated Outline Dimensions....................................................... 35
Changes to Ordering Guide .......................................................... 35
3/2016—Rev. 0 to Rev. A
Added Doubler Enabled Parameter, Table 1................................. 3
Changes to Table 2............................................................................ 5
Deleted VP, VVCO to AVDD Parameter, Table 3........................ 6
Changes to Table 4............................................................................ 7
Changes to Reference Input Section and INT, FRAC1, FRAC2,
MOD1, MOD2, and R Counter Relationship Section Title...... 12
Changes to Figure 28...................................................................... 16
Changes to Automatic Calibration (Autocalibration) Section
and Prescaler Section ..................................................................... 18
4/2015—Revision 0: Initial Version
Rev. B | Page 2 of 35
Data Sheet
ADF4355
SPECIFICATIONS
AVDD = DVDD = VRF = 3.3 V 5%, 4.75 V ≤ VP = VVCO ≤ 5.25 V, A GND = CPGND = AGNDVCO = SDGND = AGNDRF = 0 V, RSET = 5.1 kΩ,
dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
REFINA/REFINB CHARACTERISTICS
Input Frequency
For f < 10 MHz, ensure slew rate > 21V/µs
Single-Ended Mode
Differential Mode
Doubler Enabled
10
10
250
600
100
MHz
MHz
MHz
Doubler is set in Register 4, Bit DB26
Input Sensitivity
Single-Ended Mode
0.4
0.4
AVDD
1.8
V p-p
V p-p
REFINA biased at AVDD/2; ac coupling
ensures AVDD/2 bias
LVDS and LVPECL compatible,
REFINA/REFINB biased at 2.1 V;
ac coupling ensures 2.1 V bias
Differential Mode
Input Capacitance
Single-Ended Mode
Differential Mode
Input Current
6.9
1.4
pF
pF
µA
µA
MHz
60
250
125
Single-ended reference programmed
Differential reference programmed
Phase Detector Frequency
CHARGE PUMP (CP)
Charge Pump Current, Sink/Source
High Value
ICP
RSET = 5.1 kΩ
4.8
0.3
5.1
3
3
1.5
mA
mA
kΩ
%
%
%
Low Value
RSET Range
Fixed
Current Matching
0.5 V ≤ VCP1 ≤ VP − 0.5 V
0.5 V ≤ VCP1 ≤ VP − 0.5 V
VCP1 = 2.5 V
1
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
Input High Voltage
Input Low Voltage
Input Current
Input Capacitance
LOGIC OUTPUTS
Output High Voltage
VINH
VINL
IINH/IINL
CIN
1.5
V
V
µA
pF
0.6
1
3.0
1.8
VOH
DVDD − 0.4
1.5
V
V
1.8 V output selected
IOL2 = 500 µA
Output High Current
Output Low Voltage
IOH
VOL
500
0.4
µA
V
POWER SUPPLIES
Analog Power
AVDD
3.15
4.75
3.45
V
Digital Power and RF Supply Voltage
Charge Pump and VCO Voltage
Charge Pump Supply Power Current
DVDD, VRF
VP, VVCO
IP
AVDD
5.0
8
Voltages must equal AVDD
VP must equal VVCO
5.25
9
V
Digital Power Supply Current +
Analog Power Supply Curent3
DIDD, AIDD
62
69
mA
Output Dividers
Supply Current
6 to 36
70
mA
mA
Each output divide by 2 consumes 6 mA
IVCO
85
RFOUTA /RFOUT
B
Supply Current
16/20/ 20/35/ mA
RF output stage is programmable;
RFOUTB+/RFOUTB− powered off
I
RFOUT x±
42/55
50/70
Low Power Sleep Mode
500
1000
µA
µA
Hardware power-down
Software power-down
Rev. B | Page 3 of 35
ADF4355
Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
RF OUTPUT CHARACTERISTICS
VCO Frequency Range
RF Output Frequency
VCO Sensitivity
Frequency Pushing (Open-Loop)
Frequency Pulling (Open-Loop)
Harmonic Content
3400
53.125
6800
6800
MHz
MHz
MHz/V
MHz/V
MHz
Fundamental VCO range
KV
15
15
0.5
Voltage standing wave ratio (VSWR) = 2:1
Second
−27
−22
−20
−12
+8
+3
1
dBc
dBc
dBc
dBc
dBm
dBm
dB
Fundamental VCO output (RFOUTA+)
Divided VCO output (RFOUTA+)
Fundamental VCO output (RFOUTA+)
Divided VCO output (RFOUTA+)
RFOUTA+ = 1 GHz
RFOUTA+/RFOUTA− = 4.4 GHz
RFOUTA+/RFOUTA− = 4.4 GHz
RFOUTA+/RFOUTA− = 1 GHz to 4.4 GHz
Third
RF Output Power4
RF Output Power Variation
RF Output Power Variation (over
Frequency)
3
dB
Level of Signal with RF Output
Disabled
−60
−30
dBm
dBm
RFOUTA+/RFOUTA− = 1 GHz, VCO = 4 GHz
RFOUTA+/RFOUTA− = 4.4 GHz, VCO = 4.4 GHz
NOISE CHARACTERISTICS
Fundamental VCO Phase Noise
Performance
VCO noise in open-loop conditions
−116
−136
−138
−155
−113
−133
−135
−153
−110
−130
−132
−150
dBc/Hz 100 kHz offset from 3.4 GHz carrier
dBc/Hz 800 kHz offset from 3.4 GHz carrier
dBc/Hz 1 MHz offset from 3.4 GHz carrier
dBc/Hz 10 MHz offset from 3.4 GHz carrier
dBc/Hz 100 kHz offset from 5.0 GHz carrier
dBc/Hz 800 kHz offset from 5.0 GHz carrier
dBc/Hz 1 MHz offset from 5.0 GHz carrier
dBc/Hz 10 MHz offset from 5.0 GHz carrier
dBc/Hz 100 kHz offset from 6.8 GHz carrier
dBc/Hz 800 kHz offset from 6.8 GHz carrier
dBc/Hz 1 MHz offset from 6.8 GHz carrier
dBc/Hz 10 MHz offset from 6.8 GHz carrier
Normalized In-Band Phase Noise Floor
Fractional Channel5
−221
−223
−116
150
dBc/Hz
dBc/Hz
Integer Channel6
7
Normalized 1/f Noise, PN1_f
dBc/Hz 10 kHz offset; normalized to 1 GHz
fs
Integrated RMS Jitter
Spurious Signals due to Phase
−80
dBc
Frequency Detector (PFD) Frequency
1 VCP is the voltage at the CPOUT pin.
2 IOL is the output low current.
3 TA = 25°C; AVDD = DVDD = VRF = 3.3 V; VVCO = VP = 5.0 V; prescaler = 4/5; fREF = 122.88 MHz; fPFD = 61.44 MHz; and fRF = 1650 MHz.
IN
4 RF output power using the EV-ADF4355SD1Z evaluation board measured into a spectrum analyzer, with board and cable losses de-embedded. The EV-ADF4355SD1Z
RF outputs are pulled up externally using a 4.7 nH inductor. Unused RF output pins are terminated in 50 Ω.
5 Use this figure to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:
−221 + 10log(fPFD) + 20logN. The value given is the lowest noise mode for the fractional channel.
6 Use this figure to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:
−223 + 10log(fPFD) + 20logN. The value given is the lowest noise mode for the integer channel.
7 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF)
and at a frequency offset (f) is given by PN = P1_f + 10log(10 kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in the
ADIsimPLL design tool.
Rev. B | Page 4 of 35
Data Sheet
ADF4355
TIMING CHARACTERISTICS
AVDD = DVDD =VRF = 3.3 V ꢀ%, 4.7ꢀ V ≤ VP = VVCO ≤ ꢀ.2ꢀ V, AGND = CPGND = AGNDVCO = SDGND = AGNDRF = 0 V, RSET = ꢀ.1 kΩ,
dBm referred to ꢀ0 Ω, TA = TMIN to TMAX, unless otherwise noted.
Table 2. Write Timing
Parameter
Limit
50
10
5
Unit
Description
fCLK
t1
t2
t3
t4
t5
t6
t7
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
Serial peripheral interface CLK frequency
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
5
10
10
5
20 or (2/fPFD), whichever is longer ns min
Write Timing Diagram
t4
t5
CLK
t2
t3
DB3
DB2
(CONTROL BIT C3)
DB1
DB0 (LSB)
(CONTROL BIT C1)
DB31 (MSB)
DB30
DATA
LE
(CONTROL BIT C4)
(CONTROL BIT C2)
t7
t1
t6
Figure 2. Write Timing Diagram
Rev. B | Page 5 of 35
ADF4355
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Stresses at or above those listed under Absolute Maximum
TA = 25°C, unless otherwise noted.
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 3.
Parameter
VRF, DVDD, AVDD to GND1
Rating
−0.3 V to +3.6 V
−0.3 V to +0.3 V
−0.3 V to +5.8 V
−0.3 V to VP + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
2.1 V
AVDD to DVDD
VP, VVCO to GND1
CPOUT to GND1
The ADF4355 is a high performance RF integrated circuit with
an ESD rating of 2500 V and is ESD sensitive. Take proper
precautions for handling and assembly.
Digital Input/Output Voltage to GND1
Analog Input/Output Voltage to GND1
REFINA, REFINB to GND1
REFINA to REFINB
TRANSISTOR COUNT
The transistor count for the ADF4355 is 103,665 (CMOS) and
3214 (bipolar).
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
θJA, Thermal Impedance Pad Soldered
to GND1
−40°C to +85°C
−65°C to +125°C
150°C
ESD CAUTION
27.3°C/W
Reflow Soldering
Peak Temperature
260°C
40 sec
Time at Peak Temperature
Electrostatic Discharge (ESD)
Charged Device Model
Human Body Model
1000 V
2500 V
1 GND = AGND = SDGND = AGNDRF = AGNDVCO = CPGND = 0 V.
Rev. B | Page 6 of 35
Data Sheet
ADF4355
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
V
V
R
A
V
CLK
DATA
LE
BIAS
REF
SET
ADF4355
TOP VIEW
(Not to Scale)
CE
GNDVCO
AV
TUNE
DD
V
A
V
V
P
REGVCO
CP
CP
GNDVCO
VCO
OUT
GND
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO A
.
GND
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1
CLK
DATA
LE
Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
Serial Data Input. The serial data is loaded most significant bit (MSB) first with the four least significant bits (LSBs)
as the control bits. This input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register
selected by the four LSBs.
2
3
4
CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode. A
logic high on this pin powers up the device, depending on the status of the power-down bits.
5, 16
AVDD
VP
Analog Power Supply. This pin ranges from 3.15 V to 3.45 V. Connect decoupling capacitors to the analog ground
plane as close to this pin as possible. AVDD must have the same value as DVDD
.
6
7
Charge Pump Power Supply. VP must have the same value as VVCO. Connect decoupling capacitors to the ground
plane as close to VP as possible.
Charge Pump Output. When enabled, this output provides ICP to the external loop filter. The output of the loop
filter is connected to VTUNE to drive the internal VCO.
CPOUT
8
9
10
CPGND
AGND
VRF
Charge Pump Ground. This output is the ground return pin for CPOUT
Analog Ground. Ground return pin for AVDD
Power Supply for the RF Output. Connect decoupling capacitors to the analog ground plane as close to this pin
as possible. VRF must have the same value as AVDD
.
.
.
11
12
RFOUTA+
RFOUTA−
VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is available.
Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided down
version is available.
13
14
AGNDRF
RFOUTB+
RF Output Stage Ground. Ground return pins for the RF output stage.
Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a divided down version
is available.
15
17
RFOUTB−
VVCO
Complementary Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a
divided down version is available.
Power Supply for the VCO. The voltage on this pin ranges from 4.75 V to 5.25 V. Connect decoupling capacitors to
the analog ground plane as close to this pin as possible.
18, 21
19
AGNDVCO
VREGVCO
VCO Ground. Ground return path for the VCO.
VCO Compensation Node. Connect decoupling capacitors to the ground plane as close to this pin as possible.
Connect VREGVCO directly to VVCO
.
20
VTUNE
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CPOUT
output voltage. The capacitance at this pin (VTUNE input capacitance) is 9 pF.
22
23
RSET
VREF
Bias Current Resistor. Connecting a resistor between this pin and ground sets the charge pump output current.
Internal Compensation Node. DC biased at half the tuning range. Connect decoupling capacitors to the ground
plane as close to this pin as possible.
24
VBIAS
Reference Voltage. Connect a 100 nF decoupling capacitor to the ground plane as close to this pin as possible.
Rev. B | Page 7 of 35
ADF4355
Data Sheet
Pin No. Mnemonic
Description
25, 32
CREG1, CREG
2
Outputs from the LDO Regulator. CREG1 and CREG2 are the supply voltages to the digital circuits and have a
nominal voltage of 1.8 V. Decoupling capacitors of 100 nF connected to AGND are required for these pins.
26
27
PDBRF
DVDD
RF Power-Down. A logic low on this pin mutes the RF outputs. This mute function is also software controllable.
Digital Power Supply. This pin must be at the same voltage as AVDD. Place decoupling capacitors to the ground
plane as close to this pin as possible.
28
29
30
REFINB
REFINA
MUXOUT
Complementary Reference Input. If unused, ac-couple this pin to AGND
Reference Input.
Multiplexer Output. The multiplexer output allows the digital lock detect, the analog lock detect, scaled RF, or the
scaled reference frequency to be externally accessible.
.
31
SDGND
EP
Digital Σ-Δ Modulator Ground. SDGND is the ground return path for the Σ-Δ modulator.
Exposed Pad. The exposed pad must be connected to AGND
.
Rev. B | Page 8 of 35
Data Sheet
ADF4355
TYPICAL PERFORMANCE CHARACTERISTICS
–50
–50
–70
÷1
÷2
÷4
÷8
÷16
÷32
÷64
–70
–90
–90
–110
–130
–150
–170
–110
–130
–150
–170
1k
10k
100k
1M
10M
100M
100M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 4. Open-Loop VCO Phase Noise, 3.4 GHz
Figure 7. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and Dividers,
VCO = 3.4 GHz, PFD = 61.44 MHz, Loop Bandwidth = 20 kHz
–50
–50
÷1
÷2
÷4
÷8
÷16
÷32
÷64
–70
–90
–70
–90
–110
–130
–150
–170
–110
–130
–150
–170
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 5. Open-Loop VCO Phase Noise, 5.0 GHz
Figure 8. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and Dividers,
VCO = 5.0 GHz, PFD = 61.44 MHz, Loop Bandwidth = 20 kHz
–50
–70
–50
÷1
÷2
÷4
÷8
÷16
÷32
÷64
–70
–90
–90
–110
–130
–150
–170
–110
–130
–150
–170
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 6. Open-Loop VCO Phase Noise, 6.8 GHz
Figure 9. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and Dividers,
VCO = 6.8 GHz, PFD = 61.44 MHz, Loop Bandwidth = 20 kHz
Rev. B | Page 9 of 35
ADF4355
Data Sheet
10
9
8
7
6
–50
÷1
–40°C
+25°C
+85°C
÷2
–70
5
4
3
2
1
–90
–110
–130
–150
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–170
1k
1
2
3
4
5
6
7
10k
100k
1M
10M
100M
FREQUENCY (GHz)
FREQUENCY (Hz)
Figure 10. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and
Divide by 2, VCO = 3.4 GHz, PFD = 61.44 MHz, Loop Bandwidth = 2 kHz
Figure 13. Output Power vs. Frequency, RFOUTA+/RFOUTA− (7.5 nH Inductors,
10 pF Bypass Capacitors, Board Losses De-Embedded)
–50
÷1
0
SECOND HARMONIC
THIRD HARMONIC
÷2
–5
–70
–10
–15
–20
–25
–30
–35
–40
–45
–50
–90
–110
–130
–150
–170
1k
10k
100k
1M
10M
100M
1
2
3
4
5
6
7
FREQUENCY (Hz)
FREQUENCY (GHz)
Figure 11. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and
Divide by 2, VCO = 5.0 GHz, PFD = 61.44 MHz, Loop Bandwidth = 2 kHz
Figure 14. RFOUTA+/RFOUTA− Harmonics vs. Frequency (7.5 nH Inductors,
10 pF Bypass Capacitors, Board Losses De-Embedded)
–50
÷1
10
8
÷2
–70
6
4
–90
–110
–130
–150
–170
2
0
–2
–4
–6
–8
–10
1k
10k
100k
1M
10M
100M
0
1
2
3
4
5
6
7
FREQUENCY (Hz)
FREQUENCY (GHz)
Figure 12. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and
Divide by 2, VCO = 6.8 GHz, PFD = 61.44 MHz, Loop Bandwidth = 2 kHz
Figure 15. RFOUTA+/RFOUTA− Power vs. Frequency (100 nH Inductors, 100 pF
Bypass Capacitors, Board Measurement)
Rev. B | Page 10 of 35
Data Sheet
ADF4355
0.50
–80
–90
RMS JITTER (ps) 1kHz TO 20MHz
RMS JITTER (ps) 12kHz TO 20MHz
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
–100
–110
–120
–130
–140
–150
–160
0.8
1.8
2.8
3.8
4.8
5.8
6.8
1k
10k
100k
1M
10M
100M
OUTPUT FREQUENCY (GHz)
FREQUENCY (Hz)
Figure 19. Fractional-N Spur Performance, W-CDMA Band, RFOUTA+ =
2113.5 MHz, REFIN = 122.88 MHz, PFD = 61.44 MHz, Output Divide by 2
Selected, Loop Filter Bandwidth = 20 kHz, Channel Spacing = 20 kHz
Figure 16. RMS Jitter vs. Output Frequency, PFD Frequency = 61.44 MHz,
Loop Filter = 20 kHz
–80
–50
PFD = 15.36MHz
PFD = 30.72MHz
PFD = 61.44MHz
–60
–90
–100
–110
–120
–130
–140
–150
–160
–70
–80
–90
–100
–110
1k
10k
100k
1M
10M
100M
0
1
2
3
4
5
6
7
FREQUENCY (Hz)
RF
A+/RF
A– OUTPUT FREQUENCY (GHz)
OUT
OUT
Figure 17. PFD Spur Amplitude vs. RFOUTA+/RFOUTA− Output Frequency,
PFD = 15.36 MHz, PFD = 30.72 MHz, PFD = 61.44 MHz, Loop Filter = 20 kHz
Figure 20. Fractional-N Spur Performance, RFOUTA+ = 2.591 GHz,
REFIN = 122.88 MHz, PFD = 61.44 MHz, Output Divide-by-2 Selected,
Loop Filter Bandwidth = 20 kHz, Channel Spacing = 20 kHz
–80
–90
4.65
4.60
4.55
4.50
4.45
–100
–110
–120
–130
–140
–150
–160
1
4.40
4.35
4.30
4.25
4.20
4.15
1k
10k
100k
1M
10M
100M
–1
0
1
2
3
4
TIME (ms)
FREQUENCY (Hz)
Figure 18. Fractional-N Spur Performance, GSM1800 Band, RFOUTA+ =
1550.2 MHz, REFIN = 122.88 MHz, PFD = 61.44 MHz, Output Divide by 4
Selected, Loop Filter Bandwidth = 20 kHz, Channel Spacing = 20 kHz
Figure 21. Lock Time for 250 MHz Jump from 4150 MHz to 4400 MHz,
Loop Bandwidth = 20 kHz
Rev. B | Page 11 of 35
ADF4355
Data Sheet
CIRCUIT DESCRIPTION
INT, FRAC1, FRAC2, MOD1, MOD2, and R Counter
Relationship
REFERENCE INPUT SECTION
Figure 22 shows the reference input stage. The reference input
can accept both single-ended and differential signals. Use the
reference mode bit (Register 4, Bit DB9) to select the signal. To
use a differential signal on the reference input, program this bit
high. In this case, SW1 and SW2 are open, SW3 and SW4 are
closed, and the current source that drives the differential pair of
transistors switches on. The differential signal buffers and provides
an emitter-coupled logic (ECL) to the CMOS converter. When a
single-ended signal is used as the reference, program Bit DB9
in Register 4 to 0. Connect the single-ended reference signal to
REFINA. In this case, SW1 and SW2 are closed, SW3 and SW4
are open, and the current source that drives the differential pair
of transistors switches off.
The INT, FRAC1, FRAC2, MOD1, and MOD2 values, in
conjunction with the R counter, make it possible to generate
output frequencies spaced by fractions of the PFD frequency
(fPFD). For more information, see the RF Synthesizer—A Worked
Example section.
Calculate the RF VCO frequency (VCOOUT) by
VCOOUT = fPFD × N
where:
(1)
VCOOUT is the output frequency of the VCO (without using the
output divider).
f
PFD is the frequency of the phase frequency detector.
N is the desired value of the feedback counter, N.
Calculate fPFD by
REFERENCE
INPUT MODE
f
PFD = REFIN × [(1 + D)/(R × (1 + T))]
(2)
85kꢀ
where:
SW2
BUFFER
SW1
REFIN is the reference input frequency.
D is the REFIN doubler bit.
R is the preset divide ratio of the binary 10-bit programmable
reference counter (1 to 1023).
SW3
TO
R COUNTER
MULTIPLEXER
T is the REFIN divide by 2 bit (0 or 1).
AV
DD
N comprises
ECL TO CMOS
CONVERTER
FRAC2
MOD2
MOD1
FRAC1
REF
REF
A
IN
N INT
(3)
where:
B
IN
INT is the 16-bit integer value (23 to 32,767 for the 4/5
prescaler, 75 to 65,535 for the 8/9 prescaler).
2.5kΩ
2.5kΩ
SW4
FRAC1 is the numerator of the primary modulus (0 to 16,777,215).
FRAC2 is the numerator of the 14-bit auxiliary modulus
(0 to 16,383).
BIAS
GENERATOR
Figure 22. Reference Input Stage
MOD2 is the programmable, 14-bit auxiliary fractional
RF N DIVIDER
modulus (2 to 16,383).
MOD1 is a 24-bit primary modulus with a fixed value of 224 =
16,777,216.
The RF N divider allows a division ratio in the PLL feedback
path. Determine the division ratio by the INT, FRAC1, FRAC2,
and MOD2 values that this divider comprises.
Equation 3 results in a very fine frequency resolution with no
residual frequency error. To apply this formula, take the
following steps:
FRAC2
MOD2
RF N COUNTER
N = INT +
FRAC1 +
MOD1
1. Calculate N by dividing VCOOUT/fPFD
.
FROM
VCO OUTPUT/
OUTPUT DIVIDERS
TO PFD
2. The integer value of this number forms INT.
3. Subtract the INT value from the full N value.
4. Multiply the remainder by 224.
5. The integer value of this number forms FRAC1.
6. Calculate MOD2 based on the channel spacing (fCHSP) by
N COUNTER
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
INT
FRAC1
REGISTER REGISTER
FRAC2
VALUE
MOD2
VALUE
MOD2 = fPFD/GCD(fPFD, fCHSP
)
(4)
where:
GCD(fPFD, fCHSP) is the greatest common divider of the PFD
frequency and the channel spacing frequency.
Figure 23. RF N Divider
f
CHSP is the desired channel spacing frequency.
Rev. B | Page 12 of 35
Data Sheet
ADF4355
DV
DD
7. Calculate FRAC2 by the following equation:
FRAC2 = [(N − INT) × 224 − FRAC1)] × MOD2
(5)
(6)
THREE-STATE OUTPUT
DV
The FRAC2 and MOD2 fraction results in outputs with zero
frequency error for channel spacings when
DD
SD
GND
f
PFD/GCD(fPFD/fCHSP) < 16,383
where:
PFD is the frequency of the phase frequency detector.
GCD is a greatest common denominator function.
CHSP is the desired channel spacing frequency.
R DIVIDER OUTPUT
N DIVIDER OUTPUT
MUX
CONTROL
MUXOUT
ANALOG LOCK DETECT
f
DIGITAL LOCK DETECT
RESERVED
f
If zero frequency error is not required, the MOD1 and MOD2
denominators operate together to create a 38-bit resolution
modulus.
SD
GND
Figure 25. MUXOUT Block Diagram
INT N Mode
INPUT SHIFT REGISTERS
When FRAC1 and FRAC2 = 0, the synthesizer operates in
integer-N mode.
The ADF4355 digital section includes a 10-bit R counter, a
16-bit RF integer-N counter, a 24-bit FRAC1 counter, a 14-bit
auxiliary fractional counter, and a 14-bit auxiliary modulus
counter. Data clocks into the 32-bit shift register on each rising
edge of CLK. The data clocks in MSB first. Data transfers from
the shift register to one of 12 latches on the rising edge of LE.
The state of the four control bits (C4, C3, C2, and C1) in the
shift register determines the destination latch. As shown in
Figure 2, the four least significant bits (LSBs) are DB3, DB2,
DB1, and DB0. The truth table for these bits is shown in Table 5.
Figure 28 and Figure 29 summarize the programing of the latches.
R Counter
The 10-bit R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock to
the PFD. Division ratios from 1 to 1023 are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 24 is a simplified schematic
of the PFD. The PFD includes a fixed delay element that sets the
width of the antibacklash pulse. This pulse ensures that there is
no dead zone in the PFD transfer function and provides a
consistent reference spur level. Set the phase detector polarity to
positive on this device because of the positive tuning of the VCO.
Table 5. Truth Table for the C4, C3, C2, and C1 Control Bits
Control Bits
C4
0
0
0
0
0
0
0
0
1
1
1
1
1
C3
0
0
0
0
1
1
1
1
0
0
0
0
1
C2
0
0
1
1
0
0
1
1
0
0
1
1
0
C1
0
1
0
1
0
1
0
1
0
1
0
1
0
Register
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
Register 8
Register 9
Register 10
Register 11
Register 12
UP
HIGH
D1
Q1
U1
CLR1
+IN
CHARGE
PUMP
CP
U3
DELAY
DOWN
CLR2
D2 Q2
HIGH
U2
PROGRAM MODES
–IN
Table 5 and Figure 28 through Figure 42 show the program
modes that must be set up in the ADF4355.
Figure 24. PFD Simplified Schematic
MUXOUT AND LOCK DETECT
The following settings in the ADF4355 are double buffered: main
fractional value (FRAC1), auxiliary modulus value (MOD2),
auxiliary fractional value (FRAC2), reference doubler, reference
divide by 2 (RDIV2), R counter value, and charge pump current
setting. Two events must occur before the ADF4355 uses a new
value for any of the double buffered settings. First, the new value
must latch into the device by writing to the appropriate register,
and second, a new write to Register 0 must be performed.
The output multiplexer on the ADF4355 allows the user to access
various internal points on the chip. The M3, M2, and M1 bits in
Register 4 control the state of MUXOUT. Figure 25 shows the
MUXOUT section in block diagram form.
Rev. B | Page 13 of 35
ADF4355
Data Sheet
For example, to ensure that the modulus value loads correctly,
every time the modulus value updates, Register 0 must be
written to. The RF divider select in Register 6 is also double
buffered, but only when Bit DB14 of Register 4 is high.
OUTPUT STAGE
The RFOUTA+ and RFOUTA− pins of the ADF4355 connect to
the collectors of an NPN differential pair driven by buffered
outputs of the VCO, as shown in Figure 27. In this scheme, the
ADF4355 contains internal 50 Ω resistors connected to the VRF pin.
To optimize the power dissipation vs. the output power requirements,
the tail current of the differential pair is programmable using
Bits[D2:D1] in Register 6. Four current levels can be set. These
levels give approximate output power levels of −4 dBm, −1 dBm,
+2 dBm, and +5 dBm, respectively, using a 50 Ω resistor to VRF
and ac coupling into a 50 Ω load. For accurate power levels,
refer to the Typical Performance Characteristics section. With
an output power of 5 dBm, an external shunt inductor is necessary
to provide higher power levels; however, this addition results in
less wideband than the internal bias only. Terminate the unused
complementary output with a similar circuit to the used output.
VCO
The VCO core in the ADF4355 consists of four separate VCOs,
each of which uses 256 overlapping bands, which allows covering
a wide frequency range without a large VCO sensitivity (KV) and
without resultant poor phase noise and spurious performance.
The correct VCO and band are chosen automatically by the
VCO and band select logic when Register 0 is updated and auto-
calibration is enabled. The VCO VTUNE is disconnected from
the output of the loop filter and is connected to an internal
reference voltage.
The R counter output is used as the clock for the band select logic.
After band selection, normal PLL action resumes. The nominal
value of KV is 15 MHz/V when the N divider is driven from the
VCO output, or the KV value is divided by D. D is the output
divider value if the N divider is driven from the RF output divider
(chosen by programming Bits[D23:D21] in Register 6).
V
V
RF
RF
50Ω
A+
50Ω
RF
RF
A–
OUT
OUT
BUFFER/
DIVIDE BY
1/2/4/8/
VCO
The VCO shows variation of KV as the tuning voltage, VTUNE
,
16/32/64
varies within the band and from band to band. For wideband
applications covering a wide frequency range (and changing
output dividers), a value of 15 MHz/V provides the most accurate
KV, because this value is closest to the average value. Figure 26
shows how KV varies with fundamental VCO frequency along with
an average value for the frequency band. Users may prefer this
figure when using narrow-band designs.
Figure 27. Output Stage
Another feature of the ADF4355 is that the supply current to the
output stages can shut down until the ADF4355 achieves lock as
measured by the digital lock detect circuitry. The mute till lock
detect (MTLD) bit (DB11) in Register 6 enables this.
50
45
40
35
The RFOUTB+/RFOUTB− pins are duplicate outputs that can be
used independently or in addition to the RFOUTA+/RFOUTA− pins.
LINEAR
TREND LINE
30
AVERAGE
VCO SENSITIVITY
25
20
15
10
5
0
3.3
3.8
4.3
4.8
5.3
5.8
6.3
6.8
FREQUENCY (GHz)
Figure 26. KV vs. Frequency
Rev. B | Page 14 of 35
Data Sheet
ADF4355
Table 6. Total IDD (RFOUTA Refers to RFOUTA+/RFOUTA−)
Divide By
RFOUTA
Off
RFOUTA
= −4 dBm
RFOUTA
= −1 dBm
RFOUTA
= +2 dBm
RFOUTA = +5 dBm
5 V Supply (IVCO and IP)
78 mA
78 mA
78 mA
78 mA
78 mA
3.3 V Supply (AIDD, DIDD, IRF)
1
2
4
8
16
32
64
79.8 mA
87.8 mA
97.1 mA
104.9 mA
109.8 mA
113.6 mA
115.9 mA
101.3 mA
110.1 mA
119.3 mA
127.1 mA
131.8 mA
135.5 mA
137.8 mA
111.9 mA
120.6 mA
130.1 mA
137.8 mA
142.7 mA
146.5 mA
148.9 mA
122.7 mA
131.9 mA
141.6 mA
149.2 mA
154.1 mA
157.8 mA
160.1 mA
132.8 mA
141.9 mA
152.1 mA
159.7 mA
164.6 mA
168.4 mA
170.8 mA
Rev. B | Page 15 of 35
ADF4355
Data Sheet
REGISTER MAPS
REGISTER 0
CONTROL
BITS
16-BIT INTEGER VALUE (INT)
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2
DB1
DB0
N15 N14 N13 N12 N11 N10
N9
N8
N7
N6
N5
N4
N3
N2
N1 C4(0) C3(0) C2(0) C1(0)
0
0
0
0
0
0
0
0
0
0
AC1
PR1
N16
REGISTER 1
CONTROL
BITS
DBR1
RESERVED
24-BIT MAIN FRACTIONAL VALUE (FRAC1)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
F24
F23
F22
F21
F20
F19
F18
F17
F16
F15
F14
F13
F12
F11
F10
F9
F8
F7
F6
F5
F4
F3
F2
F1
0
0
0
C3(0) C2(0) C1(1)
C4(0)
0
REGISTER 2
CONTROL
BITS
DBR1
DBR 1
14-BIT AUXILIARY FRACTIONAL VALUE (FRAC2)
14-BIT AUXILIARY MODULUS VALUE (MOD2)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
M14 M13 M12 M11 M10 M9
M8
M7
M6
M5
M4
M3
M2
M1
F14
F13
F12
F11
F10
F9
F8
F7
F6
F5
F4
F3
F2
F1
C3(0) C2(1) C1(0)
C4(0)
REGISTER 3
CONTROL
BITS
24-BIT PHASE VALUE (PHASE)
DBR1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C3(0) C2(1) C1(1)
P1 C4(0)
0
SD1
PR1 PA1 P24
P23 P22
P21
P20
P19
P18
P17
P16 P15
P14 P13
P12
P11 P10
P9
P8
P7
P6
P5
P4
P3
P2
REGISTER 4
CONTROL
BITS
CURRENT
SETTING
DBR1
RESERVED
MUXOUT
10-BIT R COUNTER
DBR1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C3(1) C2(0) C1(0)
U1 C4(0)
0
0
M3
M2
M1
RD2 RD1
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
D1
CP4
CP3 CP2 CP1 U6
U5
U4
U3
U2
REGISTER 5
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
C4(0) C3(1) C2(0)
C1(1)
REGISTER 6
AUX RF
OUTPUT
POWER
RF
OUTPUT
POWER
RF DIVIDER
SELECT2
CONTROL
BITS
RESERVED
CHARGE PUMP BLEED CURRENT
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
BL2
BL3
0
BL10 BL9
1
0
1
0
D13 D12 D11
D10
BL7
BL4
BL1
0
D8
0
D6
D5
D4
D3
D2
D1
BL8
BL6
BL5
C4(0) C3(1) C2(1) C1(0)
1
2
DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
DBB = DOUBLE BUFFERED BITS—BUFFERED BY A WRITE TO REGISTER 0 WHEN BIT DB14 OF REGISTER 4 IS HIGH.
Figure 28. Register Summary (Register 0 to Register 6)
Rev. B | Page 16 of 35
Data Sheet
ADF4355
REGISTER 7
LD
CYCLE
COUNT
CONTROL
BITS
RESERVED
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
LD4
LD3 LD2 LD1 C4(0) C3(1) C2(1) C1(1)
0
0
0
1
0
0
LE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LD5
LOL
REGISTER 8
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
1
0
1
0
0
0
1
0
0
0
1
0
0
0
C4(1) C3(0) C2(0) C1(0)
REGISTER 9
SYNTHESIZER
LOCK TIMEOUT
CONTROL
BITS
VCO BAND DIVISION
TIMEOUT
AUTOMATIC LEVEL TIMEOUT
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
VC8 VC7 VC6 VC5 VC4 VC3 VC2 VC1 TL10 TL9 TL8 TL7 TL6 TL5 TL4 TL3 TL2 TL1 AL5 AL4 AL3 AL2 AL1 SL5 SL4 SL3 SL2 SL1 C4(1) C3(0) C2(0) C1(1)
REGISTER 10
ADC
CLOCK DIVIDER
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
AD8 AD7 AD6
AD5 AD4 AD3 AD2 AD1 AE2 AE1 C4(1) C3(0) C2(1) C1(0)
REGISTER 11
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
C4(1) C3(0) C2(1) C1(1)
0
REGISTER 12
CONTROL
BITS
RESERVED
RESYNC CLOCK
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P13 P12
P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1
0
0
0
0
0
1
0
0
0
0
0
1
P16 P15
C4(1) C3(1) C2(0) C1(0)
P14
Figure 29. Register Summary (Register 7 to Register 12)
Rev. B | Page 17 of 35
ADF4355
Data Sheet
CONTROL
BITS
16-BIT INTEGER VALUE (INT)
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
N15 N14 N13 N12 N11 N10
N9
N8
N7
N6
N5
N4
N3
N2
N1 C4(0) C3(0) C2(0) C1(0)
0
0
0
0
0
0
0
0
0
0
AC1
PR1 N16
N16
0
N15
0
...
...
...
...
...
...
...
...
...
...
...
...
N5
N4
N3
N2
N1
0
1
0
.
INTEGER VALUE (INT)
PR1 PRESCALER
0
0
0
.
0
0
0
.
0
0
0
.
0
0
1
.
NOT ALLOWED
0
1
4/5
8/9
0
0
NOT ALLOWED
0
0
NOT ALLOWED
.
.
...
0
0
1
1
1
.
0
0
1
.
1
1
0
.
1
1
0
.
0
1
0
.
NOT ALLOWED
0
0
23
0
0
24
VCO
AUTOCAL
AC1
.
.
...
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
65533
65534
65535
0
1
DISABLED
ENABLED
1
1
1
1
INT
= 75 WITH PRESCALER = 8/9
MIN
Figure 30. Register 0
Prescaler
REGISTER 0
The dual modulus prescaler (P/P + 1), along with the INT,
FRACx, and MODx counters, determines the overall division
ratio from the VCO output to the PFD input. The PR1 bit
(Bit DB20) in Register 0 sets the prescaler value.
Control Bits
With Bits[C4:C1] set to 0000, Register 0 is programmed. Figure 30
shows the input data format for programming this register.
Reserved
Operating at current mode logic levels, the prescaler takes the
clock from the VCO output and divides it down for the counters. It
is based on a synchronous 4/5 core. When the prescaler is set to
4/5, the maximum RF frequency allowed is 6.8 GHz. The prescaler
limits the INT value; therefore, if P is 4/5, NMIN is 23, and if P is
8/9, NMIN is 75.
Bits[DB31:DB22] are reserved and must be set to 0.
Automatic Calibration (Autocalibration)
Write to Register 0 to enact (by default) the VCO autocalibration
and to choose the appropriate VCO and VCO subband. Write a
1 to the AUTOCAL bit (AC1, Bit DB21) (Bit DB21) to enable
the autocalibration, which is the recommended mode of
operation.
16-Bit Integer Value
The 16 INT bits (Bits[DB19:DB4]) set the INT value, which
determines the integer part of the feedback division factor. The
INT value is used in Equation 3 (see the INT, FRAC1, FRAC2,
MOD1, MOD2, and R Counter Relationship section). All
integer values from 23 to 32,767 are allowed for the 4/5 prescaler.
For the 8/9 prescaler, the minimum integer value is 75, and the
maximum value is 65,535.
Set the AC1 bit to 0 to disable the autocalibration, leaving the
ADF4355 in the same band it is already in when Register 0
is updated.
Disable the autocalibration only for fixed frequency applications,
phase adjust applications, or very small (<10 kHz) frequency
jumps. Toggling AUTOCAL is also required when changing
frequency (see the Frequency Update Sequence section for
additional details).
Rev. B | Page 18 of 35
Data Sheet
ADF4355
CONTROL
BITS
1
RESERVED
24-BIT MAIN FRACTIONAL VALUE (FRAC1)
DBR
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1
0
0
0
C3(0) C2(0) C1(1)
C4(0)
0
F24
F23
.......... F2
F1
MAIN FRACTIONAL VALUE (FRAC1)
0
0
0
0
.
0
0
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
.........
0
0
1
1
.
0
1
0
1
.
0
1
2
3
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
16777212
16777213
16777214
16777215
1
DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
Figure 31. Register 1
24-Bit Main Fractional Value
REGISTER 1
The 24 FRAC1 bits (Bits[DB27:DB4]) set the numerator of the
fraction that is input to the Σ-Δ modulator. This fraction, along
with the INT value, specifies the new frequency channel that
the synthesizer locks to, as shown in the RF Synthesizer—A
Worked Example section. FRAC1 values from 0 to (MOD1 − 1)
cover channels over a frequency range equal to the PFD
reference frequency.
Control Bits
With Bits[C4:C1] set to 0001, Register 1 is programmed. Figure 31
shows the input data format for programming this register.
Reserved
Bits[DB31:DB28] are reserved and must be set to 0.
Rev. B | Page 19 of 35
ADF4355
Data Sheet
CONTROL
BITS
1
1
14-BIT AUXILIARY FRACTIONAL VALUE (FRAC2) DBR
14-BIT AUXILIARY MODULUS VALUE (MOD2) DBR
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
M14 M13 M12 M11 M10 M9
M8
M7
M6
M5
M4
M3
M2
M1
F14
F13
F12
F11
F10
F9
F8
F7
F6
F5
F4
F3
F2
F1
C3(0) C2(1) C1(0)
C4(0)
M14 M13 .......... M2
M1
0
1
0
1
.
MODULUS VALUE (MOD2)
F14
F13
.......... F2
F1
0
1
0
1
.
FRAC2 WORD
0
0
0
0
.
0
0
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
.........
0
0
1
1
.
NOT ALLOWED
0
0
0
0
.
0
0
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
.........
0
0
1
1
.
0
NOT ALLOWED
1
2
2
3
3
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
16380
16381
16382
16383
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
16381
16382
16382
16383
1
DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
Figure 32. Register 2
14-Bit Auxiliary Modulus Value (MOD2)
REGISTER 2
The 14-bit auxiliary modulus value (Bits[DB17:DB4]) sets the
auxiliary fractional modulus. Use MOD2 to correct any residual
error due to the main fractional modulus.
Control Bits
With Bits[C4:C1] set to 0010, Register 2 is programmed. Figure 32
shows the input data format for programming this register.
14-Bit Auxiliary Fractional Value (FRAC2)
The 14-bit auxiliary fractional value (Bits[DB31:DB18]) controls
the auxiliary fractional word. FRAC2 must be less than the
MOD2 value programmed in Register 2.
Rev. B | Page 20 of 35
Data Sheet
ADF4355
CONTROL
BITS
1
DBR
24-BIT PHASE VALUE (PHASE)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C3(0) C2(1) C1(1)
0
SD1
PR1 PA1 P24
P23 P22
P21
P20
P19
P18
P17
P16 P15
P14 P13 P12
P11 P10
P9
P8
P7
P6
P5
P4
P3
P2
P1 C4(0)
PHASE
ADJUST
PA1
P24
P23
0
0
0
0
.
.......... P2
P1
PHASE VALUE (PHASE)
0
1
DISABLED
ENABLED
0
0
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
.........
0
0
1
1
.
0
1
0
1
.
0
1
2
3
PHASE
PR1
.
RESYNC
.
.
.
.
.
0
1
DISABLED
ENABLED
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
16777212
16777213
16777214
16777215
SD LOAD
RESET
SD1
0
1
ON REGISTER0 UPDATE
DISABLED
1
DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
Figure 33. Register 3
This is achieved by programming the D13 bit (Bit DB24) in
Register 6 to 0, which ensures divided feedback to the N divider.
Phase resynchronization only operateswhen FRAC2 = 0.
REGISTER 3
Control Bits
With Bits[C4:C1] set to 0011, Register 3 is programmed. Figure 33
shows the input data format for programming this register.
For resync applications, enable the SD load reset in Register 3
by setting DB30 to 0.
Reserved
Phase Adjust
Bit DB31 is reserved and must be set to 0.
SD Load Reset
To adjust the relative output phase of the ADF4355 on each
Register 0 update, set the PA1 bit (Bit DB28) to 1. This feature
differs from the resynchronization feature in that it is useful
when adjustments to the phase are made continually in an
application. For this function, disable the VCO automatic
calibration by setting the AC1 bit (Bit DB21) in Register 0 to 1
and disable the SD load reset by setting the SD1 bit (Bit DB30)
in Register 3 to 1. Note that phase resync and phase adjust
cannot be used simultaneously.
When writing to Register 0, the Σ-Δ modulator resets. For
applications when the phase is continually adjusted, this may
not be desirable; therefore, in these cases, the Σ-Δ reset can be
disabled by writing a 1 to the SD1 bit (Bit DB30).
Phase Resync
To use the phase resynchronization feature, the PR1 bit (Bit DB29)
must be set to 1. If unused, the bit can be programmed to 0. The
phase resync timer must also be used in Register 12 to ensure that
the resynchronization feature is applied after the PLL has settled
to the final frequency. If the PLL has not settled to the final frequency,
phase resync may not function correctly. Resynchronization is
useful in phased array and beam forming applications. It ensures
repeatability of output phase when programming the same
frequency. In phase critical applications that use frequencies
requiring the output divider (<3400 MHz), it is necessary to
feed the N divider with the divided VCO frequency rather than
from the fundamental VCO frequency.
24-Bit Phase Value
The phase of the RF output frequency can adjust in 24-bit steps;
from 0° (0) to 360° (224 − 1). For phase adjust applications, the
phase is set by
(Phase Value/16,777,216) × 360°
When the phase value is programmed to Register 3, each
subsequent adjustment of Register 0 increments the phase by
the value in this equation.
Rev. B | Page 21 of 35
ADF4355
Data Sheet
CURRENT
SETTING
CONTROL
BITS
1
1
DBR
MUXOUT
10-BIT R COUNTER
DBR
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1
DB0
0
0
M3
M2
M1 RD2 RD1 R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
D1
CP4 CP3 CP2 CP1 U6
U5
U4
U3
U2
U1
C3(1) C2(0) C1(0)
C4(0)
REFERENCE
RD2
COUNTER
RESET
DOUBLE BUFFERED
REGISTER 6, BITS[DB23:DB21]
U1
D1
U6
0
REFIN
SINGLE
DIFF
DOUBLER
0
1
DISABLED
ENABLED
0
1
DISABLED
ENABLED
0
1
DISABLED
1
ENABLED
RD1 REFERENCE DIVIDE BY 2
CP
I
(mA)
CP
U2
U5
LDP
THREE-STATE
CP4
CP3
CP2
CP1
5.1kΩ
0
1
DISABLED
ENABLED
0
1
1.8V
3.3V
0
1
DISABLED
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.31
0.63
0.94
1.25
1.56
1.88
2.19
2.50
2.81
3.13
3.44
3.75
4.06
4.38
4.69
5.00
ENABLED
R10
R9
..........
R2
R1
R DIVIDER (R)
U4
0
PD POLARITY
NEGATIVE
POSITIVE
U3
POWER DOWN
0
0
.
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
1
.
1
0
.
1
0
1
DISABLED
ENABLED
2
1
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
1020
1021
1022
1023
M3
0
M2
0
M1
0
OUTPUT
THREE-STATE OUTPUT
0
0
1
DV
DD
0
1
0
SD
GND
0
1
1
R DIVIDER OUTPUT
N DIVIDER OUTPUT
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
RESERVED
1
0
0
1
0
1
1
1
0
1
1
1
1
DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
Figure 34. Register 4
RDIV2
REGISTER 4
Setting the RD1 bit (Bit DB25) to 1 inserts a divide by 2 toggle
flip-flop between the R counter and PFD, which extends the
maximum reference frequency input rate. This function provides
a 50% duty cycle signal at the PFD input.
Control Bits
With Bits[C4:C1] set to 0100, Register 4 is programmed. Figure 34
shows the input data format for programming this register.
Reserved
10-Bit R Counter
Bits[DB31:DB30] are reserved and must be set to 0.
The 10-bit R counter divides the input reference frequency
(REFIN) to produce the reference clock to the PFD. Division
ratios range from 1 to 1023.
MUXOUT
The on-chip multiplexer (MUXOUT) is controlled by
Bits[DB29:DB27]. For additional details, see Figure 34.
Double Buffer
Reference Doubler
The D1 bit (Bit DB14) enables or disables double buffering of
the RF divider select bits (Bits[DB23:DB21]) in Register 6. The
Program Modes section explains how double buffering works.
Setting the RD2 bit (Bit DB26) to 0 feeds the REFIN signal directly
to the 10-bit R counter, disabling the doubler. Setting this bit to
1 multiplies the reference frequency by a factor of 2 before feeding
it into the 10-bit R counter. When the doubler is disabled, the REFIN
falling edge is the active edge at the PFD input to the fractional
synthesizer. When the doubler is enabled, both the rising and
falling edges of the reference frequency become active edges at
the PFD input.
Charge Pump Current Setting
The CP4 to CP1 bits (Bits[DB13:DB10]) set the charge pump
current. Set this value to the charge pump current that the loop
filter is designed with (see Figure 34). For the lowest spurs, the
0.9 mA setting is recommended.
The maximum allowable reference frequency when the doubler
is enabled is 100 MHz.
Rev. B | Page 22 of 35
Data Sheet
ADF4355
When power-down activates, the following events occur:
Reference Mode
The ADF4355 permits use of either differential or single-ended
reference sources.
The synthesizer counters are forced to their load state
conditions.
The VCO powers down.
For optimum integer boundary spur performance, use the
single-ended setting for all references up to 250 MHz (even if
using a differential reference signal). Use the differential setting for
reference frequencies above 250 MHz.
The charge pump is forced into three-state mode.
The digital lock detect circuitry resets.
The RFOUTA+/RFOUTA− and RFOUTB+/RFOUTB− output
stages are disabled.
The input registers remain active and capable of loading
and latching data.
Level Select
To assist with logic compatibility, MUXOUT is programmable to
two logic levels. Set the U5 bit (Bit DB8) to 0 to select 1.8 V logic,
and set it to 1 to select 3.3 V logic.
Charge Pump Three-State
Setting the U2 bit (Bit DB5) to 1 puts the charge pump into
three-state mode. Set DB5 to 0 for normal operation.
Phase Detector (PD) Polarity
The U4 bit (Bit DB7) sets the phase detector polarity. When a
passive loop filter or a noninverting active loop filter is used,
set DB7 to 1 (positive). If an active filter with an inverting
characteristic is used, set this bit to 0 (negative).
Counter Reset
The U1 bit (Bit DB4) resets the R counter, N counter, and
VCO band select of the ADF4355. When DB4 is set to 1, the RF
synthesizer N counter and R counter, and the VCO band select,
are reset. For normal operation, set DB4 to 0. Toggling counter
reset (Bit DB4) is also required when changing frequency (see
the Frequency Update Sequence section for additional details).
Power-Down
The U3 bit (Bit DB6) sets the programmable power-down mode.
Setting DB6 to 1 performs a power-down. Setting DB6 to 0
returns the synthesizer to normal operation. In software power-
down mode, the ADF4355 retains all information in its registers.
The register contents are only lost if the supply voltages are
removed.
REGISTER 5
The bits in Register 5 are reserved and must be programmed as
described in Figure 35, using a hexadecimal word of 0x00800025.
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C4(0) C3(1) C2(0)
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
C1(1)
Figure 35. Register 5 (0x00800025)
Rev. B | Page 23 of 35
ADF4355
Data Sheet
AUX RF
OUTPUT
POWER
RF
OUTPUT
POWER
RF DIVIDER
SELECT1
CONTROL
BITS
RESERVED
CHARGE PUMP BLEED CURRENT
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
BL2
BL3
0
BL10 BL9
1
0
1
0
D13 D12 D11 D10
BL7
BL4
BL1
0
D8
0
D6
D5
D4
D3
D2
D1
BL8
BL6 BL5
C4(0) C3(1) C2(1) C1(0)
FEEDBACK
SELECT
D13
D2
D1
OUTPUT POWER
–4dBm
0
0
1
1
0
0
1
DIVIDED
1
0
1
–1dBm
FUNDAMENTAL
+2dBm
+5dBm
BLEED CURRENT
BL9
D12
D11
D10 RF DIVIDER SELECT
D3
0
RF OUT
0
1
DISABLED
ENABLED
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
÷1
DISABLED
ENABLED
÷2
MUTE TILL
LOCK DETECT
1
D8
÷4
0
1
MUTE DISABLED
MUTE ENABLED
÷8
GATED BLEED
BL10
D5
D4
AUXILIARY OUTPUT POWER
÷16
÷32
÷64
0
0
1
1
0
1
0
1
–4dBm
–1dBm
+2dBm
+5dBm
0
1
DISABLED
ENABLED
D6
0
AUXILIARY OUT
DISABLED
1
ENABLED
BL8
BL7
..........
BL2
BL1 BLEED CURRENT
0
0
.
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
1
.
1
0
.
1
2
.
(3.75µA)
(7.5µA)
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
252 (945µA)
253 (948.75µA)
254 (952.5µA)
255 (956.25µA)
1
BITS[DB23:DB21] ARE BUFFERED BY A WRITE TO REGISTER 0 WHEN THE DOUBLE BUFFER BIT IS ENABLED, BIT DB14 OF REGISTER 4.
Figure 36. Register 6
Use negative bleed only when operating in fractional-N mode,
that is, FRAC1 or FRAC2 is not equal to 0. Do not use negative
bleed for fPFD greater than 100 MHz.
REGISTER 6
Control Bits
With Bits[C4:C1] set to 0110, Register 6 is programmed. Figure 36
shows the input data format for programming this register.
Reserved
Bits[DB28:DB25] are reserved and must be set to 1010.
Reserved
Feedback Select
Bit DB31 is reserved and must be set to 0.
Gated Bleed
D13 (Bit DB24) selects the feedback from the output of the
VCO to the N counter. When D13 is set to 1, the signal is taken
directly from the VCO. When this bit is set to 0, the signal is
taken from the output of the output dividers. The dividers
enable coverage of the wide frequency band (54 MHz to
6800 MHz). When the divider is enabled and the feedback
signal is taken from the output, the RF output signals of two
separately configured PLLs are in phase. Divided feedback is
useful in some applications where the positive interference of
signals is required to increase the power.
Bleed currents can improve phase noise and spurs; however, due
to a potential impact on lock time, the gated bleed bit, BL10
(Bit DB30), if set to 1, ensures bleed currents are not switched
on until the digital lock detect asserts logic high. Note that this
function requires digital lock detect to be enabled.
Negative Bleed
Use of constant negative bleed is recommended for most
applications because it improves the linearity of the charge
pump leading to lower noise and spurs than leaving negative
bleed off. To enable negative bleed, write 1 to BL9 (Bit DB29),
and to disable negative bleed, write 0 to BL9 (Bit DB29).
RF Divider Select
D12 to D10 (Bits[DB23:DB21]) select the value of the RF output
divider (see Figure 36).
Rev. B | Page 24 of 35
Data Sheet
ADF4355
Charge Pump Bleed Current
Reserved
BL8 to BL1 (Bits[DB20:DB13]) control the level of the bleed
current added to the charge pump output. This current
optimizes the phase noise and spurious levels from the device.
Bit DB10 is reserved and must be set to 0.
Auxiliary RF Output Enable
Bit DB9 enables or disables the auxiliary frequency RF output
(RFOUTB+/RFOUTB−). When DB9 is set to 1, the auxiliary
frequency RF output is enabled. When DB9 is set to 0, the
auxiliary RF output is disabled.
Tests have shown that the optimal bleed set is the following:
4/N < IBLEED/ICP < 10/N
where:
Auxiliary RF Output Power
I
BLEED is the value of constant negative bleed applied to the
charge pump, which is set by the contents of Bits[BL8:BL1].
CP is the value of charge pump current setting, Bits[DB13:DB10] of
Bits[DB8:DB7] set the value of the auxiliary RF output power
level (see Figure 36).
I
Register 4.
RF Output Enable
N is the value of the feedback counter from the VCO to the PFD.
Bit DB6 enables or disables the primary RF output (RFOUTA+/
RFOUTA−). When DB6 is set to 0, the primary RF output is
disabled. When DB6 is set to 1, the primary RF output is
enabled.
Reserved
Bit DB12 is reserved and must be set to 0.
Mute Till Lock Detect
Output Power
When D8 (Bit DB11) is set to 1, the supply current to the RF
output stage is shut down until the device achieves lock, as
determined by the digital lock detect circuitry.
Bits[DB5:DB4] set the value of the primary RF output power
level (see Figure 36).
Rev. B | Page 25 of 35
ADF4355
Data Sheet
LD
CYCLE
COUNT
CONTROL
BITS
RESERVED
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
LD4
LD3 LD2 LD1 C4(0) C3(1) C2(1) C1(1)
0
0
0
1
0
0
LE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LD5
LOL
LD1 LOCK DETECT MODE
FRACTIONAL-N
0
1
INTEGER-N (2.9ns)
LD3
0
LD2
0
FRACTIONAL-N LD PRECISION
5.0ns
6.0ns
8.0ns
12.0ns
0
1
1
0
1
1
LE
LE SYNCHRONIZATION
LOL LOSS OF LOCK MODE
DISABLED
DISABLED
ENABLED
0
1
0
1
LE SYNCED TO REFIN
LD5
0
LD4
LOCK DETECT CYCLE COUNT
0
1
0
1
1024
2048
4096
8192
0
1
1
Figure 37. Register 7
Loss of Lock (LOL) Mode
REGISTER 7
Set LOL (Bit DB7) to 1 when the application is a fixed frequency
application in which the input reference frequency (REFIN) is likely
to be removed, such as a clocking application. The standard lock
detect circuit assumes that REFIN is always present; however, this
may not be the case with clocking applications. To enable this
functionality, set DB7 to 1. Loss of lock mode does not function
reliably when using a differential REFIN mode.
Control Bits
With Bits[C4:C1] set to 0111, Register 7 is programmed. Figure 37
shows the input data format for programming this register.
Reserved
Bits[DB31:DB29] are reserved and must be set to 0. Bit DB28 is
reserved and must be set to 1. Bits[DB27:DB26] are reserved
and must be set to 0.
Fractional-N Lock Detect Precision (LDP)
LE Sync
LD3 and LD2 (Bits[DB6:DB5]) set the precision of the lock detect
circuitry in fractional-N mode. LDP is available at 5.0 ns, 6.0 ns,
8.0 ns, or 12.0 ns. If bleed currents are used, use 12 ns.
When set to 1, Bit DB25 ensures that the load enable (LE) edge
is synchronized internally with the rising edge of reference
input frequency. This synchronization prevents the rare event of
reference and RF dividers from loading at the same time as a falling
edge of reference frequency, which can lead to longer lock times.
Lock Detect Mode (LDM)
If LD1 (Bit DB4) is set to 0, each reference cycle is set by
fractional-N lock detect precision as described in the
Fractional-N Lock Detect Count (LDC) section. If DB4 is
set to 1, each reference cycle is 2.9 ns long, which is more
appropriate for integer-N applications.
Reserved
Bits[DB24:DB10] are reserved and must be set to 0.
Fractional-N Lock Detect Count (LDC)
LD5 and LD4 (Bits[DB9:DB8]) set the number of consecutive
cycles counted by the lock detect circuitry before asserting lock
detect high. See Figure 37 for details.
Rev. B | Page 26 of 35
Data Sheet
ADF4355
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
1
0
1
0
0
0
1
0
0
0
0
1
0
0
C4(1)
C1(0)
C3(0) C2(0)
Figure 38. Register 8 (0x102D0428)
SYNTHESIZER
LOCK TIMEOUT
CONTROL
BITS
VCO BAND DIVISION
TIMEOUT
AUTOMATIC LEVEL TIMEOUT
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
VC8 VC7 VC6
VC5 VC4 VC3 VC2 VC1 TL10 TL9
TL8
TL7
TL6
TL5
TL4
TL3
TL2
TL1 AL5 AL4
AL3 AL2 AL1 SL5 SL4 SL3 SL2 SL1 C4(1) C3(0) C2(0) C1(1)
SL5
SL4
..........
SL2
SL1 SLC WAIT
0
0
.
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
1
.
1
0
.
1
TL10
TL9
..........
TL2
TL1 TIMEOUT
2
0
0
.
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
1
.
1
0
.
1
.
2
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
28
29
30
31
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
1020
1021
1022
1023
AL5
AL4
..........
AL2
AL1 ALC WAIT
VC8
VC7
..........
VC2
VC1 VCO BAND DIV
0
0
.
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
1
.
1
0
.
1
0
0
.
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
1
.
1
0
.
1
2
2
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
28
29
30
31
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
252
253
254
255
Figure 39. Register 9
Automatic Level Calibration Timeout
REGISTER 8
AL5 to AL1 (Bits[DB13:DB9]) set the timer value used for the
automatic level calibration of the VCO. This function combines
the PFD frequency, the timeout variable, and ALC wait variable.
Choose ALC such that the following equation is always greater
than 50 μs.
The bits in this register are reserved and must be programmed
as described in Figure 38, using a hexadecimal word of
0x102D0428.
REGISTER 9
Control Bits
(Timeout × ALC Wait/PFD Frequency) > 50 μs
With Bits[C4:C1] set to 1001, Register 9 is programmed. Figure 39
shows the input data format for programming this register.
Synthesizer Lock Timeout
SL5 to SL1 (Bits[DB8:DB4]) set the synthesizer lock timeout
value. Use this value to allow the VTUNE force to settle on the
VCO Band Division
VC8 to VC1 (Bits[DB31:DB24]) set the value of the VCO band
division clock. Determine the value of this clock by PFD/(band
division × 16) such that the result is <150 kHz.
VTUNE pin. The value must be 20 μs. Calculate the value using
the following equation:
(Timeout × Synthesizer Lock Timeout/PFD Frequency) > 20 μs
Timeout
TL10 to TL1 (Bits[DB23:DB14]) set the timeout value for the
VCO band select. Use this value as a variable in the other VCO
calibration settings.
Rev. B | Page 27 of 35
ADF4355
Data Sheet
ADC
CLOCK DIVIDER
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AE2 AE1 C4(1) C3(0) C2(1) C1(0)
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
AE1 ADC
0
1
DISABLED
ENABLED
AE2 ADC CONVERSION
0
1
DISABLED
ENABLED
AD8
AD7
..........
AD2 AD1 ADC CLK DIV
0
0
.
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
1
.
1
0
.
1
2
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
252
253
254
255
Figure 40. Register 10
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
C4(1) C3(0) C2(1) C1(1)
0
Figure 41. Register 11 (0x0061300B)
Choose the ADC_CLK_DIV value such that
REGISTER 10
Control Bits
ADC_CLK_DIV = ceiling(((fPFD/100,000) − 2)/4)
where ceiling() is a function to round up to the nearest integer.
With Bits[C4:C1] set to 1010, Register 10 is programmed.
Figure 40 shows the input data format for programming this
register.
For example, for fPFD = 61.44 MHz, set ADC_CLK_DIV = 154
so that the ADC clock frequency is 99.417 kHz. If ADC_CLK_DIV
is greater than 255, set it to 255.
Reserved
Bits[DB31:DB14] are reserved. Bits[DB23:DB22] must be set to
11, but all other bits in this range must be set to 0.
ADC Conversion Enable
AE2 (Bit DB5) ensures that the ADC performs a conversion
when a write to Register 10 is performed. It is recommended to
enable this mode.
ADC Clock Divider (ADC_CLK_DIV)
An on-board analog-to-digital converter (ADC) determines the
VTUNE setpoint relative to the ambient temperature of the ADF4355
environment. The ADC ensures that the initial tuning voltage
in any application is chosen correctly to avoid any temperature
drift issues.
ADC Enable
AE1 (Bit DB4), when set to 1, powers up the ADC for the
temperature dependent VTUNE calibration. It is recommended to
always use this function.
The ADC uses a clock that is equal to the output of the R counter
(or the PFD frequency) divided by ADC_CLK_DIV.
REGISTER 11
The bits in this register are reserved and must be programmed as
described in Figure 41, using a hexadecimal word of 0x0061300B.
AD8 to AD1 (Bits[DB13:DB6]) set the value of this divider. On
power-up, the R counter is not programmed; however, in these
power-up cases, it defaults to R = 1.
Rev. B | Page 28 of 35
Data Sheet
ADF4355
CONTROL
BITS
RESERVED
RESYNC CLOCK
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P13 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1
P12
C1(0)
C3(1) C2(0)
0
0
0
0
0
1
0
0
0
0
0
1
P16
P15
C4(1)
P14
P16
P15
...
P5
P4
P3
P2
P1
RESYNC CLOCK
0
0
0
.
0
0
0
.
...
...
...
...
...
...
...
...
...
...
...
0
0
0
.
0
0
0
.
0
0
0
.
0
0
1
.
0
1
0
.
NOT ALLOWED
1
2
...
0
0
0
.
0
0
0
.
1
1
1
.
0
0
1
.
1
1
0
.
1
1
0
.
0
1
0
.
22
23
24
...
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
65533
65534
65535
Figure 42. Register 12
For fPFD > 75 MHz (initially lock with half fPFD), use the
following sequence:
1. Register 12.
REGISTER 12
Control Bits
With Bits[C4:C1] set to 1100, Register 12 is programmed. Figure 42
shows the input data format for programming this register.
2. Register 11.
3. Register 10.
4. Register 9.
Phase Resync Clock Divider Value
5. Register 8.
6. Register 7.
7. Register 6.
8. Register 5.
P16 to P1 (Bits[DB31:DB16]) set the timeout counter for
activation of phase resync. This value must be set such that a
resync happens immediately after (and not before) the PLL has
achieved lock after reprogramming.
9. Register 4 (with the R divider doubled to output half fPFD).
10. Register 3.
11. Register 2 (for halved fPFD).
Calculate the timeout value using the following equation:
Time Out Value = Phase Resync Clock/PFD Frequency
Reserved
12. Register 1 (for halved fPFD).
13. Wait >16 ADC_CLK cycles. For example, if
ADC_CLK = 99.417 kHz, wait 16/99417 sec = 161 μs.
See the Register 10 section for more information.
14. Register 0 (for halved fPFD; autocalibration enabled).
15. Register 4 (with the R divider set for desired fPFD).
16. Register 2 (for desired fPFD).
Bits[DB15:DB4] are reserved. Bit DB10 and Bit DB4 must be set
to 1, but all other bits in this range must be set to 0.
REGISTER INITIALIZATION SEQUENCE
At initial power-up, after the correct application of voltages to
the supply pins, registers must be programmed in sequence. For
17. Register 1 (for desired fPFD).
18. Register 0 (for desired fPFD; autocalibration disabled).
f
PFD ≤ 75 MHz, use the following sequence:
1. Register 12.
2. Register 11.
3. Register 10.
4. Register 9.
5. Register 8.
6. Register 7.
7. Register 6.
8. Register 5.
9. Register 4.
10. Register 3.
11. Register 2.
12. Register 1.
13. Wait >16 ADC_CLK cycles. For example, if
ADC_CLK = 99.417 kHz, wait 16/99,417 sec = 161 μs.
See the Register 10 section for more information.
14. Register 0.
FREQUENCY UPDATE SEQUENCE
Frequency updates require updating the auxiliary modulator
(MOD2) in Register 2, the fractional value (FRAC1) in Register 1,
and the integer value (INT) in Register 0. It is recommended to
perform a temperature dependent VTUNE calibration by updating
Register 10 first. A counter reset (Bit DB4) is also required in
the frequency update sequence Therefore, for fPFD ≤ 75 MHz,
use the following sequence:
1. Register 10.
2. Register 4 (counter reset enabled [DB4 = 1]).
3. Register 2.
4. Register 1.
5. Register 0 (autocalibration disabled [DB21 = 0]).
6. Register 4 (counter reset disabled [DB4 = 0]).
Rev. B | Page 29 of 35
ADF4355
Data Sheet
7. Wait >16 ADC_CLK_DIV cycles. For example, if
The feedback path is also important. In this example, the VCO
output is fed back before the output divider (see Figure 43).
ADC_CLK_DIV = 99.417 kHz, wait 16/99417 sec =
161 µs. See the Register 10 section.
8. Register 0 (autocalibration enabled [DB21 = 1]).
In this example, divide the 122.88 MHz reference signal by 2 to
generate a fPFD of 61.44 MHz. The desired channel spacing is
200 kHz.
For fPFD > 75 MHz (initially lock with half fPFD), use the
following sequence:
fPFD
RF
OUT
PFD
VCO
÷2
1. Register 10.
2. Register 4 (counter reset enabled [DB4 = 1]).
3. Register 2 (for halved fPFD).
N
DIVIDER
4. Register 1 (for halved fPFD).
Figure 43. Loop Closed Before Output Divider
5. Register 0 (for halved fPFD; autocalibration disabled).
6. Register 4 (counter reset disabled [DB4 = 0], with the
R divider doubled to output half fPFD).
7. Wait >16 ADC_CLK cycles. For example, if
ADC_CLK = 99.417 kHz, wait 16/99417 sec = 161 μs.
See the Register 10 section for more information.
8. Register 0 (for halved fPFD; autocalibration enabled).
9. Register 4 (with the R divider set for desired fPFD).
10. Register 2 (for desired fPFD).
The worked example is as follows:
•
N = VCOOUT/fPFD = 4225.6 MHz/61.44 MHz =
68.7760416666666667
INT = int(VCO frequency/fPFD) = 68
FRAC = 0.7760416666666667
•
•
•
•
•
•
MOD1 = 16,777,216
FRAC1 = int(MOD1 × FRAC) = 13019817
Remainder = 0.6666666667 or 2/3
MOD2 = fPFD/GCD(fPFD/fCHSP) = 61.44
MHz/GCD(61.44 MHz/200 kHz) = 1536
FRAC2 = remainder × 1536 = 1024
11. Register 1 (for desired fPFD).
12. Register 0 (for desired fPFD; autocalibration disabled).
The frequency change only occurs when writing to Register 0.
•
RF SYNTHESIZER—A WORKED EXAMPLE
From Equation 8,
Use the following equations to program the ADF4355 synthesizer:
fPFD = (122.88 MHz × (1 + 0)/2) = 61.44 MHz
(9)
FRAC2
MOD2
MOD1
From Equation 7,
FRAC1+
RFOUT
where:
=
INT +
× (fPFD)/RF Divider (7)
2112.8 MHz = 61.44 MHz × ((INT + (FRAC1 +
FRAC2/MOD2)/224))/2
where:
INT = 68
FRAC1 = 13,019,817
FRAC2 = 1024
(10)
RFOUT is the RF frequency output.
INT is the integer division factor.
FRAC1 is the fractionality.
FRAC2 is the auxiliary fractionality.
MOD2 is the auxiliary modulus.
MOD1 is the fixed 24-bit modulus.
MOD2 = 1536
RF Divider = 2 (see Equation 7)
RF Divider is the output divider that divides down the VCO
frequency.
REFERENCE DOUBLER AND REFERENCE DIVIDER
The on-chip reference doubler allows the input reference signal
to be doubled. The doubler is useful for increasing the PFD
comparison frequency. To improve the noise performance of
the system, increase the PFD frequency. Doubling the PFD
frequency usually improves noise performance by 3 dB.
f
PFD = REFIN × ((1 + D)/(R × (1 + T)))
(8)
where:
REFIN is the reference frequency input.
D is the RF REFIN doubler bit.
R is the RF reference division factor.
T is the reference divide by 2 bit (0 or 1).
The reference divide by 2 divides the reference signal by 2,
resulting in a 50% duty cycle PFD frequency.
For example, in a universal mobile telecommunication system
(UMTS) where 2112.8 MHz RF frequency output (RFOUT) is
required, a 122.88 MHz reference frequency input (REFIN) is
available. Note that the ADF4355 VCO operates in the frequency
range of 3.4 GHz to 6.8 GHz. Therefore, an RF divider of 2 must
be used (VCO frequency = 4225.6 MHz, RFOUT = VCO frequency/
RF divider = 4225.6 MHz/2 = 2112.8 MHz).
SPURIOUS OPTIMIZATION AND FAST LOCK
Narrow loop bandwidths can filter unwanted spurious signals,
but these bandwidths usually have a long lock time. A wider
loop bandwidth achieves faster lock times but may lead to
increased spurious signals inside the loop bandwidth.
Rev. B | Page 30 of 35
Data Sheet
ADF4355
By combining the following two equations:
OPTIMIZING JITTER
ALC Wait > (50 µs × fPFD)/Timeout
For lowest jitter applications, use the highest possible PFD
frequency to minimize the contribution of in-band noise from
the PLL. Set the PLL filter bandwidth such that the in-band noise
of the PLL intersects with the open-loop noise of the VCO,
minimizing the contribution of both to the overall noise.
Synthesizer Lock Timeout > (20 µs × fPFD)/Timeout
The following is found:
ALC Wait = 2.5 × Synthesizer Lock Timeout
Maximize ALC Wait (to reduce Timeout to minimize time) so
that ALC Wait = 30 and Synthesizer Lock Timeout = 12.
Use the ADIsimPLL™ design tool for this task.
SPUR MECHANISMS
Finally, ALC Wait > (50 µs × fPFD)/Timeout, is rearranged as
Timeout = Ceiling((fPFD × 50 µs)/ALC Wait)
Timeout = Ceiling((61.44 MHz × 50 µs)/30) = 103
Synthesizer Lock Timeout
This section describes the two different spur mechanisms that
arise with a fractional-N synthesizer and how to minimize them
in the ADF4355.
Integer Boundary Spurs
One mechanism for fractional spur creation is the interactions
between the RF VCO frequency and the reference frequency.
When these frequencies are not integer related (the purpose of a
fractional-N synthesizer), spur sidebands appear on the VCO
output spectrum at an offset frequency that corresponds to the
beat note or the difference in frequency between an integer
multiple of the reference and the VCO frequency. These spurs
are attenuated by the loop filter and are more noticeable on
channels close to integer multiples of the reference where the
difference frequency can be inside the loop bandwidth (thus
the name, integer boundary spurs).
The synthesizer lock timeout ensures that the VCO calibration
DAC, which forces VTUNE, has settled to a steady value for the
band select circuitry.
The timeout and synthesizer lock timeout variables programmed
in Register 9 select the length of time the DAC is allowed to
settle to the final voltage before the VCO calibration process
continues to the next phase, which is VCO band selection. The
PFD frequency is used as the clock for this logic, and the
duration is set by
Timeout ×Synthesizer Lock Timeout
PFD Frequency
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism
that bypasses the loop may cause a problem. Feedthrough of
low levels of on-chip reference switching noise, through the
prescaler back to the VCO, can result in reference spur levels
as high as −80 dBc.
The calculated time must be equal to or greater than 20 µs.
VCO Band Selection
Use the PFD frequency again as the clock for the band selection
process. Calculate this value by
PFD/(VCO Band Selection × 16) < 150 kHz
The band selection takes 11 cycles of the previously calculated
value. Calculate the duration by
LOCK TIME
11 × (VCO Band Selection × 16)/PFD Frequency
The PLL lock time divides into a number of settings. All of
these are modeled in the ADIsimPLL design tool. Faster lock
times than those detailed in this data sheet are possible; contact
your local Analog Devices, Inc., sales representative for more
information.
Automatic Level Calibration Timeout
Use the automatic level calibration (ALC) function to choose
the correct bias current in the ADF4355 VCO core. Calculate
the time taken by
Lock Time—A Worked Example
5 × 11 × ALC Wait × Timeout/PFD Frequency
Assuming fPFD = 61.44 MHz,
PLL Low-Pass Filter Settling Time
VCO Band Div = Ceiling(fPFD/2,400,000) = 26
where Ceiling() rounds up to the nearest integer.
The time taken for the loop to settle is inversely proportional to
the low-pass filter bandwidth. The settling time is also modeled
in the ADIsimPLL design tool.
The total lock time for changing frequencies is the sum of the
four separate times (synthesizer lock, VCO band selection, ALC
timeout, and PLL settling time) and is all modeled in the
ADIsimPLL design tool.
Rev. B | Page 31 of 35
ADF4355
Data Sheet
APPLICATIONS INFORMATION
The LO ports of the ADL5375 can be driven differentially from
the complementary RFOUTA+/RFOUTA− outputs of the ADF4355.
Differential drive gives better second-order distortion performance
than a single-ended LO driver and eliminates the use of a balun
to convert from a single-ended LO input to the more desirable
differential LO input for the ADL5375.
DIRECT CONVERSION MODULATOR
Direct conversion architectures are increasingly being used to
implement base station transmitters. Figure 44 shows how to
use Analog Devices devices to implement such a system.
The circuit block diagram shows the AD9761 TxDAC+® being
used with the ADL5375. The use of a dual integrated DAC, such
as the AD9761, ensures minimum error contribution (over
temperature) from this portion of the signal chain.
The ADL5375 accepts LO drive levels from −6 dBm to +6 dBm.
The optimum LO power can be software programmed on the
ADF4355, which allows levels from −4 dBm to +5 dBm from
each output.
The local oscillator (LO) is implemented using the ADF4355.
The low-pass filter was designed using the ADIsimPLL design
tool for a PFD of 61.44 MHz and a closed-loop bandwidth of
20 kHz.
The RF output is designed to drive a 50 Ω load; however, it
must be ac-coupled, as shown in Figure 44. If the I and Q inputs
are driven in quadrature by 2 V p-p signals, the resulting output
power from the ADL5375 modulator is approximately 2 dBm.
51Ω
51Ω
REFIO
IOUTA
IOUTB
LOW-PASS
FILTER
MODULATED
DIGITAL
DATA
AD9761
TxDAC
QOUTA
QOUTB
LOW-PASS
FILTER
FSADJ
51Ω
51Ω
2kΩ
V
LOCK
DETECT
VCO
V
DD
100nF
32
100nF
1
25
17
5
4
26
10
6
27
DV
16
AV
30
V
PDB
V
C
RF RF
2
C
REG
MUXOUT
V
AV
CE
REG
VCO
P
DD
DD
DD
1nF 1nF
1nF 1nF
ADL5375
IBBP
FREF
FREF
29
IN
REF
REF
A
B
IN
IN
RF
B+ 14
OUT
IBBN
V
OUT
RF
B–
15
28
OUT
IN
7.5nH
7.5nH
1
2
3
CLK
DATA
LE
1nF
LOIP
11
12
RF
RF
A+
A–
QUADRATURE
PHASE
SPLITTER
OUT
LPF
ADF4355
RFOUT
LOIN
OUT
LPF
1nF
V
20
7
TUNE
DSOP
3.3kΩ
QBBN
QBBP
22
R
CP
OUT
SET
4.7kΩ
33nF
1500pF
390pF
1kΩ
CP
SD
A
A
A
V
V
GND
GND GND GNDRF
GNDVCO
REGVCO
19
V
BIAS
REF
8
31
9
13
18 21
23
24
10pF
0.1µF 10pF
0.1µF 10pF
0.1µF
Figure 44. Direct Conversion Modulator
Rev. B | Page 32 of 35
Data Sheet
ADF4355
The bottom of the chip-scale package has a central exposed
POWER SUPPLIES
thermal pad. The thermal pad on the PCB must be at least as
large as the exposed pad. On the PCB, there must be a minimum
clearance of 0.25 mm between the thermal pad and the inner
edges of the pad pattern. This clearance ensures the avoidance
of shorting.
The ADF4355-2 contains four multiband VCOs that cover an
octave range of frequencies. To ensure best performance, it is vital
to connect a low noise regulator, such as the ADM7170, to the
VVCO pin. Connect the same regulator to package pins VVCO
,
VREGVCO, and VP.
To improve the thermal performance of the package, use thermal
vias on the PCB thermal pad. If vias are used, incorporate them
into the thermal pad at the 1.2 mm pitch grid. The via diameter
must be between 0.3 mm and 0.33 mm and the via barrel must
be plated with 1 oz. of copper to plug the via.
For the 3.3 V supply pins, use two ADM7170 regulators, one for
the DVDD and AVDD supplies and one for VRF. Figure 45 shows
the recommended connections.
PRINTED CIRCUIT BOARD (PCB) DESIGN
GUIDELINES FOR A CHIP-SCALE PACKAGE
For a microwave PLL and VCO synthesizer, such as the ADF4355,
take care with the board stack-up and layout. Do not consider
using FR4 material because it is too lossy above 3 GHz. Instead,
Rogers 4350, Rogers 4003, or Rogers 3003 dielectric material is
suitable.
The lands on the 32-lead lead frame chip-scale package are
rectangular. The PCB pad for these lands must be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. Center each land on the pad to
maximize the solder joint size.
Take care with the RF output traces to minimize discontinuities
and ensure the best signal integrity. Via placement and grounding
are critical.
V
= 3.3V
OUT
V
= 6.0V
IN
VIN
EN
VOUT
VOUT
C
10µF
IN
C
10µF
OUT
ON
SENSE
OFF
ADM7170
SS
C
SS
1nF
LOCK
GND
DETECT
100nF
100nF
1
17
V
25
26
C
CE PDB V
RF RF
10
6
27
DV
16
AV
4
32
30
2
C
REG
V
MUXOUT
REG
VCO
P
DD
DD
1nF 1nF
1nF 1nF
V
= 3.3V
C
OUT
FREF
FREF
29
IN
REF
A
B
IN
IN
V
= 6.0V
RF
B+ 14
IN
OUT
VIN
EN
VOUT
VOUT
V
OUT
C
RF
B–
IN
15
28 REF
OUT
IN
OUT
10µF
ON
10µF
7.5nH
7.5nH
SENSE
1
2
3
CLK
OFF
1nF
1nF
ADM7170
DATA
LE
11
12
RF
RF
A+
A–
SS
OUT
C
ADF4355
SS
1nF
OUT
GND
V
20
7
TUNE
3.3kΩ
22
R
CP
OUT
SET
4.7kΩ
33nF
V
= 5.0V
C
V
= 6.0V
OUT
IN
1500pF
390pF
AV
5
DD
VIN
EN
VOUT
VOUT
1kΩ
C
CP
SD
A
A
A
V
V
V
BIAS
IN
GND
GND GND
GNDRF
GNDVCO
REGVCO
REF
OUT
10µF
ON
10µF
8
31
9
13
18 21
19
23
24
SENSE
OFF
ADM7170
SS
C
SS
1nF
10pF
0.1µF 10pF
0.1µF 10pF
0.1µF
GND
Figure 45. ADF4355 Power Supplies
Rev. B | Page 33 of 35
ADF4355
Data Sheet
When differential outputs are not needed, terminate the unused
output or combine it with both outputs using a balun.
OUTPUT MATCHING
The low frequency output can simply be ac-coupled to the next
circuit, if desired; however, if higher output power is required,
use a pull-up inductor to increase the output power level.
For lower frequencies below 2 GHz, it is recommended to use a
100 nH inductor on the RFOUTA+/RFOUTA− pins.
V
RF
The RFOUTA+/RFOUTA− pins are a differential circuit. Provide
each output with the same (or similar) components where
possible, such as the same shunt inductor value, bypass
capacitor, and termination.
7.5nH
100pF
RF
A+
OUT
50Ω
The auxiliary frequency output, RFOUTB+/RFOUTB−, can be
treated the same as the RFOUTA+/RFOUTA− output. If unused,
leave both RFOUTB+/RFOUTB− pins open.
Figure 46. Optimum Output Stage
Rev. B | Page 34 of 35
Data Sheet
ADF4355
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
5.10
5.00 SQ
4.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
25
32
24
1
0.50
BSC
3.75
3.60 SQ
3.55
EXPOSED
PAD
17
8
16
9
0.50
0.40
0.30
0.25 MIN
TOP VIEW
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5.
Figure 47. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADF4355BCPZ
ADF4355BCPZ-RL7
EV-ADF4355SD1Z
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
CP-32-12
CP-32-12
1 Z = RoHS Compliant Part.
©2015–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12910-0-8/17(B)
Rev. B | Page 35 of 35
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