ADD8502ACP [ADI]
IC SPECIALTY CONSUMER CIRCUIT, QCC24, 4 X 4 MM, MO-220-VGGD-2, LFCSP-24, Consumer IC:Other;
| 型号： | ADD8502ACP |
| 厂家： | 
ADI |
| 描述： | IC SPECIALTY CONSUMER CIRCUIT, QCC24, 4 X 4 MM, MO-220-VGGD-2, LFCSP-24, Consumer IC:Other CD |
| 文件： | 总16页 (文件大小：378K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated LCD
Grayscale Generator
a
ADD8502
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Two Mask Programmable Sets of Five Reference Levels
Dual 10-Bit DACs for Flicker Offset and Range Adjustment
Integrated VCOM Switching
REV2
V
DD
Single-Supply Operation: 5.0 V
Low Supply Current: 300 ꢀA
Global Power Save Mode: 1 ꢀA Max
Fast Settling Time for Load Change: 20 ꢀs
Stable with 20 nF/100 ꢁ Loads
VP0
VN0
GND
V
DD
VREF+
10-BIT
DAC A
VREF–
V0
A0
A1
A2
A3
A4
V
/2
DD
R
VP0
CMOS/TTL Input Levels
R
R
APPLICATIONS
Color TFT Cell Phones
Color TFT PDAs
V1
V2
V3
V4
VN4
V
L
MUX
SCK
GENERAL DESCRIPTION
DIGITAL
CORE
D
The ADD8502 is an integrated, high accuracy, programmable
grayscale generator. Two sets of five output reference voltages
are mask programmed to 0.2% resolution. The outputs switch
between the two sets of five levels. The reference levels are selected
from a 512 tap resistor network using a via mask.
IN
CS-LD
VP4
VN4
POWER
SAVE
LOGIC
R
R
VP4
ADD8502 includes two serially addressable, 10-bit digital-to-
analog converters (DACs) and five fast, low current buffers.
The dual DACs set the endpoint voltages applied to the resistor
network to adjust for flicker and range. The two power save modes
can reduce the total current to less than 1 µA and feature fast
recovery time from Shutdown/Sleep Mode. The ADD8502
accepts CMOS or TTL inputs for all controls, including the
common drive circuit levels.
PSK
GS1
GS2
VN0
R
R
V
/2
DD
VREF+
10-BIT
DAC B
VREF–
V
DD
ADD8502 operates over the industrial temperature range from
–40°C to +85°C and is available in a space-saving 24-lead
4 mm ꢀ 4 mm frame chip scale package.
V
COM
LOGIC
COM
COM_M
REV1 CM CV4
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
(@ V = 5.0 V, ꢂ40ꢃC ≤ T ≤ ꢄ85ꢃC, unless otherwise noted.)
ADD8502–SPECIFICATIONS
DD
A
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SYSTEM ACCURACY
VOUT Error
3
1
3
3
3
20
17
21
21
25
mV
mV
mV
mV
mV
Swing Error1
(VPn – VNn) – (VPi – VNi)
(VPn+ VNn)/2 – (VPi + VNi)/2)
Mean Error2
Mean Error between Adjacent Channels3
Mean Error between V0 and V44
DAC ACCURACY
Resolution
10
Bits
Differential Nonlinearity
Integral Nonlinearity5
Offset Error
DNL
INL
0.25
0.5
0.4
0.15
LSB
LSB
% of FSR
% of FSR
Gain Error
OUTPUT CHARACTERISTICS
Output Current
Short Circuit Current
Output Leakage Current in High-Z Mode
Slew Rate
IOUT
ISC
ILEAKAGE
SR
tS
SR
tS
φo
(VDD – 1 V)
Short to Ground
High-Z Mode
25
60
0.01
1.25
8
0.7
8
67
mA
mA
µA
1.0
12
12
RL = 100 kΩ
V/µs
µs
Settling Time to 1%
V0 to V4 Step Size
LD =100 Ω Series 16 nF
V0 to V4 Step Size
Slew Rate5
V/µs
µs
Degrees
Settling Time to 1%5
Phase Margin
VCOM SWITCHES ACTIVE IMPEDANCE
COM to VDD
COM to GND
COM to COM_M
COM to V4
Z
Z
Z
Z
See Table IV
I = 20 mA
25
25
25
25
50
50
50
50
Ω
Ω
Ω
Ω
MASK PROGRAMMABLE
RESISTOR CHAIN
Resistor Matching
RMATCH
Any Two Segments between
512 Resistor String
1
%
POWER SUPPLY
Supply Voltage
Supply Current
Shutdown Supply Current
Sleep Supply Current
Shutdown Recovery Time
Sleep Recovery Time
VDD
ISY
ISY-GLB
ISY-GS1-3
4.5
190
5
5.5
400
1
210
30
V
VDD = 5 V; No Load
Full Shutdown Mode
Mid 3 Buffers Shutdown
Global PD to 1%
270
0.2
175
23
µA
µA
µA
µs
140
V1–V3 Off to 1%
10
15
µs
LOGIC SUPPLY
Logic Input Voltage Level
Logic Input Current
VL
IVL
2.3
3.3
0.01
5.5
1
V
µA
DIGITAL I/O
Digital Input High Voltage
Digital Input Low Voltage
Digital Input Current
Digital Input Capacitance
VIH
VIL
IIN
VL ꢀ 0.7
V
V
µA
pF
VL ꢀ 0.3
1
10
GND ≤ VIN ≤ 5.5 V
CIN
NOTES
1Swing error is a comparison of measured VOUT step versus theoretical VOUT step. Theoretical values can be found on the Mask Tap Point Option sheet.
2Mean error is measured VOUT mean versus theoretical VOUT mean (see Figure 3).
3Mean errors between two adjacent channels versus theoretical (see Figure 3).
4Mean errors between V0 and V4 versus theoretical (see Figure 3).
5Slew rate and settling time are measured between the output resistor and the capacitor (see Figure 1).
R
100ꢁ
Specifications subject to change without notice.
L
C
L
16nF
V
COM
Figure 1. Slew Rate Diagram
–2–
REV. 0
ADD8502
Table I. Serial Data Timing Characteristics
Parameter
Symbol
t1
Min Typ Max
Unit
SCK Cycle Time
SCK High Time
SCK Low Time
CS-LD Setup Time
Data Setup Time
Data Hold Time
LSB SCK High to CS-LD High
Minimum CS-LD High Time
SCK to CS-LD Active Edge Setup Time
CS-LD High to SCK Positive Edge
SCK Frequency (Square Wave)
100
45
45
20
5
5
5
ns
ns
ns
ns
ns
ns
ns
ns
t2
t3
t4
t5
t6
t7
t8
t9
t10
10
5
ns
ns
MHz
10
10
NOTES
1All input signals are specified with rise/fall time –5 ns (10% to 90% of VDD) and timed from a voltage level
of (VS + VIH)/2.
2See Figure 2.
t
t
5
1
SCK
t
t
t
t
t
t
6
3
2
7
10
9
D
C3
C2
X1
X0
IN
t
t
4
8
CS-LD
Figure 2. Serial Write Interface
VO
VP0
SEE NOTE 2 ON SPECIFICATIONSTABLE
VN0
V0 – V1
SEE NOTE 3 ON SPECIFICATIONSTABLE
VP1
VN1
V1
SEE NOTE 4 ON
SPECIFICATIONSTABLE
VN2
VP2
V2
VN3
SEE NOTE 1 ON SPECIFICATIONSTABLE
V3
V4
VP3
VN4
VP4
Figure 3. Output Wave Form Diagram
–3–
REV. 0
ADD8502
ABSOLUTE MAXIMUM RATINGS*
1
2
Package Type
ꢅJA
34.8
ꢆJB
Unit
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VL to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to GND . . . . . . . . . . . . . –0.3 V to +7 V
VOUT to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD +0.3 V
VCOM to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD +0.3 V
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 10 sec)
24-Lead LFCSP (ACP)
13
°C/W
NOTES
1θJA is specified for worst-case conditions, i.e., θJA is specified for device soldered
in circuit board for surface-mount packages.
2ψJB is applied for calculating the junction temperature by reference to the board
temperature.
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Model
ADD8502ACP –40°C to +85°C 24-Lead LFCSP CP-24
Available in 7” reel only.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADD8502 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. 0
ADD8502
PIN CONFIGURATION
24 23 22 21 20 19
1
2
3
4
5
6
18
V0
V
L
PIN 1
17 V1
16 V2
D
IN
IDENTIFIER
SCK
ADD8502
TOP VIEW
V3
15
CS-LD
CM
(Not to Scale)
14 V4
13 GND
CV4
7
8
9
10 11 12
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
I/O Description
Pin No. Mnemonic Name
1
2
VL
DIN
Logic Select Pin
Serial Data Input
I
I
Logic Supply Voltage. Connect to supply used for system logic. Can accept 2.7 V to VDD.
When CS is LOW, the input on this pin is shifted into the internal shift register on
the rising edge of SCK.
3
4
5
6
7
SCK
CS-LD
CM
Serial Clock
Load
I
I
I
I
I
Accepts up to 10 MHz input. The rising edge on this clock will shift the data on
DIN Pin into the internal shift registers.
When CS-LD is LOW, SCK is enabled for shifting data on the DIN input into the
internal shift register on the rising edge of SCK. Data is loaded MSB first.
When CM is LOW, COM will output the voltage level input on COM_M.
When CM is HIGH, COM levels will be determined by the input on REV1.
If CV4 is HIGH, V4 output is the output of the op amp A4. If CV4 is LOW, V4 is
connected to COM and op amp A4 is shut down. Refer to Table II.
With CM HIGH, a HIGH on REV1 will cause COM to output the voltage level
input at VDD. A LOW on REV1 will cause COM to output the voltage level input
at GND.
Logic Control 2
for VCOM
Logic Control V4
CV4
REV1
Logic Control 1
for VCOM
8
9
NC
NC
No Connect
No Connect
Unused Pin
Unused Pin
10
COM
Common Output
O
I
If CM is LOW, COM will output the voltage input at COM_M. If CM is HIGH,
COM will output the voltage input at VDD when REV1 is HIGH and will output
the voltage input at GND when REV1 is LOW. Refer to Table II.
COM_M is a system voltage reference input between 2.5 V and 3.5 V. This may
be the system 3.3 V supply.
11
COM_M
Common System
VREF
12
13
14
NC
GND
V4
No Connect
Ground
Output
Unused Pin
Ground. Nominally 0 V.
Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF).
When PSK is LOW, these outputs will be Hi-Z.
I
O
15
16
17
18
V3
V2
V1
V0
Output
Output
Output
Output
O
O
O
O
I
Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF).
When PSK is LOW or GS1 and GS2 = HIGH, these outputs will be Hi-Z.
Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF).
When PSK is LOW or GS1 and GS2 = HIGH, these outputs will be Hi-Z.
Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF).
When PSK is LOW or GS1 and GS2 = HIGH, these outputs will be Hi-Z.
Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF).
When PSK is LOW, these outputs will be Hi-Z.
19
20
VDD
NC
Supply
No Connect
Supply Voltage. Nominally 5 V.
Unused Pin
REV. 0
–5–
ADD8502
Pin No. Mnemonic Name
I/O Description
21
REV2
Reference Output
Select
I
When PSK is HIGH and GS1 or GS2 is LOW, then INVERT selects the output
levels on V0 to V4. If INVERT is HIGH, outputs V0 to V4 are connected to
reference levels VP0 to VP4, respectively. If INVERT is LOW, outputs V0 to V4
are connected to reference levels VN0 to VN4, respectively. When PSK is HIGH
and GS1 and GS2 are HIGH, V1–V3 are, Hi-Z state, but V0 and V4 are still
connected to reference levels VP0 and VP4 when INVERT is HIGH. Outputs V0
and V4 switch to VN0 and VN4 when REV is LOW.
22
23
24
GS2
GS1
PSK
Sleep Mode
Select
I
I
I
When GS1 and GS2 are HIGH, the middle three output buffers are shut down
and V1, V2, and V3 are put into Hi-Z states. Other combinations of GS1 and GS2
leave the outputs of A1 to A3 fully active.
When GS1 and GS2 are HIGH, the middle three output buffers are shut down
and V1, V2, and V3 are Hi-Z. Other combinations of GS1 and GS2 leave the
outputs of A1 to A3 fully active.
When PSK is pulled LOW, the chip will be put into the full Power-Down Mode.
The DACs, resistor ladder network preamps, and output buffers will all be shut
down, and A0 to A4 will be in Hi-Z states. Recovery from full power-down to
normal operation is within 30 µs.
Sleep Mode
Select
Global Power
Shutdown
All digital inputs accept CMOS or TTL logic levels.
–6–
REV. 0
Typical Performance Characteristics–
ADD8502
250
5
3
V
DD
= 5V
V
DD
= 5V
DAC B
200
150
100
50
DAC A
1
–1
–3
–5
0
ꢂ40
0
128
256
384
512
640
768
896 1025
25
85
CODE – LSB
TEMPERATURE – ꢃC
TPC 4. Shutdown Current vs. Temperature
TPC 1. DAC Integral Nonlinearity
5
3
190
V
DD
= 5V
DAC A
V
= 5V
DD
185
180
175
170
165
160
155
1
ꢂ1
ꢂ3
ꢂ5
DAC B
0
128
256
384
512
640
768
896 1024
ꢂ40
25
85
CODE – LSB
TEMPERATURE – ꢃC
TPC 5. Sleep Supply Current vs. Temperature
TPC 2. DAC Differential Nonlinearity
0.5
ꢂ0
350
V
DD
= 5V
V
DD
= 5V
DAC A
300
250
200
150
100
50
ꢂ0.5
ꢂ1.0
ꢂ1.5
ꢂ2.0
ꢂ2.5
ꢂ3.0
DAC B
0
ꢂ40
ꢂ40
25
TEMPERATURE – ꢃC
85
25
85
TEMPERATURE – ꢃC
TPC 3. Offset Error vs. Temperature
TPC 6. Supply Current vs. Temperature
–7–
REV. 0
ADD8502
350
10.0
9.5
9.0
8.5
8.0
7.5
7.0
V
DD
= 5V
300
250
200
150
100
2
3
4
5
6
7
ꢂ40
25
85
V
–V
DD
TEMPERATURE – ꢃC
TPC 7. System Supply Current at Full Power
TPC 10. Sleep Recovery Time vs. Temperature
10
400
350
300
250
200
150
100
50
V
DD
= 5V
8
6
4
2
0
0
2.0
ꢂ2
ꢂ40
25
85
2.5
3.0
3.5
4.0
4.5
– V
5.0
5.5
6.0
6.5
7.0
V
TEMPERATURE – ꢃC
DD
TPC 8. System Supply Current at Shutdown
TPC 11. Output Leakage
28
0
0
0
0
0
0
0
0
0
V
DD
= 5V
V
DD
= 5V
27
26
25
24
23
22
21
20
19
18
REV2
V0
ꢂ40
25
85
0
0
0
0
0
0
0
0
0
0
0
TEMPERATURE – ꢃC
TIME – 10ꢀs/DIV
TPC 9. Shutdown Recovery Time vs. Temperature
TPC 12. V0 Output Swing Response to REV2
–8–
REV. 0
ADD8502
25
20
15
10
5
400
350
300
250
200
150
100
50
V
DD
= 5V
0
ꢂ40
0
–15 –13 –11 –9 –7 –5 –3 –1
1
3
5
7
9
11 13 15
25
85
OUTPUTVOLTAGE MEAN ERROR
TEMPERATURE – ꢃC
TPC 13. VCOM Switch-On-Resistance vs. Temperature
TPC 16. VOUT Swing Mean vs. Distribution
800
700
600
500
400
300
200
100
0
2.0
1.5
VP3–VP4
1.0
0.5
VP2–VP3
0
–0.5
–1.0
VP1–VP2
VP0–VP1
–23
–18
–13
–8
–3
2
7
12
17
22
ꢂ40
25
TEMPERATURE – ꢃC
85
OUTPUTVOLTAGE – mV
TPC 14. VOUT Error Distribution
TPC 17. Mean Error between Adjacent Channel
vs. Temperature
2.0
0.6
0.4
1.5
1.0
V0
0.2
VN2–VN3
0
0.5
V1
V2
VN3–VN4
ꢂ0.2
0
ꢂ0.4
VN1–VN2
–0.5
–1.0
–1.5
–2.0
–2.5
V3
ꢂ0.6
ꢂ0.8
ꢂ1.0
ꢂ1.2
V4
VN0–VN1
ꢂ1.4
ꢂ40
25
85
ꢂ40
25
85
TEMPERATURE – ꢃC
TEMPERATURE – ꢃC
TPC 18. Mean Error between Adjacent Channel
vs. Temperature
TPC 15. Swing Error vs. Temperature
–9–
REV. 0
ADD8502
2.0
1.5
1.0
0.5
10
9
V
DD
= 5V
VP0–VP4
RISING EDGE
8
0
ꢂ0.5
ꢂ1.0
ꢂ1.5
ꢂ2.0
7
6
5
4
FALLING EDGE
VN0–VN4
ꢂ2.5
ꢂ40
25
TEMPERATURE – ꢃC
85
ꢂ40
45
TEMPERATURE – ꢃC
125
TPC 22. Settling Time at VOUT vs. Temperature
TPC 19. Mean Error between V0 and V4 vs. Temperature
5
0
V
L
= 2.5V
0
0
0
0
0
0
0
0
SOURCE
4
SINK
3
V
HIGH
TH
V
LOW
TH
2
1
0
0
20
40
60
80
0
0
0
0
0
0
0
0
0
0
0
OUTPUT CURRENT – mA
TIME – 500mV/DIV
TPC 23. Output Current Source and Sink
TPC 20. REV1 Hysteresis
1.40
1.35
1.30
1.25
1.20
V
DD
= 5V
SLEW RATE FALLING
SLEW RATE RISING
1.15
1.10
1.05
1.00
ꢂ40
25
85
TEMPERATURE – ꢃC
TPC 21. Slew Rate vs. Temperature
–10–
REV. 0
ADD8502
OPERATION
Transfer Function
The transfer function for the ADD8502 is given in the following
equations:
V
V
V
OUTA = 4.941 V
OUTB = 0.244 V
TX = 4.831 V
Equations 1–3 will provide a theoretical calculation of the out-
puts. The actual will vary with load, process, and architecture.
See Specifications table.
1. Digital-to-analog transfer function for DAC A. An output can
be derived from Equation 1 as:
VDD
DA
1024
SERIAL INTERFACE
VOUTA
=
1+
(1)
The ADD8502 has a 3-wire serial interface (CS-LD, SCK, and
DIN). The writing sequence begins by bringing the CS-LD line
LOW. Data on the DIN line is clocked into the 16-bit shift regis-
ter on the rising edge of SCK. The serial clock frequency can be
as high as 10 MHz. When the last data bit is clocked in,
CS-LD line needs to be brought HIGH to load the DAC regis-
ters and the operation mode is dependent upon the control bits.
2
2. Digital-to-analog transfer function for DAC B. An output can
be derived from Equation 2 as:
DB V
DD
VOUTB
=
(2)
2
1024
Input Shift Register
Where DA and DB are decimal equivalents of the binary codes
The input shift register is 16 bits wide (see Figure 4). The first
four control bits (C3, C2, C1, and C0) are used to set the different
operating modes of the device. The next 10 bits are the data bits
and the last two bits are “Don’t Cares.” This composes a full word
that is transferred to the DAC register on the rising edge of CS-LD.
that are loaded to the DAC Register from 0 to 1023.
3. Using any programmed tap point from the 512 resistor string,
the system output can be derived from Equation 3:
TX
512
VTX = (VOUTA − VOUTB
)
+ VOUTB
In a normal write sequence, the CS-LD line is kept LOW for at
least 16 rising edges of SCK and then it is brought HIGH to
update the DACs. However, if CS-LD is brought HIGH before
the 16th rising edge, this acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as invalid.
Neither an update of the DAC register contents nor a change in
the operation mode occurs.
(3)
Where TX is any tap point of the 512 resistor string. It is mask
programmable. VTX is the voltage output at any output (VO, ... V4)
and will switch between two voltages depending on the mask
programmed tap points.
Example: VDD = 5 V, DA = 1,000, DB = 100, and TX = 500.
DB15 (MSB)
DB0 (LSB)
C3
C2
C1
C0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X1
X0
DON’T
CARE
DATA BITS
CONTROL BITS
Figure 4. Input Register Contents
REV. 0
–11–
ADD8502
Table II. DAC Control Function
Control Code
C3 C2 C1 C0
Input Register
Status
DAC Register
(Sleep/Wake)
Power-Down Status
Comments
Status
0
0
0
0
0
0
0
0
1
0
1
0
No Change
No Update
No Change
No Change
No Change
No operation; power-down status unchanged
(part stays in Wake or Sleep Mode).
Load DAC A
Load DAC B
No Update
No Update
Load input Register A with data. DAC outputs
unchanged. Power-down status unchanged.
Load input Register B with data. DAC outputs
unchanged. Power-down status unchanged.
0
0
0
0
0
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
Not Used
Not Used
Not Used
Not Used
Not Used
1
0
0
0
No Change
Update Outputs
Wake
Wake
Load both DAC registers with existing contents
of input registers. Update DAC outputs. Part
wakes up.
1
0
0
1
Load DAC A
Update Outputs
Load input Register A. Load DAC registers with
new contents of input register A and existing
contents of Register B. Update DAC outputs.
Part wakes up.
1
0
1
0
Load DAC B
Update Outputs
Wake
Load input Register B. Load DAC registers with
new contents of input Register B and existing
contents of Register A. Update DAC outputs.
Part wakes up.
1
1
0
1
1
0
1
0
Not Used
Not Used
1
1
0
1
No Change
No Change
No Update
Wake
Part wakes up. Input and DAC registers
unchanged. DAC outputs reflect existing
contents of DAC registers.
1
1
1
1
1
1
0
1
No Update
Sleep
Wake
Power down the IC, put in into Sleep Mode.
Load DACs
A, B with Same
10-Bit Code
Update
Outputs
Load both input registers. Load both DAC
registers with new contents of input registers.
Update DAC outputs. Part wakes up.
Modes of Operation
Access to the DAC register is controlled by the control codes,
C0 to C3. The user can update both DACs simultaneously as
well as individually. It depends on the selected control codes to
The ADD8502 has various modes of operation, such as updating
both DACs simultaneously or changing the power-down status
(Sleep/Wake). These are selected by writing the appropriate
4-bit control code (C0–C3). The details for each mode are
summarized in Table II.
update individual output or both outputs simultaneously.
Initial Power-Up Condition
The ADD8502 has preset DAC conditions when its initially
powered on. The DACs are loaded with 1110 1011 11 for the
upper DAC and 0000 1010 00 for the lower DAC. The part is
powered up in a normal operation mode (Wake Status).
Low Power Serial Interface
To reduce the power consumption of the device ever further, the
interface only powers up fully when the device is being written
to. As soon as the 16-bit control word has been written to the
part, the SCK and DIN input buffers are powered down. They
only power up again following a falling edge of CS-LD.
Power-Down Modes
The ADD8502 has two shutdown modes. One mode is to fully
shut down the device using PSK or the digital serial control code,
and the other mode is to shut down V1 to V3 buffers using GS1
and GS2. See Table III for the priority of the shutdown control
functions.
Double-Buffered Interface
The ADD8502 has double-buffered interfaces consisting of two
banks of registers: input and DAC. The input register is con-
nected directly to the input shift register, and the digital code is
transferred to the relevant input register on completion of a
valid write sequence. The DAC register contains the digital
code used by the resistor string.
–12–
REV. 0
ADD8502
The ADD8502 will have a quiescent current less than 1 µA when
it is fully shut down and all output buffers are switched to a high
impedance state. The only active circuitries are the digital logics
and the latches for the serial control. When the device is brought
back from Sleep Mode to normal operation, it will use the last
serial word to update the DACs or a new control code or data if
any was loaded when the part was in Sleep Mode; i.e., the contents
of the input register, DAC register, and power-down status shown
VCOM Logic
VCOM operation is described in Table IV. The VCOM logic is
always active and its logic inputs are CM, REV1, and CV4.
When CM is LOW, COM is connected to COM_M. When CM
is HIGH, COM is determined by the logic input of REV1. If
REV1 is HIGH, COM is connected to VDD. When REV1 is
LOW, COM is connected to GND.
CV4 controls the V4 output. If CV4 goes LOW, V4 is connected
to COM and A4 is shut down with its output in a Hi-Z state.
When CV4 is HIGH, the switch connecting V4 to COM is open
and A4 is in normal operation mode.
in Table II is retained as long as VDD and VL are on.
The second power save mode (mid 3 buffers are shut down) is
using GS1 and GS2. In a condition where both GS1 and GS2
logics are HIGH, the output buffers (V1, V2, and V3) are shut
down and switched into a high impedance state.
Table IV. VCOM Logic Control
Inputs
Outputs
VCOM
Table III. Shutdown Control Function
CM
L
REV1
CV4
L
V4
Serial
Control
Operation
GS1 GS2 Mode
X
X
L
COM_M
COM_M
GND
COM
A4
PSK
H
L
H
Wake
Wake
Wake
Wake
Sleep
X
L
L
Normal Operation
Normal Operation
Normal Operation
Mid 3 Buffers are Shutdown
Full Shutdown
H
L
COM
COM
A4
H
L
H
L
H
H
L
L
VDD
H
H
H
X
X
H
H
GND
H
H
X
X
H
H
H
VDD
A4
H
X = Don’t Care
L
Full Shutdown
X = Don’t Care
REV. 0
–13–
ADD8502
V
L
V
DD
LOGIC LEVEL
TRANSLATOR
SCK
LOGIC LEVEL
TRANSLATOR
D
IN
V0
V1
LOGIC LEVEL
TRANSLATOR
CS-LD
V2
LOGIC LEVEL
TRANSLATOR
PSK
V3
LOGIC LEVEL
TRANSLATOR
GS1
ADD8502
CORE
V4
LOGIC LEVEL
TRANSLATOR
GS2
REV1
REV2
CM
COM
LOGIC LEVEL
TRANSLATOR
LOGIC LEVEL
TRANSLATOR
COM_M
LOGIC LEVEL
TRANSLATOR
V
L
V
DD
LOGIC LEVEL
TRANSLATOR
CV4
GND
Figure 5. CST ESD and Logic Level Translation Scheme
ADD8502 Description
•
No damage to the digital inputs will occur with applied
voltages up to 7 V (see Absolute Maximum Ratings section
of data sheet).
•
The ADD8502 uses logic level translators to convert external
logic levels to levels suitable for use in the ADD8502 core.
•
•
No current will flow between VDD and VL under normal
operating conditions.
•
The logic level translators are intended to be powered from
the same supply voltage as is used to power the external
logic driving the ADD8502.
Logic voltages can be present on the logic input pins even if
VL is powered down. Inputs are limited by max supply rating
of 7 V.
•
•
VDD may be powered down while normal voltages are present
on the VL and logic input pins.
•
•
Digital input pins have ESD protection connected to GND.
V
DD and VL are independent and can be in the range 0 V to
5.5 V.
All other input and output pins have ESD protection connected
to GND and VDD.
–14–
REV. 0
ADD8502
V
OUTA
ADD8502-000 MASK OPTION
DAC A
Table V. Default Power-Up Conditions
DAC Setpoints (0 ≤ D ≤ 1023)
Decimal Code Voltage
VP
0
VP
1
VP
2
VP
3
VP
4
VN
4
VN
3
VN
2
VN
1
VN
0
Unit
Upper DAC
Lower DAC
943
40
4.8022
0.0977
V
V
Resistor Tap Points (0 ≤ X ≤ 512)
Tap Point
Voltage
Unit
DAC B
VP0
VP1
VP2
VP3
VP4
VN0
VN1
VN2
VN3
VN4
450
271
203
137
3
4.2325
2.5878
1.9630
1.3565
0.1252
0.3825
2.0732
2.7624
3.4699
4.7747
V
V
V
V
V
V
V
V
V
V
V
OUTB
Figrue 6. Tap Point References
Tap point voltages can be derived from the following equation:
X
512
31
Vx = VOUTB
+
V
− VOUTB
[
]
OUTA
215
290
367
509
Where VOUTA and VOUTB can be derived from the transfer func-
tions under the Operation Section of the datasheet.
The ADD8502 uses a single resistor string consisting of 512
individual elements. Both sets of reference voltages (VP0–VP4,
N0–VN4) are generated from this single string. Two separate
Supply voltage = 5 V
V
resistor networks are shown to demonstrate the tap points, which
are changeable by mask option and completely independent of
each other.
REV. 0
–15–
ADD8502
OUTLINE DIMENSIONS
24-Lead Frame Chip Scale Package [LFCSP]
4x4 mm Body
(CP-24)
0.60 MAX
4.0
BSC SQ
0.25
MIN
PIN 1
INDICATOR
0.60 MAX
1
19
18
24
PIN 1
INDICATOR
0.50
BSC
3.75
BSC SQ
TOP
VIEW
BOTTOM
VIEW
0.50
0.40
0.30
2.25
1.70
0.75
6
13
12
7
2.50
REF
0.70 MAX
0.65 NOM
1.00
0.90
0.85
12ꢀ MAX
0.05 MAX
0.02 NOM
0.25
REF
0.30
0.23
0.18
COPLANARITY
0.08
SEATING
PLANE
COMPLIANTTO JEDEC STANDARDS MO-220-VGGD-2
–16–
REV. 0
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