ADCMP603BCPZ-WP [ADI]
Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparator; 轨到轨，速度非常快， 2.5 V至5.5 V ，单电源TTL / CMOS比较器
| 型号： | ADCMP603BCPZ-WP |
| 厂家： | 
ADI |
| 描述： | Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparator |
| 文件： | 总16页 (文件大小：320K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,
Single-Supply TTL/CMOS Comparator
ADCMP603
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
V
CCO
CCI
Fully specified rail to rail at VCC = 2.5 V to 5.5 V
Input common-mode voltage from −0.2 V to VCC + 0.2 V
Low glitch CMOS-/TTL-compatible output stage
Complementary outputs
3.5 ns propagation delay
12 mW at 3.3 V
V
NONINVERTING
INPUT
P
Q OUTPUT
Q OUTPUT
TTL
ADCMP603
V
INVERTING
INPUT
N
Shutdown pin
Single-pin control for programmable hysteresis and latch
Power supply rejection > 50 dB
−40°C to +125°C operation
LE/HYS INPUT
S
INPUT
DN
APPLICATIONS
Figure 1.
High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
Pulse spectroscopy
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators
Automatic test equipment (ATE)
GENERAL DESCRIPTION
The device passes 4.5 kV HBM ESD testing and the absolute
maximum ratings include current limits for all pins.
The ADCMP603 is a very fast comparator fabricated on
XFCB2, an Analog Devices, Inc. proprietary process. This
comparator is exceptionally versatile and easy to use. Features
include an input range from VEE − 0.5 V to VCC + 0.2 V, low noise
complementary TTL-/CMOS-compatible output drivers, latch
inputs with adjustable hysteresis and a shutdown input.
The complementary TTL-/CMOS-compatible output stage is
designed to drive up to 5 pF with full timing specs and to
degrade in a graceful and linear fashion as additional
capacitance is added. The comparator input stage offers robust
protection against large input overdrive, and the outputs do not
phase reverse when the valid input signal range is exceeded.
Latch and programmable hysteresis features are also provided
with a unique single-pin control option.
The device offers 3.5 ns propagation delay with 10 mV
overdrive on 4 mA typical supply current.
A flexible power supply scheme allows the device to operate
with a single +2.5 V positive supply and a −0.5 V to +2.8 V
input signal range up to a +5.5 V positive supply with a −0.5 V
to +5.8 V input signal range. Split input/output supplies with no
sequencing restrictions support a wide input signal range while
still allowing independent output swing control and power
savings.
The ADCMP603 is available in a 12-lead LFCSP package.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADCMP603
TABLE OF CONTENTS
Features .............................................................................................. 1
Application Information................................................................ 10
Power/Ground Layout and Bypassing..................................... 10
TTL-/CMOS-Compatible Output Stage ................................. 10
Using/Disabling the Latch Feature........................................... 10
Optimizing Performance........................................................... 11
Comparator Propagation Delay Dispersion ........................... 11
Comparator Hysteresis .............................................................. 11
Crossover Bias Point .................................................................. 12
Minimum Input Slew Rate Requirement................................ 12
Typical Application Circuits ......................................................... 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Timing Information ......................................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
REVISION HISTORY
10/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADCMP603
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VCCI = VCCO = 2.5 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
DC INPUT CHARACTERISTICS
Voltage Range
Common-Mode Range
Differential Voltage
Offset Voltage
Bias Current
Offset Current
Capacitance
VP, VN
VCC = 2.5 V to 5.5 V
VCC = 2.5 V to 5.5 V
VCC = 2.5 V to 5.5 V
−0.5
−0.2
VCC + 0.2
VCC + 0.2
V
V
V
VCC + 0.8
2
2
VOS
IP, IN
−5.0
−5.0
−2.0
+5.0
+5.0
2.0
mV
μA
μA
pF
kΩ
kΩ
dB
dB
CP, CN
1.0
700
350
85
Resistance, Differential Mode
Resistance, Common Mode
Active Gain
−0.5 V to VCC + 0.2 V
−0.2 V to VCC + 0.2 V
200
100
AV
CMRR
Common-Mode Rejection Ratio
VCCI = 2.5 V, VCCO = 2.5 V,
VCM = −0.2 V to +2.7 V
50
50
V
V
CCI = 5.5 V, VCCO = 5.5 V,
CM = −0.2 V to +5.7 V
dB
Hysteresis
RHYS = ∞
0.1
mV
LATCH ENABLE PIN CHARACTERISTICS
VIH
VIL
IIH
IOL
Hysteresis is shut off
Latch mode guaranteed
VIH = VCC
2.0
−0.2
−6
VCC
+0.8
+6
V
V
μA
mA
+0.4
VIL = 0.4 V
−0.1
HYSTERESIS MODE AND TIMING
Hysteresis Mode Bias Voltage
Resistor Value
Hysteresis Current
Latch Setup Time
Latch Hold Time
Latch-to-Output Delay
Latch Minimum Pulse Width
SHUTDOWN PIN CHARACTERISTICS
VIH
Current sink −1 ꢀA
Hysteresis = 120 mV
Hysteresis = 120 mV
VOD = 50 mV
VOD = 50 mV
VOD = 50 mV
1.145
65
−18
1.25
80
−14
−2.0
2.0
1.35
95
−10
V
kΩ
μA
ns
ns
ns
ns
tS
tH
tPLOH, tPLOL
tPL
30
23
VOD = 50 mV
Comparator is operating
Shutdown guaranteed
VIH = VCC
VIL = 0 V
IOUT < 0.5 mA
VOD = 100 mV, output valid
VCCO = 2.5 V to 5.5 V
IOH = 8 mA VCCO = 2.5 V
IOH = 6 mA VCCO = 2.5 V
IOL = 8 mA, VCCO = 2.5 V
IOL = 6 mA, VCCO = 2.5 V
2.0
−0.2
−6
VCCO
+0.6
+6
V
V
μA
μA
ns
ns
VIL
IIH
IOL
+0.4
−80
20
50
Sleep Time
Wake-Up Time
tSD
tH
DC OUTPUT CHARACTERISTICS
Output Voltage High Level
Output Voltage High Level −40°C
Output Voltage Low Level
Output Voltage Low Level −40°C
VOH
VOH
VOL
VOL
VCC − 0.4
VCC − 0.4
V
V
V
V
0.4
0.4
Rev. 0 | Page 3 of 16
ADCMP603
Parameter
Symbol
tR/tF
Conditions
Min
Typ
Max
Unit
AC PERFORMANCE1
Rise Time /Fall time
10% to 90%, VCCO = 2.5 V
10% to 90%, VCCO = 5.5 V
VOD = 50 mV, VCCO = 2.5 V
VOD = 50 mV, VCCO = 5.5 V
VOD = 10 mV, VCCO = 2.5 V
2.2
4.5
3.5
4.8
5
ns
ns
ns
ns
ns
ps
Propagation Delay
tPD
Propagation Delay Skew—Rising to
Falling Transition
Propagation Delay Skew—Q to QB
tPINSKEW
tDIFFSKEW
VCCO = 2.5 V to 5.5 V
VOD = 50 mV
VCCO =2.5 V to 5.5 V
VOD = 50 mV
500
300
ps
Overdrive Dispersion
Common-Mode Dispersion
10 mV < VOD < 125 mV
−2 V < VCM < VCCI + 2 V
1.5
200
ns
ps
V
OD = 50 mV
Minimum Pulse Width
PWMIN
VCCI = VCCO = 2.5 V
PWOUT = 90% of PWIN
VCCI = VCCO = 5.5 V
3.3
5.5
ns
ns
PWOUT = 90% of PWIN
POWER SUPPLY
Input Supply Voltage Range
Output Supply Voltage Range
Positive Supply Differential
Positive Supply Differential
Input Section Supply Current
Output Section Supply Current
Power Dissipation
VCCI
VCCO
VCCI − VCCO
VCCI − VCCO
IVCCI
IVCCO
PD
PD
PSRR
2.5
2.5
−3.0
−5.5
5.5
5.5
+3.0
+5.5
1.8
3.5
11
V
V
V
V
mA
mA
mW
mW
dB
μA
Operating
Nonoperating
VCCI = 2.5 V to 5.5 V
VCCI = 2.5 V to 5.5 V
VCC = 2.5 V
VCC = 5.5 V
VCCI = 2.5 V to 5.5 V
VCC =2.5 V
1.1
2.3
9
21
30
Power Supply Rejection Ratio
Shutdown Mode Supply Current
−50
290
430
1 VIN = 100 mV square input at 50 MHz, VCM = 0 V, CL = 5 pF, VCCI = VCCO = 2.5 V, unless otherwise noted.
Rev. 0 | Page 4 of 16
ADCMP603
TIMING INFORMATION
Figure 2 illustrates the ADCMP603 latch timing relationships. Table 2 provides definitions of the terms shown in Figure 2.
1.1V
LATCH ENABLE
tS
tPL
tH
V
IN
DIFFERENTIAL
INPUT VOLTAGE
V
± V
OS
N
V
OD
tPDL
tPLOH
Q OUTPUT
50%
50%
tF
tPDH
Q OUTPUT
tPLOL
tR
Figure 2. System Timing Diagram
Table 2. Timing Descriptions
Symbol Timing
Description
tPDH
tPDL
tPLOH
tPLOL
tH
Input to output high delay
Propagation delay measured from the time the input signal crosses the reference ( the
input offset voltage) to the 50% point of an output low-to-high transition.
Propagation delay measured from the time the input signal crosses the reference ( the
input offset voltage) to the 50% point of an output high-to-low transition.
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.
Input to output low delay
Latch enable to output high delay
Latch enable to output low delay
Minimum hold time
Minimum time after the negative transition of the latch enable signal that the input signal
must remain unchanged to be acquired and held at the outputs.
tPL
tS
Minimum latch enable pulse width
Minimum setup time
Minimum time that the latch enable signal must be high to acquire an input signal change.
Minimum time before the negative transition of the latch enable signal occurs that an
input signal change must be present to be acquired and held at the outputs.
tR
Output rise time
Output fall time
Voltage overdrive
Amount of time required to transition from a low to a high output as measured at the 20%
and 80% points.
Amount of time required to transition from a high to a low output as measured at the 20%
and 80% points.
tF
VOD
Difference between the input voltages VA and VB.
Rev. 0 | Page 5 of 16
ADCMP603
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter
Rating
Supply Voltages
Input Supply Voltage (VCCI to GND)
Output Supply Voltage
(VCCO to GND)
−0.5 V to +6.0 V
−0.5 V to +6.0 V
Positive Supply Differential
−6.0 V to +6.0 V
(VCCI − VCCO
Input Voltages
Input Voltage
Differential Input Voltage
Maximum Input/Output Current
Shutdown Control Pin
)
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
−0.5 V to VCCI + 0.5 V
(VCCI + 0.5 V)
50 mA
Table 4. Thermal Resistance
Package Type
1
θJA
Unit
Applied Voltage (HYS to GND)
Maximum Input/Output Current
Latch/Hysteresis Control Pin
Applied Voltage (HYS to GND)
Maximum Input/Output Current
Output Current
−0.5 V to VCCO + 0.5 V
50 mA
ADCMP603 LFCSP 12-lead
62
°C/W
1 Measurement in still air.
ESD CAUTION
−0.5 V to VCCO + 0.5 V
50 mA
50 mA
Temperature
Operating Temperature, Ambient
Operating Temperature, Junction
Storage Temperature Range
−40°C to +125°C
150°C
−65°C to +150°C
Rev. 0 | Page 6 of 16
ADCMP603
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
9
8
7
V
V
1
2
3
EE
CCO
ADCMP603
TOP VIEW
(Not to Scale)
LE/HYS
V
CCI
V
S
DN
EE
Figure 3. ADCMP603 Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
VCCO
VCCI
VEE
Output Section Supply.
Input Section Supply.
Negative Supply Voltage.
4
VP
Noninverting Analog Input.
5
VEE
Negative Supply Voltage.
6
VN
Inverting Analog Input.
7
8
9
SDN
LE/HYS
VEE
Shutdown. Drive this pin low to shut down the device.
Latch/Hysteresis Control. Bias with resistor or current for hysteresis adjustment; drive low to latch.
Negative Supply Voltage.
10
Q
Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the analog
voltage at the inverting input, VN, if the comparator is in compare mode. See the LE/HYS pin description (Pin 8)
for more information.
11
12
VEE
Q
Negative Supply Voltage.
Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the
analog voltage at the inverting input, VN, if the comparator is in compare mode. See the LE pin description
(Pin 8) for more information.
Heat Sink
Paddle
VEE
The metallic back surface of the package is electrically connected to VEE. It can be left floating because Pin 3, Pin 5,
Pin 9, and Pin 11 provide adequate electrical connection. It can also be soldered to the application board if
improved thermal and/or mechanical stability is desired. Exposed metal at package corners is connected to the
heat sink paddle.
Rev. 0 | Page 7 of 16
ADCMP603
TYPICAL PERFORMANCE CHARACTERISTICS
VCCI = VCCO = 2.5 V, TA = 25°C, unless otherwise noted.
4
3
800
600
V
= 5.5V
V
= 2.5V
CC
CC
400
200
2
1
0
–200
–400
–600
–800
0
OUTPUT VOLTAGE
–1
–2
–5
0
5
10
20
15
–1
0
1
2
3
4
5
6
7
LE/HYSTERESIS PIN VOLTAGE (V)
LOAD CURRENT (mA)
Figure 4. LE/HYS Pin I/V Curve
Figure 7. VOL vs. Load Current
200
150
100
50
1000
100
10
V
= 5.5V
CC
V
= 2.5V
CC
V
= 5.5V
CC
V
= 2.5V
CC
0
–50
–100
–150
1
50
–1
0
1
2
3
4
5
6
7
150
250
350
450
550
650
SHUTDOWN PIN VOLTAGE (V)
HYSTERESIS RESISTOR (kΩ)
Figure 5. SDN Pin I/V Curve
Figure 8. Hysteresis vs. RHYS
20
350
300
250
200
150
100
50
V
= 2.5V
I
@ +125°C
CC
B
15
10
I
@ +25°C
B
HYSTERESIS @ +125°C
I
@ –40°C
B
5
HYSTERESIS @ +25°C
0
–5
–10
–15
–20
HYSTERESIS @ –40°C
0
–1.0 –0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
–2
–4
–6
–8
–10
–12
–14
–16
–18
COMMON-MODE VOLTAGE (V)
HYSTERESIS PIN CURRENT (µA)
Figure 9. Hysteresis vs. Hysteresis Pin Current
Figure 6. Input Bias Current vs. Input Common Mode
Rev. 0 | Page 8 of 16
ADCMP603
8
7
6
5
4
3
2
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140
OVERDRIVE (mV)
500mV/DIV
M2.00ns
Figure 10. Propagation Delay vs. Input Overdrive
Figure 12. 50 MHz Output Voltage Waveform at VCCO = 2.5 V
4.0
3.8
V
= 2.5V
CC
3.6
3.4
3.2
3.0
PROP DELAY RISE ns
PROP DELAY FALL ns
–0.6
0
0.6
1.2
1.8
2.4
3.0
COMMON-MODE VOLTAGE (V)
1.00V/DIV
M2.00ns
Figure 13. 50 MHz Output Voltage Waveform at VCCO = 5.5 V
Figure 11. Propagation Delay vs. Input Common Mode
Rev. 0 | Page 9 of 16
ADCMP603
APPLICATION INFORMATION
This delay is measured to the 50% point for the supply in use;
therefore, the fastest times are observed with the VCC supply at
2.5 V, and larger values are observed when driving loads that
switch at other levels.
POWER/GROUND LAYOUT AND BYPASSING
The ADCMP603 comparator is a very high speed device. Despite
the low noise output stage, it is essential to use proper high speed
design techniques to achieve the specified performance. Because
comparators are uncompensated amplifiers, feedback in any phase
relationship is likely to cause oscillations or undesired hysteresis. Of
critical importance is the use of low impedance supply planes,
particularly the output supply plane (VCCO) and the ground plane
(GND). Individual supply planes are recommended as part of a
multilayer board. Providing the lowest inductance return path for
switching currents ensures the best possible performance in the
target application.
When duty cycle accuracy is critical, the logic being driven
should switch at 50% of VCC and load capacitance should be
minimized. When in doubt, it is best to power VCCO or the
entire device from the logic supply and rely on the input PSRR
and CMRR to reject noise.
Overdrive and input slew rate dispersions are not significantly
affected by output loading and VCC variations.
The TTL-/CMOS-compatible output stage is shown in the
simplified schematic diagram (Figure 14). Because of its
inherent symmetry and generally good behavior, this output
stage is readily adaptable for driving various filters and other
unusual loads.
It is also important to adequately bypass the input and output
supplies. Multiple high quality 0.01 μF bypass capacitors should
be placed as close as possible to each of the VCCI and VCCO supply
pins and should be connected to the GND plane with redundant
vias. At least one of these should be placed to provide a physically
short return path for output currents flowing back from ground
to the VCCO pin. High frequency bypass capacitors should be
carefully selected for minimum inductance and ESR. Parasitic
layout inductance should also be strictly controlled to maximize
the effectiveness of the bypass at high frequencies.
V
LOGIC
A1
Q1
+IN
–IN
OUTPUT
If the input and output supplies have been connected separately
such that VCCI ≠ VCCO, care should be taken to bypass each of
these supplies separately to the GND plane. A bypass between
them is futile and defeats the purpose of having separate pins. It
is recommended that the GND plane separate the VCCI and VCCO
planes when the circuit board layout is designed to minimize
coupling between the two supplies and to take advantage of the
additional bypass capacitance from each respective supply to
the ground plane. This enhances the performance when split
input/output supplies are used. If the input and output supplies
A
V
A2
Q2
GAIN STAGE
OUTPUT STAGE
Figure 14. Simplified Schematic Diagram of
TTL-/CMOS-Compatible Output Stage
are connected together for single-supply operation such that VCCI
=
USING/DISABLING THE LATCH FEATURE
VCCO, coupling between the two supplies is unavoidable; however,
The latch input is designed for maximum versatility. It can
safely be left floating for fixed hysteresis or be tied to VCC to
remove the hysteresis, or it can be driven low by any standard
TTL/CMOS device as a high speed latch.
careful board placement can help keep output return currents
away from the inputs.
TTL-/CMOS-COMPATIBLE OUTPUT STAGE
Specified propagation delay performance can be achieved only
In addition, the pin can be operated as a hysteresis control pin
with a bias voltage of 1.25 V nominal and an input resistance of
approximately 7000 Ω, allowing the comparator hysteresis to be
easily controlled by either a resistor or an inexpensive CMOS DAC.
by keeping the capacitive load at or below the specified minimums.
The low skew complementary outputs of the ADCMP603 are
designed to directly drive one Schottky TTL or three low power
Schottky TTL loads or the equivalent. For large fan outputs,
buses, or transmission lines, use an appropriate buffer to
maintain the excellent speed and stability of the comparator.
Hysteresis control and latch mode can be used together if an
open drain, an open collector, or a three-state driver is connected
parallel to the hysteresis control resistor or current source.
With the rated 5 pF load capacitance applied, more than half of
the total device propagation delay is output stage slew time,
even at 2.5 V VCC. Because of this, the total prop delay decreases
as VCCO decreases, and instability in the power supply may
appear as excess delay dispersion.
Due to the programmable hysteresis feature, the logic threshold
of the latch pin is approximately 1.1 V regardless of VCC
.
Rev. 0 | Page 10 of 16
ADCMP603
INPUT VOLTAGE
OPTIMIZING PERFORMANCE
1V/ns
As with any high speed comparator, proper design and layout
techniques are essential for obtaining the specified performance.
Stray capacitance, inductance, inductive power and ground
impedances, or other layout issues can severely limit performance
and often cause oscillation. Large discontinuities along input
and output transmission lines can also limit the specified pulse-
width dispersion performance. The source impedance should
be minimized as much as is practicable. High source impedance,
in combination with the parasitic input capacitance of the
comparator, causes an undesirable degradation in bandwidth at
the input, thus degrading the overall response. Thermal noise
from large resistances can easily cause extra jitter with slowly
slewing input signals; higher impedances encourage undesired
coupling.
V
± V
OS
N
10V/ns
DISPERSION
Q/Q OUTPUT
Figure 16. Propagation Delay—Slew Rate Dispersion
COMPARATOR HYSTERESIS
The addition of hysteresis to a comparator is often desirable in a
noisy environment, or when the differential input amplitudes
are relatively small or slow moving. Figure 17 shows the transfer
function for a comparator with hysteresis. As the input voltage
approaches the threshold (0.0 V, in this example) from below
the threshold region in a positive direction, the comparator
switches from low to high when the input crosses +VH/2, and the
new switching threshold becomes −VH/2. The comparator remains
in the high state until the new threshold, −VH/2, is crossed from
below the threshold region in a negative direction. In this manner,
noise or feedback output signals centered on 0.0 V input cannot
cause the comparator to switch states unless it exceeds the region
bounded by VH/2.
COMPARATOR PROPAGATION
DELAY DISPERSION
The ADCMP603 comparator is designed to reduce propagation
delay dispersion over a wide input overdrive range of 5 mV to
VCCI – 1 V. Propagation delay dispersion is the variation in
propagation delay that results from a change in the degree of
overdrive or slew rate (that is, how far or how fast the input
signal exceeds the switching threshold).
Propagation delay dispersion is a specification that becomes
important in high speed, time-critical applications, such as data
communication, automatic test and measurement, and instru-
mentation. It is also important in event-driven applications, such
as pulse spectroscopy, nuclear instrumentation, and medical
imaging. Dispersion is defined as the variation in propagation
delay as the input overdrive conditions are changed (Figure 15
and Figure 16).
OUTPUT
V
OH
V
OL
ADCMP603 dispersion is typically < 2 ns as the overdrive varies
from 10 mV to 125 mV. This specification applies to both
positive and negative signals because the device has very closely
matched delays for both positive-going and negative-going
inputs.
INPUT
0
–V
2
+V
2
H
H
Figure 17. Comparator Hysteresis Transfer Function
500mV OVERDRIVE
The customary technique for introducing hysteresis into a
comparator uses positive feedback from the output back to the
input. One limitation of this approach is that the amount of
hysteresis varies with the output logic levels, resulting in
hysteresis that is not symmetric about the threshold. The
external feedback network can also introduce significant
parasitics that reduce high speed performance and induce
oscillation in some cases.
INPUT VOLTAGE
10mV OVERDRIVE
V
± V
OS
N
DISPERSION
Q/Q OUTPUT
Figure 15. Propagation Delay—Overdrive Dispersion
Rev. 0 | Page 11 of 16
ADCMP603
1000
100
10
The ADCMP603 comparator offers a programmable hysteresis
feature that can significantly improve accuracy and stability.
Connecting an external pull-down resistor or a current source
from the LE/HYS pin to GND varies the amount of hysteresis in
a predictable, stable manner. Leaving the LE/HYS pin
disconnected or driving it high removes the hysteresis. The
maximum hysteresis that can be applied using this pin is
approximately 160 mV. Figure 18 illustrates the amount of
hysteresis applied as a function of the external resistor value,
and Figure 9 illustrates hysteresis as a function of the current.
V
= 5.5V
CC
V
= 2.5V
CC
The hysteresis control pin appears as a 1.25 V bias voltage seen
through a series resistance of 7 kΩ 20% throughout the hysteresis
control range. The advantages of applying hysteresis in this manner
are improved accuracy, improved stability, reduced component
count, and maximum versatility. An external bypass capacitor is
not recommended on the HYS pin because it impairs the latch
function and often degrades the jitter performance of the device.
As described in the Using/Disabling the Latch Feature section,
hysteresis control need not compromise the latch function.
1
50
150
250
350
450
550
650
HYSTERESIS RESISTOR (kΩ)
Figure 18. Hysteresis vs. RHYS Control Resistor
MINIMUM INPUT SLEW RATE REQUIREMENT
With the rated load capacitance and normal good PC Board
design practice, as discussed in the Optimizing Performance
section, these comparators should be stable at any input slew
rate with no hysteresis. Broadband noise from the input stage is
observed in place of the violent chattering seen with most other
high speed comparators. With additional capacitive loading or
poor bypassing, more persistent oscillations are seen. This
oscillation is due to the high gain bandwidth of the comparator
in combination with feedback parasitics in the package and PC
board. In many applications, chattering is not harmful since the
first cycle of the oscillation occurs close to VOS.
CROSSOVER BIAS POINT
In both op amps and comparators, rail-to-rail inputs of this type
have a dual front-end design. Certain devices are active near the
VCC rail and others are active near the VEE rail. At some predeter-
mined point in the common-mode range, a crossover occurs. At
this point, typically VCC/2, the direction of the bias current reverses
and the measured offset voltages and currents change.
The ADCMP603 slightly elaborates on this scheme. Crossover
points can be found at approximately 0.8 V and 1.6 V.
Rev. 0 | Page 12 of 16
ADCMP603
TYPICAL APPLICATION CIRCUITS
5V
2.5V TO 5V
10kΩ
0.02µF
10kΩ
0.1µF
INPUT
+
OUTPUT
–
ADCMP603
INPUT
2kΩ
CMOS
OUTPUT
V
REF
2kΩ
ADCMP603
0.1µF
LE/HYS
0.1µF
Figure 22. Duty Cycle to Differential Voltage Converter
Figure 19. Self-Biased, 50% Slicer
2.5V TO 5V
ADCMP603
CMOS
V
DD
2.5V TO 5V
LE/HYS
DIGITAL
INPUT
74 AHC
1G07
CMOS
OUTPUT
LVDS
100Ω
ADCMP603
HYSTERESIS
CURRENT
10kΩ
Figure 23. Hysteresis Adjustment with Latch
Figure 20. LVDS-to-CMOS Receiver
2.5V
CMOS
PWM
OUTPUT
ADCMP603
INPUT
1.25V
±50mV
5V
INPUT
1.25V
REF
10kΩ
10kΩ
10kΩ
150pF
OUTPUT
ADCMP603
ADCMP601
LE/HYS
LE/HYS
10kΩ
82pF
100kΩ
10kΩ
CONTROL
VOLTAGE
0V TO 2.5V
150kΩ
150kΩ
Figure 24. Oscillator and Pulse-Width Modulator
Figure 21. Voltage-Controlled Oscillator
Rev. 0 | Page 13 of 16
ADCMP603
2
OUTLINE DIMENSIONS
0.75
0.55
0.35
3.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
*
1.45
1.30 SQ
1.15
10 11
12
4
0.45
1
9
PIN 1
INDICATOR
TOP
VIEW
2.75
BSC SQ
8
7
2
3
6
5
EXPOSED PAD
(BOTTOM VIEW)
0.25 MIN
0.50
BSC
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SEATING
PLANE
0.20 REF
0.30
0.23
0.18
*
COMPLIANT TO JEDEC STANDARDS MO-220-VEED-1
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 25. 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-12-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
CP-12-1
CP-12-1
Branding
G0D
G0D
ADCMP603BCPZ-WP1
ADCMP603BCPZ-R21
12-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
12-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
12-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
ADCMP603BCPZ-R71
CP-12-1
G0D
1 Z = Pb-free part.
Rev. 0 | Page 14 of 16
ADCMP603
NOTES
Rev. 0 | Page 15 of 16
ADCMP603
2
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05915-0-10/06(0)
Rev. 0 | Page 16 of 16
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