ADAU1702JSTZ_技术文档

SigmaDSP^®28-/56-Bit Audio Processor

with Two ADCs and Four DACs

ADAU1702

FEATURES

GENERAL DESCRIPTION

28-/56-bit, 25 MIPS digital audio processor

Two ADCs: SNR of 100 dB, THD + N of −83 dB

Four DACs: SNR of 104 dB, THD + N of −90 dB

Complete standalone operation

Self-boot from serial EEPROM

Auxiliary ADC with 4-input mux for analog control

GPIOs for digital controls and outputs

Fully programmable with SigmaStudio™ graphical tool

28-bit × 28-bit multiplier with 56-bit accumulator for full

double-precision processing

The ADAU1702 is a complete single-chip audio system with a

28-/56-bit audio DSP, ADCs, DACs, and microcontroller-like

control interfaces. Signal processing includes equalization, cross-

over, bass enhancement, multiband dynamics processing, delay

compensation, speaker compensation, and stereo image widening

and can be used to compensate for real-world limitations of

speakers, amplifiers, and listening environments, providing a

dramatic improvements of perceived audio quality.

Its signal processing is comparable to that found in high

end studio equipment. Most processing is done in full 56-bit,

double-precision mode, resulting in very good low level signal

performance. The ADAU1702 is a fully programmable DSP. The

easy to use SigmaStudio software allows the user to graphically

configure a custom signal processing flow using blocks such as

biquad filters, dynamics processors, level controls, and GPIO

interface controls.

Clock oscillator for generating master clock from crystal

PLL for generating master clock from 64 × f_S, 256 × f_S,

384 × f_S, or 512 × f_Sclocks

Flexible serial data input/output ports with I²S-compatible,

left-justified, right-justified, and TDM modes

Sampling rates up to 192 kHz supported

On-chip voltage regulator for compatibility with 3.3 V systems

48-lead, plastic LQFP

APPLICATIONS

ADAU1702 programs can be loaded on power-up either from a

serial EEPROM through its own self-boot mechanism or from

an external microcontroller. On power-down, the current state

of the parameters can be written back to the EEPROM from the

ADAU1702 to be recalled the next time the program is run.

Multimedia speaker systems

MP3 player speaker docks

Automotive head units

Minicomponent stereos

Digital televisions

Studio monitors

Two Σ-Δ ADCs and four Σ-Δ DACs provide a 98.5 dB analog

input to analog output dynamic. Each ADC has a THD + N of

−83 dB, and each DAC has a THD + N of −90 dB. Digital input

and output ports allow a glueless connection to additional

ADCs and DACs. The ADAU1702 communicates through an

I²C® bus or a 4-wire SPI® port.

Speaker crossovers

Musical instrument effects processors

In-seat sound systems (aircraft/motor coaches)

FUNCTIONAL BLOCK DIAGRAM

PLL

DIGITAL DIGITAL ANALOG ANALOG PLL LOOP

VDD

GROUND VDD GROUND MODE FILTER

CRYSTAL

2

3.3V

3

CLOCK

OSCILLATOR

1.8V

REGULATOR

PLL

FILTD/CM

ADAU1702

2

2-CHANNEL

ANALOG

INPUT

DAC

STEREO

ADC

4-CHANNEL

ANALOG

OUTPUT

28-/56-BIT, 25MIPS

AUDIO PROCESSOR CORE

10ms DELAY MEMORY

FILTA/

ADC_RES

2

CONTROL

RESET/

MODE

SELECT

8-CH

DIGITAL

INPUT

8-BIT

AUX

ADC

8-CH

DIGITAL

OUTPUT

INTERFACE

AND

GPIO

SELFBOOT

INPUT/OUTPUT MATRIX

5

4

2

RESET SELF

BOOT

I

C/SPI

AND

DIGITAL IN AUX ADC DIGITAL OUT

OR

WRITEBACK

GPIO

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADAU1702

TABLE OF CONTENTS

Features .............................................................................................. 1

RAMs and Registers....................................................................... 29

Address Maps.............................................................................. 29

Parameter RAM.......................................................................... 29

Data RAM ................................................................................... 29

Read/Write Data Formats ......................................................... 29

Control Register Map..................................................................... 31

Control Register Details ................................................................ 33

2048 to 2055 (0x0800 to 0x0807)—Interface Registers......... 33

2056 (0x808)—GPIO Pin Setting Register.............................. 34

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Analog Performance .................................................................... 3

Digital Input/Output.................................................................... 4

Power.............................................................................................. 4

Temperature Range ...................................................................... 4

PLL and Oscillator........................................................................ 4

Regulator........................................................................................ 5

Digital Timing Specifications ..................................................... 5

Digital Timing Diagrams................................................................. 7

Absolute Maximum Ratings............................................................ 9

Thermal Resistance ...................................................................... 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 13

System Block Diagram................................................................... 14

Overview.......................................................................................... 15

Initialization .................................................................................... 16

Power-Up Sequence ................................................................... 16

Control Registers Setup ............................................................. 16

Recommended Program/Parameter Loading Procedure ..... 16

Power-Reduction Modes ........................................................... 16

Using the Oscillator.................................................................... 17

Setting Master Clock/PLL Mode.............................................. 17

Voltage Regulator ....................................................................... 18

Audio ADCs .................................................................................... 19

Audio DACs .................................................................................... 20

Control Ports................................................................................... 21

I²C Port ........................................................................................ 22

SPI Port ........................................................................................ 25

Self-Boot ...................................................................................... 26

Signal Processing ............................................................................ 28

Numeric Formats........................................................................ 28

Programming.............................................................................. 28

2057 to 2060 (0x809 to 0x80C)—

Auxiliary ADC Data Registers.................................................. 35

2064 to 2068 (0x0810 to 0x814)—Safeload Data Registers.........36

2069 to 2073 (0x0815 to 0x819) Safeload Address Registers ......36

2074 to 2075 (0x081A to 0x081B)—Data Capture Registers......37

2076 (0x081C)—DSP Core Control Register ......................... 38

2078 (0x081E)—Serial Output Control Register ................... 39

2079 (0x081F)—Serial Input Control Register....................... 40

2080 to 2081 (0x0820 to 0x0821)—

Multipurpose Pin Configuration Registers............................. 41

2082 (0x0822)—Auxiliary ADC and Power Control ............ 42

2084 (0x0824)—Auxiliary ADC Enable.................................. 42

2086 (0x0826)—Oscillator Power-Down................................ 42

2087 (0x0827)—DAC Setup...................................................... 43

Multipurpose Pins .......................................................................... 44

Auxiliary ADC............................................................................ 44

General-Purpose Input/Output Pins....................................... 44

Serial Data Input/Output Ports ................................................ 44

Layout Recommendations............................................................. 47

Parts Placement .......................................................................... 47

Grounding................................................................................... 47

Typical Application Schematics.................................................... 48

Self-Boot Mode........................................................................... 48

I²C Control .................................................................................. 49

SPI Control.................................................................................. 50

Outline Dimensions....................................................................... 51

Ordering Guide .......................................................................... 51

REVISION HISTORY

10/06—Revision 0: Initial Version

Rev. 0 | Page 2 of 52

ADAU1702

SPECIFICATIONS

AVDD = 3.3 V, DVDD = 1.8 V, PVDD = 3.3 V, IOVDD = 3.3 V, ambient temperature 25° C, master clock input 12.288 MHz, unless

otherwise noted .

ANALOG PERFORMANCE

Table 1.

Parameter

Min Typ

Max

Unit

Test Conditions/Comments

ADC INPUTS

Number of Channels

Resolution

2

24

Stereo input

Bits

Full-Scale Input

100 (283)

μA_rms(μA_p-p

)

2 V_rmsinput with 20 kΩ (18 kΩ external + 2 kΩ

internal) series resistor

Signal-to-Noise Ratio

A-Weighted

100

dB

Dynamic Range

A-Weighted

Total Harmonic Distortion + Noise

Interchannel Gain Mismatch

Crosstalk

−60 dB with respect to full-scale analog input

−3 dB with respect to full-scale analog input

Analog channel-to-channel crosstalk

95

100

−83

25

−82

1.5

dB

mdB

dB

V

250

+11

DC Bias

Gain Error

−11

%

DAC OUTPUTS

Number of Channels

Resolution

4

24

Two stereo output channels

Bits

Full-Scale Analog Output

Signal-to-Noise Ratio

A-Weighted

0.9 (2.5)

V_rms(V_P-P)

104

dB

Dynamic Range

A-Weighted

Total Harmonic Distortion + Noise

Crosstalk

Interchannel Gain Mismatch

Gain Error

−60 dB with respect to full-scale analog output

99

104

−90

−100

25

dB

mdB

%

−1 dB with respect to full-scale analog output

Analog channel-to-channel crosstalk

250

+10

−10

DC Bias

1.5

V

VOLTAGE REFERENCE

Absolute Voltage (CM, FILTA, FILTD)

AUXILIARY ADC

Full-Scale Analog Input

INL

DNL

Offset

Input Impedance

V

3.0

0.5

1.0

15

V

LSB

mV

kΩ

30

Rev. 0 | Page 3 of 52

ADAU1702

DIGITAL INPUT/OUTPUT

Table 2.

Parameter

Min

Typ

Max

IOVDD

0.8

Unit

V

Comments

Input Voltage, High (V_IH)

Input Voltage, Low (V_IL)

2.0

Input Leakage, High (I_IH)

Input Leakage, Low (I_IL)

1

μA

V

pF

mA

Excluding MCLKI

Excluding MCLKI and bidirectional pins

Bidirectional Pin Pull-Up Current, Low

MCLKI Input Leakage, High (I_IH)

MCLKI Input Leakage, Low (I_IL)

High Level Output Voltage (V_OH), I_OH= 2 mA

Low Level Output Voltage (V_OL), I_OL= 2 mA

Input Capacitance

150

3

2.0

0.8

5

GPIO Output Drive

2

POWER

Table 3.

Parameter

Min

Typ

Max¹

Unit

SUPPLY VOLTAGE

Analog Voltage

Digital Voltage

PLL Voltage

IOVDD Voltage

3.3

1.8

3.3

V

SUPPLY CURRENT

Analog Current (AVDD and PVDD)

Digital Current (DVDD)

Analog Current, Reset

Digital Current, Reset

DISSIPATION

50

40

35

1.5

85

60

55

4.5

mA

Operation (AVDD, DVDD, PVDD)²

286.5

118

mW

Reset, All Supplies

POWER SUPPLY REJECTION RATIO (PSRR)

1 kHz, 200 mV_P-PSignal at AVDD

50

dB

¹Maximum specifications are measured across a temperature range of −40°C to +130°C (case) and across a DVDD range of 1.62 V to 1.98 V and an AVDD range of 2.97 V

to 3.63 V.

²Power dissipation does not include IOVDD power because the current drawn from this supply is dependent on the loads at the digital output pins.

TEMPERATURE RANGE

Table 4.

Parameter

Min

Typ

Max

Unit

Functionality Guaranteed

0°C

70°C

°C ambient

PLL AND OSCILLATOR

Table 5.

Parameter

Min

MCLK_Nom − 20%

Typ

Max

Unit

Comments

PLL Operating Range

MCLK_Nom + 20%

MHz

MCLK_Nom is the nominal input in a

given mode (for example, 12.288 MHz in

256 × f_Smode with a f_sof 48 kHz)

PLL Lock Time

20

ms

Crystal Oscillator g_m

(Transconductance)

78

mmho

Rev. 0 | Page 4 of 52

ADAU1702

REGULATOR

Table 6. Regulator¹

Parameter

Min

Typ

Max

Unit

DVDD Voltage

1.7

1.8

1.84

V

¹Regulator specifications are calculated using a Zetex Semiconductors FZT953 transistor in the circuit.

DIGITAL TIMING SPECIFICATIONS

Table 7. Digital Timing¹

Limit

Parameter

T_MIN

T_MAX

Unit

Description

MASTER CLOCK

t_MP

36

48

73

291

244

366

488

1953

ns

MCLK period, 512 f_Smode.

MCLK period, 384 f_Smode.

MCLK period, 256 f_Smode.

MCLK period, 64 f_Smode.

t_MP

SERIAL PORT

t_BIL

t_BIH

t_LIS

t_LIH

t_SIS

t_SIH

t_LOS

t_LOH

40

10

ns

INPUT_BCLK low pulse width.

INPUT_BCLK high pulse width.

INPUT_LRCLK setup. Time to INPUT_BCLK rising.

INPUT_LRCLK hold. Time from INPUT_BCLK rising.

SDATA_INx setup. Time to BCLK_IN rising.

SDATA_INx hold. Time from BCLK_IN rising.

OUTPUT_LRCLK setup in slave mode.

OUTPUT_LRCLK hold in slave mode.

OUTPUT_BCLK falling to OUTPUT_LRCLK timing skew.

SDATA_OUTx delay. Time from OUTPUT_BCLK falling in slave mode.

SDATA_OUTx delay. Time from OUTPUT_BCLK falling in master mode.

t_TS

5

40

t_SODS

t_SODM

SPI PORT

f_CCLK

t_CCPL

t_CCPH

t_CLS

t_CLH

t_CLPH

t_CDS

t_CDH

t_COD

I²C PORT

f_SCL

t_SCLH

t_SCLL

t_SCS

6.25

MHz

ns

CCLK frequency.

CCLK pulse width low.

CCLK pulse width high.

CLATCH setup. Time to CCLK rising.

CLATCH hold. Time from CCLK rising.

CLATCH pulse width high.

CDATA setup. Time to CCLK rising.

CDATA hold. Time from CCLK rising.

COUT delay. Time from CCLK falling.

80

0

100

80

0

80

101

400

kHz

μs

ns

SCL frequency.

SCL high.

SCL low.

Setup time, relevant for repeated start condition.

Hold time. After this period, the first clock is generated.

Data setup time.

SCL rise time.

SCL fall time.

0.6

1.3

0.6

100

t_SCH

t_DS

t_SCR

t_SCF

t_SDR

t_SDF

300

SDA rise time.

SDA fall time.

t_BFT

0.6

Bus-free time. Time between stop and start.

Rev. 0 | Page 5 of 52

ADAU1702

Limit

T_MAX

Parameter

T_MIN

Unit

Description

MULTIPURPOSE PINS AND RESET

t_GRT

t_GFT

t_GIL

50

1.5 ×

1/f_S

ns

μs

GPIO rise time.

GPIO fall time.

GPIO input latency. Time until high/low value is read by core.

RESET low pulse width.

t_RLPW

20

ns

¹All timing specifications are given for the default (I²S) states of the serial input port and the serial output port (see Table 66).

Rev. 0 | Page 6 of 52

ADAU1702

DIGITAL TIMING DIAGRAMS

t_LIH

t_BIH

BCLK_IN

t_BIL

t_LIS

LRCLK_IN

t_SIS

SDATA_INX

LEFT-JUSTIFIED

MODE

MSB

MSB–1

t_SIH

t_SIS

SDATA_INX

I S MODE

2

MSB

t_SIH

t_SIS

SDATA_INX

RIGHT-JUSTIFIED

MODE

LSB

MSB

t_SIH

8-BIT CLOCKS

(24-BIT DATA)

12-BIT CLOCKS

(20-BIT DATA)

14-BIT CLOCKS

(18-BIT DATA)

16-BIT CLOCKS

(16-BIT DATA)

Figure 2. Serial Input Port Timing

t_LCH

t_BIH

t_TS

BCLK_OUTX

t_BIL

t_LOS

LRCLK_OUTX

t_SODS

t_SODM

SDATA_OUTX

LEFT-JUSTIFIED

MODE

MSB

MSB–1

t_SODS

t_SODM

SDATA_OUTX

2

I S MODE

MSB

t_SODS

t_SODM

SDATA_OUTX

RIGHT-JUSTIFIED

MODE

LSB

MSB

8-BIT CLOCKS

(24-BIT DATA)

12-BIT CLOCKS

(20-BIT DATA)

14-BIT CLOCKS

(18-BIT DATA)

16-BIT CLOCKS

(16-BIT DATA)

Figure 3. Serial Output Port Timing

Rev. 0 | Page 7 of 52

ADAU1702

t_CLS

t_CLH

t_CLPH

t_CCPL

t_CCPH

CLATCH

CCLK

CDATA

t_CDH

t_CDS

COUT

t_COD

Figure 4. SPI Port Timing

t_DS

t_SCH

SDA

t_SCR

t_SCLH

SCLK

t_SCS

t_BFT

t_SCLLt_SCF

Figure 5. I²C Port Timing

t_MP

MCLK

RESET

t_RLPW

RESET

Figure 6. Master Clock and

Timing

Rev. 0 | Page 8 of 52

ADAU1702

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Table 8.

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Parameter

Rating

DVDD to GND

AVDD to GND

IOVDD to GND

Digital Inputs

0 V to 2.2 V

0 V to 4.0 V

DGND − 0.3 V, IOVDD + 0.3 V

Table 9. Thermal Resistance

Package Type

θ_JA

θ_JC

Unit

48-Lead LQFP

72

19.5

°C/W

Maximum Junction Temperature 135°C

Storage Temperature Range

Soldering (10 sec)

−65°C to +150°C

300°C

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. 0 | Page 9 of 52

ADAU1702

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

48 47 46 45 44 43 42 41 40 39 38 37

AGND

ADC1

1

2

36

35

34

33

32

31

30

29

28

27

26

25

AVDD

PLL_LF

PVDD

PGND

MCLKI

OSCO

RSVD

MP2

PIN 1

INDICATOR

ADC_RES

ADC0

3

4

ADAU1702

RESET

SELFBOOT

ADDR0

MP4

5

TOP VIEW

6

(Not to Scale)

7

8

MP5

9

MP3

MP1

10

MP8

MP0 11

DGND

MP9

12

DGND

13 14 15 16 17 18 19 20 21 22 23 24

Figure 7. 48-Lead LQFP Pin Configuration

Table 10. Pin Function Descriptions

Pin No.

Mnemonic

Type¹

Page No. Description

1, 37, 42

AGND

PWR

Analog Ground Pin. The AGND, DGND, and PGND pins can be tied directly

together in a common ground plane. AGND should be decoupled to an

AVDD pin with a 100 nF capacitor.

2

ADC1

A_IN

19

Analog Audio Input 1. Full-scale 100 ꢀA_rmsinput. Current input allows input

voltage level to be scaled with an external resistor. An 18 kΩ resistor gives a

2 V_rmsfull-scale input.

3

4

ADC_RES

ADC0

A_IN

19

ADC Reference Current. The full-scale current of the ADCs can be set with an

external 18 kΩ resistor connected between this pin and ground.

Analog Audio Input 0. Full-scale 100 ꢀA_rmsinput. Current input allows input

voltage level to be scaled with an external resistor. An 18 kΩ resistor gives a

2 V_rmsfull-scale input.

5

6

RESET

D_IN

Active Low Reset Input. Reset is triggered on a high-to-low edge and the

ADAU1702 exits reset on a low-to-high edge. For more information about

initialization, see the Power-Up Sequence section.

Enable/Disable Self-Boot. SELFBOOT selects control port (low) or self-boot

(high). Setting this pin high initiates a self-boot operation when the ADAU1702

is brought out of reset. This pin can be tied directly to the control voltage or

pulled up/down with a resistor.

I²C and SPI Address 0. In combination with ADDR1, this pin allows up to four

ADAU1702s to be used on the same I²C bus and up to two ICs to be used

with a common SPI CLATCH signal.

SELFBOOT

26

22

7

ADDR0

D_IN

8

9

MP4

MP5

MP1

MP0

DGND

D_IO

PWR

44

Multipurpose GPIO or Serial Input Port LRCLK (INPUT_LRCLK).

Multipurpose GPIO or Serial Input Port BCLK (INPUT_BCLK).

Multipurpose GPIO or Serial Input Port Data 1 (SDATA_IN0).

Multipurpose GPIO or Serial Input Port Data 0 (SDATA_IN1).

Digital Ground Pin. The AGND, DGND, and PGND pins can be tied directly

together in a common ground plane. DGND should be decoupled to a

DVDD pin with a 100 nF capacitor.

10

11

12, 25

13, 24

DVDD

PWR

1.8 V Digital Supply. This can be supplied either externally or generated

from a 3.3 V supply with the on-board 1.8 V regulator. DVDD should be

decoupled to DGND with a 100 nF capacitor.

Rev. 0 | Page 10 of 52

ADAU1702

Pin No.

14

15

Mnemonic

MP7

MP6

Type¹

D_IO

Page No. Description

44

Multipurpose GPIO or Serial Output Port Data 1 (SDATA_OUT1).

Multipurpose GPIO, Serial Output Port Data 0, or TDM Data Output

(SDATA_OUT0).

16

17

MP10

VDRIVE

D_IO

A_OUT

44

5

Multipurpose GPIO or Serial Output Port LRCLK (OUTPUT_LRCLK).

Drive for 1.8 V Regulator. The base of the voltage regulator external PNP

transistor is driven from VDRIVE.

18

IOVDD

PWR

Supply for Input and Output Pins. The voltage on this pin sets the highest

input voltage that should be seen on the digital input pins. This pin is also

the supply for the digital output signals on the control port and MP pins.

IOVDD should always be set to 3.3 V. The current draw of this pin is variable

because it is dependent on the loads of the digital outputs.

19

20

MP11

ADDR1/CDATA/WB

D_IO

D_IN

44

Multipurpose GPIO or Serial Output Port BCLK (OUTPUT_BCLK).

22, 24, 26 ADDR1: I²C Address 1. In combination with ADDR0, this sets the I²C address

of the IC so that four ADAU1702s can be used on the same I²C bus.

CDATA: SPI Data Input.

WB: EEPROM Writeback Trigger. A rising (default) or falling (if set in the

EEPROM messages) edge on this pin triggers a writeback of the interface

registers to the external EEPROM. This function can be used to save

parameter data on power-down.

21

CLATCH/WP

D_IO

24, 26

CLATCH: SPI Latch Signal. Must go low at the beginning of an SPI transaction

and high at the end of a transaction. Each SPI transaction can take a different

number of CCLKs to complete, depending on the address and read/write bit

that are sent at the beginning of the SPI transaction.

WP: Self-Boot EEPROM Write Protect. This pin is an open-collector output

when in self-boot mode. The ADAU1702 pulls this low to prohibit writes to

an external EEPROM. This pin should be pulled high to 3.3 V.

22

23

SDA/COUT

SCL/CCLK

D_IO

21, 24

SDA: I²C Data. This pin is a bidirectional open-collector. The line connected

to this pin should have a 2.2 kΩ pull-up resistor.

COUT: This SPI data output is used for reading back registers and memory

locations. It is three-stated when an SPI read is not active.

SCL: I²C Clock. This pin is always an open-collector input when in I²C control

mode. In self-boot mode, this pin is an open-collector output (I²C master).

The line connected to this pin should have a 2.2 kΩ pull-up resistor.

CCLK: SPI Clock. This pin can either run continuously or be gated off in

between SPI transactions.

26

27

28

29

MP9

MP8

MP3

MP2

D_IO/A_IO 44

X

Multipurpose GPIO, Serial Output Port Data 3 (SDATA_OUT3), or Auxiliary

ADC Input 0.

Multipurpose GPIO, Serial Output Port Data 2 (SDATA_OUT2), or Auxiliary

ADC Input 3.

Multipurpose GPIO, Serial Input Port Data 3 (SDATA_IN3), or Auxiliary

ADC Input 2.

Multipurpose GPIO, Serial Input Port Data 2 (SDATA_IN2), or Auxiliary

ADC Input 1.

30

31

RSVD

OSCO

Reserved. Tie to ground, either directly or through a pull-down resistor.

D_OUT

17

Crystal Oscillator Circuit Output. A 100 Ω damping resistor should be

connected between this pin and the crystal. This output should not be used

to directly drive a clock to another IC. If the crystal oscillator is not used, this

pin can be left disconnected.

32

33

MCLKI

PGND

D_IN

PWR

17

Master Clock Input. MCLKI can either be connected to a 3.3 V clock signal or

can be the input from the crystal oscillator circuit.

PLL Ground Pin. The AGND, DGND, and PGND pins can be tied directly

together in a common ground plane. PGND should be decoupled to PVDD

with a 100 nF capacitor.

34

35

PVDD

PWR

3.3 V Power Supply for the PLL and the Auxiliary ADC Analog Section. This

should be decoupled to PGND with a 100 nF capacitor.

PLL Loop Filter Connection. Two capacitors and a resistor need to be connected

to this pin, as shown in the Setting Master Clock/PLL Mode section.

3.3 V Analog Supply. This should be decoupled to AGND with a 100 nF capacitor.

PLL Mode Setting. PLL_MODE0 and PLL_MODE1 set the output frequency

PLL_LF

A_OUT

17

36, 48

38

AVDD

PLL_MODE0

PWR

D_IN

Rev. 0 | Page 11 of 52

ADAU1702

Pin No.

Mnemonic

Type¹

Page No. Description

of the master clock PLL. See the Setting Master Clock/PLL Mode section for

more details.

39

PLL_MODE1

D_IN

17

40

CM

A_OUT

1.5 V Common-Mode Reference. A 47 ꢀF decoupling capacitor should be

connected between this pin and ground to reduce crosstalk between the

ADCs and DACs. The material of the capacitors is not critical. This pin can be

used to bias external analog circuits, as long as they are not drawing current

from CM (for example, the noninverting input of an op amp).

41

FILTD

A_OUT

DAC Filter Decoupling Pin. Should be connected to a 10 ꢀF capacitor to ground.

The capacitor material is not critical. The voltage on the FILTD is 1.5 V.

43

44

45

46

47

VOUT3

VOUT2

VOUT1

VOUT0

FILTA

A_OUT

20

VOUT0 to VOUT3 are the DAC Outputs. Full-scale output voltage is 0.9 V_rms. These

outputs can be used with either active or passive output reconstruction filters.

ADC Filter Decoupling Pin. Should be connected to a 10 ꢀF capacitor to ground.

The capacitor material is not critical. The voltage on the FILTA pin is 1.5 V.

¹PWR = power/ground, A_IN = analog input, D_IN = digital input, A_OUT = analog output, D_IO = digital input/output, D_IO/A_IO = digital input/output or analog

input/output.

Rev. 0 | Page 12 of 52

ADAU1702

TYPICAL PERFORMANCE CHARACTERISTICS

0.10

0.08

0.06

0.04

0.02

0

0.20

f_S= 48kHz

0.15

0.10

0.05

0

–0.02

–0.04

–0.06

–0.08

–0.10

–0.05

–0.10

–0.15

–0.2

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2

FREQUENCY (kHz)

0

0.5

1.0

1.5

2.0

FREQUENCY (kHz)

Figure 10. DAC Pass-Band Filter Response, f_S= 48 kHz

Figure 8. ADC Pass-Band Filter Response, f_S= 48 kHz

10

0

f_S= 48kHz

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

f_S= 48kHz

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

FREQUENCY (kHz)

Figure 9. ADC Stop-Band Filter Response, f_S= 48 kHz

Figure 11. DAC Stop-Band Filter Response, f_S= 48 kHz

Rev. 0 | Page 13 of 52

ADAU1702

SYSTEM BLOCK DIAGRAM

+3.3V

100nF

3.3V TO 1.8V

REGULATOR

CIRCUIT

100nF

10µF

+

10µF

+

IOVDD

PVDD

AVDD

DVDD VDRIVE

18kΩ

ADC0

ADC1

VOUT0

VOUT1

VOUT2

VOUT3

AUDIO ADC

INPUT SIGNALS

18kΩ

DAC OUTPUT FILTERS

(ACTIVEORPASSIVE)

ADC_RES

FILTA

10µF

100nF

FILTD

+

10µF

100nF

MP0

MP1

MP2

MP3

MP4

MP5

MP6

MP7

MP8

MP9

MP10

MP11

MULTIPURPOSE

PIN INTERFACES

ADAU1702

ADCS

DACS

CM

ADDR0

ADDR1/CDATA/WB

CLATCH/WP

EEPROM,

MICROCONTROLLER,

AND/OR SELFBOOT

LOGIC

+3.3V

SDA/COUT

SCL/CCLK

SELFBOOT

475Ω

56nF

3.3nF

PLL_LF

PLL_MODE0

PLL_MODE1

MCLKI

PLL

SETTINGS

RESET LOGIC

RESET

RSVD

3 TO 25MHz

22pF

OSCO

AGND

DGND

PGND

100Ω

22pF

Figure 12. System Block Diagram

Rev. 0 | Page 14 of 52

ADAU1702

OVERVIEW

The core of the ADAU1702 is a 28-bit DSP (56-bit with double-

precision processing) optimized for audio processing. The

program and parameter RAMs can be loaded with a custom

audio processing signal flow built by using SigmaStudio graphical

programming software from Analog Devices, Inc. The values

stored in the parameter RAM control individual signal processing

blocks, such as equalization filters, dynamics processors, audio

delays, and mixer levels. A safeload feature allows for transparent

parameter updates and prevents clicks in the output signals.

variety of different clock speeds. The PLL can accept inputs of

64 × f_S, 256 × f_S, 384 × f_S, or 512 × f_Sto generate the internal

master clock of the core.

The SigmaStudio software is used to program and control the

SigmaDSP through the control port. Along with designing and

tuning a signal flow, the tools can be used to configure all of the

DSP registers and burn a new program into the external EEPROM.

SigmaStudio’s graphical interface allows anyone with digital or

analog audio processing knowledge to easily design a DSP

signal flow and port it to a target application. At the same time,

it provides enough flexibility and programmability for an

experienced DSP programmer to have in-depth control of the

design. In SigmaStudio, the user can connect graphical blocks

(such as biquad filters, dynamics processors, mixers, and

delays), compile the design, and load the program and

parameter files into the ADAU1702 memory through the

control port. Signal processing blocks available in the provided

libraries include

The program RAM, parameter RAM, and register contents can

be saved in an external EEPROM, from which the ADAU1702

can self-boot on start-up. In this standalone mode, parameters

can be controlled through the on-board multipurpose pins. The

ADAU1702 can accept controls from switches, potentiometers,

rotary encoders, and IR receivers. Parameters such as volume

and tone settings can be saved to the EEPROM on power-down

and recalled again on power-up.

The ADAU1702 can operate with digital or analog inputs and

outputs, or a mix of both. The stereo ADC and four DACs each

have an SNR of at least +100 dB and a THD + N of at least

−83 dB. The 8-channel, flexible serial data input/output ports

allow glueless interconnection to a variety of ADCs, DACs,

general-purpose DSPs, S/PDIF receivers and transmitters, and

sample rate converters. The serial ports of the ADAU1702 can

be configured in I²S, left-justified, right-justified, or TDM serial

port compatible modes.

•

Single- and double-precision biquad filters

Processors with peak or rms detection for monochannel

and multichannel dynamics

Mixers and splitters

Tone and noise generators

Fixed and variable gain

Loudness

Delay

Stereo enhancement

Dynamic bass boost

Noise and tone sources

FIR filters

•

Twelve multipurpose (MP) pins allow the ADAU1702 to input

external control signals and output flags or controls to other

devices in the system. The MP pins can be configured as digital

I/Os, inputs to the 4-channel auxiliary ADC, or set up as the

serial data I/O ports. As inputs, they can be connected to buttons,

switches, rotary encoders, potentiometers, IR receivers, or other

external circuitry to control the internal signal processing program.

When configured as outputs, these pins can be used to drive

LEDs, control other ICs, or connect to other external circuitry

in an application.

Level detectors

GPIO control and conditioning

Additional processing blocks are always being developed.

Analog Devices also provides proprietary and third-party

algorithms for applications such as matrix decoding, bass

enhancement, and surround virtualizers. Contact Analog

Devices for information about licensing these algorithms.

The ADAU1702 has a sophisticated control port that supports

complete read/write capability of all memory locations. Control

registers are provided to offer complete control of the chip’s

configuration and serial modes. The ADAU1702 can be

configured for either SPI or I²C control, or can self-boot from

an external EEPROM.

The ADAU1702 operates from a 1.8 V digital power supply

and a 3.3 V analog supply. An on-board voltage regulator can

be used to operate the chip from a single 3.3 V supply. It is

fabricated on a single monolithic, integrated circuit and is

packaged in a 48-lead LQFP for operation over the 0°C to

+70°C temperature range.

An on-board oscillator can be connected to an external crystal

to generate the master clock. In addition, a master clock phase-

locked loop (PLL) allows the ADAU1702 to be clocked from a

Rev. 0 | Page 15 of 52

ADAU1702

INITIALIZATION

This section details the procedure for properly setting up the

ADAU1702. The following five-step sequence provides an

overview of how to initialize the IC:

PLL_MODE1 pins. The reset is synchronized to the falling edge

of the internal clock.

Table 11 lists typical times to boot the ADAU1702 into an

application’s operational state, assuming a 400 kHz I²C clock

loading a full program, parameter set, and all registers (about

6.5 kB). In reality, most applications will not fill the RAMs and

therefore boot time (Column 3 of Table 11) will be less.

1. Apply power to ADAU1702.

2. Wait for PLL to lock.

3. Load SigmaDSP program and parameters.

4. Set up registers (including multipurpose pins and digital

interfaces).

5. Turn off the default muting of the converters, clear the

data registers, and initialize the DAC setup register (see

the Control Registers Setup section for specific settings).

CONTROL REGISTERS SETUP

The following registers must be set as described in this section

to initialize the ADAU1702. These settings are the basic

minimum settings needed to operate the IC with an analog

input/output of 48 kHz. More registers may need to be set,

depending on the application. See the RAMs and Registers

section for additional settings.

To only test analog audio pass-through (ADCs to DACs), Steps 3

and 4 can be skipped and the default internal program can be used.

POWER-UP SEQUENCE

DSP Core Control Register (Address 2076)

Set Bits [4:2] (ADM, DAM, and CR) each to 1.

DAC Setup Register (Address 2087)

Set Bits [0:1] (DS [1:0]) to 01.

The ADAU1702 has a built-in power-up sequence that

initializes the contents of all internal RAMs on power-up or

when the device is brought out of a reset. On the positive edge

of

, the contents of the internal program boot ROM are

RESET

copied to the internal program RAM memory, the parameter

RAM is filled with values (all 0s) from its associated boot ROM,

and all registers are initialized to 0s. The default boot ROM

program copies audio from the inputs to outputs without

processing it (see Figure 13). In this program, serial digital

Input 0 and Input 1 are output on DAC0 and DAC1 and serial

digital Output 0 and Output 1. ADC0 and ADC1 are output on

DAC2 and DAC3. The data memories are also zeroed at power-

up. New values should not be written to the control port until

the initialization is complete.

RECOMMENDED PROGRAM/PARAMETER

LOADING PROCEDURE

When writing large amounts of data to the program or parameter

RAM in direct write mode, the processor core should be disabled

to prevent unpleasant noises from appearing at the audio output.

1. Set Bit 3 and Bit 4 (active low) of the core control register

to 1 to mute the ADCs and DACs. This begins a volume

ramp-down.

2. Set Bit 2 (active low) of the core control register to 1. This

zeroes the SigmaDSP accumulators, the data output registers,

and the data input registers.

3. Fill the program RAM using burst mode writes.

4. Fill the parameter RAM using burst mode writes.

5. Deassert Bit 2 to Bit 4 of the core control register.

Table 11. Power-Up Time

Max Program/

Init.

Time

Parameter/Register

MCLKI Input

Boot Time (I²C)

Total

3.072 MHz (64 × f_S)

85 ms

133 ms

218 ms

156 ms

154 ms

149 ms

144 ms

11.289 MHz (256 × f_S) 23 ms

12.288 MHz (256 × f_S) 21 ms

18.432 MHz (384 × f_S) 16 ms

24.576 MHz (512 × f_S) 11 ms

DAC0

SDATA_OUT0

SDATA_IN0

DAC1

DAC2

DAC3

The PLL start-up time lasts for 2¹⁸cycles of the clock on the

MCLKI pin. This time ranges from 10.7 ms for a 24.576 MHz

(512 × f_S) input clock to 85.3 ms for a 3.072 MHz (64 × f_S) input

clock. This start-up time is measured from the rising edge of

ADC0

ADC1

Figure 13. Default Program Signal Flow

. Following the PLL startup, the duration of the ADAU1702

RESET

POWER-REDUCTION MODES

boot cycle is about 42 μs for a f_Sof 48 kHz. The user should

avoid writing to or reading from the ADAU1702 during this

start-up time. For an MCLK input of 12.288 MHz, the full

initialization sequence (PLL startup plus boot cycle) is

approximately 21 ms. As the device comes out of a reset,

the clock mode is immediately set by the PLL_MODE0 and

Sections of the ADAU1702 chip can be turned on and off as

needed to reduce power consumption. These include the ADCs,

DACs, and voltage reference.

The individual analog sections can be turned off by writing to

the auxiliary ADC and power control register. By default, the

ADCs, DACs, and reference are enabled (all bits set to 0). Each

Rev. 0 | Page 16 of 52

ADAU1702

of these can be turned off by writing a 1 to the appropriate bits

in this register. The ADC power-down mode powers down both

ADCs, and each DAC can be powered down individually. The

current savings is about 15 mA when the ADCs are powered

down and about 4 mA for each DAC that is powered down. The

voltage reference, which is supplied to both the ADCs and

DACs, should only be powered down if all ADCs and DACs are

powered down. The reference is powered down by setting both

Bit 6 and Bit 7 of the control register.

If the oscillator is not utilized in the design, it can be powered

down to save power. This can be done if a system master clock

is already available in the system. By default, the oscillator is

powered on. The oscillator powers down when a 1 is written to

the OPD bit of the oscillator power-down register (see Table 60).

SETTING MASTER CLOCK/PLL MODE

The MCLK input of the ADAU1702 feeds a PLL, which generates

the 25 MIPS SigmaDSP core clock. In normal operation, the

input to MCLK must be one of the following: 64 × f_S, 256 × f_S,

384 × f_S, or 512 × f_S, where f_Sis the input sampling rate. The

mode is set on PLL_MODE0 and PLL_MODE1 as described in

Table 12. If the ADAU1702 is set to receive double-rate signals

(by reducing the number of program steps per sample by a factor

of 2 using the core control register), the master clock frequencies

must be 32 × f_S, 128 × f_S, 192 × f_S, or 256 × f_S. If the ADAU1702

is set to receive quad-rate signals (by reducing the number of

program steps per sample by a factor of 4 using the core control

register), the master clock frequencies must be 16 × f_S, 64 × f_S,

96 × f_S, or 128 × f_S. On power-up, a clock signal must be present

on MCLK so that the ADAU1702 can complete its initialization

routine.

USING THE OSCILLATOR

The ADAU1702 can use an on-board oscillator to generate its

master clock. The oscillator is designed to work with a 256 × f_S

master clock, which is 12.288 MHz for a f_Sof 48 kHz and

11.2896 MHz for a f_Sof 44.1 kHz. The crystal in the oscillator

circuit should be an AT-cut, parallel resonator operating at its

fundamental frequency. Figure 14 shows the external circuit

recommended for proper operation.

ADAU1702

C1

100Ω

OSCO

C2

MCLKI

Table 12. PLL Modes

MCLKI Input

PLL_MODE0

PLL_MODE1

Figure 14. Crystal Oscillator Circuit

64 × f_S

256 × f_S

384 × f_S

512 × f_S

0

1

0

1

0

1

The 100 Ω damping resistor on OSCO gives the oscillator a

voltage swing of approximately 2.2 V. The crystal shunt capaci-

tance should be 7 pF. Its load capacitance should be about 18 pF,

although the circuit supports values of up to 25 pF. The necessary

values of the C1 and C2 load capacitors can be calculated from

the crystal load capacitance as follows:

The clock mode should not be changed without also resetting

the ADAU1702. If the mode is changed during operation, a

click or pop can result in the output signals. The state of the

C1×C2

C1+C2

C_L

=

+C_stray

PLL_MODEx pins should be changed while

is held low.

RESET

where C_strayis the stray capacitance in the circuit and is usually

assumed to be approximately 2 pF to 5 pF.

The PLL loop filter should be connected to the PLL_LF pin. This

filter, shown in Figure 15, includes three passive components—

two capacitors and a resistor. The values of these components

do not need to be exact; the tolerance can be up to 10% for the

resistor and up to 20% for the capacitors. The 3.3 V signal shown in

Figure 15 can be connected to the AVDD supply of the chip.

3.3V

OSCO should not be used to directly drive the crystal signal to

another IC. This signal is an analog sine wave and is not

appropriate to drive a digital input. There are two options for

using the ADAU1702 to provide a master clock to other ICs in

the system. The first, and less recommended method, is to use a

high impedance input digital buffer on the OSCO signal. If this

is done, minimize the trace length to the buffer input. The

second method is to use a clock from the serial output port.

Pin MP11 can be set as an output (master) clock divided down

from the internal core clock. If this pin is set to serial output

port (OUTPUT_BCLK) mode in the multipurpose pin

configuration register (2081) and the port is set to master in

the serial output control register (2078), the desired output

frequency can also be set in the serial output control register

with Bits OBF [1:0] (see Table 49).

475Ω

3.3nF

56nF

ADAU1702

PLL_LF

Figure 15. PLL Loop Filter

Rev. 0 | Page 17 of 52

ADAU1702

Two specifications must be considered when choosing a

regulator transistor: The transistor’s current amplification factor

(h_FEor beta) should be at least 100, and the transistor’s collector

must be able to dissipate the heat generated when regulating

from 3.3 V to 1.8 V. The maximum digital current drawn from

the ADAU1702 is 60 mA. The equation to determine the

minimum power dissipation of the transistor is as follows:

VOLTAGE REGULATOR

The digital voltage of the ADAU1702 must be set to 1.8 V. The

chip includes an on-board voltage regulator that allows the

device to be used in systems without an available 1.8 V supply

but with an available 3.3 V supply. The only external components

needed in such instances are a PNP transistor, a resistor, and a

few bypass capacitors. Only one pin, VDRIVE, is necessary to

support the regulator.

(3.3 V − 1.8 V) × 60 mA = 90 mW

There are many transistors, such as the FZT953 from Zetex

Semiconductors, with these specifications available in small

SOT-23 or SOT-223 packages.

The recommended design for the voltage regulator is shown

in Figure 16. The 10 ꢀF and 100 nF capacitors shown in this

configuration are recommended for bypassing, but are not

necessary for operation. Each DVDD pin should have its own

100 nF bypass capacitor, but only one bulk capacitor (10 ꢀF to

47 ꢀF) is needed for both DVDD pins. With this configuration,

3.3 V is the main system voltage; 1.8 V is generated at the

transistor’s collector, which is connected to the DVDD pins.

VDRIVE is connected to the base of the PNP transistor. If the

regulator is not used in the design, VDRIVE can be tied to

ground.

3.3V

10µF

+

1kΩ

100nF

ADAU1702

DVDD

VDRIVE

Figure 16. Voltage Regulator Configuration

Rev. 0 | Page 18 of 52

ADAU1702

AUDIO ADCS

The ADAU1702 has two Σ-Δ ADCs. The signal-to-noise ratio

(SNR) of the ADCs is 100 dB and the THD + N is −83 dB.

The values of the resistors (internal plus external) in series with

the ADC0 and ADC1 pins can be calculated as follows:

The stereo audio ADCs are current input; therefore, a voltage-

to-current resistor is required on the inputs. This means that

the voltage level of the input signals to the system can be set to

any level; only the input resistors need to be scaled to provide

the proper full-scale current input. The ADC0 and ADC1 input

pins, as well as ADC_RES, have an internal 2 kꢁ resistor for

ESD protection. The voltage seen directly on the ADC input

pins is the 1.5 V common mode.

48,000

f_{S _ NEW}

R_{Input Total}= (RMS Input Voltage)×10 kΩ×

Table 13 lists the external and total resistor values for common

signal input levels at a 48 kHz sampling rate. A full-scale rms

input voltage of 0.9 V is shown in the table because a full-scale

signal at this input level is equal to a full-scale output on the DACs.

Table 13. ADC Input Resistor Values

The external resistor connected to ADC_RES sets the full-scale

current input of the ADCs. The full range of the ADC inputs is

100 ꢀA_rmswith an external 18 kꢁ resistor on ADC_RES (20 kꢁ

total, because it is in series with the internal 2 kꢁ). The only

reason to change the ADC_RES resistor is if a sampling rate

other than 48 kHz is used.

Total ADC0/ADC1

ADC0/ADC1 Input Resistance

Full-Scale

RMS Input

Voltage (V) Value (kΩ)

ADC_RES

Resistor

Value (kΩ)

(External +

Internal) (kΩ)

0.9

1.0

2.0

18

7

8

18

9

10

20

The voltage-to-current resistors connected to ADC0/ADC1 set

the full-scale voltage input of the ADCs. With a full-scale current

input of 100 ꢀA_rms,a 2.0 V_rmssignal with an external 18 kꢁ resistor

(in series with the 2 kꢁ internal resistor) results in an input using

the full range of the ADC. The matching of these resistors to the

ADC_RES resistor is important to the operation of the ADCs.

For these three resistors, a 1% tolerance is recommended.

Figure 17 shows a typical configuration of the ADC inputs for

a 2.0 V_rmsinput signal for a f_Sof 48 kHz. The 47 μF capacitors are

used to ac-couple the signals so that the inputs are biased at 1.5 V.

ADAU1702

47µF

18kΩ

ADC0

Either the ADC0 and/or ADC1 input pins can be left

unconnected if that channel of the ADC is unused.

47µF

ADC1

These calculations of resistor values assume a 48 kHz sample

rate. The recommended input and current setting resistors

scale linearly with the sample rate because the ADCs have a

switched-capacitor input. The total value (2 kꢁ internal plus

external resistor) of the ADC_RES resistor with sample rate

ADC_RES

Figure 17. Audio ADC Input Configuration

f

_{S_NEW}can be calculated as follows:

48,000

f_{S _ NEW}

R_total= 20 kΩ×

Rev. 0 | Page 19 of 52

ADAU1702

AUDIO DACS

The ADAU1702 includes four Σ-Δ DACs. The SNR of the DAC

is 104 dB and the THD + N is −90 dB. A full-scale output on the

DACs is 0.9 V_rms(2.5 V_p-p).

shows a triple-pole, active, low-pass filter that provides a steeper

roll-off and better stop-band attenuation than the passive filter.

In this configuration, the V+ and V− pins of the AD8606 op

amp are set to VDD and ground, respectively.

The DACs are in an inverting configuration. If a signal inversion

from input to output is undesirable, it can be reversed by using

either an inverting configuration for the output filter or by simply

inverting the signal in the SigmaDSP program flow.

To properly initialize the DACs, Bits DS [1:0] in the DAC setup

register (Address 2087) should be set to 01.

47µF

560Ω

FILTER_OUT

DAC_OUT

The DAC outputs can be filtered with either an active or a

passive reconstruction filter. A single-pole, passive low-pass

filter with a 50 kHz corner frequency, as shown in Figure 18, is

sufficient to filter the DAC out-of-band noise, although an

active filter may provide better audio performance. Figure 19

5.6nF

Figure 18. Passive DAC Output Filter

C8

470µF

4.75kΩ 4.75kΩ

47µF

DAC_OUT

604Ω

3.3nF

FILTER_OUT

150pF

49.9kΩ

AD8606

Figure 19. Active DAC Output Filter

Rev. 0 | Page 20 of 52

ADAU1702

CONTROL PORTS

within the ADAU1702 are directly addressable and their sizes

exceed the range of single-byte addressing. All subsequent bytes

(starting with Byte 3) contain the data, such as control port data,

program data, or parameter data. The number of bytes per word

depends on the type of data that is being written. The exact formats

for specific types of writes are shown in Table 22 to Table 31.

The ADAU1702 can operate in one of three control modes:

•

I²C control

SPI control

Self-boot (no external controller)

The ADAU1702 has both a 4-wire SPI control port and a

2-wire I²C bus control port. Each can be used to set the RAMs

and registers. When the SELFBOOT pin is low at power-up, the

part defaults to I²C mode but can be put into SPI control mode

by pulling the CLATCH/WP pin low three times. When the

SELFBOOT pin is set high at power-up, the ADAU1702 loads

its program, parameters, and register settings from an external

EEPROM on startup.

The ADAU1702 has several mechanisms for updating signal

processing parameters in real time without causing pops or

clicks. If large blocks of data need to be downloaded, the output

of the DSP core can be halted (using the CR bit in the DSP core

control register (Address 2076)), new data can be loaded, and

then the device can be restarted. This is typically done during

the booting sequence at start-up or when loading a new program

into RAM. In cases where only a few parameters need to be

changed, they can be loaded without halting the program. To

avoid unwanted side effects while loading parameters on the fly, the

SigmaDSP provides the safeload registers. The safeload registers

can be used to buffer a full set of parameters (for example, the

five coefficients of a biquad) and then transfer these parameters

into the active program within one audio frame. The safeload

mode uses internal logic to prevent contention between the

DSP core and the control port.

The control port is capable of full read/write operation for all

addressable memory and registers. Most signal processing

parameters are controlled by writing new values to the param-

eter RAM using the control port. Other functions, such as mute

and input/output mode control, are programmed by writing to

the registers.

All addresses may be accessed in both a single-address mode or

a burst mode. The first byte (Byte 0) of a control port write

contains the 7-bit chip address plus the R/ bit. The next two

bytes (Byte 1 and Byte 2) together form the subaddress of the

memory or register location within the ADAU1702. This

subaddress must be two bytes because the memory locations

W

The control port pins are multifunctional, depending on the

mode in which the part is operating. Table 14 details these

multiple functions.

Table 14. Control Port Pins and SELFBOOT Pin Functions

I²C Mode

SPI Mode

Self-Boot

SCL/CCLK

SDA/COUT

ADDR1/CDATA/WB

CLATCH/WP

ADDR0

SCL—input

SDA—open-collector output

ADDR1—input

Unused input—tie to ground or VDD

ADDR0—input

CCLK—input

SCL—output

SDA—open-collector output

WB—writeback trigger

WP—EEPROM write protect, open-collector output

Unused input—tie to ground or VDD

COUT—output

CDATA—input

CLATCH—input

ADDR0—input

Rev. 0 | Page 21 of 52

ADAU1702

I²C PORT

Addressing

The ADAU1702 supports a 2-wire serial (I²C-compatible)

microprocessor bus driving multiple peripherals. Two pins,

serial data (SDA) and serial clock (SCL), carry information

between the ADAU1702 and the system I²C master controller.

In I²C mode, the ADAU1702 is always a slave on the bus,

meaning it cannot initiate a data transfer. Each slave device is

recognized by a unique address. The address byte format is

shown in Table 15. The ADAU1702 slave addresses are set with

the ADDR0 and ADDR1 pins. The address resides in the first

seven bits of the I²C write. The LSB of this byte sets either a read

or write operation. Logic Level 1 corresponds to a read operation,

and Logic Level 0 corresponds to a write operation. Bit 5 and

Bit 6 of the address are set by tying the ADDRx pins of the

ADAU1702 to Logic Level 0 or Logic Level 1. The full byte

Initially, each device on the I²C bus is in an idle state and

monitoring the SDA and SCL lines for a start condition and

the proper address. The I²C master initiates a data transfer by

establishing a start condition, defined by a high-to-low transition

on SDA while SCL remains high. This indicates that an address/

data stream follows. All devices on the bus respond to the start

condition and shift the next eight bits (the 7-bit address plus the

R/ bit) MSB first. The device that recognizes the transmitted

W

address responds by pulling the data line low during the ninth

clock pulse. This ninth bit is known as an acknowledge bit. All

other devices withdraw from the bus at this point and return to

the idle condition. The R/ bit determines the direction of the

W

data. A Logic 0 on the LSB of the first byte means the master

will write information to the peripheral, whereas a Logic 1

means the master will read information from the peripheral

after writing the subaddress and repeating the start address. A

data transfer takes place until a stop condition is encountered.

A stop condition occurs when SDA transitions from low to high

while SCL is held high. Figure 20 shows the timing of an I²C

write, and Figure 21 shows an I²C read.

write

addresses, including the pin settings and read/

shown in Table 16.

bit, are

Burst mode addressing, where the subaddresses are automati-

cally incremented at word boundaries, can be used for writing

large amounts of data to contiguous memory locations. This

increment happens automatically after a single-word write unless a

stop condition is encountered. The registers and RAMs in the

ADAU1702 range in width from one to five bytes, so the auto-

increment feature knows the mapping between subaddresses and

the word length of the destination register (or memory location). A

data transfer is always terminated by a stop condition.

Stop and start conditions can be detected at any stage during the

data transfer. If these conditions are asserted out of sequence with

normal read and write operations, the ADAU1702 immediately

jumps to the idle condition. During a given SCL high period,

the user should only issue one start condition, one stop condition,

or a single stop condition followed by a single start condition. If

an invalid subaddress is issued by the user, the ADAU1702 does

not issue an acknowledge and returns to the idle condition. If

the user exceeds the highest subaddress while in auto-increment

mode, one of two actions is taken. In read mode, the ADAU1702

outputs the highest subaddress register contents until the master

device issues a no acknowledge, indicating the end of a read. A

no-acknowledge condition is where the SDA line is not pulled

low on the ninth clock pulse on SCL. If the highest subaddress

location is reached while in write mode, the data for the invalid

byte is not loaded into any subaddress register, a no acknowledge

is issued by the ADAU1702, and the part returns to the idle

condition.

Both SDA and SCL should have 2.2 kꢁ pull-up resistors on the

lines connected to them. The voltage on these signal lines should

not be more than IOVDD (3.3 V).

Table 15. ADAU1702 I²C Address Byte Format

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5

Bit 6

Bit 7

0

1

0

1

ADDR1 ADDR0 R/W

Table 16. ADAU1702 I²C Addresses

Read/Write

ADDR1 ADDR0

Slave Address

0x68

0x69

0x6A

0x6B

0x6C

0x6D

0x6E

0x6F

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Rev. 0 | Page 22 of 52

ADAU1702

SCK

SDA

ADR

SEL

0

R/W

0

ACK. BY

ADAU1702

ACK .BY

ADAU1702

START BY

MASTER

FRAME 2

SUBADDRESS BYTE 1

FRAME 1

CHIP ADDRESS BYTE

SCK

(CONTINUED)

SDA

(CONTINUED)

ACK. BY

ADAU1702

ACK. BY STOP BY

ADAU1702 MASTER

FRAME 3

DATA BYTE 1

FRAME 2

SUBADDRESS BYTE 2

Figure 20. I²C Write to ADAU1702 Clocking

SCK

SDA

ADR

R/W

SEL

ACK. BY

ADAU1702

ACK BY

ADAU1702

START BY

MASTER

FRAME 1

CHIP ADDRESS BYTE

FRAME 2

SUBADDRESS BYTE 1

SCK

(CONTINUED)

SDA

(CONTINUED)

ADR

SEL

R/W

ACK. BY

ACK BY

ADAU1702

REPEATED

START BY MASTER

ADAU1702

FRAME 3

SUBADDRESS BYTE 2

FRAME 4

CHIP ADDRESS BYTE

SCK

(CONTINUED)

SDA

(CONTINUED)

ACK BY

MASTER

ACK. BY

STOP BY

MASTER MASTER

FRAME 5

READ DATA BYTE 1

FRAME 6

READ DATA BYTE 2

Figure 21. I²C Read from ADAU1702 Clocking

Rev. 0 | Page 23 of 52

ADAU1702

I²C Read and Write Operations

data back to the master. The master then responds every ninth

pulse with an acknowledge pulse to the ADAU1702.

Figure 22 shows the timing of a single-word write operation.

Every ninth clock, the ADAU1702 issues an acknowledge by

pulling SDA low.

Figure 25 shows the timing of a burst mode read sequence. This

figure shows an example where the target read registers are two

bytes. The ADAU1702 increments its subaddress every two bytes

because the requested subaddress corresponds to a register or

memory area with word lengths of two bytes. Other address

ranges may have a variety of word lengths ranging from one to

five bytes. The ADAU1702 always decodes the subaddress and

sets the auto-increment circuit so that the address increments

after the appropriate number of bytes.

Figure 23 shows the timing of a burst mode write sequence.

This figure shows an example where the target destination

registers are two bytes. The ADAU1702 knows to increment its

subaddress register every two bytes because the requested

subaddress corresponds to a register or memory area with a

2-byte word length.

The timing of a single-word read operation is shown in Figure 24.

Figure 22 to Figure 25 use the following abbreviations:

S = start bit

P = stop bit

AM = acknowledge by master

AS = acknowledge by slave

Note that the first R/ bit is 0, indicating a write operation. This is

W

because the subaddress still needs to be written to set up the

internal address. After the ADAU1702 acknowledges the receipt

of the subaddress, the master must issue a repeated start command

followed by the chip address byte with the R/ set to 1 (read).

W

This causes the ADAU1702 SDA to reverse and begin driving

S

Chip address, AS Subaddress high AS Subaddress low

R/W = 0

AS Data Byte 1 AS Data Byte 2

…

AS Data Byte N

P

Figure 22. Single-Word I²C Write Format

Chip address, AS Subaddress AS Subaddress AS Data-

AS Data-

Word 1,

Byte 2

AS Data-

Word 2,

Byte 1

AS Data-

Word 2,

AS

…

R/W = 0

high

low

Word 1,

Byte 1

Byte 2

Figure 23. Burst Mode I²C Write Format

S

Chip address, AS Subaddress AS Subaddress AS

S

Chip address, AS Data

AM Data

Byte 2

…

AM Data

Byte N

P

R/W = 0

high

low

R/W = 1

Byte 1

Figure 24. Single-Word I²C Read Format

Chip address,

R/W = 0

AS Subaddress

high

AS Subaddress

low

AS

S

Chip address,

R/W = 1

AS Data-

AM Data-

Word 1,

Byte 2

AM

…

Word 1,

Byte 1

Figure 25. Burst Mode I²C Read Format

Rev. 0 | Page 24 of 52

ADAU1702

SPI PORT

Table 17. ADAU1702 SPI Address Byte Format

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6

ADDR0 R/W

By default, the ADAU1702 is in I²C mode, but can be put into SPI

control mode by pulling CLATCH/WP low three times. The SPI

port uses a 4-wire interface, consisting of CLATCH, CCLK,

CDATA, and COUT signals and is always a slave port. The

CLATCH signal should go low at the beginning of a transaction

and high at the end of a transaction. The CCLK signal latches

CDATA on a low-to-high transition. COUT data is shifted out of

the ADAU1702 on the falling edge of CCLK and should be

clocked into a receiving device, such as a microcontroller, on the

CCLK rising edge. The CDATA signal carries the serial input

data, and the COUT signal is the serial output data. The COUT

signal remains three-stated until a read operation is requested.

This allows other SPI-compatible peripherals to share the same

readback line. All SPI transactions have the same basic format

shown in Table 18. A timing diagram is shown in Figure 4. All

data should be written MSB first. The ADAU1702 cannot be

taken out of SPI mode without a full reset.

Bit 7

0

Subaddress

The 12-bit subaddress word is decoded into a location in one of

the memories or registers. This subaddress is the location of the

appropriate RAM location or register. The MSBs of the subaddress

are zero-padded to bring the word to a full 2-byte length.

Data Bytes

The number of data bytes varies according to the register or

memory being accessed. During a burst mode write, an initial

subaddress is written followed by a continuous sequence of data

for consecutive memory/register locations. The detailed data

format for continuous mode operation is shown in Table 23 and

Table 25 in the Read/Write Data Formats section.

A sample timing diagram for a single-write SPI operation to the

parameter RAM is shown in Figure 26. A sample timing diagram

of a single-read SPI operation is shown in Figure 27. The COUT

pin goes from three-state to being driven at the beginning of

Byte 3. In this example, Byte 0 to Byte 2 contain the addresses

Chip Address R/

W

The first byte of an SPI transaction includes the 7-bit chip address

and a R/ bit. The chip address is set by the ADDR0 pin. This

W

allows two ADAU1702s to share a CLATCH signal, yet still operate

independently. When ADDR0 is low, the chip address is 0000000;

when it is high, the address is 0000001 (see Table 17). The LSB

of this first byte determines whether the SPI transaction is a

read (Logic Level 1) or a write (Logic Level 0).

and R/ bit and subsequent bytes carry the data.

W

Table 18. Generic Control Word Format

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4¹

data

chip_adr [6:0], R/W

0000, subadr [11:8]

subadr [7:0]

data

¹Continues to end of data.

CLATCH

CCLK

CDATA

BYTE 0

BYTE 1

BYTE 2

BYTE 3

Figure 26. SPI Write to ADAU1702 Clocking (Single-Write Mode)

CLATCH

CCLK

CDATA

COUT

BYTE 1

BYTE 0

HI-Z

DATA

Figure 27. SPI Read from ADAU1702 Clocking (Single-Read Mode)

Rev. 0 | Page 25 of 52

ADAU1702

EEPROM Format

SELF-BOOT

The EEPROM data contains a sequence of messages. Each

discrete message is one of the seven types defined in Table 19.

Each message consists of a sequence of one or more bytes. The

first byte identifies the message type. Bytes are written MSB

first. Most messages are block write (0x01) types, which are

used for writing to the ADAU1702 program RAM, parameter

RAM, and control registers.

On power-up, the ADAU1702 can load a program and a set

of parameters that have been saved in an external EEPROM.

Combined with the auxiliary ADC and the multipurpose pins,

this eliminates the need for a microcontroller in the system. The

self-booting is accomplished by the ADAU1702 acting as a master

on the I²C bus on start-up, which occurs when the SELFBOOT

pin is set high. The ADAU1702 cannot self-boot in SPI mode.

The body of the message following the message type should

start with a 0x00 byte—this is the chip address. As with all

other control port transactions, following the chip address is

a 2-byte register/memory address field.

The maximum necessary EEPROM size for program and

parameters is 6688 bytes, or just over 6.5 kB. This does not

include register settings or overhead bytes, but such factors do

not add a significant number of bytes. This much memory is

only needed if the program RAM (512 × five bytes), parameter

RAM (1024 × four bytes), and interface registers (8 × four

bytes) are completely full. An 8 kB EEPROM has sufficient

memory for this application.

Table 20 shows an example of what should be stored in the

EEPROM, starting with EEPROM Address 0. In this example,

the interface registers are first set to control port write mode

(Line 1), which is followed by 18 no-operation (no-op) bytes

(Line 2 to Line 4) so that the interface register data appears on

Page 2 of the EEPROM. Next, follows the write header (Line 4)

and then 32 bytes of interface register data (Line 5 to Line 8).

Finally, the program RAM data, starting at ADAU1702 Address

0x04, 0x00 is written (Line 9 to Line 11). In this example, the

program length is 70 words, or 350 bytes, so 332 more bytes

are included in the EEPROM but are not shown in Table 20.

A self-boot operation is triggered on the rising edge of

RESET

when the SELFBOOT and WP pins are set high. The ADAU1702

reads the program, parameters, and register settings from the

EEPROM. After the ADAU1702 finishes self-booting, additional

messages can be sent to the ADAU1702 on the I²C bus, although

this typically is not necessary in a self-booting application. The

I²C device address is 0x68 for a write and 0x69 for a read in this

mode. The ADDRx pins have different functions when the chip

is in this mode, so the settings on them are ignored.

Writeback

A writeback occurs when the WB pin is triggered and data is

written to the EEPROM from the ADAU1702. This function is

typically used to save the volume setting and other parameter

settings to the EEPROM just before power is removed from the

system. A rising edge on the WB pin triggers a writeback when

the device is in self-boot mode, unless a message to set the WB

to the falling edge sensitive (0x05) is contained in the self-boot

message sequence. Only one writeback takes place unless a

message to set multiple writebacks (0x04) is contained in the

self-boot message sequence. The WP pin is pulled low when a

writeback is triggered to allow writing to the EEPROM.

The ADAU1702 does not self-boot if WP is set low. Holding

this pin low allows the EEPROM to be programmed in-circuit.

The WP pin is pulled low (it typically has a resistor pull-up) to

enable writes to the EEPROM, but this in turn disables the self-

boot function until the WP pin is returned high.

The ADAU1702 is a master on the I²C bus during self-boot and

writeback. Although it is uncommon for an application using

self-boot to also have a microcontroller connected to the control

lines, care should be taken that no other device tries to write to the

I²C bus during self-boot or writeback. The ADAU1702 generates

SCL at 8 × f_S; therefore, for a f_Sof 48 kHz, SCL runs at 384 kHz.

SCL has a duty cycle of 3/8 in accordance with the I²C specification.

The ADAU1702 is only capable of writing back the contents of

the interface registers to the EEPROM. These registers are usually

set by the DSP program, but can also be written to directly after

setting Bit 6 of the core control register. The parameter settings

that should be saved are configured in SigmaStudio.

The ADAU1702 reads from EEPROM Chip Address 0xA1. The

LSBs of the addresses of some EEPROMs are pin configurable;

in most cases, these pins should be tied low to set this address.

Rev. 0 | Page 26 of 52

ADAU1702

The writeback function writes data from the ADAU1702

interface registers to the second page of the self-boot EEPROM,

Address 32 to Address 63. Starting at EEPROM Address 26

(so that the interface register data begins at Address 32), the

EEPROM should be programmed with six bytes—the message

byte (0x01), two length bytes, the chip address (0x00), and the

2-byte subaddress for the interface registers (0x08, 0x00). There

must be a message to the DSP core control register to enable

writing to the interface registers prior to the interface register

data in the EEPROM. This should be stored in EEPROM

Address 0. No-op messages (0x03) can be used in between

messages to ensure that these conditions are met.

The ADAU1702 writes to EEPROM Chip Address 0xA0. The

LSBs of the addresses of some EEPROMs are pin configurable; in

most cases, these pins should be tied low to set the address to 0xA0.

The maximum number of bytes that is written back from the

ADAU1702 is 35 (eight 4-byte interface registers plus three

bytes of EEPROM-addressing overhead). With SCL running at

384 kHz, the writeback operation takes approximately 73 μs to

complete after being triggered. Ensure that sufficient power is

available to the system to allow enough time for a writeback to

complete, especially if the WB signal is triggered from a falling

power supply voltage.

Table 19. EEPROM Message Types

Message ID

Message Type

Following Bytes

0x00

End

None

0x01

Write

Two bytes indicating message length followed by appropriate

number of data bytes

0x02

0x03

0x04

0x05

0x06

Delay

Two bytes for delay

No operation executed

Set multiple writeback

Set WB to falling edge sensitive

End and wait for writeback

None

Table 20. EEPROM Data Example

1

0x01

0x00

0x03

0x05

0x03

0x00

0x08

0x1C

0x00

0x40

Write

Length

Device addr.

Core control register address

Core control register data

2

0x03

0x00

0x03

0x08

0x03

0x00

No-op bytes

3

0x03

0x00

No-op bytes

4

0x01

0x23

0x00

No-op bytes

Write

Length

Device addr.

Interface register address

5

0x00

0x01

0x00

0x61

0x01

0x00

0x01

0x00

Interface register data

6

0x00

Interface register data

7

0x00

Interface register data

8

0x00

Interface register data

9

0x01

0x00

0x04

Write

Length

Device addr.

Program RAM address

Program RAM data

10

11

0x00

0xE8

Program RAM data

0x00

0x00 0x01

0x00

0x08

Program RAM data (continues for 332 more bytes)

Rev. 0 | Page 27 of 52

ADAU1702

SIGNAL PROCESSING

The ADAU1702 is designed to provide all audio signal processing

functions commonly used in stereo or multichannel playback

systems. The signal processing flow is designed using the

SigmaStudio software, which allows graphical entry and real-

time control of all signal processing functions.

with a range of 1.0 (minus 1 LSB) to −1.0. Figure 28 shows the

maximum signal levels at each point in the data flow in both

binary and decibel levels.

4-BIT SIGN EXTENSION

SIGNAL

PROCESSING

(5.23 FORMAT)

SERIAL

PORT

DIGITAL

CLIPPER

DATA IN

Many of the signal processing functions are coded using full,

56-bit, double-precision arithmetic data. The input and output

word lengths of the DSP core are 24 bits. Four extra headroom

bits are used in the processor to allow internal gains of up to

24 dB without clipping. Additional gains can be achieved by

initially scaling down the input signal in the DSP signal flow.

1.23

(0dB)

1.23

(0dB)

1.23

(0dB)

5.23

(24dB)

5.23

(24dB)

Figure 28. Numeric Precision and Clipping Structure

PROGRAMMING

On power-up, the ADAU1702 default program passes the

unprocessed input signals to the outputs (shown in Figure 13),

but the outputs are muted by default (see the Power-Up Sequence

section). There are 512 instruction cycles per audio sample,

resulting in about 25 MIPS available. The SigmaDSP runs in a

stream-oriented manner, meaning that all 512 instructions are

executed each sample period. The ADAU1702 can also be set

up to accept double- or quad-speed inputs by reducing the

number of instructions per sample that are set in the core

control register.

NUMERIC FORMATS

DSP systems commonly use a standard numeric format.

Fractional number systems are specified by an A.B format,

where A is the number of bits to the left of the decimal point

and B is the number of bits to the right of the decimal point.

The ADAU1702 uses the same numeric format for both the

parameter and data values. The format is as follows.

Numerical Format: 5.23

The part can be programmed easily using SigmaStudio (Figure 29),

a graphical tool provided by Analog Devices. No knowledge of

writing line-level DSP code is required. More information about

SigmaStudio can be found at www.analog.com.

Linear range: −16.0 to (+16.0 − 1 LSB)

Examples:

1000 0000 0000 0000 0000 0000 0000 = −16.0

1110 0000 0000 0000 0000 0000 0000 = −4.0

1111 1000 0000 0000 0000 0000 0000 = −1.0

1111 1110 0000 0000 0000 0000 0000 = −0.25

1111 1111 0011 0011 0011 0011 0011 = −0.1

1111 1111 1111 1111 1111 1111 1111 = (1 LSB below 0.0)

0000 0000 0000 0000 0000 0000 0000 = 0.0

0000 0000 1100 1100 1100 1100 1101 = 0.1

0000 0010 0000 0000 0000 0000 0000 = 0.25

0000 1000 0000 0000 0000 0000 0000 = 1.0

0010 0000 0000 0000 0000 0000 0000 = 4.0

0111 1111 1111 1111 1111 1111 1111 = (16.0 − 1 LSB).

The serial port accepts up to 24 bits on the input and is sign-

extended to the full 28 bits of the DSP core. This allows internal

gains of up to 24 dB without internal clipping.

A digital clipper circuit is used between the output of the DSP

core and the DACs or serial port outputs (see Figure 28). This

clips the top four bits of the signal to produce a 24-bit output

Figure 29. SigmaStudio Screen Shot

Rev. 0 | Page 28 of 52

ADAU1702

RAMS AND REGISTERS

Table 21. RAM Map and Read/Write Modes

Memory

Size

Address Range

Read

Yes

Write

Yes

Write Modes

Parameter RAM

Program RAM

Reserved

1024 × 32

512 × 40

N/A

0 to 1023 (0x0000 to 0x03FF)

1024 to 1535 (0x0400 to 0x05FF)

1536 to 2047 (0x0600 to 0x07FF) ²

Direct write¹safeload write

Direct write¹

N/A

No

¹Internal registers should be cleared first to avoid clicks/pops.

²Addresses 1536 to 2047 (0x0600 to 0x07FF) are reserved RAM locations and data can not be written to them.

not busy. This method is not available for writing to the

program RAM or control registers.

ADDRESS MAPS

Table 21 shows the RAM map and Table 32 shows the ADAU1702

register map. The address space encompasses a set of registers

and two RAMs: one holds signal processing parameters and one

holds the program instructions. The program RAM and parameter

RAM are initialized on power-up from on-board boot ROMs

(see the Power-Up Sequence section).

DATA RAM

The ADAU1702 data RAM is used to store audio data words for

processing. For the most part, this process is transparent to the

user. The user cannot directly address this RAM space, which

has a size of 0.5k words, from the control port.

All RAMs and registers have a default value of all 0s, except for

the program RAM, which is loaded with the default program

(see the Initialization section).

Data RAM utilization should be considered when implementing

blocks that require large amounts of data RAM space, such as

delays. The SigmaDSP core processes delay times in one-sample

increments; therefore, the total pool of delay available to the user

equals 512 multiplied by the sample period. For a f_Sof 48 kHz,

the pool of available delay is a maximum of about 11 ms. In

practice, this much data memory is not available to the user

because every block in a design uses a few data memory locations

for its processing. In most DSP programs, this does not signifi-

cantly impact the total delay time. The SigmaStudio compiler

manages the data RAM and indicates if the number of addresses

needed in the design exceeds the maximum available.

PARAMETER RAM

The parameter RAM is 32 bits wide and occupies Address 0

to Address 1023. Each parameter is padded with four 0s before

the MSB to extend the 28-bit word to a full 4-byte width. The

parameter RAM is initialized to all 0s on power-up. The data

format of the parameter RAM is twos complement, 5.23.

This means that the coefficients can range from +16.0 (minus

1 LSB) to −16.0, with 1.0 represented by the binary word

0000 1000 0000 0000 0000 0000 0000 or by the hexadecimal

word 0x00 0x80 0x00 0x00.

READ/WRITE DATA FORMATS

The read/write formats of the control port are designed to

be byte oriented. This allows easy programming of common

microcontroller chips. To fit into a byte-oriented format, 0s are

appended to the data fields before the MSB to extend the data-

word to eight bits. For example, 28-bit words written to the

parameter RAM are appended with four leading 0s to equal

32 bits (4 bytes); 40-bit words written to the program RAM are

not appended with 0s because they are already a full five bytes.

These zero-padded data fields are appended to a 3-byte field

consisting of a 7-bit chip address, a read/write bit, and an 11-bit

RAM/register address. The control port knows how many data

bytes to expect based on the address given in the first three bytes.

The parameter RAM can be written using one of the two

following methods: a direct read/write or a safeload write.

Direct Read/Write

This method allows direct access to the program RAM and

parameter RAM. This mode of operation is typically used

during a complete new loading of the RAM using burst mode

addressing. The clear registers bit in the core control register

should be set to 0 using this mode to avoid any clicks or pops in

the outputs. Note that this mode can be used during live program

execution, but because there is no handshaking between the

core and the control port, the parameter RAM is unavailable to

the DSP core during control writes, resulting in clicks and pops

in the audio stream.

The total number of bytes for a single-location write command

can vary from four bytes (for a control register write) to eight

bytes (for a program RAM write). Burst mode can be used to fill

contiguous register or RAM locations. A burst mode write begins

by writing the address and data of the first RAM or register location

to be written. Rather than ending the control port transaction

(by issuing a stop command in I²C mode or by bringing the

CLATCH signal high in SPI mode after the data-word), as

would be done in a single-address write, the next data-word

can be written immediately without specifying its address. The

Safeload Write

Up to five safeload registers can be loaded with the parameter

RAM address/data. The data is then transferred to the requested

address when the RAM is not busy. This method can be used

for dynamic updates while live program material is playing

through the ADAU1702. For example, a complete update of one

biquad section can occur in one audio frame while the RAM is

Rev. 0 | Page 29 of 52

ADAU1702

ADAU1702 control port auto-increments the address of each write

even across the boundaries of the different RAMs and registers.

Table 23 and Table 25 show examples of burst mode writes.

Table 22. Parameter RAM Read/Write Format (Single Address)

Byte 0

Byte 1

Byte 2

Byte 3

Bytes 4:6

chip_adr [6:0], W/R

000000, param_adr [9:8]

param_adr [7:0]

0000, param [27:24]

param [23:0]

Table 23. Parameter RAM Block Read/Write Format (Burst Mode)

Byte 0

Byte 1

Byte 2

Byte 3

Bytes 4:6

Bytes 7:10

Bytes 11:14

chip_adr [6:0], W/R

000000,

param_adr [7:0] 0000, param [27:24] param [23:0]

param_adr [9:8]

<—param_adr—>

param_adr + 1

param_adr + 2

Table 24. Program RAM Read/Write Format (Single Address)

Byte 0

Byte 1

Byte 2

Bytes 3:7

chip_adr [6:0], W/R

00000, prog_adr [10:8]

prog_adr [7:0]

prog [39:0]

Table 25. Program RAM Block Read/Write Format (Burst Mode)

Byte 0

Byte 1

Byte 2

Bytes 3:7

Bytes 8:12

Bytes 13:17

chip_adr [6:0], W/R

00000, prog_adr [10:8]

prog_adr [7:0]

prog [39:0]

<—prog_adr—>

prog_adr + 1

prog_adr + 2

Table 26. Control Register Read/Write Format (Core, Serial Out 0, Serial Out 1)

Byte 0

Byte 1

Byte 2

Byte 3

data [15:8]

Byte 4

chip_adr [6:0], W/R

0000, reg_adr [11:8]

reg_adr [7:0]

data [7:0]

Table 27. Control Register Read/Write Format (RAM Configuration, Serial Input)

Byte 0

Byte 1

Byte 2

Byte 3

chip_adr [6:0], W/R

0000, reg_adr [11:8]

reg_adr [7:0]

data [7:0]

Table 28. Data Capture Register Write Format

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4

0000, data_capture_adr [11:8]

data_capture_adr [7:0]

000, progCount [10:6]¹progCount [5:0]¹, regSel [1:0]²

chip_adr [6:0], W/R

¹ProgCount [10:0] is the value of the program counter where the data capture occurs (the table of values is generated by the SigmaStudio compiler).

²RegSel [1:0] selects one of four registers (see the 2074 to 2075 (0x081A to 0x081B)—Data Capture Registers section).

Table 29. Data Capture (Control Port Readback) Register Read Format

Byte 0

Byte 1

Byte 2

Bytes 3:5

chip_adr [6:0], W/R

0000, data_capture_adr [11:8]

data_capture_adr [7:0]

data [23:0]

Table 30. Safeload Address Register Write Format

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4

param_adr [7:0]

chip_adr [6:0], W/R

0000, safeload_adr [11:8]

safeload_adr [7:0]

000000, param_adr [9:8]

Table 31. Safeload Data Register Write Format

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4

Bytes 5:7

data [23:0]

chip_adr [6:0], W/R

0000, safeload_adr [11:8] safeload_adr [7:0]

00000000

0000, data [27:24]

Rev. 0 | Page 30 of 52

ADAU1702

CONTROL REGISTER MAP

Table 32. Register Map¹

MSB

LSB

D39 D38 D37 D36 D35 D34 D33 D32

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0