ADAQ4001 [ADI]
16-Bit, 2 MSPS, μModule Data Acquisition Solution;
| 型号： | ADAQ4001 |
| 厂家： | 
ADI |
| 描述： | 16-Bit, 2 MSPS, μModule Data Acquisition Solution |
| 文件： | 总38页 (文件大小：3653K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
ADAQ4001
16-Bit, 2 MSPS, µModule Data Acquisition Solution
FEATURES
GENERAL DESCRIPTION
®
► Improved design journey
The ADAQ4001 is a µModule precision data acquisition (DAQ),
signal chain solution that reduces the development cycle of a preci-
sion measurement system by transferring the signal chain design
challenge of component selection, optimization, and layout from the
designer to the device.
► Fully differential ADC driver with selectable input range
► Input ranges with 5 V VREF: ±10 V, ±5 V, or ±2.5 V
► Essential passive components included
► ±0.005% iPassives matched resistor array
► Wide input common-mode voltage range
► High common-mode rejection ratio
► Single-ended to differential conversion
► Increased signal chain density
► Small, 7 mm × 7 mm, 0.80 mm pitch, 49-ball CSP_BGA
► 4× footprint reduction vs. discrete solution
► On-board reference buffer with VCM generation
► High performance
► Throughput: 2 MSPS, no pipeline delay
► Guaranteed 16-bit no missing codes
► INL: ±4.6 ppm typical, ±11.9 ppm guaranteed
► SINAD: 95.6 dB typical (G = 0.454)
► Offset error drift: 0.7 ppm/°C typical (G = 0.454)
► Gain error drift: ±0.5 ppm/°C typical
► Low total power dissipation: 51.6 mW typical at 2 MSPS
Using system-in-package (SIP) technology, the ADAQ4001 reduces
end system component count by combining multiple common signal
processing and conditioning blocks into a single device. These
blocks include a high resolution 16-bit, 2 MSPS successive approx-
imation register (SAR), analog-to-digital converter (ADC), a low
noise, fully differential ADC driver amplifier (FDA), and a stable
reference buffer.
®
Using Analog Devices, Inc., iPassives technology, the ADAQ4001
also incorporates crucial passive components with superior match-
ing and drift characteristics to minimize temperature dependent
error sources and to offer optimized performance (see Figure 1).
Housing this signal chain solution in a small, 7 mm × 7 mm, 0.80
mm pitch, 49-ball chip scale package ball grid array (CSP_BGA)
enables compact form factor designs without sacrificing perform-
ance and simplifies end system bill of materials management.
This level of system integration makes the ADAQ4001 much less
sensitive to printed circuit board (PCB) layout while still providing
flexibility to adapt to a wide range of signal levels.
™
™
► SPI-/QSPI -/MICROWIRE -/DSP-compatible serial interface
► Versatile logic interface supply with 1.8 V, 2.5 V, 3 V, or 5 V
The serial peripheral interface (SPI)-compatible, serial user inter-
face is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using a
separate VIO supply. The specified operation of theADAQ4001 is
from −40°C to +125°C.
APPLICATIONS
► Automatic test equipment
► Machine automation
► Process controls
Table 1. µModule Data Acquisition Solutions
Type
500 kSPS
≥1000 kSPS
► Medical instrumentation
► Digital control loops
16-Bit
18-bit
ADAQ7988
ADAQ7980, ADAQ4001
ADAQ4003
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
DOCUMENT FEEDBACK
TECHNICAL SUPPORT
Data Sheet
ADAQ4001
TABLE OF CONTENTS
Features................................................................ 1
Applications........................................................... 1
Functional Block Diagram......................................1
General Description...............................................1
Specifications........................................................ 3
Timing Specifications......................................... 7
Absolute Maximum Ratings.................................10
Thermal Resistance......................................... 10
Electrostatic Discharge (ESD) Ratings.............10
ESD Caution.....................................................10
Pin Configuration and Function Descriptions.......11
Typical Performance Characteristics...................13
Terminology......................................................... 19
Theory of Operation.............................................21
Circuit Information ........................................... 21
Transfer Functions........................................... 21
Applications Information...................................... 22
Typical Application Diagrams........................... 22
Analog Inputs................................................... 24
Ease of Drive Features.....................................24
Voltage Reference Input ..................................26
Power Supply (Power Tree)............................. 26
Power-Down Mode...........................................26
Digital Interface................................................ 26
Register Read and Write Functionality.............27
Status Word......................................................29
3-Wire CS Turbo Mode.................................... 30
3-Wire CS Mode Without the Busy Indicator....31
3-Wire CS Mode with the Busy Indicator..........32
4-Wire CS Turbo Mode.................................... 33
4-Wire CS Mode Without the Busy Indicator....34
4-Wire CS Mode with the Busy Indicator..........35
Daisy-Chain Mode ...........................................36
Layout Guidelines.............................................37
Outline Dimensions............................................. 38
Ordering Guide.................................................38
Evaluation Boards............................................ 38
REVISION HISTORY
5/2021—Revision 0: Initial Version
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Rev. 0 | 2 of 38
Data Sheet
ADAQ4001
SPECIFICATIONS
VDD = 1.8 V ± 5%, VS+ = 5.5 V ± 5%, VS− = 0 V, VIO = 1.7 V to 5.5 V, reference voltage (VREF) = 5 V, sampling frequency (fS) = 2 MSPS, all
specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, and turbo mode enabled, unless otherwise noted. ADC driver
configured in single-ended to differential configuration and normal mode, unless otherwise noted.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
RESOLUTION
16
Bit
ANALOG INPUTS
Input Impedance (ZIN
IN+, IN−, R1K1+, R1K1−, R1K+, and R1K−
Single-ended to differential configuration
G = 0.454, input voltage (VIN) = 22 V p-p
G = 0.909, VIN = 11 V p-p
)
1.3
kΩ
kΩ
kΩ
Ω
1.44
1.33
778
G = 1, VIN = 10 V p-p
G = 1.9, VIN = 5.2 V p-p
Fully differential configuration
G = 0.454 and G = 0.909, VIN = 22 V p-p and
11 V p-p
1.1
kΩ
G = 1, VIN = 10 V p-p
G = 1.9, VIN = 5.2 V p-p
G = 0.454, VIN = 22 V p-p
G = 0.909, VIN = 11 V p-p
G = 1, VIN = 10 V p-p
G = 1.9, VIN = 5.2 V p-p
IN+ and IN−
1
kΩ
Ω
V
523
Differential Input Voltage Ranges1
−2.2 × VREF
−1.1 × VREF
−VREF
+2.2 × VREF
+1.1 × VREF
+VREF
V
V
−0.526 × VREF
+0.526 × VREF
V
Input Capacitance
THROUGHPUT
15
pF
Complete Cycle
500
ns
Conversion Time
290
40
320
2
ns
Acquisition Phase2
Throughput Rate3
Transient Response4
DC ACCURACY
290
0
ns
MSPS
µs
Single-ended to differential configuration
All gains, VS− = −1 V
No Missing Codes
Integral Nonlinearity Error (INL)
16
Bits
−11.9
−0.78
−9.56
−0.63
±4.6
±0.3
±3.8
±0.25
57
+11.9
+0.78
+9.56
+0.63
ppm
LSB5
ppm
LSB5
μV
Differential Nonlinearity Error (DNL)
Transition Noise
All gains, VS− = −1 V
G = 0.454
G = 0.909
63.2
60.9
61.3
±0.005
±0.5
±0.1
±0.06
±0.01
+0.7
+1.6
+2.6
90
μV
G = 1
μV
G = 1.9
μV
Gain Error
All gains
−0.05
−3
+0.05
+3
% FS
ppm/°C
mV
Gain Error Drift
Offset Error
All gains
G = 0.454
−1
+1
G = 0.909, G = 1
−0.9
−1.5
−8
+0.9
+1.5
+8
mV
G = 1.9
mV
Offset Error Drift
G = 0.454
ppm/°C
ppm/°C
ppm/°C
dB
G = 0.909 and G = 1
G = 1.9
−10
−15
+10
+15
Common-Mode Rejection Ratio (CMRR)
Power Supply Rejection Ratio (PSRR)
Positive
Fully differential configuration, all gains
VDD = 1.71 V to 1.89 V
72
dB
dB
VS+ = 5.225 V to 5.775 V, VS− = 0 V
110
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Data Sheet
ADAQ4001
SPECIFICATIONS
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
Negative
1/f Noise6
VS+ = +5.5 V, VS− = 0 V to −0.5 V
107
2
dB
RTI, Bandwidth = 0.1 Hz to 10 Hz, Normalized to
0V, all gains
µV p-p
Input Current Noise
AC ACCURACY
Input frequency (fIN) = 100 kHz
1
pA/√Hz
Single-ended to differential and fully differential
configuration
Dynamic Range
All gains, −60 dBFS
93.0
dB
G = 0.454
95.8
95
dB
G = 0.909
dB
G = 1
95.3
95.2
99
dB
G = 1.9
dB
Oversampled Dynamic Range
Total RMS Noise (RTO)
Oversampling ratio (OSR) = 2, all gains
OSR = 256, all gains
G = 0.454
dB
118
57
dB
µV rms
µV rms
µV rms
µV rms
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
dB
G = 0.909
63.2
60.9
61.3
21.7
24
G = 1
G = 1.9
Noise Spectral Density7
G = 0.454
G = 0.909
G = 1
23.2
23.3
G = 1.9
Signal-to-Noise Ratio (SNR)
fIN = 1 kHz, −0.5 dBFS
G = 0.454
92.7
95.6
94.3
95.3
94.9
94.3
87.7
94.5
91.5
dB
G = 0.909
dB
G = 1
dB
G = 1.9
dB
fIN = 100 kHz, G = 0.909
fIN = 400 kHz, G = 0.909
Low power mode enabled, G = 0.909
VS+ = 3.3 V, VS− = 0 V, VREF = 2.5 V, G = 0.909
fIN = 1 kHz, −0.5 dBFS
G = 0.454
dB
dB
dB
dB
Signal-to-Noise + Distortion (SINAD)
92.5
dB
95.6
94.2
95.3
94.8
93.8
85.6
94.4
91.4
−120
−100
−95
dB
G = 0.909
dB
G = 1
dB
G = 1.9
dB
fIN = 100 kHz, G = 0.909
fIN = 400 kHz, G = 0.909
Low power mode enabled, G = 0.909
VS+ = 3.3 V, VS− = 0 V, VREF = 2.5 V, G = 0.909
fIN = 1 kHz, −0.5 dBFS, all gains
fIN = 100 kHz, G = 0.909
fIN = 400 kHz, G = 0.909
Low power mode enabled, G = 0.909
VS+ = 3.3 V, VS− = 0 V, VREF = 2.5 V, G = 0.909
fIN = 1 kHz, −0.5 dBFS, all gains
fIN = 100 kHz, G = 0.909
fIN = 400 kHz, G = 0.909
Low power mode enabled, G = 0.909
VS+ = 3.3 V, VS− = 0 V, VREF = 2.5 V, G = 0.909
dB
dB
dB
dB
Total Harmonic Distortion (THD)
dB
dB
dB
−110
−118
122
dB
dB
Spurious-Free Dynamic Range (SFDR)
dB
101
dB
95
dB
110
dB
118
dB
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Data Sheet
ADAQ4001
SPECIFICATIONS
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
−3 dB Input Bandwidth
Aperture Delay
Aperture Jitter
4.4
1
MHz
ns
1
ps rms
REFERENCE
VREF Range
Buffer enabled
2.4
5.1 or VS+ − 0.08
VREF/2 + 0.003
V
Input Current (IREF
REF_OUT Current (IREF_OUT
VCMO
)
Buffer enabled
60
µA
mA
)
Buffer disabled, 2 MSPS, VREF = 5 V
1.27
8
VCMO Voltage (VVCMO
Output Impedance
DIGITAL INPUTS
Logic Levels
)
VREF/2 − 0.003
VREF/2
5
V
kΩ
SDI, SCK, and CNV
Input Low Voltage (VIL)
Input High Voltage (VIH
Input Low Current (IIL)
VIO > 2.7 V
VIO ≤ 2.7 V
VIO > 2.7 V
VIO ≤ 2.7 V
−0.3
+0.3 × VIO
+0.2 × VIO
VIO + 0.3
VIO + 0.3
+1
V
−0.3
V
)
0.7 × VIO
0.8 × VIO
−1
V
V
µA
µA
pF
Input High Current (IIH
Input Pin Capacitance
DIGITAL OUTPUTS9
Data Format
)
−1
+1
6
Twos complement
0.4
Output Low Voltage (VOL
)
Sink current (ISINK) = +500 µA
V
V
Output High Voltage (VOH
POWER-DOWN MODE
FDA and Reference Buffer
PD_REF, PD_AMP
Low
)
Source current (ISOURCE) = −500 µA
VIO − 0.3
Powered down, low power mode
Enabled, normal mode
All devices enabled
Low to High10
<1
V
V
High
>1.7
Turn-on Time
120
1
μs
μs
High11
POWER REQUIREMENTS
VDD
1.71
1.8
5.5
0
1.89
V
V
V
V
VS+
3
VS− + 10
0.1
VS−
VS+ − 10
1.7
VIO
5.5
Total Standby Current12, 13
Static, all devices enabled
Normal mode
11
14
mA
mA
μA
Low power mode
6.5
100
8.3
250
Power-Down Current
ADC driver, reference buffer disabled
VDD = VIO = 1.8 V, VS+ = 5.5 V, VS− = 0 V
Power Dissipation
Normal Mode
VS+
41.5
9.5
51.5
12.0
0.7
mW
mW
mW
mW
VDD
VIO
0.6
Total
51.6
64.2
High-Z mode enabled
VS+
44.0
53.0
mW
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Data Sheet
ADAQ4001
SPECIFICATIONS
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
VDD
12.8
0.6
16.5
0.7
mW
mW
mW
VIO
Total
57.4
70.2
Low Power Mode
VS+
VDD
VIO
30.2
9.5
37.4
12.0
0.6
mW
mW
mW
mW
0.5
Total
40.2
50.0
High-Z mode enabled
VS+
31.4
12.7
0.5
37.8
16.4
0.6
mW
mW
mW
mW
VDD
VIO
Total
44.6
54.8
TEMPERATURE RANGE
Specified Performance
TMIN to TMAX
−40
+125
°C
1
VIN must be within the allowed input common-mode range as per Figure 35, Figure 36, and Figure 37 and is dependent on the VS+ and VS− supply rails used.
The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS.
2
3
A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 70 MHz. Refer to Table 5 for the maximum achievable throughput
for different modes of operation.
4
5
6
7
8
9
Transient response is the time required for the ADAQ4001 to acquire a full-scale input step to ±1 LSB accuracy.
The weight of the LSB, referred to input, changes depending on the input voltage range. See Table 10 for the LSB size.
See the 1/f noise plot in Figure 28.
Noise Spectral Density for each gain can be calculated using the equation: Total RMS Noise (RTO)/√(π/2xBW), where BW is the -3dB Input Bandwidth equal to 4.4 MHz
The VCMO voltage can be used for other circuitry, but it should be driven with a buffer to ensure the VCMO voltage remains stable as per the specified range.
There is no pipeline delay. Conversion results are available immediately after a conversion is completed.
10The time it takes for a reference buffer to charge a 10 μF reference capcitor to 90% of the reference voltage.
11The time it takes for the FDA to charge the 1 nF filter capacitor to 90 % of the final value.
12With all digital inputs forced to VIO or GND as required.
13The total standby current during the acquisition phase.
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Data Sheet
ADAQ4001
SPECIFICATIONS
TIMING SPECIFICATIONS
VDD = 1.8 V ± 5%, VS+ = 5.5 V ± 5%, VS− = 0 V, VIO = 1.71 V to 5.5V, VREF = 5 V, fS = 2 MSPS, all specifications TMIN to TMAX, high-Z mode
disabled, span compression disabled, and turbo mode enabled, unless otherwise noted.
Table 3. Digital Interface Timing
Parameter
Symbol
Min
Typ
Max
Unit
Conversion Time—CNV Rising Edge to Data Available
Acquisition Phase1
tCONV
tACQ
tCYC
290
320
ns
ns
ns
ns
290
500
10
Time Between Conversions
CNV Pulse Width (CS Mode)2
SCK Period (CS Mode)3
tCNVH
tSCK
VIO > 2.7 V
9.8
ns
ns
VIO > 1.7 V
12.3
SCK Period (Daisy-Chain Mode)4
tSCK
VIO > 2.7 V
20
25
3
ns
ns
ns
ns
ns
VIO > 1.7 V
SCK Low Time
tSCKL
tSCKH
tHSDO
tDSDO
SCK High Time
3
SCK Falling Edge to Data Remains Valid Delay
SCK Falling Edge to Data Valid Delay
VIO > 2.7 V
1.5
7.5
ns
ns
VIO > 1.7 V
10.5
CNV or SDI Low to SDO D15 MSB Valid Delay (CS Mode)
VIO > 2.7 V
tEN
10
13
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VIO > 1.7 V
CNV Rising Edge to First SCK Rising Edge Delay
Last SCK Falling Edge to CNV Rising Edge Delay
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Hold Time from CNV Rising Edge (Daisy-Chain Mode)
SDI Valid Setup Time from SCK Rising Edge (Daisy-Chain Mode)
SDI Valid Hold Time from SCK Rising Edge (Daisy-Chain Mode)
tQUIET1
tQUIET2
tDIS
190
60
20
tSSDICNV
tHSDICNV
tHSCKCNV
tSSDISCK
tHSDISCK
2
2
12
2
2
1
The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS.
For turbo mode, tCNVH must match the tQUIET1 minimum.
2
3
4
A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 70 MHz.
A 50% duty cycle is assumed for SCK.
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Data Sheet
ADAQ4001
SPECIFICATIONS
Table 4. Register Read and Write Timing
Parameter
Symbol
Min
Typ
Max
Unit
READ AND WRITE OPERATION
CNV Pulse Width1
tCNVH
tSCK
10
ns
SCK Period
VIO > 2.7 V
9.8
12.3
3
ns
ns
ns
ns
VIO > 1.7 V
SCK Low Time
tSCKL
tSCKH
SCK High Time
3
READ OPERATION
CNV Low to SDO D15 MSB Valid Delay
VIO > 2.7 V
tEN
10
13
ns
ns
ns
VIO > 1.7 V
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO > 2.7 V
tHSDO
tDSDO
1.5
7.5
10.5
20
ns
ns
ns
VIO > 1.7 V
CNV Rising Edge to SDO High Impedance
WRITE OPERATION
tDIS
SDI Valid Setup Time from SCK Rising Edge
SDI Valid Hold Time from SCK Rising Edge
CNV Rising Edge to SCK Edge Hold Time
CNV Falling Edge to SCK Active Edge Setup Time
tSSDISCK
tHSDISCK
tHCNVSCK
tSCNVSCK
2
2
0
6
ns
ns
ns
ns
1
For turbo mode, tCNVH must match the tQUIET1 minimum.
Figure 2. Voltage Levels for Timing
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Data Sheet
ADAQ4001
SPECIFICATIONS
Table 5. Achievable Throughput for Different Modes of Operation
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
THROUGHPUT, CS MODE
3-Wire and 4-Wire Turbo Mode
SCK frequency (fSCK) = 100 MHz, VIO ≥
2.7 V
2
MSPS
fSCK = 80 MHz, VIO < 2.7 V
fSCK = 100 MHz, VIO ≥ 2.7 V
fSCK = 80 MHz, VIO < 2.7 V
fSCK = 100 MHz, VIO ≥ 2.7 V
fSCK = 80 MHz, VIO < 2.7 V
fSCK = 100 MHz, VIO ≥ 2.7 V
fSCK = 80 MHz, VIO < 2.7 V
2
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
3-Wire and 4-Wire Turbo Mode and Six Status Bits
3-Wire and 4-Wire Mode
2
1.86
1.82
1.69
1.64
1.5
3-Wire and 4-Wire Mode and Six Status Bits
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Data Sheet
ADAQ4001
ABSOLUTE MAXIMUM RATINGS
Table 6.
THERMAL RESISTANCE
Parameter
Rating
Thermal performance is directly linked to PCB design and operating
environment. Careful attention to PCB thermal design is required.
Analog Inputs
R1K+, R1K−,R1K1+, R1K1− to GND
Supply Voltage
−16 V to +16 V or ±18 mA
θJA is the natural convection, junction to ambient thermal resistance
measured in a one cubic foot sealed enclosure.
REF_OUT and VIO to GND
VDD to GND
−0.3 V to +6.0 V
−0.3 V to +2.1 V
−6 V to +2.4 V
11 V
θJC is the junction to case thermal resistance.
VDD to VIO
Table 7. Thermal Resistance
VS+ to VS−
Package Type1
θJA
θJC
Unit
JEDEC Board Layers
VS+ to GND
−0.3 V to +11 V
−11 V to +0.3 V
−0.3 V to VIO +0.3 V
−0.3 V to VIO +0.3 V
BC-49-5
53.5
54.9
°C/W
2S2P
VS− to GND
1
Digital Inputs to GND
Digital Outputs to GND
Temperature
Test Condition 1: thermal impedance simulated values are based upon use of a
2S2P JEDEC standard PCB configuration per JEDEC Standard JESD51-7.
Storage Range
Junction
−65°C to +150°C
150°C
ELECTROSTATIC DISCHARGE (ESD) RATINGS
The following ESD information is provided for handling of ESD-sen-
sitive devices in an ESD protected area only.
Lead Soldering
260°C reflow as per JEDEC
J-STD-020
Human body model (HBM) per ANSI/ESDA/JEDDEC JS-001.
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operat-
ing conditions for extended periods may affect product reliability.
Field induced charged device model (FICDM) per ANSI/ ESDA/JE-
DEC JS-002.
ESD Ratings for the ADAQ4001
Table 8. ADAQ4001, 49-Ball CSP_BGA
ESD Model
Withstand Threshold (V)
Class
HBM
4000
1000
2
FICDM
C4
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Charged devi-
ces and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
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Data Sheet
ADAQ4001
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration, Top View
Figure 4. Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
A1, A7, B5, E6, G1, G7
GND
P
Power Supply Ground.
A2
VDD
P
1.8 V Power Supply. The VDD range is 1.71 V to 1.89 V.
Positive Output of the Fully Differential ADC Driver.
Negative Supply of the Fully Differential ADC Driver.
Reference Buffer Output Voltage.
A3, B3
A4, B4, C3, C4
A5
OUT+
VS−
AO
P
REF_OUT
REF
AO
AI
AI
P
A6
Reference Buffer Input Voltage.
B1, B2
B6, B7
R1K−
VIO
1 kΩ Resistor Input to Negative Input of the Fully Differential ADC Driver.
Input and Output Interface Digital Power. Nominally, the VIO pins are at the same supply as the host interface (1.8
V, 2.5 V, 3 V, or 5 V).
C1, C2
R1K1−
DNC
AI
1.1 kΩ Resistor Input to Negative Input of the Fully Differential ADC Driver.
Do Not Connect. Do not connect to this pin.
C5, D3 to D5, F5, F6
C6
N/A
DI
PD_AMP
Power-Down Amplifier. Active low. Connect the PD_AMP pin to GND to power down the fully differential ADC
driver. Otherwise, connect the PD_AMP pin to logic high.
C7
SDI
DI
Serial Data Input. This input provides multiple features. SDI selects the interface mode of the ADC as follows:
Daisy-chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input
to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is
output on SDO with a delay of 16 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the
serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator feature is
enabled. With CNV low, the device can be programmed by clocking in a 16-bit word on SDI on the rising edge of
SCK.
D1
D2
D6
IN−
AI
AI
DI
Negative Input of the Fully Differential ADC Driver.
Positive Input of the Fully Differential ADC Driver.
IN+
PD_REF
Power-Down Reference Buffer. Active low. Connect the PD_REF pin to GND to power down the reference buffer.
Otherwise, connect the PD_REF pin to logic high.
D7
SCK
DI
AI
Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock.
1.1 kΩ Resistor Input to Positive Input of the Fully Differential ADC Driver.
E1, E2
R1K1+
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Data Sheet
ADAQ4001
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 9. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
E3
MODE
DI
Power Mode for the Fully Differential ADC Driver. Full performance when the MODE pin is high, and low power
mode when the MODE pin is low.
E4, F4, G4, G5
VS+
P
Fully Differential ADC Driver and Reference Buffer Positive Supply.
E5
ADCIN+
SDO
AO
DO
AI
Positive Input to the ADC. Extra capacitance can be added on the ADCIN+ pin to reduce the RC filter bandwidth.
Serial Data Output. The conversion result is output on the SDO pin. SDO synchronizes to SCK.
1 kΩ Resistor Input to Positive Input of the Fully Differential ADC Driver.
E7
F1, F2
F3, G3
F7
R1K+
OUT−
CNV
AO
DI
Negative Output of the Fully Differential ADC Driver.
Convert Input. This input has multiple functions. On its leading edge, CNV initiates the conversions and selects the
interface mode of the device: daisy-chain mode or CS mode. In CS mode, the SDO pin is enabled when CNV is
low. In daisy-chain mode, the data is read when CNV is high.
G2
G6
VCMO
AO
AO
Fully Differential ADC Driver Output Common-Mode Voltage. Nominally, VREF/2.
ADCIN−
Negative Input to the ADC. Extra capacitance can be added on the ADCIN− pin to reduce the RC filter bandwidth.
1
P is power, AO is analog output, AI is analog input, N/A is not applicable, DI is digital input, and DO is digital output.
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Data Sheet
ADAQ4001
TYPICAL PERFORMANCE CHARACTERISTICS
VS+ = 5.5 V, VS− = 0 V, VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, TA = 25°C, high-Z mode disabled, span compression disabled, turbo mode
enabled, and fS = 2 MSPS, unless otherwise noted.
Figure 8. DNL vs. Code for Various Temperatures, VREF = 5 V, G = 0.454
Figure 5. INL vs. Code for Various Temperatures, VREF = 5 V, G = 0.454
Figure 9. Histogram of a DC Input at the Code Center, VREF = 2.5 V and
VREF = 5 V
Figure 6. Histogram of a DC Input at the Code Transition, VREF = 2.5 V and
VREF = 5 V
Figure 10. ADC Driver Open-Loop Gain and Phase vs. Frequency
Figure 7. Transition Noise vs. Temperature for G = 0.454, G = 0.909, G = 1,
and G = 1.9 and VREF = 5 V and VREF = 2.5 V
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Data Sheet
ADAQ4001
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 11. 1 kHz, −0.5 dBFS Input Tone Fast Fourier Transform (FFT),
Wide View, G = 1,VREF = 5 V, Differential
Figure 14. 1 kHz, −0.5 dBFS Input Tone FFT, Wide View, G = 1, VREF = 2.5 V,
Differential
Figure 12. 1 kHz, −0.5 dBFS Input Tone FFT, Wide View, G = 1,VREF = 5 V,
Single-Ended
Figure 15. 1 kHz, −0.5 dBFS Input Tone FFT, Wide View, G = 1, VREF = 2.5 V,
Single-Ended
Figure 13. 1 kHz, −0.5 dBFS Input Tone FFT, Wide View, Differential,
G = 0.909, VREF = 5 V, Low Power Mode
Figure 16. 1 kHz, −0.5 dBFS Input Tone FFT, Wide View, Differential,
G = 0.909, VREF = 2.5 V, Low Power Mode
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Data Sheet
ADAQ4001
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 17. 100 kHz, −0.5 dBFS Input Tone FFT, Wide View, G = 1, VREF = 5 V
Figure 20. 400 kHz, −0.5 dBFS Input Tone FFT, G = 1, Wide View, VREF = 5 V
Figure 18. SNR, SINAD, and Effective Number of Bits (ENOB) vs. Reference
Voltage for G = 0.454, G = 0.909, and G = 1.9, fIN = 1 kHz
Figure 21. THD vs. Reference Voltage, G = 0.454, G = 0.909, and G = 1.9,
fIN = 1 kHz
Figure 19. SNR, SINAD, and ENOB vs. Temperature, G = 1.9, G = 0.909, and
G = 0.454, fIN = 1 kHz
Figure 22. SFDR vs. Reference Voltage for G = 0.454, G = 0.909, and G = 1.9,
fIN = 1 kHz
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Data Sheet
ADAQ4001
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 23. THD vs. Temperature for G = 0.454, G = 0.909, and G = 1.9,
fIN = 1 kHz
Figure 26. SFDR vs. Temperature for G = 0.454, G = 0.909, and G = 1.9,
fIN = 1kHz
Figure 27. THD and SFDR vs. Frequency for G = 0.909 and G = 1.9, VREF = 5 V
Figure 24. SNR, SINAD, and ENOB vs. Frequency for G = 1.9 and G = 0.909,
VREF = 5 V
Figure 28. Voltage Noise for 0.1 Hz to 10 Hz Bandwidth, 100 kSPS, 250
Samples Averaged per Reading
Figure 25. Dynamic Range and SNR vs. Oversampling Rate for G = 0.454,
G = 0.909, and G = 1.9, and for Input Frequencies, 2 MSPS
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Data Sheet
ADAQ4001
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 29. Operating Current vs. Temperature, 2 MSPS
Figure 32. Power vs. Throughput
Figure 30. Gain Error vs. Temperature, VREF = 5.0V, Normal Mode
Figure 33. Offset Error vs. Temperature for G = 0.454, G = 0.909, G = 1, and
G = 1.9
Figure 31. PSRR vs. Frequency
Figure 34. CMRR vs. Frequency for G = 0.454, G = 0.909, and G = 1.9
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Data Sheet
ADAQ4001
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 35. Input Common-Mode Voltage vs. FDA Output Voltage, G = 0.454,
Differential Input
Figure 38. Small Signal Frequency Response and 0.1 dB Flatness for G = 1.9,
G = 0.454, and G = 0.909 at Normal and Low Power Mode
Figure 36. Input Common-Mode Voltage vs. FDA Output Voltage, G = 0.909,
Differential Input
Figure 39. Output Drive Recovery, fIN = 1 kHz
Figure 37. Input Common-Mode Voltage vs. FDA Output Voltage, G = 1.9,
Differential Input
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Data Sheet
ADAQ4001
TERMINOLOGY
Gain Error Drift
Integral Nonlinearity (INL) Error
Gain error drift is the ratio of the gain error change due to a
temperature change of 1°C and the full-scale range. Gain error drift
is expressed in parts per million per degree Celsius as follows:
INL error is the deviation of each individual code from a line drawn
from negative full scale through positive full scale. The point used
as negative full scale occurs ½ LSB before the first code transition.
Positive full scale is defined as a level 1½ LSB beyond the last
code transition. The deviation is measured from the middle of each
code to the true straight line (see Figure 40).
Gain Error Drift (ppm/°C) = 106 × (Gain Error_TMAX − Gain Er-
ror_TMIN) / (TMAX − TMIN
)
where:
Differential Nonlinearity (DNL) Error
TMAX = 125℃.
TMIN = −40℃.
In an ideal ADC, code transitions are 1 LSB apart. DNL is the maxi-
mum deviation from this ideal value. DNL error is often specified in
terms of resolution for which no missing codes are guaranteed.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms amplitude
of the input signal and the peak spurious signal, including harmon-
ics.
Offset Error
The first transition occurs at a level ½ LSB above analog ground.
Offset error is the difference between the ideal midscale input
voltage (0 V) and the actual voltage producing the midscale output
code.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave input.
ENOB is related to SINAD as follows:
Offset Error Drift
ENOB = (SINADdB − 1.76)/6.02
Offset error drift is the ratio of the offset error change due to a
temperature change of 1°C and the full-scale code range. Offset
error drift is expressed in parts per million per degree Celsius as
follows:
ENOB is expressed in bits.
Total Harmonic Distortion (THD)
Offset Error Drift (ppm/°C) = 106 × (Offset Error_TMAX − Offset
THD is the ratio of the rms sum of the first five harmonic compo-
nents to the rms value of a full-scale input signal and is expressed
in decibels.
Error_TMIN / (TMAX − TMIN
)
where:
Dynamic Range
TMAX = 125 ℃.
TMIN = −40 ℃ .
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured. The value for dynamic range is
expressed in decibels. Dynamic range is measured with a signal at
−60 dBFS so that the range includes all noise sources and DNL
artifacts.
Gain Error
The first transition occurs at a level ½ LSB above nominal negative
full scale and the last transition occurs for an analog voltage 1½
LSB below the nominal full scale. The gain error is the deviation
of the difference between the actual level of the last transition and
the actual level of the first transition from the ideal levels after the
offset error is removed. Gain error is expressed as a percentage as
follows:
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Gain Error (%) = 100 × ((PFS − NFS)ACTUAL_CODE − (PFS −
NFS)IDEAL_CODE) / (PFS − NFS)IDEAL_CODE
Signal-to-Noise-and-Distortion Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components that are less than the
Nyquist frequency, including harmonics but excluding dc. The value
of SINAD is expressed in decibels.
where:
PFS is the positive full scale.
NFS is the negative full scale.
Aperture Delay
Aperture delay is the measure of the acquisition performance and
is the time between the rising edge of the CNV input and when the
input signal is held for a conversion.
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Data Sheet
TERMINOLOGY
ADAQ4001
Transient Response
Power Supply Rejection Ratio (PSRR)
Transient response is the time required for the ADC to acquire a
full-scale input step to ±1 LSB accuracy.
PSRR is the ratio of the power in the µModule output at f to the
power of a 500 mV p-p sine wave applied to the VDD and VS+
supply voltage centered at 5 V and 100 mV p-p for a VS− supply
voltage centered at − 1 V of f.
Common-Mode Rejection Ratio (CMRR)
CMRR is the ratio of the power in the µModule output at the
frequency, f, to the power of a 1.3 V p-p sine wave applied to the
input common-mode voltage of f.
PSRR (dB) = 10log(PµModule_IN/PµModule_OUT
)
where:
PµModule_IN is the power at f at each of the VDD, VS+, and VS−
supply pins.
PµModule_OUT is the power at f in the µModule output.
CMRR (dB) = 10log(PµModule_IN/PµModule_OUT
)
where:
PµModule_IN is the common-mode power at f applied to the inputs.
PµModule_OUT is the power at f in the µModule output.
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Data Sheet
ADAQ4001
THEORY OF OPERATION
ADAQ4001 is running at its maximum throughput rate. Note that
for the ADAQ4001, the full throughput rate of 2 MSPS can be
achieved only with turbo mode enabled. Because the ADAQ4001
has on-board conversion clocks, the serial clock (SCK) is not
required for the conversion process.
CIRCUIT INFORMATION
The ADAQ4001 SiP is a fast, precision DAQ signal chain that uses
SAR architecture. As shown in Figure 1, the ADAQ4001 μModule
DAQ solution contains a high bandwidth, fully differential ADC
driver, a low noise reference buffer, and a 16-bit SAR ADC, along
with the critical precision passive components required to achieve
optimized performance with pin-selectable gain options of 0.454,
0.909, 1, or 1.9. All active components in the circuit, including
iPassives thin film resistors with ±0.005% matching, are designed
by Analog Devices and are factory calibrated to achieve a high
degree of specified accuracy and minimize temperature dependent
error sources.
The ADAQ4001 interfaces to any 1.8 V to 5 V digital logic family.
The device is housed in a 7 mm × 7 mm, 0.80 mm pitch, 49-ball
CSP_BGA that provides significant space savings and allows flexi-
ble configurations.
TRANSFER FUNCTIONS
The ideal transfer characteristics for the ADAQ4001 are shown in
Figure 40 and Table 10.
The ADAQ4001 is capable of converting 2,000,000 samples per
second (2 MSPS). The ADAQ4001 has a valid first conversion after
being powered down for long periods that can reduce power con-
sumed in applications where the ADC does not convert constantly.
The ADAQ4001 offers a significant reduction in form factor and total
cost of ownership compared to traditional discrete signal chains
from a selection of individual components, PCB size, and manufac-
turing perspective, while still providing the flexibility to adapt to a
wide array of applications.
The ADAQ4001 incorporates a fully differential, high speed ADC
driver with integrated precision resistors. The precision resistors
can be pin strapped to achieve different gains for the fully differen-
tial ADC driver, which allows the user to match the input signal
range. The fully differential ADC driver can be used in a differential
manner or to perform a single-ended to differential conversion for a
single-ended input.
Figure 40. ADC Ideal Transfer Function (FSR Is Full-Scale Range)
The fast conversion time of the ADAQ4001, along with turbo mode,
allows low clock rates to read back conversions, even when the
Table 10. Output Codes and Ideal Input Voltages
Analog Inputs
Span Compression Enabled
(32,767 × 0.8 × VREF)/(32,768 × G)
Digital Output Code1
(Twos Complement, Hex)
Description
Span Compression Disabled
FSR − 1 LSB
Midscale + 1 LSB
Midscale
(32,767 × VREF)/(32,768 × G)
VREF/(32,768 × G)
0 V
0x7FFF2
0x0001
0x0000
0xFFFF
0x8001
0x80003
0.8 × VREF/(32,768 × G)
0 V
Midscale − 1 LSB
−FSR + 1 LSB
−FSR
−VREF/(32,768 × G)
−(32,767 × VREF)/(32,768 × G)
−VREF × G
−0.8 × VREF/(32,768 × G)
−(32,767 × 0.8 × VREF)/(32,768 × G)
−0.8 × VREF × G
1
This output code assumes that the negative input, IN−, of the ADC driver is being driven.
2
3
This output code is also the code for an overranged analog input (IN+ − IN− above VREF with the span compression disabled and above 0.8 × VREF with the span
compression enabled).
This output code is also the code for an underranged analog input (IN+ − IN− below −VREF with the span compression disabled and below 0.8 × −VREF with the span
compression enabled).
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Data Sheet
ADAQ4001
APPLICATIONS INFORMATION
Table 11. Gain Configuration and Input Range
TYPICAL APPLICATION DIAGRAMS
Input
Range
Input Signal on
Pins
Gain
Test Conditions
Figure 41 through Figure 48 show the recommended connection
diagrams for the ADAQ4001 when applying a single-ended and
differential input signal for four different gain options with respect to
the ground reference. Table 11 shows how the input signal should
be applied for a given gain or input range option.
0.454
±11 V
R1K1−, R1K1+
Leave the IN− and IN+ pins floating.
Connect the OUT+ to R1K− pins and
OUT− to R1K+ pins together. See
Figure 41 and Figure 45.
0.909
1
±5.5 V
±5 V
R1K1−, R1K1+
R1K−, R1K+
Leave the IN−, IN+, R1K−, and R1K+
pins floating. See Figure 42 and
Figure 46.
Leave the IN−, IN+, R1K1−, and
R1K1+ pins floating. See Figure 43
and Figure 47.
1.9
±2.6 V
R1K−/R1K1−,
R1K+/R1K1+
Leave the IN− and IN+ pins floating.
Connect the R1K− to R1K1− pins and
R1K+ to R1K1+ pins together. See
Figure 44 and Figure 48.
Figure 41. Single-Ended to Differential Configuration with G = 0.454
Figure 42. Single-Ended to Differential Configuration with G = 0.909
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Data Sheet
ADAQ4001
APPLICATIONS INFORMATION
Figure 43. Single-Ended to Differential Configuration with G = 1
Figure 44. Single-Ended to Differential Configuration with G = 1.9
Figure 45. Differential Configuration with G = 0.454
Figure 46. Differential Configuration with G = 0.909
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Data Sheet
ADAQ4001
APPLICATIONS INFORMATION
Figure 47. Differential Configuration with G = 1
Figure 48. Differential Configuration with G = 1.9
is disabled by default but can be enabled by writing to the register
(see Table 15). Disable high-Z mode for input frequencies above
100 kHz or when multiplexing.
ANALOG INPUTS
High Frequency Input Signals
Figure 24 and Figure 27 show the ADAQ4001 ac performance
over a wide input frequency range using a 5 V reference voltage.
The ADAQ4001 maintains exceptional ac performance for input
frequencies up to the Nyquist frequency with minimal performance
degradation.
Driving the ADAQ4001 Using a High
Impedance PGIA
The majority of instrumentation and programmable gain instrumen-
tation amplifiers (PGIAs) are single-ended outputs that cannot
directly drive the fully differential data acquisition signal chain. How-
ever, the LTC6373 PGIA offers fully differential outputs, low noise,
low distortion, and high bandwidth. The LTC6373 is dc-coupled on
the input and the output with programmable gain settings (using the
A2, A1, and A0 pins). These features enable the LTC6373 to drive
the ADAQ4001 directly in many signal chain applications without
sacrificing precision performance.
EASE OF DRIVE FEATURES
Input Span Compression
The ADAQ4001 includes a span compression feature that increas-
es the headroom and foot room available to the ADC driver by
reducing the input range by 10% from the top and bottom of the
range while still accessing all available ADC codes. The SNR
decreases by approximately 1.9 dB (20 × log(8/10)) for the reduced
input range when span compression is enabled. Span compression
is disabled by default but can be enabled by writing to the relevant
register bit (see the Digital Interface section).
In Figure 51, the LTC6373 is used in a differential input to dif-
ferential output configuration with dual supplies of ±15 V. The
LTC6373 can also be used in a single-ended input to differential
output configuration, if required. The LTC6373 is directly driving
the ADAQ4001 with its gain set as 0.454. The VOCM pin of the
LTC6373 is connected to ground and its outputs swing between
−5.5 V and +5.5 V (opposite in phase). The FDA of the ADAQ4001
level shifts the outputs of the LTC6373 to match the desired input
common mode of the ADAQ4001 and provides the signal amplitude
necessary to utilize the maximum 2 × VREF peak-to-peak differential
signal range of the ADC inside the ADAQ4001 µModule. Figure
ADC High-Z Mode
The ADAQ4001 incorporates ADC high-Z mode, which reduces the
nonlinear charge kickback when the capacitor DAC switches back
to the input at the start of the acquisition. The ADC high-Z mode
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Data Sheet
ADAQ4001
APPLICATIONS INFORMATION
49 and Figure 50 show the SNR and THD performance using the
various gain settings of the LTC6373 for the circuit configuration
shown in Figure 51.
Figure 50. THD vs. LTC6373 Gain Setting, LTC6373 Driving the ADAQ4001
(Gain = 0.454)
Figure 49. SNR vs. LTC6373 Gain Setting, LTC6373 Driving the ADAQ4001
(Gain = 0.454)
Figure 51. LTC6373 Driving ADAQ4001 (G = 0.454)
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Data Sheet
ADAQ4001
APPLICATIONS INFORMATION
user guide for more details. The ADAQ4001 is insensitive to power
supply variations (PSRR) over a wide frequency range, as shown in
Figure 31.
VOLTAGE REFERENCE INPUT
The ADAQ4001 voltage reference input (REF) is the noninverting
node of the on-board, low noise reference buffer. The reference
buffer is included to optimally drive the dynamic input impedance of
the SAR ADC reference node.
The ADAQ4001 ADC powers down automatically at the end of each
conversion phase. Therefore, the power scales linearly with the
sampling rate. This feature makes the device ideal for low sampling
rates (even a few samples per second) and battery-powered appli-
cations. Figure 32 shows the ADAQ4001 total power dissipation
and individual power dissipation for each rail.
Also housed in the ADAQ4001 is a 10 µF decoupling capacitor that
is ideally laid out within the device. This decoupling capacitor is a
required piece of the SAR architecture. The REF_OUT capacitor is
not just a bypass capacitor. This capacitor is part of the SAR ADC
that cannot fit simply on the silicon. During the bit decision process,
the storage capacitor replenishes the charge of the internal capaci-
tive DAC because the bits are settled in a few tens of nanoseconds
or faster. As the binary bit weighted conversion is processed, small
chunks of charge are taken from the 10 µF capacitor. The internal
capacitor array is a fraction of the size of the decoupling capacitor,
but this large value storage capacitor is required to meet the SAR
bit decision settling time. There is no need for an additional lower
value ceramic decoupling capacitor (for example, 100 nF) between
the REF_OUT and GND pins.
POWER-DOWN MODE
The power-down mode of the FDA is asserted by applying a low
logic level (GND) to the PD_AMP pin to minimize the quiescent
current consumed when the ADAQ4001 is not used. When the
PD_AMP pin is connected to GND, the FDA output is high impe-
dance. When the PD_AMP pin is connected to a high logic level,
the ADAQ4001 operates normally. The logic levels for the PD_AMP
pin are determined by VS+.
DIGITAL INTERFACE
The reference value sets the maximum ADC input voltage that the
SAR capacitor array can quantize. The reference buffer is set in
the unity-gain configuration. Therefore, the user sets the reference
voltage value with the REF pin and observes this value at the
REF_OUT pin. The user is responsible for selecting a reference
voltage value that is appropriate for the system under design.
Allowable reference values range from 2.4 V to 5.1 V. However,
do not violate the input common-mode voltage range specification
of the reference buffer. With the inclusion of the reference buffer,
the user can implement a much lower power reference source than
many traditional SAR ADC signal chains because the reference
source drives a high impedance node instead of the dynamic
load of the SAR capacitor array. Find the root sum square of the
reference buffer noise and the reference source noise to arrive at
a total noise estimate. Generally, the reference buffer has a noise
density much less than that of the reference source.
Although the ADAQ4001 has a reduced number of pins, the device
offers flexibility in its serial interface modes. The ADAQ4001 can
also be programmed via 16-bit SPI writes to the configuration
registers.
™
When in CS mode, the ADAQ4001 is compatible with SPI, QSPI
®
,
MICROWIRE , digital hosts, and digital signal processors (DSPs).
In this mode, the ADAQ4001 can use either a 3-wire or 4-wire
interface. A 3-wire interface using the CNV, SCK, and SDO signals
minimizes wiring connections, which is useful in isolated applica-
tions. A 4-wire interface using the SDI, CNV, SCK, and SDO signals
allows CNV, which initiates the conversions, to be independent
of the readback timing (SDI). This interface is useful in low jitter
sampling or simultaneous sampling applications.
The ADAQ4001 provides a daisy-chain feature using SDI for cas-
cading multiple ADCs on a single data line, similar to a shift
register.
For the highest performance and lower drift, use a reference like
the ADR4550, or use a low power reference like the ADR3450 at
the expense of a decrease in the noise performance.
The mode in which the ADAQ4001 operates depends on the SDI
level when the CNV rising edge occurs. CS mode is selected if SDI
is high, and daisy-chain mode is selected if SDI is low. The SDI
hold time is such that when SDI and CNV are connected together,
daisy-chain mode is automatically selected.
POWER SUPPLY (POWER TREE)
The ADAQ4001 uses four power supply pins: an ADC driver posi-
tive supply (VS+) and negative supply (VS−), a core ADC supply
(VDD), and a digital input and output interface supply (VIO). VIO
allows direct interface with any 1.8 V, 2.5 V, 3 V, or 5 V logic. To
reduce the number of supplies needed, VIO and VDD can be tied
together for 1.8 V operation. A combination of the ADP5070 (dual,
high performance, dc-to-dc switching regulator), the LT3032 (dual,
low noise, positive and negative, low dropout voltage linear regula-
tor), and the LT3023 (dual, micropower, low noise, low dropout
regulator) can generate independently regulated positive and nega-
tive rails for all four power supply pins, including ±15 V rails for any
additional signal conditioning. Refer to the EVAL-ADAQ4001FMCZ
In either 3-wire or 4-wire mode, the ADAQ4001 offers the option of
forcing a start bit in front of the data bits. This start bit can be used
as a busy signal indicator to interrupt the digital host and trigger
the data reading. Otherwise, without a busy indicator, the user must
time out the maximum conversion time prior to readback.
The busy indicator feature is enabled in CS mode if CNV or SDI is
low when the ADC conversion ends.
The state of SDO on power-up is either low or high-Z depending on
the states of CNV and SDI (see Table 12).
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Data Sheet
ADAQ4001
APPLICATIONS INFORMATION
Table 12. State of SDO on Power-Up
Each access to the register map must start with a write to the
8-bit command register in the SPI block. The ADAQ4001 ignores
all 1s until the first 0 is clocked in (represented by WEN in Figure
52, Figure 53, and Table 14). The value loaded into the command
register is always 0 followed by seven command bits. This com-
mand determines whether that operation is a write or a read. The
ADAQ4001 command register is listed in Table 14.
CNV
SDI
SDO
0
0
1
1
0
1
0
1
Low
Low
Low
High-Z
The ADAQ4001 has a turbo mode capability in both 3-wire and 4-
wire mode. Turbo mode is enabled by writing to the configuration
register and replaces the busy indicator feature when enabled. Tur-
bo mode allows a slower SPI clock rate, making interfacing simpler.
The maximum throughput of 2 MSPS for the ADAQ4001 can be
achieved only with turbo mode enabled and a minimum SCK rate
of 70 MHz. The SCK rate must be sufficiently fast to ensure the
conversion result is clocked out before another conversion initiates.
The minimum required SCK rate for an application can be derived
based on the sample period (tCYC), the number of bits that must
be read (including the data and optional status bits), and the digital
interface mode used. Timing diagrams and explanations for each
digital interface mode are provided in the digital modes of operation
sections (see the 3-Wire CS Turbo Mode section and the 4-Wire CS
Mode with the Busy Indicator section).
Table 14. Command Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WEN
R/W
0
1
0
1
0
0
All register read and writes must occur while CNV is low. Data
on SDI is clocked in on the rising edge of SCK. Data on SDO is
clocked out on the falling edge of SCK. At the end of the data
transfer, SDO is put in a high impedance state on the rising edge
of CNV if daisy-chain mode is not enabled. If daisy-chain mode is
enabled, SDO goes low on the rising edge of CNV. Register reads
are not allowed in daisy-chain mode.
A register write requires three signal lines: SCK, CNV, and SDI.
During a register write to read the current conversion results on
SDO, the CNV pin must be brought low after the conversion
completes. Otherwise, the conversion results may be incorrect on
SDO. However, the register write occurs regardless.
Status bits can also be clocked out at the end of the conversion
data if the status bits are enabled in the configuration register. The
six status bits are described in Table 13.
The LSB of each configuration register is reserved because a user
reading 16-bit conversion data may be limited to a 16-bit SPI frame.
The state of SDI on the last bit in the SDI frame may be the state
that persists when CNV rises. Because interface mode is partly set
based on the SDI state when CNV rises, in this scenario, the user
may need to set the final SDI state.
The ADAQ4001 is configured by 16-bit SPI writes to the desired
configuration register. The 16-bit word can be written via the
SDI line while CNV is held low. The 16-bit word consists of an
8-bit header and 8-bit register data. For isolated systems, the
ADuM141D is recommended, which can support the 70 MHz SCK
rate required to run the ADAQ4001 at its full throughput of 2 MSPS.
The timing diagrams in Figure 52 through Figure 54 show how data
is read and written when the ADAQ4001 is configured in register
read, write, and daisy-chain mode.
REGISTER READ AND WRITE FUNCTIONALITY
The ADAQ4001 register bits are programmable, and the default
statuses of the bits are detailed in Table 13. The register map is
shown in Table 15. The OV clamp flag is a read-only sticky bit, and
this bit is cleared only if the register is read and the overvoltage
condition is no longer present. The OV clamp flag indicates the
overvoltage condition when this bit is set to 0.
Table 13. Register Bits
Register Bits
Default Status
OV Clamp Flag
Span Compression
High-Z Mode
1 bit, 1 = inactive (default)
1 bit, 0 = disabled (default)
1 bit, 0 = disabled (default)
1 bit, 0 = disabled (default)
1 bit, 0 = disabled (default)
Turbo Mode
Enable Six Status Bits
Table 15. Register Map
ADDR, Bits[1:0] Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
0x0
Reserved
Reserved
Reserved
Enable six
status bits
Span
compression
High-Z
mode
Turbo
mode
OV clamp flag (read only sticky
bit)
0xE1
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Data Sheet
ADAQ4001
APPLICATIONS INFORMATION
Figure 52. Register Read Timing Diagram
Figure 53. Register Write Timing Diagram
Figure 54. Register Write Timing Diagram, Daisy-Chain Mode
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Data Sheet
ADAQ4001
APPLICATIONS INFORMATION
The SDO line returns to high impedance after the sixth status bit is
clocked out (except in daisy-chain mode). The user is not required
to clock out all status bits to start the next conversion. Figure
55 shows the serial interface timing diagram for 3-wire CS mode
without the busy indicator, including the status bits.
STATUS WORD
The 6-bit status word can be appended to the end of a conversion
result, and the default conditions of these bits are shown in Table
16. The status bits must be enabled in the register setting. When
the OV clamp flag is 0, this bit indicates an overvoltage condition.
The OV clamp flag status bit updates on a per conversion basis.
Table 16. Status Bits (Default Conditions)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OV clamp flag
Span compression
High-Z mode
Turbo mode
Reserved
Reserved
Figure 55. 3-Wire CS Mode Without the Busy Indicator, Including Status Bits, Serial Interface Timing Diagram (SDI High)
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Data Sheet
ADAQ4001
APPLICATIONS INFORMATION
high impedance. The user must wait the tQUIET1 time after CNV
is brought high before bringing CNV low to clock out the previous
conversion result. When the conversion is complete (after tCONV),
the ADAQ4001 enters the acquisition phase and powers down. The
user must also wait the tQUIET2 time after the last falling edge of
SCK to when CNV is brought high.
3-WIRE CS TURBO MODE
To connect a single ADAQ4001 device to an SPI-compatible digital
host, use 3-wire CS turbo mode. This mode provides additional
time during the end of the ADC conversion process to clock out
the previous conversion result, providing a lower SCK rate. The
ADAQ4001 can achieve a throughput rate of 2 MSPS only with
turbo mode enabled and a minimum SCK rate of 70 MHz.
When CNV goes low, the MSB is output to SDO. The remaining
data bits are clocked by subsequent SCK falling edges. The data
is valid on both SCK edges. Although the rising edge can capture
the data, a digital host using the SCK falling edge allows a faster
reading rate, provided it has an acceptable hold time, as dictated by
tHSDO (see Table 3). If the status bits are not enabled, SDO returns
to high impedance after the 16th SCK falling edge. If the status bits
are enabled, the bits are shifted out on SDO on the 17th through
the 22nd SCK falling edges (see the Status Word section). SDO
returns to high impedance after the 16th SCK falling edge, or when
CNV goes high (whichever occurs first). The user must also provide
a delay of tQUIET2 between the final SCK falling edge and the next
CNV rising edge to ensure the specified performance.
Figure 56 shows the connection diagram, and Figure 57 shows the
corresponding timing diagram.
To enable turbo mode, set the turbo mode enable bit in the configu-
ration register to 1 (see Table 13). This mode replaces the 3-wire
mode with the busy indicator mode by programming the turbo
mode bit, Bit 1 (see Table 15). Writing to the user configuration
register requires SDI to be connected to the digital host (see the
Register Read and Write Functionality section). When turbo mode
is enabled, the conversion result read on SDO corresponds to the
result of the previous conversion.
When performing conversions in this mode, SDI must be held high,
and a CNV rising edge initiates a conversion and forces SDO to
Figure 56. 3-Wire CS Turbo Mode Connection Diagram (SDI High)
Figure 57. 3-Wire CS Turbo Mode Serial Interface Timing Diagram (SDI High)
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Data Sheet
ADAQ4001
APPLICATIONS INFORMATION
maximum possible conversion time to avoid the generation of the
busy signal indicator.
3-WIRE CS MODE WITHOUT THE BUSY
INDICATOR
When the conversion completes, the ADAQ4001 enters the acquis-
ition phase and powers down. When CNV goes low, the MSB is
output onto SDO. The remaining data bits are clocked by subse-
quent SCK falling edges. The data is valid on both SCK edges.
Although the rising edge can capture the data, a digital host using
the SCK falling edge allows a faster reading rate, provided that the
digital host has an acceptable hold time. After the 16th SCK falling
edge or when CNV goes high (whichever occurs first), SDO returns
to high impedance.
To connect a single ADAQ4001 device to an SPI-compatible digital
host, use 3-wire CS mode without the busy indicator.
Figure 58 shows the connection diagram, and Figure 59 shows the
corresponding timing diagram.
When SDI is connected to VIO, a rising edge on CNV initiates
a conversion, selects the CS mode, and forces SDO to high
impedance. After a conversion initiates, it continues until completion
irrespective of the state of CNV. This feature can be useful, for
instance, to bring CNV low to select other SPI devices, such
as analog multiplexers. However, CNV must return high before
the minimum conversion time elapses and then held high for the
There must not be any digital activity on SCK during the conver-
sion.
Figure 58. 3-Wire CS Mode Without the Busy Indicator Connection Diagram (SDI High)
Figure 59. 3-Wire CS Mode Without the Busy Indicator Serial Interface Timing Diagram (SDI High)
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Data Sheet
ADAQ4001
APPLICATIONS INFORMATION
this transition can be used as an interrupt signal to initiate the data
reading controlled by the digital host. The ADAQ4001 then enters
the acquisition phase and powers down. The data bits are then
clocked out, MSB first, by subsequent SCK falling edges. The data
is valid on both SCK edges. Although the rising edge can capture
the data, a digital host using the SCK falling edge allows a faster
reading rate, provided that the digital host has an acceptable hold
time. After the optional 17th SCK falling edge or when CNV goes
high (whichever occurs first), SDO returns to high impedance.
3-WIRE CS MODE WITH THE BUSY INDICATOR
To connect a single ADAQ4001 device to an SPI-compatible digital
host that has an interrupt input (IRQ), use 3-wire CS mode with the
busy indicator.
Figure 60 shows the connection diagram, and Figure 61 shows the
corresponding timing diagram.
When SDI is connected to VIO, a rising edge on CNV initiates
a conversion, selects the CS mode, and forces SDO to high impe-
dance. SDO is maintained in high impedance until the completion
of the conversion irrespective of the state of CNV. Prior to the
minimum conversion time, CNV can select other SPI devices, such
as analog multiplexers. However, CNV must be returned low before
the minimum conversion time elapses and then held low for the
maximum possible conversion time to guarantee the generation of
the busy signal indicator.
If multiple ADAQ4001 devices are selected at the same time, the
SDO output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention as
short as possible to limit extra power dissipation.
There must not be any digital activity on the SCK during the
conversion.
When the conversion completes, SDO goes from high impedance
to low impedance. With a pull-up resistor of 1 kΩ on the SDO line,
Figure 60. 3-Wire CS Mode with the Busy Indicator Connection Diagram (SDI High)
Figure 61. 3-Wire CS Mode with the Busy Indicator Serial Interface Timing Diagram (SDI High)
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Data Sheet
ADAQ4001
APPLICATIONS INFORMATION
edge. The user must wait tQUIET1 after CNV is brought high before
bringing SDI low to clock out the previous conversion result. The
user must also wait tQUIET2 after the last falling edge of SCK to
when CNV is brought high.
4-WIRE CS TURBO MODE
To connect a single ADAQ4001 to an SPI-compatible digital host,
use 4-wire CS turbo mode. This mode provides additional time
during the end of the ADC conversion process to clock out the pre-
vious conversion result, giving a lower SCK rate. The ADAQ4001
can achieve a throughput rate of 2 MSPS only when turbo mode is
enabled and using a minimum SCK rate of 70 MHz.
When the conversion is complete, the ADAQ4001 enters the ac-
quisition phase and powers down. The ADC result can be read
by bringing its SDI input low, which consequently outputs the MSB
onto SDO. The remaining data bits are then clocked by subsequent
SCK falling edges. The data is valid on both SCK edges. Although
the rising edge can capture the data, a digital host using the SCK
falling edge allows a faster reading rate, provided that the digital
host has an acceptable hold time. After the 16th SCK falling edge
or when SDI goes high (whichever occurs first), SDO returns to
high impedance.
Figure 62 shows the connection diagram, and Figure 63 shows the
corresponding timing diagram.
This mode replaces the 4-wire with busy indicator mode by pro-
gramming the turbo mode bit, Bit 1 (see Table 15).
With SDI high, a rising edge on CNV initiates a conversion. The
previous conversion data is available to read after the CNV rising
Figure 62. 4-Wire CS Turbo Mode Connection Diagram
Figure 63. 4-Wire CS Turbo Mode Timing Diagram
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Data Sheet
ADAQ4001
APPLICATIONS INFORMATION
returned high before the minimum conversion time elapses and
then held high for the maximum possible conversion time to avoid
the generation of the busy signal indicator.
4-WIRE CS MODE WITHOUT THE BUSY
INDICATOR
To connect multiple ADAQ4001 devices to an SPI-compatible digital
host, use 4-wire CS mode without the busy indicator.
When the conversion is complete, the ADAQ4001 enters the ac-
quisition phase and powers down. Each ADC result can be read
by bringing its SDI input low, which consequently outputs the MSB
onto SDO. The remaining data bits are then clocked by subsequent
SCK falling edges. The data is valid on both SCK edges. Although
the rising edge can capture the data, a digital host using the SCK
falling edge allows a faster reading rate, provided that the digital
host has an acceptable hold time. After the 16th SCK falling edge
or when SDI goes high (whichever occurs first), SDO returns to
high impedance and another ADAQ4001 can be read.
Figure 64 shows a connection diagram example using two
ADAQ4001 devices, and Figure 65 shows the corresponding timing
diagram.
With SDI high, a rising edge on CNV initiates a conversion, selects
the CS mode, and forces SDO to high impedance. In this mode,
CNV must be held high during the conversion phase and the
subsequent data readback. If SDI and CNV are low, SDO is driven
low. Prior to the minimum conversion time, SDI can select other
SPI devices, such as analog multiplexers. However, SDI must be
Figure 64. 4-Wire CS Mode Without the Busy Indicator Connection Diagram
Figure 65. 4-Wire CS Mode Without the Busy Indicator Serial Interface Timing Diagram
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Data Sheet
ADAQ4001
APPLICATIONS INFORMATION
SPI devices, such as analog multiplexers. However, SDI must be
returned low before the minimum conversion time elapses and then
held low for the maximum possible conversion time to guarantee
the generation of the busy signal indicator.
4-WIRE CS MODE WITH THE BUSY INDICATOR
To connect a single ADAQ4001 device to an SPI-compatible digital
host that has an interrupt input (IRQ), use 4-wire CS mode with
the busy indicator. Use this mode to keep CNV, which samples
the analog input, independent of the signal used to select the data
reading. This independence is particularly important in applications
where low jitter on CNV is desired.
When the conversion is complete, SDO goes from high impedance
to low impedance. With a pull-up resistor of 1 kΩ on the SDO line,
this transition can be used as an interrupt signal to initiate the data
readback controlled by the digital host. The ADAQ4001 then enters
the acquisition phase and powers down. The data bits are then
clocked out, MSB first, by subsequent SCK falling edges. The data
is valid on both SCK edges. Although the rising edge can capture
the data, a digital host using the SCK falling edge allows a faster
reading rate, provided that the digital host has an acceptable hold
time. After the optional 17th SCK falling edge or when SDI goes
high (whichever occurs first), SDO returns to high impedance.
Figure 66 shows the connection diagram, and Figure 67 shows the
corresponding timing diagram.
With SDI high, a rising edge on CNV initiates a conversion, selects
the CS mode, and forces SDO to high impedance. In this mode,
CNV must be held high during the conversion phase and the
subsequent data readback. If SDI and CNV are low, SDO is driven
low. Prior to the minimum conversion time, SDI can select other
Figure 66. 4-Wire CS Mode with the Busy Indicator Connection Diagram
Figure 67. 4-Wire CS Mode with the Busy Indicator Serial Interface Timing Diagram
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Data Sheet
ADAQ4001
APPLICATIONS INFORMATION
its data MSB first, and 16 × N clocks are required to read back
the N ADCs. The data is valid on both SCK edges. The maximum
conversion rate is reduced because of the total readback time.
DAISY-CHAIN MODE
To daisy-chain multiple ADAQ4001 devices on a 3-wire or 4-wire
serial interface, use daisy-chain mode. This feature is useful for
reducing component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a limited
interfacing capacity. Data readback is analogous to clocking a shift
register.
It is possible to write to each ADC register in daisy-chain mode (see
Figure 69). This mode requires 4-wire operation because data is
clocked in on the SDI line with CNV held low. The same command
byte and register data can be shifted through the entire chain to
program all ADCs in the chain with the same register contents,
which requires 8 × (N + 1) clocks for N ADCs. It is possible to
write different register contents to each ADC in the chain by writing
to the furthest ADC in the chain, first using 8 × (N + 1) clocks,
then the second furthest ADC with 8 × N clocks, and so on until
reaching the nearest ADC in the chain, which requires 16 clocks for
the command and register data.
Figure 68 shows a connection diagram example using two
ADAQ4001 devices, and Figure 69 shows the corresponding timing
diagram.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects daisy-chain
mode, and disables the busy indicator. In this mode, hold CNV high
during the conversion phase and the subsequent data readback.
When the conversion is complete, the MSB is output onto SDO,
and the ADAQ4001 enters the acquisition phase and powers down.
The remaining data bits stored in the internal shift register are
clocked out of SDO by subsequent SCK falling edges. For each
ADC, SDI feeds the input of the internal shift register and is clocked
by the SCK rising edges. Each ADC in the daisy chain outputs
It is not possible to read register contents in daisy-chain mode.
However, the six status bits can be enabled if the user wants to
determine the ADC configuration. Note that enabling the status
bits requires six extra clocks to clock out the ADC result and the
status bits per ADC in the chain. Turbo mode cannot be used in
daisy-chain mode.
Figure 68. Daisy-Chain Mode Connection Diagram
Figure 69. Daisy-Chain Mode Serial Interface Timing Diagram
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Data Sheet
ADAQ4001
APPLICATIONS INFORMATION
and to handle the transient currents. Therefore, the additional
LAYOUT GUIDELINES
external decoupling capacitors are not required without causing any
performance impact or electromagnetic interference (EMI) issues,
saving board space. This performance impact was verified on
the EVAL-ADAQ4001FMCZ by removing the external decoupling
capacitors on the output of reference and LDO regulators that
generate the on-board rails (REF, VS+, VS−, VDD, and VIO).
Figure 70 shows that any spurs are buried well below −120 dB
in the noise floor whether the external decoupling capacitors are
used or removed. The recommended board layout is outlined in the
EVAL-ADAQ4001FMCZ user guide (UG-1533).
The PCB layout is critical for preserving signal integrity and ach-
ieving the expected performance from the ADAQ4001. It is recom-
mended to design a multilayer board with an internal, clean ground
plane and a separate power plane to route various supply rails
beneath the ADAQ4001. Care must be taken with the placement of
individual components and routing of various signals on the board.
It is recommended to route input and output signals symmetrically
while keeping the power supply circuitry away from the analog
signal path. Keep the sensitive analog and digital sections separate
and confined to certain areas of the board and avoid crossover of
digital and analog signals.
The pinout of the ADAQ4001 eases the layout and allowing its
analog signals on the left side and its digital signals on the right
side. Fast switching signals, such as CNV or clocks, must not run
near or crossover analog signal paths to prevent noise coupling to
the ADAQ4001. Remove the ground and power planes beneath the
input and output pins of the ADAQ4001 to avoid undesired parasitic
capacitance, especially underneath summing junction nodes (IN+
and IN−) and any floating inputs. Any undesired parasitic capaci-
tance on the summing junction nodes can reduce the phase margin
of the FDA and impact the distortion and linearity performance of
the ADAQ4001.
The ADAQ4001 enables a high channel density PCB layout by
incorporating all the necessary decoupling ceramic capacitors for
the reference and power supply (REF, VS+, VS−, VDD, and VIO)
pins to provide a low impedance path to ground at high frequencies
Figure 70. FFT with Shorted Inputs
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Data Sheet
ADAQ4001
OUTLINE DIMENSIONS
7.10
7.00 SQ
6.90
A1 BALL
CORNER
A1 BALL
CORNER
7
6
5
4
3
2
1
1.10
REF
A
B
C
4.80 REF
SQ
D
E
F
G
0.80
BSC
BOTTOM VIEW
TOP VIEW
DETAIL A
SIDE VIEW
2.432
2.332
2.232
1.65 REF
DETAIL A
0.372
0.332
0.292
0.40
0.35
0.30
COPLANARITY
0.08
0.50
0.45
0.40
SEATING
PLANE
BALL DIAMETER
Figure 71. 49-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-49-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Packing Quantity
Package Option
ADAQ4001BBCZ
−40°C to +125°C
−40°C to +125°C
49-Ball Chip Scale Package Ball Grid Array [CSP-BGA] Tray, 416
49-Ball Chip Scale Package Ball Grid Array [CSP-BGA] Reel, 2000
BC-49-5
BC-49-5
ADAQ4001BBCZ-RL13
1
Z = RoHS Compliant Part.
EVALUATION BOARDS
Model1
Description
Evaluation Board
EVAL-ADAQ4001FMCZ
1
The EVAL-ADAQ4001FMCZ is compatible with the EVAL-SDP-CH1Z. See the UG-1533 for more details.
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