ADADC80-Z-12 [ADI]
12-Bit Successive-Approximation Integrated Circuit ADC;
| 型号： | ADADC80-Z-12 |
| 厂家： | 
ADI |
| 描述： | 12-Bit Successive-Approximation Integrated Circuit ADC CD 转换器 |
| 文件： | 总17页 (文件大小：273K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-Bit Successive-Approximation
Integrated Circuit ADC
ADADC80
FUNCTIONAL BLOCK DIAGRAM
FEATURES
1
2
3
32
31
30
True 12-bit operation: maximum nonlinearity 0.012ꢀ
Low gain temperature coefficient (TC): 30 ppm/°C
maximum
Low power: 800 mW
Fast conversion time: 25 μs
BIT 6
BIT 5
BIT 7
BIT 8
BIT 9
BIT 4
12-BIT
SAR
BIT 3
4
5
6
7
29 BIT 10
28
27
26
BIT 2
BIT 11
Precision 6.3 V reference for external application
Short-cycle capability
BIT 1 (MSB)
NC
BIT 12 (LSB)
NC
Parallel data output
8
25
–15V OR –12V
BIT 1 (MSB)
Monolithic DAC with scaling resistors for stability
Low chip count, high reliability
Industry-standard pin configuration
“Z” models for 12 V supplies
5V DIGITAL
SUPPLY
CLOCK
AND
CONTROL
CIRCUITS
9
24 REF OUT (6.3V)
12-BIT DAC
10
11
12
13
14
15
16
23
DIGITAL GND
CLOCK OUT
COMPARATOR
IN
BIPOLAR
OFFSET OUT
22
21
20
19
18
17
STATUS
SHORT CYCLE
COMP
10V SPAN IN
CLOCK INHIBIT
EXTERNAL
CLOCK IN
20V SPAN IN
REFERENCE
CONVERT
START
ANALOG GND
ADADC80
GAIN ADJUST
15V OR 12V
NC = NO CONNECT
Figure 1.
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
The ADADC801 is a complete 12-bit successive-approximation
analog-to-digital converter (ADC) that includes an internal
clock, reference, and comparator. Its hybrid IC design uses MSI
digital and linear monolithic chips in conjunction with a 12-bit
monolithic digital-to-analog converter (DAC) to provide
modular performance and versatility with IC size, price, and
reliability.
1. The ADADC80 is a complete 12-bit ADC. No external
components are required to perform a conversion.
2. A monolithic 12-bit feedback DAC is used for reduced chip
count and higher reliability.
3. The internal buried Zener reference is laser trimmed to
6.3 ꢁ. The reference voltage is available externally and can
supply up to 1.5 mA beyond the current required for the
reference and bipolar offset.
Important performance characteristics of the ADADC80
include a maximum linearity error of 0.012ꢀ at 25°C,
maximum gain TC of 30 ppm/°C, typical power dissipation of
800 mW, and maximum conversion time of 25 μs. Monotonic
operation of the feedback DAC guarantees no missing codes
over the temperature range of −25°C to +85°C.
4. The scaling resistors are included on the monolithic DAC
for exceptional thermal tracking.
5. The ADADC80 directly replaces other devices of this type,
providing significant increases in performance.
6. The fast conversion rate of the ADADC80 makes it an
excellent choice for applications requiring high system
throughput rates.
7. The short cycle and external clock options are provided
for applications requiring faster conversion speed or
lower resolution.
The design of the ADADC80 includes scaling resistors that
provide an analog signal range of 2.5 ꢁ, 5.0 ꢁ, 10 ꢁ, 0 ꢁ to
+5.0 ꢁ, or 0 ꢁ to +10.0 ꢁ. The 6.3 ꢁ precision reference can be
used for external applications. All digital signals are fully DTL
and TTL compatible; output data is in parallel form.
The ADADC80 is available in grades specified for use over the
−25°C to +85°C temperature range and is available in a 32-lead
ceramic DIP.
1 The serial output function is no longer supported on this product after
Date Code 9616.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
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Fax: 781.461.3113 ©2002–2008 Analog Devices, Inc. All rights reserved.
ADADC80* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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DESIGN RESOURCES
• ADADC80 Material Declaration
• PCN-PDN Information
DOCUMENTATION
• Quality And Reliability
Data Sheet
• Symbols and Footprints
• ADADC80: 12-Bit Successive Approximation Integrated
Circuit A/D Converter Scanned Data Sheet
DISCUSSIONS
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SOFTWARE AND SYSTEMS REQUIREMENTS
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ADADC80
TABLE OF CONTENTS
Features .............................................................................................. 1
Timing ............................................................................................8
Digital Output Data ......................................................................9
Input Scaling ..................................................................................9
Offset Adjustment...................................................................... 10
Gain Adjustment ........................................................................ 10
Calibration................................................................................... 11
Grounding................................................................................... 12
Control Modes............................................................................ 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
Functional Block Diagram .............................................................. 1
Product Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ........................................................................ 8
REVISION HISTORY
2/08—Rev. D to Rev. E
8/03—Rev. C to Rev. D
Updated Format..................................................................Universal
Pin 7 Changed to NC .........................................................Universal
Changes to Specifications Section.................................................. 3
Added Absolute Maximum Ratings Section................................. 5
Updated Outline Dimensions....................................................... 13
Changes to Ordering Guide .......................................................... 13
Changes to Specifications.................................................................2
4/03—Rev. B to Rev. C
Changes to General Description .....................................................1
9/02—Rev. A to Rev. B
Changes to Figure 1...........................................................................6
Updated Outline Dimensions....................................................... 11
Rev. E | Page 2 of 16
ADADC80
SPECIFICATIONS
Typical @ 25°C, 15 ꢁ, and +5 ꢁ, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
RESOLUTION
ANALOG INPUTS
Voltage Ranges
Bipolar
12
Bits
2.ꢀ or ꢀ or 10
0 to +ꢀ or 0 to +10
V
V
Unipolar
Impedance (Direct Input)
0 to +ꢀ, 2.ꢀ V
0 to +10, ꢀ V
10 V
2.ꢀ
ꢀ
10
kΩ
kΩ
kΩ
DIGITAL INPUTS1
Positive Pulse During Conversion (CONVERT
START)
100
ns
Logic Loading
External Clock (EXTERNAL CLOCK IN)
1
1
TTL load
TTL load
TRANSFER CHARACTERISTICS ERROR
Gain Error2
0.1
% of FSR3
Offset2
Bipolar
Unipolar
Linearity Error4
Inherent Quantization Error
0.1
0.0ꢀ
% of FSR
% of FSR
% of FSR
LSB
0.012
½
½
Differential Linearity Error
LSB
No Missing Codes Temperature Range
Power Supply Sensitivity
1ꢀ V
+ꢀ V
−2ꢀ
−2ꢀ
+8ꢀ
°C
0.0030
0.001ꢀ
% of FSR/% VS
% of FSR/% VS
DRIFT
Specification Temperature Rangeꢀ
+8ꢀ
30
°C
ppm/°C
Gain
Offset
Bipolar
Unipolar
Linearity
1ꢀ
3
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
3
Monotonicity
Guaranteed
22
CONVERSION SPEED6
DIGITAL OUTPUTS (ALL CODES COMPLEMENTARY)
Parallel, BIT 1 (MSB) to BIT 12 (LSB)
Output Codes7
17
2ꢀ
μs
Bipolar
COB, CTC
Unipolar
CSB
Output Drive
2
TTL loads
TTL loads
Status (STATUS)
Status Output Drive
Internal Clock (CLOCK OUT)
Clock Output Drive
Frequency8
Logic 1 during conversion
2
2
ꢀ7ꢀ
TTL loads
kHz
Rev. E | Page 3 of 16
ADADC80
Parameter
Min
Typ
Max
Unit
INTERNAL REFERENCE VOLTAGE
+6.3 V
10
mV
Maximum External Current
(With No Degradation of Specifications)
Temperature Coefficient of Driftꢀ
1.ꢀ
10
mA
ppm/°C
20
POWER REQUIREMENTS
Rated Voltages
Range for Rated Accuracyꢀ
1ꢀ, +ꢀ
V
+ꢀ V
1ꢀ V
“Z” Modelsꢀ, 9
+4.7ꢀ
14.0
+ꢀ.2ꢀ
16.0
V
V
+ꢀ V
1ꢀ V
+4.7ꢀ
11.4
+ꢀ.2ꢀ
16.0
V
V
Supply Drain
+1ꢀ V
−1ꢀ V
+ꢀ V
+10
−20
+70
mA
mA
mA
TEMPERATURE RANGE
Specification
Operating (Derated Specifications)
Storage
−2ꢀ
−ꢀꢀ
−ꢀꢀ
+8ꢀ
+100
+12ꢀ
°C
°C
°C
1 DTL/TTL compatible, that is, Logic 0 = 0.8 V maximum and Logic 1 = 2.0 V minimum for digital inputs, Logic 0 = 0.4 V maximum and Logic 1 = 2.4 V minimum for digital outputs.
2 Adjustable to zero with external trimpots.
3 FSR means full-scale range, that is, unit connected for 10 V range has +20 V FSR.
4 Error shown is the same as ½ LSB maximum for resolution of analog-to-digital converter.
ꢀ Guaranteed by design. Not production tested.
6 Conversion time with internal clock.
7 See Table 4. Complementary offset binary is COB, complementary straight binary is CSB, and complementary twos complement is CTC.
8 For conversion speeds specified.
9 For “Z” models, order ADADC80-Z-12.
Rev. E | Page 4 of 16
ADADC80
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Supply Voltage
18 V
7 V
0.3 V
VS
−0.3 V to VDD + 0.3 V
17ꢀ°C
1ꢀ0°C
Logic Supply Voltage
Analog Ground to Digital Ground
Analog Inputs (Pin 13, Pin 14)
Digital Input
Junction Temperature
Storage Temperature
Lead Temperature (Soldering, 10 sec)
300°C
ESD CAUTION
Rev. E | Page ꢀ of 16
ADADC80
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
BIT 6
BIT 7
2
BIT 5
BIT 8
3
BIT 4
BIT 9
4
BIT 3
BIT 10
ADADC80
TOP VIEW
(Not to Scale)
5
BIT 2
BIT 11
6
BIT 1 (MSB)
NC
BIT 12 (LSB)
NC
7
8
BIT 1 (MSB)
5V DIGITAL SUPPLY
DIGITAL GND
COMPARATOR IN
BIPOLAR OFFSET OUT
10V SPAN IN
20V SPAN IN
–15V OR –12V
REF OUT (6.3V)
CLOCK OUT
STATUS
9
10
11
12
13
14
SHORT CYCLE
CLOCK INHIBIT
EXTERNAL CLOCK IN
ANALOG GND 15
16
18 CONVERT START
17
GAIN ADJUST
15V OR 12V
NC = NO CONNECT
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1 to 6
7
Mnemonic
Function
BIT 6 to BIT 1 (MSB)
NC
Digital Outputs.
No Connection.
8
BIT 1 (MSB)
MSB Inverted Digital Output.
Digital Positive Supply (Nominally 0.2ꢀ V).
Digital Ground.
Offset Adjust.
Bipolar Offset Output.
Analog Input 10 V Signal Range.
Analog Input 20 V Signal Range.
Analog Ground.
9
10
11
12
13
14
1ꢀ
16
17
18
19
20
21
22
23
ꢀV DIGITAL SUPPLY
DIGITAL GND
COMPARATOR IN
BIPOLAR OFFSET OUT
10V SPAN IN
20V SPAN IN
ANALOG GND
GAIN ADJUST
1ꢀV OR 12V
CONVERT START
EXTERNAL CLOCK IN
CLOCK INHIBIT
SHORT CYCLE
STATUS
Gain Adjust.
Analog Positive Supply (Nominally 1.0 V for +1ꢀ V or 0.6 V for +12 V).
Enables Conversion.
External Clock Input.
Clock Inhibit.
Shortens Conversion Cycle to Desired Resolution.
Logic High, ADC Converting/Logic Low, ADC Data Valid.
Internal Clock Output.
CLOCK OUT
24
2ꢀ
26
REF OUT (6.3V)
−1ꢀV OR −12V
NC
6.3 V Reference Output.
Analog Negative Supply (Nominally 1.0 V for −1ꢀ V or 0.6 V for −12 V).
No Connection.
27 to 32
BIT 12 (LSB) to BIT 7
Digital Outputs.
Rev. E | Page 6 of 16
ADADC80
TYPICAL PERFORMANCE CHARACTERISTICS
1.00
1.00
0.75
0.75
0.50
0.50
0.25
0
8-BIT
10-BIT
12-BIT
8-BIT
10-BIT
12-BIT
0.25
0
0
2
4
6
8
10 12 14 16 18 20 22 24 26
0
2
4
6
8
10 12 14 16 18 20 22 24 26
CONVERSION TIME (µs)
CONVERSION TIME (µs)
Figure 5. Differential Linearity Error vs. Conversion Time (Normalized)
Figure 3. Linearity Error vs. Conversion Time (Normalized)
0.3
0.08
0.06
0.04
0.02
0.2
0.1
0
0
TYPICAL
–0.02
–0.1
–0.04
–0.06
–0.08
–0.2
–0.3
–55
–25
0
25
85
100
–25
0
25
70
85
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 6. Reference Drift, Error vs. Temperature
Figure 4. Gain Drift Error vs. Temperature
Rev. E | Page 7 of 16
ADADC80
THEORY OF OPERATION
Upon receipt of a CONꢁERT START command, the ADADC80
converts the voltage at its analog input into an equivalent 12-bit
binary number. This conversion is accomplished as follows:
All changes to the SAR parallel bit and to the STATUS bit are
initialized on the leading edge, and the gated clock inhibit
signal is removed on the trailing edge of the CONꢁERT START
signal. At time t0, BIT 1 is reset and BIT 2 to BIT 12 are set
unconditionally. At t1, the BIT 1 decision is made (keep) and
BIT 2 is unconditionally reset. At t2, the BIT 2 decision is made
(keep) and BIT 3 is reset unconditionally. This sequence
continues until the BIT 12 (LSB) decision (keep) is made at t12.
After a 40 ns delay period, the STATUS flag is reset, indicating
that the conversion is complete and the parallel output data is
valid. Resetting the STATUS flag restores the gated clock inhibit
signal, forcing the clock output to the Logic 0 state.
1. The 12-bit successive-approximation register (SAR) has its
12-bit outputs connected both to the device bit output pins
and to the corresponding bit inputs of the feedback DAC.
2. The analog input is successively compared to the feedback
DAC output, one bit at a time (MSB first, LSB last).
3. The decision to keep or reject each bit is then made at the
completion of each bit comparison period, depending on
the state of the comparator at that time.
TIMING
Parallel data bits become valid on the positive-going clock edge
(see Figure 7).
The timing diagram is shown in Figure 7. Receipt of a
CONꢁERT START signal sets the STATUS flag, indicating that
a conversion is in progress. This, in turn, removes the inhibit
applied to the gated clock, permitting it to run through 13 cycles.
Incorporation of this 40 ns delay guarantees that the parallel
data is valid at the Logic l to Logic 0 transition of the STATUS
flag, permitting a parallel data transfer to be initiated by the
trailing edge of the STATUS signal.
MAXIMUM THROUGHPUT TIME
CONVERT
START
2
CONVERSION TIME
1
INTERNAL
CLOCK
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
3
STATUS
t12
*
*
*
*
*
*
*
*
*
*
MSB
0
BIT 2
BIT 3
1
1
BIT 4
BIT 5
0
0
BIT 6
BIT 7
BIT 8
BIT 9
1
1
1
0
1
BIT 10
BIT 11
1
LSB
0
NOTES
1
1
THE CONVERT START PULSE WIDTH IS 100ns MINIMUM AND MUST REMAIN LOW DURING A CONVERSION.
THE CONVERSION IS INITIATED BY THE RISING EDGE OF THE CONVERT COMMAND.
2
25µs FOR 12 BITS AND 21µs FOR 10 BITS (MAXIMUM).
3t1 SHOWS THE MSB DECISION AND t11 SHOWS THE LSB DECISION 40ns PRIOR TO THE STATUS GOING LOW.
*BIT DECISIONS.
Figure 7. Timing Diagram (Binary Code 011001110110)
Rev. E | Page 8 of 16
ADADC80
diagram of Figure 7). Short cycle pin connections and
DIGITAL OUTPUT DATA
associated maximum 12-, 10-, and 8-bit conversion times are
summarized in Table 4. When 12-bit resolution is required,
SHORT CYCLE (Pin 21) is connected to 5ꢁ DIGITAL SUPPLY
(Pin 9).
Parallel data from TTL storage registers is in negative true form.
Parallel data output coding is complementary binary for
unipolar ranges and either complementary offset binary or
complementary twos complement binary for bipolar ranges,
depending on whether BIT 1 (Pin 6) or its logical inverse
INPUT SCALING
BIT 1 (MSB)
(Pin 8) is used as the MSB. Parallel data becomes
The ADADC80 input should be scaled as close to the maximum
input signal range as possible to use the maximum signal
resolution of the ADC. Connect the input signal as shown in
Table 5. See Figure 8 for circuit details.
valid approximately 40 ns before the STATUS flag returns to
Logic 0, permitting parallel data transfer to be clocked on the
1 to 0 transition of the STATUS flag.
Parallel data outputs change state on positive-going clock edges.
There are 13 negative-going clock edges in the complete 12-bit
conversion cycle, as shown in Figure 7. The first edge shifts an
invalid bit into the register, which is shifted out on the 13th
negative-going clock edge.
13
10V SPAN IN
R2
5kΩ
14
20V SPAN IN
R1
5kΩ
11
COMPARATOR IN
TO SAR
FROM
DAC
SHORT CYCLE Input
COMPARATOR
The SHORT CYCLE input (Pin 21) permits the timing cycle shown
in Figure 7 to be terminated after any number of desired bits has
been converted, allowing somewhat shorter conversion times in
applications not requiring full 12-bit resolution. When 10-bit
resolution is desired, Pin 21 is connected to the BIT 11 output
(Pin 28). The conversion cycle then terminates, and the
6.3kΩ
BIPOLAR
OFFSET OUT
V
12
15
REF
ANALOG
GND
Figure 8. Input Scaling Circuit
STATUS flag resets after the BIT 10 decision (t10 + 40 ns in timing
Table 4. Short Cycle Connections
Connect SHORT CYCLE (Pin 21) to
ꢀV DIGITAL SUPPLY (Pin 9)
BIT 11 (Pin 28)
Resolution (Bits)
(ꢀ FSR)
0.024
0.100
Maximum Conversion Time (μs)
STATUS Flag Reset
t12 + 40 ns
t10 + 40 ns
12
10
8
2ꢀ
21
17
BIT 9 (Pin 30)
0.390
t8 + 40 ns
Table 5. Input Scaling Connections
Connect BIPOLAR OFFSET OUT
(Pin 12) to
Connect 20V SPAN IN
(Pin 14) to
Input Signal Range
10 V
ꢀ V
2.ꢀ V
0 V to +ꢀ V
0 V to +10 V
Output Code
COB or CTC
COB or CTC
COB or CTC
CSB
Connect Input Signal to
20V SPAN IN (Pin 14)
10V SPAN IN (Pin 13)
10V SPAN IN (Pin 13)
10V SPAN IN (Pin 13)
10V SPAN IN (Pin 13)
COMPARATOR IN (Pin 11)
COMPARATOR IN (Pin 11)
COMPARATOR IN (Pin 11)
ANALOG GND (Pin 1ꢀ)
ANALOG GND (Pin 1ꢀ)
Input Signal
Open
COMPARATOR IN (Pin 11)
COMPARATOR IN (Pin 11)
Open
CSB
Rev. E | Page 9 of 16
ADADC80
Table 6. Input Voltage Range and LSB Values
Binary Output
Analog Input Voltage Range
Defined as
10 V
COB1
5 V
COB1
2.5 V
COB1
0 V to +10 V
0 V to +5 V
Code Designation
or CTC2
or CTC2
or CTC2
CSB3
CSB3
One Least Significant Bit (LSB)
FSR
2n
20 V
2n
10 V
2n
ꢀ V
2n
10 V
2n
ꢀ V
2n
n = 8
n = 10
n = 12
78.13 mV
19.ꢀ3 mV
4.88 mV
39.06 mV
9.77 mV
2.44 mV
19.ꢀ3 mV
4.88 mV
1.22 mV
39.06 mV
9.77 mV
2.44 mV
19.ꢀ3 mV
4.88 mV
1.22 mV
Transition Values
MSB LSB
000. . . 0004
011. . . 111
111. . . 110
+Full scale
Midscale
−Full scale
10 V − 3/2 LSB
0
ꢀ V − 3/2 LSB
0
2.ꢀ V − 3/2 LSB
0
10 V − 3/2 LSB ꢀ V − 3/2 LSB
ꢀ V
2.ꢀ V
−10 V + 1/2 LSB −ꢀ V + 1/2 LSB −2.ꢀ V + 1/2 LSB 0 V + 1/2 LSB
0 V + 1/2 LSB
1 COB = complementary offset binary.
2
MSB MSB
).
CTC = complementary twos complement; obtained by using the complement of the most significant bit (
is available on Pin 8.
3 CSB = complementary straight binary.
4 Voltages given are the nominal value for transition to the code specified.
OFFSET ADJUSTMENT
The zero adjust circuit consists of a potentiometer connected
across ꢁS with its slider connected through a 1.8 MΩ resistor
to COMPARATOR IN (Pin 11) for all ranges. As shown in
Figure 9, the tolerance of this fixed resistor is not critical, and a
carbon composition type is generally adequate. Using a carbon
composition resistor with a −1200 ppm/°C tempco contributes
a worst-case offset tempco of 8 × 244 × 10−6 × 1200 ppm/°C =
2.3 ppm/°C of FSR if the offset adjustment potentiometer is set
at either end of its adjustment range. Because the maximum
offset adjustment required is typically no more than 4 LSB,
use of a carbon composition offset summing resistor typically
contributes no more than 1 ppm/°C of FSR offset tempco.
In either zero adjust circuit, the fixed resistor connected to
COMPARATOR IN (Pin 11) should be located close to this pin
to keep the pin connection runs short. Pin 11 is quite sensitive
to external noise pickup.
GAIN ADJUSTMENT
The gain adjust circuit consists of a potentiometer connected
across ꢁS with its slider connected through a 10 MΩ resistor
to the GAIN ADJUST (Pin 16), as shown in Figure 11.
+15V
GAIN
ADJUST
10kΩ
TO
100kΩ
10MΩ
GAIN
ADJUST
16
ADADC80
0.01µF
+15V
–15V
COMPARATOR
IN
10kΩ
TO
100kΩ
Figure 11. Gain Adjustment Circuit
11
ADADC80
1.8MΩ
An alternative gain adjust circuit, which contributes negligible
gain tempco if metal film resistors (tempco < 100 ppm/°C) are
used, is shown in Figure 12.
–15V
Figure 9. Offset Adjustment Circuit
+15V
An alternative offset adjust circuit, which contributes negligible
offset tempco if metal film resistors (tempco < 100 ppm/°C) are
used, is shown in Figure 10. Note that the abbreviation MF in
Figure 10 and Figure 12 refer to metal film resistors.
+15V
270kΩ
MF
270kΩ
MF
GAIN
ADJUST
10kΩ
TO
100kΩ
16
ADADC80
6.8kΩ
0.1µF
–15V
Figure 12. Low Tempco Gain Adjustment Circuit
COMPARATOR
180kΩ
MF
IN
10kΩ
TO
100kΩ
OFFSET
ADJUST
11
ADADC80
22kΩ
MF
180kΩ
MF
–15V
A
Figure 10. Low Tempco Zero Adjustment Circuit
Rev. E | Page 10 of 16
ADADC80
input to +FSR − 2 LSB = 9.9952 ꢁ; adjust gain for 000000000001
digital output code. Full-scale gain is now calibrated. For half-
scale calibration check, set analog input to 5.0000 ꢁ; digital
output code should be 011111111111.
CALIBRATION
External zero adjustment and gain adjustment potentiometers,
connected as shown in Figure 13 and Figure 14, are used for
device calibration. To prevent interaction of these two adjustments,
zero is always adjusted first and gain second. Zero is adjusted
with the analog input near the most negative end of the analog
range (0 for unipolar and −FS for bipolar input ranges). Gain is
adjusted with the analog input near the most positive end of the
analog range.
−10 V to +10 V Range
Set analog input to −9.9951 ꢁ; adjust zero for 111111111110
digital output (complementary offset binary) code. Set analog
input to +9.9902 ꢁ; adjust gain for 000000000001 digital output
(complementary offset binary) code. For half-scale calibration
check, set analog input to 0.0000 ꢁ; digital output (complemen-
tary offset binary) code should be 011111111111.
0 V to 10 V Range
Set analog input to +1 LSB = 0.0024 ꢁ; adjust zero for digital
output = 111111111110. Zero is now calibrated. Set analog
ADADC80
SAR
DAC
REF OUT
(6.3V)
24
17
REF
+15V
–15V
15V OR 12V
+
+
ANALOG
GND
15
25
DIGITAL
BIPOLAR
OFFSET SPAN SPAN COMPARATOR
OUT IN IN IN
20V
10V
GND
5V DIGITAL
COMPARATOR
GAIN
–15V OR
–12V
SUPPLY
9
ADJUST
10
16
12
14
13
11
–15V
+5V
+
1.8MΩ
10kΩ
–15V
10kΩ
+15V
10MΩ
ANALOG
INPUT
0.01µF
+15V
Figure 13. Analog and Power Connections for Unipolar 0 V to 10 V Input Range
ADADC80
SAR
REF OUT
(6.3V)
24
17
REF
DAC
+15V
–15V
15V OR 12V
+
+
ANALOG
GND
15
25
DIGITAL
BIPOLAR
OFFSET SPAN SPAN COMPARATOR
OUT IN IN IN
20V
10V
GND
5V DIGITAL
COMPARATOR
GAIN
–15V OR
–12V
SUPPLY
9
ADJUST
10
16
12
14
13
11
–15V
+5V
+
1.8MΩ
10kΩ
–15V
10kΩ
+15V
10MΩ
ANALOG
INPUT
0.01µF
+15V
Figure 14. Analog and Power Connections for Bipolar 10 V Input Range
Rev. E | Page 11 of 16
ADADC80
Other Ranges
common (analog power return), and analog signal ground.
These grounds must be tied together at one point, usually at the
system power-supply ground. Ideally, a single solid ground is
desirable. However, because current flows through the ground
wires and etch stripes of the circuit cards, and because these
paths have resistance and inductance, hundreds of millivolts can
be generated between the system ground point and the ground
pin of the ADADC80. Therefore, separate ground returns
should be provided to minimize the current flow in the path
from sensitive points to the system ground point, and the two
device grounds should be tied together. In this way, supply
currents and logic gate return currents are not summed into the
same return path as analog signals, where they would cause
measurement errors.
Coding relationships and calibration points for 0 ꢁ to +5 ꢁ,
−2.5 ꢁ to +2.5 ꢁ, and −5 ꢁ to +5 ꢁ ranges can be found by
halving the corresponding code equivalents listed for the 0 ꢁ to
+10 ꢁ and −10 ꢁ to +10 ꢁ ranges, respectively.
Zero and full-scale calibration can be accomplished to a
precision of approximately 1/4 LSB using the static adjustment
procedure described previously. By summing a small sine- or
triangular-wave voltage with the signal applied to the analog
input, the output can be cycled through each of the calibration
codes of interest to more accurately determine the center (or
end points) of each discrete quantization level. A detailed
description of this dynamic calibration technique is presented
in A/D Conversion Notes, D. Sheingold, Analog Devices, Inc.,
1977, Part II, Chapter 3.
Each of the ADADC80 supply terminals should be capacitively
decoupled as close to the ADADC80 as possible. A large value
capacitor, such as 1 μF in parallel with a 0.1 μF capacitor, is
usually sufficient. Analog supplies are bypassed to the analog
power return pin, and the logic supply is bypassed to the logic
power return pin.
GROUNDING
Many data-acquisition components have two or more ground
pins that are not connected together within the device. These
grounds are usually referred to as the logic power return, analog
ANALOG
PS
DIGITAL
PS
+15V
C
–15V
C
5V
0.01
µF
0.01
µF
0.01 0.01
µF µF
0.01 0.01
µF µF
DIG
COM
0.01
µF
17
15
25
10
9
AD521
AD583
SAMPLE AND
HOLD
15V OR ANALOG –15V OR DIGITAL
12V
5V
INST. AMP
GND
–12V
GND DIGITAL
SUPPLY
*ANALOG
GROUND
ADADC80
OUTPUT
REFERENCE
DIGITAL
GROUND
*IF INDEPENDENT, OTHERWISE RETURN
AMPLIFIER REFERENCE TO MECCA AT
ANALOG P.S. COMMON.
Figure 15. Basic Grounding Practice
Rev. E | Page 12 of 16
ADADC80
10-BIT
OPERATION
CONTROL MODES
ADADC80
EXTERNAL
CLOCK IN
19
28
BIT 11
The timing sequence of the ADADC80 allows the device to be
easily operated in a variety of systems with different control
modes. The most common control modes are illustrated in
Figure 16, Figure 17, and Figure 18.
EXTERNAL
CLOCK
12-BIT
OPERATION
SHORT
CYCLE
21
20
5V
CLOCK
INHIBIT
CONVERT
START
18
DIGITAL
COMMON
DIGITAL
COMMON
10-BIT
OPERATION
ADADC80
Figure 17. Continuation Conversion with External Clock Conversion Initiated
by 14th Clock Pulse (Clock Runs Continuously)
CONVERT
18
28
BIT 11
START
CONVERT
COMMAND
SHORT
CYCLE
21
20
19
12-BIT
OPERATION
10-BIT
OPERATION
ADADC80
CLOCK
INHIBIT
EXTERNAL
CLOCK IN
19
22
28
BIT 11
EXTERNAL
CLOCK
EXTERNAL
CLOCK IN
5V
12-BIT
OPERATION
STATUS
Figure 16. Internal Clock—Normal Operating Mode,
Conversion Initiated by the Rising Edge of Convert Command
(Internal Clock Runs Only During Conversion)
SHORT
CYCLE
21
20
5V
CLOCK
INHIBIT
CONVERT
START
18
DIGITAL
COMMON
CONVERT
COMMAND
Figure 18. Continuous External Clock Conversion Initiated by Rising Edge of
Convert Command (Convert Command Must Be Synchronized with Clock)
Rev. E | Page 13 of 16
ADADC80
OUTLINE DIMENSIONS
SEE NOTE 4
0.005 (0.13) MIN
0.098 (2.49) MAX
17
32
0.910 (23.11) MAX
0.870 (22.10) MIN
1
16
PIN 1
INDICATOR
SEE NOTE 1
1.616 (41.05) MAX
0.060 (1.52) MAX
0.040 (1.02) MIN
SEE NOTE 2
0.280 (7.11)
MAX
0.012 (0.30) MAX
0.009 (0.23) MIN
0.120 (3.05)
MIN
0.180 (4.57)
MIN
0.930 (23.62) MAX
0.890 (22.61) MIN
SEE NOTE 5
0.100 (2.54)
BSC
SEE NOTE 3, 6
0.020 (0.51) MAX
0.016 (0.41) MIN
0.055 (1.40) MAX
0.035 (0.89) MIN
NOTES:
1. INDEX AREA; A NOTCH OR A LEAD ONE IDENTIFICATION MARK IS
LOCATED ADJACENT TO LEAD ONE.
2. DIMENSION SHALL BE MEASURED FROM THE SEATING PLANE TO THE BASE PLANE.
3. THE BASIC PIN SPACING IS 0.100" (2.54 mm) BETWEEN CENTERLINES.
4. APPLIES TO ALL FOUR CORNERS.
5. THE DIMENSION SHALL BE MEASURED AT THE CENTERLINE OF THE LEADS.
6. THIRTY SPACES.
7. CONTROLLING DIMENSIONS ARE IN INCHES. MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 19. 32-Lead Side Brazed Ceramic DIP for Hybrid [SBDIP_H]
(DH-32D)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model
ADADC80-12
ADADC80-Z-121
Temperature Range
–2ꢀ°C to +8ꢀ°C
–2ꢀ°C to +8ꢀ°C
Package Description
32-Lead SBDIP_H
32-Lead SBDIP_H
Package Option
DH-32D
DH-32D
1 “Z “= Models for 12 V supplies. This part is not RoHS compliant.
Rev. E | Page 14 of 16
ADADC80
NOTES
Rev. E | Page 1ꢀ of 16
ADADC80
NOTES
©2002–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01202-0-2/08(E)
Rev. E | Page 16 of 16
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